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DSD Lab: Experiment-3

The document describes an experiment to design and implement a BCD to 7-segment decoder using behavioral modeling. It includes the circuit diagram, truth table, K-maps to derive the logic equations for each segment, VHDL code for the decoder, VHDL testbench code, and screenshots of the program and simulation showing the BCD to 7-segment decoder is working properly.

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raman Mehta
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60 views

DSD Lab: Experiment-3

The document describes an experiment to design and implement a BCD to 7-segment decoder using behavioral modeling. It includes the circuit diagram, truth table, K-maps to derive the logic equations for each segment, VHDL code for the decoder, VHDL testbench code, and screenshots of the program and simulation showing the BCD to 7-segment decoder is working properly.

Uploaded by

raman Mehta
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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DSD LAB

EXPERIMENT-3

AIM : TO DESIGN AND IMPLEMENT A BCD TO 7-SEGMENT DECODER


USING BEHAVIOURAL MODELLING.

APPARATUS USED : EDA PLAYGROUND , LOGISIM

THEORY :
BLOCK DIAGRAM :

CIRCUIT DIAGRAM :
TRUTH TABLE :

K-MAPS :
FOR ‘a’:
F = B’D’ + C + BD + A

FOR ‘b’:

F = B’ + C’D’ + CD

FOR ‘c’:

F = C’ + D + B

FOR ‘d’:
F = B’D’ + B’C + BC’D + CD’ + A

FOR ‘e’:

F = B’D’ + CD’

FOR ‘f’:

F = C’D’ + BC’ + BD’ + A

FOR ‘g’:
F = B’C + BC’ + A + BD’
PROGRAM CODE :

VHDL CODE :
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity decoder is
port(
ABCD : in std_logic_vector(3 downto 0);
segment :out std_logic_vector(6 downto 0)
);
end entity;

architecture behavioural of decoder is


begin
process(ABCD)
begin
case ABCD is
when "0000" => segment <="1111110";
when "0001" => segment <="0110000";
when "0010" => segment <="1101101";
when "0011" => segment <="1111001";
when "0100" => segment <="0110011";
when "0101" => segment <="1011011";
when "0110" => segment <="1011111";
when "0111" => segment <="1110000";
when "1000" => segment <="1111111";
when "1001" => segment <="1111011";
when others => segment <="0000000";
end case;

end process;
end behavioural;

TESTBENCH CODE :

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity testbench is
end entity;

architecture behaviour of testbench is


component decoder
port(
ABCD : in std_logic_vector(3 downto 0);
segment :out std_logic_vector(6 downto 0)
);
end component;

signal BCDin : std_logic_vector(3 downto 0);

signal Segment : std_logic_vector(6 downto 0);


begin
DUT : decoder port map(BCDin , Segment);

stim_proc: process
begin
BCDin <= "0000";
wait for 100 ns;
BCDin <= "0001";
wait for 100 ns;
BCDin <= "0010";
wait for 100 ns;
BCDin <= "0011";
wait for 100 ns;
BCDin <= "0100";
wait for 100 ns;
BCDin <= "0101";
wait for 100 ns;
BCDin <= "0110";
wait for 100 ns;
BCDin <= "0111";
wait for 100 ns;
BCDin <= "1000";
wait for 100 ns;
BCDin <= "1001";
wait for 100 ns;
assert false report "Test done." severity note;
wait;
end process;
end behaviour;
PROGRAM SCREENSHOT :

SIMULATION :

LOGISIM SCREENSHOT :
RESULT : THE PROGRAM AND THE SIMULATION OF BCD TO 7-
SEGMENT IS WORKING PROPERLY.

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