4

Fundamentals of Logic

Relay schematic Ladder logic program

Gate logic
LS1 LS2 SOL A B Y A
Y
LS1 LS2 SOL B Output
Inputs

Boolean equation: AB = Y

Chapter Objectives
After completing this chapter, you will be able to: This chapter gives an overview of digital logic
• Describe the binary concept and the functions
gates and illustrates how to duplicate this type
of gates of control on a PLC. Boolean algebra, which is a
• Draw the logic symbol, construct a truth table, and shorthand way of writing digital gate diagrams,
state the Boolean equation for the AND, OR, and NOT is discussed briefly. Some small hand-held pro-
functions grammers have digital logic keys, such as AND,
• Construct circuits from Boolean expressions and derive OR, and NOT, and are programmed using Bool-
Boolean equations for given logic circuits ean expressions.
• Convert relay ladder schematics to ladder logic
programs
• Develop elementary programs based on logic gate
functions
• Program instructions that perform logical operations

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4.1 The Binary Concept the outcome and a symbol that represents the operation.
For the purpose of this discussion, the outcome or out-
The PLC, like all digital equipment, operates on the binary put is called Y and the signal inputs are called A, B, C,
principle. The term binary principle refers to the idea that and so on. Also, binary 1 represents the presence of a
many things can be thought of as existing in only one of signal or the occurrence of some event, and binary 0
two states. These states are 1 and 0. The 1 and 0 can rep- represents the absence of the signal or nonoccurrence
resent ON or OFF, open or closed, true or false, high or of the event.
low, or any other two conditions. The key to the speed and
accuracy with which binary information can be processed The AND Function
is that there are only two states, each of which is distinctly The symbol drawn in Figure 4-3 is that of an AND
different. There is no in-between state so when informa- gate. An AND gate is a device with two or more in-
tion is processed the outcome is either yes or no. puts and one output. The AND gate output is 1 only
A logic gate is a circuit with several inputs but only if all inputs are 1. The AND truth table in Figure 4-3
one output that is activated by particular combinations of shows the resulting output from each of the possible
input conditions. The two-state binary concept, applied input combinations.
to gates, can be the basis for making decisions. The high Logic gate truth tables show each possible input to the
beam automobile lighting circuit of Figure 4-1 is an ex- gate or circuit and the resultant output depending upon the
ample of a logical AND decision. For this application, combination of the input(s).
the high beam light can be turned on only when the light Since logic gates are digital ICs (Integrated Circuits)
switch AND the high beam switch are closed. their input and output signals can be in only one of two
The dome light automobile circuit of Figure 4-2 is an possible digital states, i.e., logic 0 or logic 1. Thus, the
example of a logical OR decision. For this application, the logic state of the output of a logic gate depends on the
dome light will be turned on whenever the passenger door logic states of each of its individual inputs. Figure 4-4
switch OR the driver door switch is activated.
Logic is the ability to make decisions when one or
more different factors must be taken into account before AND truth table
an action is taken. This is the basis for the operation of Inputs Output
the PLC, where it is required for a device to operate when A
A B Y
Inputs Y
certain conditions have been met. B Output 0 0 0
0 1 0
Two-input AND 1 0 0
4.2 AND, OR, and NOT Functions gate symbol 1 1 1

The operations performed by digital equipment are Figure 4-3 AND gate.
based on three fundamental logic functions: AND, OR,
and NOT. Each function has a rule that will determine
0
A
Output (Y ) = 0
0
B
Light switch High beam
AND light 0
High beam A
switch Output (Y ) = 0 Truth table
Inputs Output 1
B A B Y
0 0 0
Figure 4-1 The logical AND. 0 1 0
1 1 0 0
A
Output (Y ) = 0 1 1 1
0
B
Passenger
door switch
Dome light 1
OR A
Driver
Output (Y ) = 1
door switch 1
Inputs Output B

Figure 4-2 The logical OR. Figure 4-4 AND logic gate digital signal states.

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 Hardwired circuit
Truth table Logic representation
SW-A SW-B
SW- A SW- B Light SW-A
Light
Open (0) Open (0) Off (0)
Light Open (0) Closed (1) Off (0)
Closed (1) Open (0) Off (0)
Closed (1) Closed (1) On (1) SW-B

Figure 4-5 AND logic gate operates similarly to control devices connected in series.

illustrates the four possible combinations of inputs for a 0

A
2-input AND gate. The basic rules that apply to an AND Output (Y ) = 0
0
gate are: B

• If all inputs are 1, the output will be 1. 0

A Truth table
• If any input is 0, the output will be 0.
1 Output (Y ) = 1 Inputs Output
The AND logic gate operates similarly to control B A B Y
devices connected in series, as illustrated in Figure 4-5. 0 0 0
1 0 1 1
The light will be on only when both switch A and switch A 1 0 1
B are closed. 0 Output (Y ) = 1 1 1 1
B

The OR Function 1
A
The symbol drawn in Figure 4-6 is that of an OR gate. An
1 Output (Y ) = 1
OR gate can have any number of inputs but only one out- B
put. The OR gate output is 1 if one or more inputs are 1.
The truth table in Figure 4-6 shows the resulting output Y Figure 4-7 OR logic gate digital signal states.
from each possible input combination.

Figure 4-7 illustrates the four possible combinations of

OR truth table
inputs for a 2-input OR gate. The basic rules that apply to
an OR gate are:
Inputs Output
A
Inputs Y
A B Y • If one or more inputs are 1, the output is 1.
Output 0 0 0
B
0 1 1 • If all inputs are 0, the output will be 0.
Two-input OR 1 0 1
1 1 1 The OR logic gate operates similarly to control devices
gate symbol
connected in parallel, as illustrated in Figure 4-8. The
Figure 4-6 OR gate. light will be on if switch A or switch B or both are closed.

Hardwired circuit

SW-A Truth table

Logic representation
SW- A SW- B Light SW-A
Light
SW-B Open (0) Open (0) Off (0)
Open (0) Closed (1) On (1)
Light Closed (1) Open (0) On (1)
Closed (1) Closed (1) On (1) SW-B

Figure 4-8 OR logic gate operates similarly to control devices connected in parallel.

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 NOT truth table normally closed pushbutton in series with a lamp.
A NOT A When the input pushbutton is not actuated, the output
A A (NOT A)
Input Output 0 1 lamp is ON. When the input pushbutton is actuated,
1 0 the output lamp switches OFF.
The NOT function is most often used in conjunction
Figure 4-9 NOT function.
with the AND or the OR gate. Figure 4-11 shows the NOT
function connected to one input of an AND gate for a low-
The NOT Function pressure indicator circuit. If the power is on (1) and the
The symbol drawn in Figure 4-9 is that of a NOT function. pressure switch is not closed (0), the warning light will
Unlike the AND and OR functions, the NOT function can be on (1).
have only one input. The NOT output is 1 if the input is 0. The NOT symbol placed at the output of an AND gate
The output is 0 if the input is 1. The result of the NOT opera- would invert the normal output result. An AND gate with
tion is always the inverse of the input, and the NOT function an inverted output is called a NAND gate. The NAND
is, therefore, called an inverter. The NOT function is often gate symbol and truth table are shown in Figure 4-12. The
depicted by using a bar across the top of the letter, indicat- NAND function is often used in integrated circuit logic
ing an inverted output. The small circle at the output of the arrays and can be used in programmable controllers to
inverter is referred to as a bubble and indicates that an inver- solve complex logic.
sion of the logical function has taken place. The same rule about inverting the normal output result
The logical NOT function can be performed on applies if a NOT symbol is placed at the output of the OR
a contact input simply by using a normally closed gate. The normal output is inverted, and the function is re-
instead of a normally open contact. Figure 4-10 shows ferred to as a NOR gate. The NOR gate symbol and truth
an example of the NOT function constructed using a table are shown in Figure 4-13.

Hardwired circuit

Truth table Logic representation

N.C. pushbutton
+ Pushbutton Light Light
Light Not pressed (0) On (1)
– Pressed (1) Off (0)

Single input

Figure 4-10 NOT function constructed using a normally closed pushbutton.

(Power on) NAND truth table

A= 1 Low-pressure Inputs Output
indicator on (1) A A B Y
Inputs Y
B Output 0 0 1
B= 0 (1) 0 1 1
(Pressure Two-input 1 0 1
NAND gate 1 1 0
switch open)
Truth table
Pressure Pressure
Figure 4-12 NAND gate symbol and truth table.
switch Power indicator
0 1 1
1 1 0
(Power on)
A=1 NOR truth table
Low-pressure
indicator off (0) Inputs Output
A A B Y
Inputs Y
B=1 (0) 0 0 1
B Output
(Pressure 0 1 0
switch closed) Two-input 1 0 0
NOR gate 1 1 0
Figure 4-11 NOT function is most often used in
conjunction with an AND gate. Figure 4-13 NOR gate symbol and truth table.

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 Truth table A A
Inputs Output AND AB OR A+B
B B
A B Y
A
Inputs Y 0 0 0
B Output 0 1 1 A A
1 0 1 NAND AB NOR A+B
1 1 0
B B

Figure 4.14 The XOR gate symbol and truth table.

A NOT A

The Exclusive-OR (XOR) Function Figure 4-16 Logic operators used singly to form logical
An often-used combination of gates is the exclusive-OR statements.
(XOR) function. The XOR gate symbol and truth table are
shown in Figure 4-14. The output of this circuit is HIGH the NOT operation. The Boolean equations are used to
only when one input or the other is HIGH, but not both. express the mathematical function of the logic gate.
The exclusive-OR gate is commonly used for the com- PLC digital systems may be designed using Boolean al-
parison of two binary numbers. gebra. Circuit functions are represented by Boolean equa-
tions. Figure 4-16 illustrates how logic operators AND,
NAND, OR, NOR, and NOT are used singly to form logi-
4.3 Boolean Algebra cal statements. Figure 4-17 illustrates how basic logic op-
erators are used in combination to form Boolean equations.
The mathematical study of the binary number system
An understanding of the technique of writing simpli-
and logic is called Boolean algebra. The purpose of this
fied Boolean equations for complex logical statements is
algebra is to provide a simple way of writing complicated
a useful tool when creating PLC control programs. Some
combinations of logic statements. There are many appli-
laws of Boolean algebra are different from those of ordi-
cations where Boolean algebra could be applied to solv-
nary algebra. These three basic laws illustrate the close
ing PLC programming problems.
comparison between Boolean algebra and ordinary alge-
Figure 4-15 summarizes the basic operators of Bool-
bra, as well as one major difference between the two:
ean algebra as they relate to the basic AND, OR, and
NOT functions. Inputs are represented by capital letters
A, B, C, and so on, and the output by a capital Y. The COMMUTATIVE LAW
dot (•), or no symbol, represents the AND operation,
an addition sign (+) represents the OR operation, the A+B=B+A
circle with an addition sign ∙ represents the__ exclusive-
A⋅B=B⋅A
OR operation, and a bar over the letter A represents

Logic symbol Logic statement Boolean equation Boolean notations

A Symbol Meaning
Y is 1 if Y=A• B
Y or and
A and B are 1 •
B Y = AB
+ or
A
Y is 1 if – not
Y Y= A+B
A or B is 1
B ° invert

= result in
Y is 1 if A is 0
A Y Y=A
Y is 0 if A is 1

Figure 4-15 Boolean algebra as related to AND, OR, and NOT functions.

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 A A
AB A+B
AND Y = AB + C OR Y = (A + B) C
B OR B AND
C C

A A
AB A+B
NAND Y = AB + C NOR Y = (A + B) C
B OR B AND
C C

Figure 4-17 Logic operators used in combination to form Boolean equations.

B
ASSOCIATIVE LAW
C
(A + B) + C = A + (B + C )
(A ⋅ B) ⋅ C = A ⋅ (B ⋅ C )
D

DISTRIBUTIVE LAW Y
A Output
A ⋅ (B + C) = (A ⋅ B) + (A ⋅ C ) Inputs
A + (B ⋅ C) = (A + B) ⋅ (A + C ) Figure 4-19 Logic gate circuit developed from the Boolean
This law holds true only in expression Y = A(BC + D).
Boolean algebra.

1 - OR gate with input C and output from previous

AND gate
Figure 4-19 shows a logic gate circuit developed from
4.4 Developing Logic Gate Circuits the Boolean expression Y = A(BC + D). The procedure
from Boolean Expressions is as follows:
As logic gate circuits become more complex, the need to Boolean expression: Y = A(BC + D)
express these circuits in Boolean form becomes greater. Gates required: (by inspection)
Figure 4-18 shows a logic gate circuit developed from the 1 - AND gate with inputs B and C
Boolean expression Y = AB + C. The procedure is as 1 - OR gate with inputs BC and D
follows: 1 - AND gate with input A and the output from the
Boolean expression: Y = AB + C OR gate
Gates required: (by inspection)
1 - AND gate with input A and B 4.5 Producing the Boolean Equation
for a Given Logic Gate Circuit
A simple logic gate is quite straightforward in its opera-
tion. However, by grouping these gates into combinations,
A it becomes more difficult to determine which combinations
of inputs will produce an output. The Boolean equation for
B the logic circuit of Figure 4-20 is determined as follows:
• The output of the OR gate is A + B
Y –
C Output • The output of the inverter is D
Inputs
• Based on the input combination applied to the AND
Figure 4-18 Logic gate circuit developed from the Boolean gate the Boolean equation for the circuit is Y = C
–
expression Y = AB + C. D (A +B)

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 A L1 START L2
A+B STOP OL
B M
C M
C Y
Output
D G
D M
Inputs

R
Figure 4-20 Determining the Boolean equation for a logic circuit.
M
Rail
A Rung
A AB
1
Figure 4-22 Motor stop/start relay ladder schematic.
Inputs Y relays and relay ladder schematics. Relay ladder sche-
Output
matics are universally used and understood in industry.
2 Figure 4-22 shows a typical relay ladder schematic of a
B
B AB
motor stop/start control station with pilot lights. The control
scheme is drawn between two vertical supply lines. All the
Figure 4-21 Determining the Boolean equation for a logic circuit. components are placed between these two lines, called rails
or legs, connecting the two power lines with what look like
The Boolean equation for the logic circuit of rungs of a ladder—thus the name, relay ladder schematic.
Figure 4-21 is determined as follows: Hardwired logic is fixed; it is changeable only by
– altering the way devices are electrically interconnected. In
• The output of AND gate 1 is AB
– contrast, programmable control is based on the basic logic
• The output of AND gate 2 is AB
functions, which are programmable and easily changed.
• Based on the combination of inputs applied to the
These functions (AND, OR, NOT) are used either singly
OR gate the Boolean equation for the circuit is
– – or in combinations to form instructions that will determine
Y = AB + AB
if a device is to be switched on or off. The form in which
4.6 Hardwired Logic versus these instructions are implemented to convey commands
to the PLC is called the language. The most common
Programmed Logic PLC language is ladder logic. Figure 4-23 shows a typi-
The term hardwired logic refers to logic control functions cal ladder logic program for the motor start/stop circuit.
that are determined by the way devices are electrically in- The instructions used are the relay equivalent of normally
terconnected. Hardwired logic can be implemented using open (NO) and normally closed (NC) contacts and coils.
Relay coil
equivalent
Input STOP START OL Output
M
L1 module module L2
Rung 1

STOP M
M
M G
START Rung 2

Relay contact
equivalent G

M R
OL
Rung 3
R
PROGRAM

Figure 4-23 Motor stop/start ladder logic program.

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 PLC contact symbolism is a simple way of expressing Because the PLC uses ladder logic diagrams, the con-
the control logic in terms of symbols. These symbols are version from any existing relay logic to programmed
basically the same as those used for representing hard- logic is simplified. Each rung is a combination of input
wired relay control circuits. A rung is the contact sym- conditions (symbols) connected from left to right, with
bolism required to control an output. Some PLCs allow the symbol that represents the output at the far right.
a rung to have multiple outputs while others allow only The symbols that represent the inputs are connected in
one output per rung. A complete ladder logic program then series, parallel, or some combination of the two to obtain
consists of several rungs, each of which controls an output. the desired logic. The following group of examples
In programmed logic all mechanical switch contacts are illustrates the relationship between the relay ladder sche-
represented by a software contact symbol and all electro- matic, the ladder logic program, and the equivalent logic
magnetic coils are represented by a software coil symbol. gate circuit.

Relay schematic Ladder logic program

Gate logic
LS1 LS2 SOL A B Y A
Y
LS1 LS2 SOL B Output
Inputs

Boolean equation: AB = Y

Example 4-1 Two limit switches connected in series and used to control a solenoid valve.

Relay schematic Ladder logic program

Gate logic
LS1 SOL A Y
A
LS1 Y
LS2 SOL
B Output
B
Inputs
LS2
Boolean equation: A + B = Y

Example 4-2 Two limit switches connected in parallel and used to control a solenoid valve.

Relay schematic Ladder logic program Gate logic

PL
LS1 PS A C Y A
G AB
LS1 PS PL B Y
LS2
B C Output
Inputs
LS2
Boolean equation: (A + B)C = Y

Example 4-3 Two limit switches connected in parallel with each other and in series with a pressure switch.

Relay schematic Ladder logic program Gate logic

PL A C Y A
LS1 FS1 A+B
R
LS1 FS1 B
PL
Y
LS2 FS2 B D C Output

LS2 FS1 D C+D

Inputs

Boolean equation: (A + B) (C + D) = Y

Example 4-4 Two limit switches connected in parallel with each other and in series with two sets of flow
switches (that are connected in parallel with each other), and used to control a pilot light.

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 Relay schematic Ladder logic program
Gate logic
Horn
LS1 LS2 A B Y
A
AB
LS1 LS2 Horn B Y
LS3
C C Output
Inputs
LS3
Boolean equation: (AB) + C = Y

Example 4-5 Two limit switches connected in series with each other and in parallel with a third limit
switch, and used to control a warning horn.

Gate logic

Relay schematic Ladder logic program A

PL A B Y
LS1 LS2 B
R Y
LS1 LS2 PL C Output
LS3 LS4
C D
D
LS3 LS4 Inputs

Boolean equation: (AB) + (CD) = Y

Example 4-6 Two limit switches connected in series with each other and in parallel with two other limit
switches (that are connected in series with each other), and used to control a pilot light.

Relay schematic Ladder logic program Gate logic

PB SOL A B Y
LS1 B
B
LS1 PB SOL Y
A Output
Inputs

Boolean equation: AB = Y

Example 4-7 One limit switch connected in series with a normally closed pushbutton and used to control
a solenoid valve. This circuit is programmed so that the output solenoid will be turned on when the limit switch
is closed and the pushbutton is not pushed.

Relay schematic Ladder logic program Gate logic

PB1
PB2 PL A B Y A
Y
PL B
A B Inputs
Y
PB1 PB2 Output

Boolean equation: AB + AB = Y
A+B=Y

Example 4-8 Exclusive-OR circuit. The output lamp of this circuit is ON only when pushbutton A or B is pressed, but not both.
This circuit has been programmed using only the normally open A and B pushbutton contacts as the inputs to the program.

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 Relay schematic Ladder logic program Gate logic
Stops Starts
PB1 Stops Starts
PB3 PB4 Motor M Starts
C D A
M
C D A A
PB3 PB4 PB1 Motor
PB2 B Stops
B
C M
B PB2
Motor M D

M Motor

Example 4-9 A motor control circuit with two start/stop buttons. When either start button is depressed, the motor runs. By use of
a seal-in contact, it continues to run when the start button is released. Either stop button stops the motor when it is depressed.

4.7 Programming Word Level Logic

Instructions MOV MVM AND OR XOR NOT CLR

Most PLCs provide word-level logic instructions as Compare Compute/Math Move/Logical File/Misc
part of their instruction set. Table 4-1 shows how to
select the correct word logic instruction for different Input A AND
situations. BITWISE AND
Figure 4-24 illustrates the operation of the AND in- Source A B3:5
1100110011001100
struction to perform a word-level AND operation using Source B B3:7
the bits in the two source addresses. This instruction tells 1111111100000000
Destination B3:10
the processor to perform an AND operation on B3:5 and 1100110000000000
B3:7 and to store the result in destination B3:10 when
input device A is true. The destination bits are a result of Source A 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0
B3:5
the logical AND operation.
Figure 4-25 illustrates the operation of a word-level Source B 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
B3:7
OR instruction, which ORs the data in Source A, bit by
Destination
bit, with the data in Source B and stores the result at the B3:10
1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0
destination address. The address of Source A is B3:1,
the address of Source B is B3:2, and the destination Figure 4-24 Word-level AND instruction.
address is B3:20. The instruction may be programmed
conditionally, with input instruction(s) preceding it, or
unconditionally, as shown, without any input instruc- MOV MVM AND OR XOR NOT CLR
tions preceding it.
Figure 4-26 illustrates the operation of a word-level Compare Compute/Math Move/Logical File/Misc

XOR instruction. In this example, data from input I:1.0

are compared, bit by bit, with data from input I:3.0. OR
BITWISE INCLUS OR
Source A B3:1

Table 4-1 Selecting Logic Instructions Source B B3:2

Destination B3:20
. . . use this
If you want to . . . instruction.
Source A 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0
Know when matching bits in two different AND B3:1
words are both ON
Know when one or both matching bits in two OR Source B 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
different words are ON B3:2

Know when one or the other bit of matching XOR Destination

1 1 1 1 1 1 1 1 1 1 0 0 1 1 0 0
bits in two different words is ON B3:20
Reverse the state of bits in a word NOT
Figure 4-25 Word-level OR instruction.

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 MOV MVM AND OR XOR NOT CLR

Compare Compute/Math Move/Logical File/Misc

XOR
BITWISE EXCLUS OR
Source A Ι:1.0

Source B Ι:3.0

Destination O:4.0 Rotating cam limit switch

Source A 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0
Ι:1.0

Source B 0 0 0 0 0 0 0 0 1 1 1 0 1 0 1 1
Ι:3.0

Destination
0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1
O:4.0

Figure 4-26 Word-level XOR instruction.

Source: Image Courtesy of Rockwell Automation, Inc.

Any mismatches energize the corresponding bit in word

O:4.0. As you can see, there is a 1 in every bit location in MOV MVM AND OR XOR NOT CLR
the destination corresponding to the bit locations where
Source  A and Source B are different, and a 0 in the Compare Compute/Math Move/Logical File/Misc
destination where Source A and Source B are the same.
The XOR is often used in diagnostics, where real-world
Input A NOT
inputs, such as rotary cam limit switches, are compared
with their desired states. NOT
Figure 4-27 illustrates the operation of a word-level
Source B3:9
NOT instruction. This instruction inverts the bits from the Destination B3:10
source word to the destination word. The bit pattern in
B3:10 is the result of the instruction being true and is the Source
0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0
inverse of the bit pattern in B3:9. B3:9
For 32-bit PLCs, such as the Allen-Bradley Control-
Logix controller, the source and destination may be a Destination
1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1
B3:10
SINT (one-byte integer), INT (two-byte integer), or DINT
(four-byte integer). Figure 4-27 Word-level NOT operation.

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