NAME: ISHWAR SANJAY PATIL PRN: 2032217

COURSE CODE: EE253U SUBJECT: DIGITAL ELECTRONIC AND

MICROPROCESSOR

EXPERIMENT NO: 1
AIM: To study the operation of logic gates, verification or Boolean laws and DE
Morgan’s theorem.
PART-1: To study the operation of logic gates

OBJECTIVE:
Identify various ICs and their specification
a. OR gate
b. AND gate
c. NAND gate
d. NOR gate
COMPONENTS REQUIRED:
 Breadboard.
 Connecting wires.
 IC 7400, IC 7408, IC 7432, IC 7406, IC 7402, IC 7404, IC 7486
THEORY:
The basic logic gates are the building blocks of more complex logic circuits. These
logic gates perform the basic Boolean functions, such as AND, OR, NAND, NOR,
Inversion, Exclusive-OR, Exclusive-NOR. Fig. below shows the circuit symbol,
Boolean function, and truth. It is seen from the Fig that each gate has one or two
binary inputs, A and B, and one binary output, C. The small circle on the output of
the circuit symbols designates the logic complement. The AND, OR, NAND, and
NOR gates can be extended to have more than two inputs. A gate can be extended
to have multiple inputs if the binary operation it represents is commutative and
associative.

These basic logic gates are implemented as small-scale integrated circuits (SSICs)
or as part of more complex medium scale (MSI) or very large-scale (VLSI)
Department Of Electrical Engineering
NAME: ISHWAR SANJAY PATIL PRN: 2032217
COURSE CODE: EE253U SUBJECT: DIGITAL ELECTRONIC AND
MICROPROCESSOR

integrated circuits. Digital IC gates are classified not only by their logic operation,
but also the specific logic- circuit family to which they belong. Each logic family
has its own basic electronic circuit upon which more complex digital circuits and
functions are developed. The following logic families are the most frequently used.
TTL-Transistor-transistor logic
ECL-Emitter-coupled logic
MOS-Metal-oxide semiconductor
CMOS -Complementary metal-oxide semiconductor
TTL and ECL are based upon bipolar transistors. TTL has a popularity among
logic families.
ECL is used only in systems requiring high-speed operation. MOS and CMOS, are
based on field effect transistors. They are widely used in large scale integrated
circuits because of their high component density and relatively low power
consumption. CMOS logic consumes far less power than MOS logic. There are
various commercial integrated circuit chips available. TTL ICs are usually
distinguished by numerical designation as the 5400 and 7400 series.

PROCEDURE:
1. Check the components for their working.
2. Insert the appropriate IC into the IC base.
3. Make connections as shown in the circuit diagram.
4. Provide the input data via the input switches and observe the output on output
LEDs

Department Of Electrical Engineering

NAME: ISHWAR SANJAY PATIL PRN: 2032217
COURSE CODE: EE253U SUBJECT: DIGITAL ELECTRONIC AND
MICROPROCESSOR

PART-2: Verification or Boolean laws and DE Morgan’s theorem.

Department Of Electrical Engineering

NAME: ISHWAR SANJAY PATIL PRN: 2032217
COURSE CODE: EE253U SUBJECT: DIGITAL ELECTRONIC AND
MICROPROCESSOR

OBJECTIVES:
 To verify the basic rules of Boolean algebra using logic gates
 To verify the two elements of DE Morgan’s Theorem
 To develop digital circuit building and troubleshooting skills
COMPONENTS NEEDED:
 One 7408 IC – quad two-input AND gate
 One 7432 IC – quad two-input OR gate
 One 7404 IC – hex inverter (NOT gate)
EQUIPMENT NEEDED:
 Knight electronics ML-2001 logic trainer
 Logic Probe
DISCUSSION:
BOOLEAN ALGEBRA IS SIMILAR to other mathematical topics in that there
are identities that can be used to simplify the work that needs to be done. The
basic identities of Boolean algebra are:

A+0=A A*0 = 0
A+1=1 A*1 = A
A+A=A AA = A
A + A’ = 1 AA’ = 0
A’’ = A A + A’B = A + B
A + AB = A

Since seeing is believing, this experiment will demonstrate all of the single
variable Boolean identities using AND, OR and NOT gates in this experiment.

Department Of Electrical Engineering

NAME: ISHWAR SANJAY PATIL PRN: 2032217
COURSE CODE: EE253U SUBJECT: DIGITAL ELECTRONIC AND
MICROPROCESSOR

Recall that the DE Morgan’s Theorem (Figure 1) simplifies the inverted product
(AB)’ or inverted sum (C + D)’ into a form that is more usable form for overall
simplification of a digital circuit. This theorem also provides a means of
converting to universal gate NAND and NOR. Both parts of DE Morgan’s
Theorem will be proven in this experiment.

PROCEDURE:
1. Boolean Identities
1.1. Design and draw the logic diagrams for the equivalent Boolean Identity
circuits in table 1 using the AND, OR and NOT gates. Include the pin numbers on

Department Of Electrical Engineering

NAME: ISHWAR SANJAY PATIL PRN: 2032217
COURSE CODE: EE253U SUBJECT: DIGITAL ELECTRONIC AND
MICROPROCESSOR

the gate inputs and outputs. Reference the datasheets to determine the pin out of
the chips.
1.2. Build each circuit from procedure 1.1 using the trainer. Test each circuits
output for both input states. Use the Level Switches to toggle the inputs.
1.3. Before turning on the power to the trainer review the wiring for errors. If at
any time during the experiment the results do not match the theoretical or
expected results use the logic probe to troubleshoot the circuit.
1.4. Start with all the input switches as LOW. Turn on the power to the trainer. If
at any time during the experiment the results do not match the theoretical or
expected results use the logic probe to troubleshoot the circuit.
1.5. Adjust the switches to the inputs listed in Table 1. Record the output states
(AND and AND-NOT) for each input combination.
1.6. Design and draw the logic diagram for a two-input NAND gate using the
7420 chip. The NAND gate in the 7420 chip has four inputs and only two inputs
will be used in the experiment. Be sure to draw the two unused input pins. What
will be done with these two unused pins? Include the pin numbers on the gate
inputs and outputs
1.7. Build the NAND gate circuit using the 7420 chip and the trainer. Use the
Level Switches to toggle the inputs. Reference the datasheets to determine the pin
out of the chips. Vcc for all the TTL chips will use the +5V power supply.
1.8. Before turning on the power to the trainer review the wiring for errors. If at
any time during the experiment the results do not match the theoretical or
expected results use the logic probe to troubleshoot the circuit.
1.9. Start with all the input switches as LOW. Turn on the power to the trainer.
1.10. Adjust the switches to the inputs listed in Table. Record the output state for
the NAND gate for each input combination.

Department Of Electrical Engineering