E9d6f Compal La-A691p r1.0 Schematics
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joe wiillsonE9d6f Compal La-A691p r1.0 Schematics
Uploaded by
joe wiillsonA B C D E
MODEL NAME :ZAW12
PCB NO : LA-A691P
1 BOM P/N : DA60012B000 LA-A691P M/B 1
DA40001G410 LS-9105P POWER BUTTON/B
DA40001FP10 LS-9102P USB/B
DA40001FQ10 LS-9103P TP BUTTON/B
DA40001FR10 LS-9104P ODD/B
2
Dell / Compal Confidential 2
Schematic Document
AMD FP2 Richland Processor with DDRIII + Bolton M3 FCH
AMD VGA Sun XT
2013-05-23
Rev: 1.0
3
X76@ : VRAM Group 3
46@ : for 46 level CH@ : Chelsea M2
R1@ : R1 P/N for PCB
@ : Nopop Component SE@ : Seymour M2
R3@ : R3 P/N for PCB
CONN@ : Connector Component TH@ : Thames-XT
THR1@ : Thames-XT R1 P/N
UMA@ : Only for UMA Mars@ : Mars Pro M2
THR3@ : Thames-XT R3 P/N
DIS@ : Only for Discrete A4R1@ : A4 APU-R1
CHR1@ : Chelsea-Pro R1 P/N
GCLK@ : Green CLK implemented A6R1@ : A6 APU-R1
CHR3@ : Chelsea-Pro R3 P/N
NGCLK@ : Non Green CLK implemented A8R1@ : A8 APU-R1
R@ : RTD2132-R
@3221: ALC 3221 A8@ : A8 APU Symbol
4
S@ : RTD2132-S 4
@3223 : ALC 3223 Hud@ : HUDSON-M3
KBBL@ : KeyBoard Backlight
EMC@ : EMC Parts Bol@ : BOLTON-M3
Security Classification Compal Secret Data Compal Electronics, Inc.
NEMC@ : EMC不 不不不 Issued Date 2012/09/11 Deciphered Date 2014/03/12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-9103P
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, July 10, 2013 Sheet 1 of 52
A B C D E
A B C D E
1 1
Memory BUS(DDRIII)
AMD FP2 APU Dual Channel DDRIII-DIMM X2
BANK 0, 1, 2, 3, 4 ,5 ,6 ,7
1.5V DDRIII 1333MT/s page 10,11
Richland LV Upgradeable to 4G Memory
BGA 813 pin 8GB Max
DP Port0, Port1
LVDS
Translator HDMI Conn. DP Port2 page 5,~9
RTD2136R page 19
page 17
x4 UMI Gen. 1 Port 0
SATA HDD Conn.
P.32
2.5GT/s per lane
LVDS Conn.
page 18
SATA Port 1
SATA ODD Conn.
P.32
2 2
USB 3.0 Port 2,3
PCI-E 2.0 USB 3.0 Conn. 1
Bolton M3 Port 1,2
USB 3.0 Conn. 2 P.33
GPP1 GPP0 USB2.0
uFCBGA-656 USB 2.0 Conn. 3
Daughter
WLAN/WiMAX LAN(10/100) Port 0,10
Board
Realtek 8105E USB 2.0 Conn. 4 P.34
page 35
page 29
page 12,~16 HD Audio Port 9
Digital Camera
P.18
RJ45 CONN Port 1
page 29 Mini Card (WLAN)
LPC BUS P.35
Port 6 Card Reader 3 in 1
SM BUS RTS5170 P.31 Socket
RTC CKT. ENE KBC
P.12 SPI ROM KB9012page
3
page 13
36
Analog Mic. 3
Power On/Off CKT. PS/2 Headphone Jack
P.38
Audio Codec Mic. Jack combo
Int.KBD Touch Pad
DC/DC Interface CKT. page 38 page 38 ALC3223 P.30
P.39 Int. Speaker R / L
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/09/11 Deciphered Date 2014/03/12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block diagram
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-9103P
Date: Wednesday, July 10, 2013 Sheet 2 of 52
A B C D E
A B C D E
Compal Confidential
Project Code : VAW03
File Name : LA-9103P
1 1
LS-9101P (PWR/B)
UE5
Lid (SA00003VQ00)
SW1 4 pin-Hot Bar
(SN100004Y00)
PBATT
Battery
JMINI
PWR-BTN FFC
4 pin MINI Card JLVDS
40 pin
PJPDC JKB
5 pin 30 pin
2 2
JTP
LS-9102P (USB/B)
6 pin
JHDMI HDMI
JPWR
JODD
4 pin JFAN
3 pin USB2.0 JUSB4
USB-DB FFC 8 pin
HDT 8 pin Hot Bar
JLAN RJ-45
JXDP
LA-9103P M/B JDB
8 pin
JUSB1 USB3.0 Top Side JHDD
RTC JRTC
Bottom Side
2 pin
JUSB2 USB3.0 (OAK 15")
3 3
JUSB3 USB2.0
JREAD
TP-MB FFC JSPK
6 pin 4 pin
JHP Card
HP Reader
Led1 Led3
Led2 Led4
TP-Module
TP-BTN FFC
4 4 pin 4
LS-9103P (TP-BTN/B)
4 pin
Hot Bar
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/09/11 Deciphered Date 2014/03/12 Title
SW2 SW3 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DaughterB block diagram
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9103P
Date: Wednesday, July 10, 2013 Sheet 3 of 52
A B C D E
A
Board ID Table for AD channel
Vcc 3.3V +/- 5% BOARD ID Table
Ra 100K +/- 5%
Board ID Rb V AD_BID min V AD_BID typ V AD_BID max EC AD3 Board ID PCB Revision USB PORT# DESTINATION
0 0 0 V 0 V 0.155 V 0x00-0x0C 0 0.1
1 8.2K +/- 5% 0.168 V 0.250 V 0.362 V 0x0D-0x1C 1 0.2 0 USB conn.3 DEBUG PORT
2 18K +/- 5% 0.375 V 0.503 V 0.621 V 0x1D-0x30 2 0.3
3 33K +/- 5% 0.634 V 0.819 V 0.945 V 0x31-0x49 3 1.0 SD028330280 1 MINI CARD (WLAN)
4 56K +/- 5% 0.958 V 1.185 V 1.359 V 0x4A-0x69 4
5 100K +/- 5% 1.372 V 1.650 V 1.838 V 0x6A-0x8E 5 2 USB conn.4
6 200K +/- 5% 1.851 V 2.200 V 2.420 V 0x8F-0xBB 6
7 NC 2.433 V 3.300 V 3.300 V 0xBC-0xFF 7 3 NC
4 NC
EC SM Bus1 address EC SM Bus2 address FCH
5 NC
Device Address HEX Device Address HEX
Smart Battery 000 1011 11h 0x16 ADM1032ARMZ 100 1101 4Dh 0x9A
6 Card Reader
Charger IC 000 1001 09h 0x12 SB-TSI 100 1100 4Ch 0x98
RTD2132 100 1010 4Ah 0x94
7 NC
GPU 100 0001 41h 0x82
SM Bus Controller 0 (FCH_SMB1 ~ FCH_SMB4, SMB_ALERT#) Symbol Note : 8 NC
Device
APU SIC/SID (FCH_SMB3)
Address HEX
: means Digital Ground 9 Camera
10 USB conn.2
SM Bus Controller 1 (FCH_SMB0)
: means Analog Ground
Device Address HEX 11 NC
DDR DIMM1 (FCH_SMB0) 1001-000xb 90 12 NC
DDR DIMM2 (FCH_SMB0) 1001-001xb 92
1 1
WLAN (FCH_SMB0)
13 USB conn.1
DIFFERENTIAL DESTINATION SATA DESTINATION PCI EXPRESS DESTINATION
CLKOUT_PCIE0 None SATA0 HDD Lane 1 10/100 LAN
CLKOUT_PCIE1 None SATA1 ODD Lane 2 MINI CARD (WLAN)
CLKOUT_PCIE2 10/100 LAN SATA2 None Lane 3 None
CLK CLKOUT_PCIE3 MINI CARD WLAN SATA3 None Lane 4 None
CLKOUT_PCIE4 None SATA4 None Lane 5 None
CLKOUT_PCIE5 None SATA5 None Lane 6 None
CLKOUT_PCIE6 None Lane 7 None
CLKOUT_PCIE7 None Lane 8 None
CLKOUT_PEG_B None
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/09/11 Deciphered Date 2014/03/12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9103P
Date: Wednesday, July 10, 2013 Sheet 4 of 52
A
A B C D E
21 PCIE_CRX_GTX_P[0..7] PCIE_CTX_GRX_P[0..7] 21
21 PCIE_CRX_GTX_N[0..7] PCIE_CTX_GRX_N[0..7] 21
U1A
PCIE_CRX_GTX_P0 AP1 AN1 PCIE_CTX_C_GRX_P0 CC48 DIS@ 1 2 0.1U_0402_16V7K PCIE_CTX_GRX_P0
PCIE_CRX_GTX_N0 AP2 P_GFX_RXP[0] P_GFX_TXP[0] AN2 PCIE_CTX_C_GRX_N0 CC49 DIS@ 1 2 0.1U_0402_16V7K PCIE_CTX_GRX_N0
PCIE_CRX_GTX_P1 AM1 P_GFX_RXN[0] P_GFX_TXN[0] AM4 PCIE_CTX_C_GRX_P1 CC50 DIS@ 1 2 0.1U_0402_16V7K PCIE_CTX_GRX_P1
PCIE_CRX_GTX_N1 AM2 P_GFX_RXP[1] P_GFX_TXP[1] AM3 PCIE_CTX_C_GRX_N1 CC51 DIS@ 1 2 0.1U_0402_16V7K PCIE_CTX_GRX_N1
PCIE_CRX_GTX_P2 AK3 P_GFX_RXN[1] P_GFX_TXN[1] AK2 PCIE_CTX_C_GRX_P2 CC52 DIS@ 1 2 0.1U_0402_16V7K PCIE_CTX_GRX_P2
PCIE_CRX_GTX_N2 AK4 P_GFX_RXP[2] P_GFX_TXP[2] AK1 PCIE_CTX_C_GRX_N2 CC53 DIS@ 1 2 0.1U_0402_16V7K PCIE_CTX_GRX_N2
1 PCIE_CRX_GTX_P3 AJ1 P_GFX_RXN[2] P_GFX_TXN[2] AH1 PCIE_CTX_C_GRX_P3 CC54 DIS@ 1 2 0.1U_0402_16V7K PCIE_CTX_GRX_P3 1
PCIE_CRX_GTX_N3 AJ2 P_GFX_RXP[3] P_GFX_TXP[3] AH2 PCIE_CTX_C_GRX_N3 CC55 DIS@ 1 2 0.1U_0402_16V7K PCIE_CTX_GRX_N3
PCIE_CRX_GTX_P4 AH4 P_GFX_RXN[3] P_GFX_TXN[3] AF3 PCIE_CTX_C_GRX_P4 CC56 DIS@ 1 2 0.1U_0402_16V7K PCIE_CTX_GRX_P4
PCIE_CRX_GTX_N4 AH3 P_GFX_RXP[4] P_GFX_TXP[4] AF4 PCIE_CTX_C_GRX_N4 CC57 DIS@ 1 2 0.1U_0402_16V7K PCIE_CTX_GRX_N4
PCIE_CRX_GTX_P5 AF2 P_GFX_RXN[4] P_GFX_TXN[4] AE1 PCIE_CTX_C_GRX_P5 CC58 DIS@ 1 2 0.1U_0402_16V7K PCIE_CTX_GRX_P5
PCIE_CRX_GTX_N5 AF1 P_GFX_RXP[5] P_GFX_TXP[5] AE2 PCIE_CTX_C_GRX_N5 CC59 DIS@ 1 2 0.1U_0402_16V7K PCIE_CTX_GRX_N5
PCIE_CRX_GTX_P6 AD1 P_GFX_RXN[5] P_GFX_TXN[5] AD4 PCIE_CTX_C_GRX_P6 CC60 DIS@ 1 2 0.1U_0402_16V7K PCIE_CTX_GRX_P6
PCIE_CRX_GTX_N6 AD2 P_GFX_RXP[6] P_GFX_TXP[6] AD3 PCIE_CTX_C_GRX_N6 CC61 DIS@ 1 2 0.1U_0402_16V7K PCIE_CTX_GRX_N6
PCIE_CRX_GTX_P7 AB3 P_GFX_RXN[6] P_GFX_TXN[6] AB2 PCIE_CTX_C_GRX_P7 CC62 DIS@ 1 2 0.1U_0402_16V7K PCIE_CTX_GRX_P7
GRAPHICS
PCIE_CRX_GTX_N7 AB4 P_GFX_RXP[7] P_GFX_TXP[7] AB1 PCIE_CTX_C_GRX_N7 CC63 DIS@ 1 2 0.1U_0402_16V7K PCIE_CTX_GRX_N7
AA1 P_GFX_RXN[7] P_GFX_TXN[7] Y1
AA2 P_GFX_RXP[8] P_GFX_TXP[8] Y2
Y4 P_GFX_RXN[8] P_GFX_TXN[8] V3
Y3 P_GFX_RXP[9] P_GFX_TXP[9] V4
V2 P_GFX_RXN[9] P_GFX_TXN[9] U1
V1 P_GFX_RXP[10] P_GFX_TXP[10] U2
T1 P_GFX_RXN[10] P_GFX_TXN[10] T4
T2 P_GFX_RXP[11] P_GFX_TXP[11] T3
P3 P_GFX_RXN[11] P_GFX_TXN[11] P2
P4 P_GFX_RXP[12] P_GFX_TXP[12] P1
N1 P_GFX_RXN[12] P_GFX_TXN[12] M1 U1 A4R1@ U1 A4R3@
N2 P_GFX_RXP[13] P_GFX_TXP[13] M2
M4 P_GFX_RXN[13] P_GFX_TXN[13] K3
M3 P_GFX_RXP[14] P_GFX_TXP[14] K4
K2 P_GFX_RXN[14] P_GFX_TXN[14] J1
SA00006KC0L SA00006KC1L
K1 P_GFX_RXP[15] P_GFX_TXP[15] J2
P_GFX_RXN[15] P_GFX_TXN[15]
A4 SERIES AM5145SHE23HL 2G BGA 813P A4 SERIES AM5145SHE23HL 2G BGA 813P A31 !
AH5 AG7 PCIE_CTX_C_DRX_P0 CC80 1 2 0.1U_0402_16V7K
29 PCIE_CRX_DTX_P0 AH6 P_GPP_RXP[0] P_GPP_TXP[0] AG8 PCIE_CTX_C_DRX_N0 1 2 0.1U_0402_16V7K PCIE_CTX_DRX_P0 29
LAN CC81 LAN U1 A6R1@ U1 A6R3@
29 PCIE_CRX_DTX_N0 AG5 P_GPP_RXN[0] P_GPP_TXN[0] AE7 1 2 CC82 PCIE_CTX_DRX_N0 29
PCIE_FTX_C_DRX_P1 0.1U_0402_16V7K
35 PCIE_FRX_DTX_P1 AG6 P_GPP_RXP[1] P_GPP_TXP[1] AE8 PCIE_FTX_C_DRX_N1 0.1U_0402_16V7K 1 2 CC83 PCIE_FTX_DRX_P1 35
WLAN 35 PCIE_FRX_DTX_N1 P_GPP_RXN[1] P_GPP_TXN[1] PCIE_FTX_DRX_N1 35 WLAN
AE6 AD7
2 AE5 P_GPP_RXP[2] P_GPP_TXP[2] AD8
SA00006KD0L SA00006KD1L 2
AD6 P_GPP_RXN[2] P_GPP_TXN[2] AB6
GPP
AD5 P_GPP_RXP[3] P_GPP_TXP[3] AB5
P_GPP_RXN[3] P_GPP_TXN[3] Move from FCH for WLAN/EXP PCIE I/F. 20110819 A6 SERIES AM5345SHE23HL 2.2G BGA813 A6 SERIES AM5345SHE23HL 2.2G BGA813
AM10 AN6 UMI_TXP0_C CC84 1 2 0.1U_0402_16V7K U1 A8R1@ U1 A8R3@
12 UMI_RXP0 AN10 P_UMI_RXP[0] P_UMI_TXP[0] AM6 UMI_TXN0_C 1 2 UMI_TXP0 12
CC85 0.1U_0402_16V7K
12 UMI_RXN0 AN8 P_UMI_RXN[0] P_UMI_TXN[0] AP6 1 2 UMI_TXN0 12
UMI_TXP1_C CC86 0.1U_0402_16V7K
12 UMI_RXP1 AM8 P_UMI_RXP[1] P_UMI_TXP[1] AR6 1 2 UMI_TXP1 12
UMI_TXN1_C CC87 0.1U_0402_16V7K SA00006KE0L SA00006KE1L
12 UMI_RXN1 AP8 P_UMI_RXN[1] P_UMI_TXN[1] AP4 UMI_TXP2_C 1 2 UMI_TXN1 12
CC88 0.1U_0402_16V7K
12 UMI_RXP2 AR8 P_UMI_RXP[2] P_UMI_TXP[2] AR4 UMI_TXN2_C 1 2 UMI_TXP2 12
CC89 0.1U_0402_16V7K
12 UMI_RXN2 AR7 P_UMI_RXN[2] P_UMI_TXN[2] AP3 UMI_TXP3_C 1 2 UMI_TXN2 12
CC90 0.1U_0402_16V7K A8 SERIES AM5545SHE44HL 1.7G BGA813 A8 SERIES AM5545SHE44HL 1.7G BGA 813P A31 !
12 UMI_RXP3 AP7 P_UMI_RXP[3] P_UMI_TXP[3] AR3 1 2 UMI_TXP3 12
UMI_TXN3_C CC91 0.1U_0402_16V7K
UMI
12 UMI_RXN3 P_UMI_RXN[3] P_UMI_TXN[3] UMI_TXN3 12
U1 A10R1@
1 2 P_ZVDDP AR11 AP11 P_ZVSS 1 2
+1.2VS P_ZVDDP P_ZVSS
RC1 196_0402_1% RC2 196_0402_1%
TRINITY-A8-SERIES_BGA813 SA00006KH0L
A8@ A10 SERIES AM5745SIE44HL 2.1G BGA 813P
ZZZ R1@
PCB 11R LA-A691P REV0 M/B 4
DA60012B000
ZZZ1 R3@
3 3
PCB VAW03 LA-9103P LS-9101P/9102P/9103P GOLD A31 !
DAZ0XO00101
Power Sequence of APU
+1.5V
+2.5VS Group A
+1.5VS
+APU_CORE
Group B
4 +APU_CORE_NB 4
+1.2VS
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/09/11 Deciphered Date 2014/03/12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
FP2 PCIE/UMI
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9103P
Date: Wednesday, July 10, 2013 Sheet 5 of 52
A B C D E
A B C D E
1 1
U1B
10 DDRA_SMA[15..0] DDRA_SMA0 AA28 F15 DDRA_SDQ0 DDRA_SDQ[63..0] 10 U1C
R29 MA_ADD[0] MA_DATA[0] E15 11 DDRB_SMA[15..0] Y33 C16 DDRB_SDQ[63..0] 11
DDRA_SMA1 DDRA_SDQ1 DDRB_SMA0 DDRB_SDQ0
DDRA_SMA2 T30 MA_ADD[1] MA_DATA[1] H19 DDRA_SDQ2 DDRB_SMA1 R32 MB_ADD[0] MB_DATA[0] B17 DDRB_SDQ1
DDRA_SMA3 R28 MA_ADD[2] MA_DATA[2] F19 DDRA_SDQ3 DDRB_SMA2 T31 MB_ADD[1] MB_DATA[1] B20 DDRB_SDQ2
DDRA_SMA4 R26 MA_ADD[3] MA_DATA[3] E14 DDRA_SDQ4 DDRB_SMA3 P33 MB_ADD[2] MB_DATA[2] C20 DDRB_SDQ3
DDRA_SMA5 P26 MA_ADD[4] MA_DATA[4] H15 DDRA_SDQ5 DDRB_SMA4 P32 MB_ADD[3] MB_DATA[3] A16 DDRB_SDQ4
DDRA_SMA6 P27 MA_ADD[5] MA_DATA[5] E17 DDRA_SDQ6 DDRB_SMA5 P31 MB_ADD[4] MB_DATA[4] B16 DDRB_SDQ5
DDRA_SMA7 P30 MA_ADD[6] MA_DATA[6] D18 DDRA_SDQ7 DDRB_SMA6 N32 MB_ADD[5] MB_DATA[5] B19 DDRB_SDQ6
DDRA_SMA8 P29 MA_ADD[7] MA_DATA[7] DDRB_SMA7 M33 MB_ADD[6] MB_DATA[6] A20 DDRB_SDQ7
DDRA_SMA9 M28 MA_ADD[8] G20 DDRA_SDQ8 DDRB_SMA8 M32 MB_ADD[7] MB_DATA[7]
DDRA_SMA10 AB26 MA_ADD[9] MA_DATA[8] E20 DDRA_SDQ9 DDRB_SMA9 L32 MB_ADD[8] B22 DDRB_SDQ8
DDRA_SMA11 M26 MA_ADD[10] MA_DATA[9] H23 DDRA_SDQ10 DDRB_SMA10 AB31 MB_ADD[9] MB_DATA[8] C22 DDRB_SDQ9
DDRA_SMA12 M29 MA_ADD[11] MA_DATA[10] G23 DDRA_SDQ11 DDRB_SMA11 M31 MB_ADD[10] MB_DATA[9] A26 DDRB_SDQ10
DDRA_SMA13 AE27 MA_ADD[12] MA_DATA[11] E19 DDRA_SDQ12 DDRB_SMA12 K32 MB_ADD[11] MB_DATA[10] B26 DDRB_SDQ11
DDRA_SMA14 L26 MA_ADD[13] MA_DATA[12] H20 DDRA_SDQ13 DDRB_SMA13 AF33 MB_ADD[12] MB_DATA[11] B21 DDRB_SDQ12
DDRA_SMA15 L27 MA_ADD[14] MA_DATA[13] E22 DDRA_SDQ14 DDRB_SMA14 K33 MB_ADD[13] MB_DATA[12] A22 DDRB_SDQ13
MA_ADD[15] MA_DATA[14] D22 DDRA_SDQ15 DDRB_SMA15 J32 MB_ADD[14] MB_DATA[13] C24 DDRB_SDQ14
DDRA_SBS0# AB27 MA_DATA[15] MB_ADD[15] MB_DATA[14] B25 DDRB_SDQ15
10 DDRA_SBS0# DDRA_SBS1# AA29 MA_BANK[0] H25 DDRA_SDQ16 DDRB_SBS0# AB33 MB_DATA[15]
10 DDRA_SBS1# DDRA_SBS2# M30 MA_BANK[1] MA_DATA[16] F25 DDRA_SDQ17 11 DDRB_SBS0# DDRB_SBS1# AA32 MB_BANK[0] A28 DDRB_SDQ16
10 DDRA_SBS2# MA_BANK[2] MA_DATA[17] D28 DDRA_SDQ18 11 DDRB_SBS1# DDRB_SBS2# K31 MB_BANK[1] MB_DATA[16] B28 DDRB_SDQ17
10 DDRA_SDM[7..0] DDRA_SDM0 D16 MA_DATA[18] D29 DDRA_SDQ19 11 DDRB_SBS2# MB_BANK[2] MB_DATA[17] B31 DDRB_SDQ18
DDRA_SDM1 D20 MA_DM[0] MA_DATA[19] E23 DDRA_SDQ20 11 DDRB_SDM[7..0] DDRB_SDM0 C18 MB_DATA[18] A32 DDRB_SDQ19
DDRA_SDM2 E25 MA_DM[1] MA_DATA[20] D24 DDRA_SDQ21 DDRB_SDM1 B23 MB_DM[0] MB_DATA[19] C26 DDRB_SDQ20
DDRA_SDM3 F30 MA_DM[2] MA_DATA[21] D26 DDRA_SDQ22 DDRB_SDM2 C28 MB_DM[1] MB_DATA[20] B27 DDRB_SDQ21
DDRA_SDM4 AK29 MA_DM[3] MA_DATA[22] D27 DDRA_SDQ23 DDRB_SDM3 D31 MB_DM[2] MB_DATA[21] A30 DDRB_SDQ22
DDRA_SDM5 AL25 MA_DM[4] MA_DATA[23] DDRB_SDM4 AM31 MB_DM[3] MB_DATA[22] C30 DDRB_SDQ23
DDRA_SDM6 AM20 MA_DM[5] G28 DDRA_SDQ24 DDRB_SDM5 AN30 MB_DM[4] MB_DATA[23]
2 DDRA_SDM7 AM16 MA_DM[6] MA_DATA[24] G29 DDRA_SDQ25 DDRB_SDM6 AR24 MB_DM[5] B33 DDRB_SDQ24 2
MA_DM[7] MA_DATA[25] H27 DDRA_SDQ26 DDRB_SDM7 AN18 MB_DM[6] MB_DATA[24] C32 DDRB_SDQ25
DDRA_SDQS0 G17 MA_DATA[26] J29 DDRA_SDQ27 MB_DM[7] MB_DATA[25] F33 DDRB_SDQ26
10 DDRA_SDQS0 DDRA_SDQS0# H17 MA_DQS_H[0] MA_DATA[27] E28 DDRA_SDQ28 DDRB_SDQS0 B18 MB_DATA[26] F32 DDRB_SDQ27
10 DDRA_SDQS0# DDRA_SDQS1 F22 MA_DQS_L[0] MA_DATA[28] F27 DDRA_SDQ29 11 DDRB_SDQS0 DDRB_SDQS0# A18 MB_DQS_H[0] MB_DATA[27] B32 DDRB_SDQ28
10 DDRA_SDQS1 DDRA_SDQS1# G22 MA_DQS_H[1] MA_DATA[29] H29 DDRA_SDQ30 11 DDRB_SDQS0# DDRB_SDQS1 B24 MB_DQS_L[0] MB_DATA[28] C31 DDRB_SDQ29
10 DDRA_SDQS1# E26 MA_DQS_L[1] MA_DATA[30] H28 11 DDRB_SDQS1 A24 MB_DQS_H[1] MB_DATA[29] E32
DDRA_SDQS2 DDRA_SDQ31 DDRB_SDQS1# DDRB_SDQ30
10 DDRA_SDQS2 F26 MA_DQS_H[2] MA_DATA[31] 11 DDRB_SDQS1# B30 MB_DQS_L[1] MB_DATA[30] F31
DDRA_SDQS2# DDRB_SDQS2 DDRB_SDQ31
10 DDRA_SDQS2# DDRA_SDQS3 H30 MA_DQS_L[2] AH29 DDRA_SDQ32 11 DDRB_SDQS2 DDRB_SDQS2# B29 MB_DQS_H[2] MB_DATA[31]
10 DDRA_SDQS3 DDRA_SDQS3# G30 MA_DQS_H[3] MA_DATA[32] AJ30 DDRA_SDQ33 11 DDRB_SDQS2# DDRB_SDQS3 D32 MB_DQS_L[2] AK32 DDRB_SDQ32
10 DDRA_SDQS3# DDRA_SDQS4 AL29 MA_DQS_L[3] MA_DATA[33] AM28 DDRA_SDQ34 11 DDRB_SDQS3 DDRB_SDQS3# D33 MB_DQS_H[3] MB_DATA[32] AL32 DDRB_SDQ33
10 DDRA_SDQS4 AL30 MA_DQS_H[4] MA_DATA[34] AM27 11 DDRB_SDQS3# AM32 MB_DQS_L[3] MB_DATA[33] AP32
DDRA_SDQS4# DDRA_SDQ35 DDRB_SDQS4 DDRB_SDQ34
10 DDRA_SDQS4# AH25 MA_DQS_L[4] MA_DATA[35] AH27 11 DDRB_SDQS4 AM33 MB_DQS_H[4] MB_DATA[34] AN31
DDRA_SDQS5 DDRA_SDQ36 DDRB_SDQS4# DDRB_SDQ35
10 DDRA_SDQS5 DDRA_SDQS5# AJ25 MA_DQS_H[5] MA_DATA[36] AH28 DDRA_SDQ37 11 DDRB_SDQS4# DDRB_SDQS5 AN28 MB_DQS_L[4] MB_DATA[35] AK31 DDRB_SDQ36
10 DDRA_SDQS5# DDRA_SDQS6 AK20 MA_DQS_L[5] MA_DATA[37] AJ29 DDRA_SDQ38 11 DDRB_SDQS5 DDRB_SDQS5# AP29 MB_DQS_H[5] MB_DATA[36] AK33 DDRB_SDQ37
10 DDRA_SDQS6 DDRA_SDQS6# AL20 MA_DQS_H[6] MA_DATA[38] AK27 DDRA_SDQ39 11 DDRB_SDQS5# DDRB_SDQS6 AP23 MB_DQS_L[5] MB_DATA[37] AN32 DDRB_SDQ38
10 DDRA_SDQS6# AK15 MA_DQS_L[6] MA_DATA[39] 11 DDRB_SDQS6 AP24 MB_DQS_H[6] MB_DATA[38] AP33
DDRA_SDQS7 DDRB_SDQS6# DDRB_SDQ39
10 DDRA_SDQS7 AL15 MA_DQS_H[7] AK26 11 DDRB_SDQS6# AR18 MB_DQS_L[6] MB_DATA[39]
DDRA_SDQS7# DDRA_SDQ40 DDRB_SDQS7
10 DDRA_SDQS7# MA_DQS_L[7] MA_DATA[40] AJ26 11 DDRB_SDQS7 AP18 MB_DQS_H[7] AP30
DDRA_SDQ41 DDRB_SDQS7# DDRB_SDQ40
DDRA_CLK0 W29 MA_DATA[41] AK23 DDRA_SDQ42 11 DDRB_SDQS7# MB_DQS_L[7] MB_DATA[40] AR30 DDRB_SDQ41
10 DDRA_CLK0 DDRA_CLK0# Y30 MA_CLK_H[0] MA_DATA[42] AJ23 DDRA_SDQ43 DDRB_CLK0 W32 MB_DATA[41] AP27 DDRB_SDQ42
10 DDRA_CLK0# W26 MA_CLK_L[0] MA_DATA[43] AM26 11 DDRB_CLK0 Y32 MB_CLK_H[0] MB_DATA[42] AN26
DDRA_CLK1 DDRA_SDQ44 DDRB_CLK0# DDRB_SDQ43
10 DDRA_CLK1 DDRA_CLK1# W27 MA_CLK_H[1] MA_DATA[44] AL26 DDRA_SDQ45 11 DDRB_CLK0# DDRB_CLK1 V33 MB_CLK_L[0] MB_DATA[43] AR32 DDRB_SDQ44
10 DDRA_CLK1# U29 MA_CLK_L[1] MA_DATA[45] AM24 11 DDRB_CLK1 V32 MB_CLK_H[1] MB_DATA[44] AP31
DDRA_SDQ46 DDRB_CLK1# DDRB_SDQ45
V30 MA_CLK_H[2] MA_DATA[46] AL23 DDRA_SDQ47 11 DDRB_CLK1# U32 MB_CLK_L[1] MB_DATA[45] AR28 DDRB_SDQ46
U26 MA_CLK_L[2] MA_DATA[47] V31 MB_CLK_H[2] MB_DATA[46] AP28 DDRB_SDQ47
U27 MA_CLK_H[3] AK22 DDRA_SDQ48 T33 MB_CLK_L[2] MB_DATA[47]
MA_CLK_L[3] MA_DATA[48] AH22 DDRA_SDQ49 T32 MB_CLK_H[3] AP25 DDRB_SDQ48
DDRA_CKE0 L29 MA_DATA[49] AK19 DDRA_SDQ50 MB_CLK_L[3] MB_DATA[48] AN24 DDRB_SDQ49
10 DDRA_CKE0 DDRA_CKE1 K30 MA_CKE[0] MA_DATA[50] AH19 DDRA_SDQ51 DDRB_CKE0 H32 MB_DATA[49] AR22 DDRB_SDQ50
10 DDRA_CKE1 MA_CKE[1] MA_DATA[51] AM22 DDRA_SDQ52 11 DDRB_CKE0 DDRB_CKE1 H33 MB_CKE[0] MB_DATA[50] AP21 DDRB_SDQ51
DDRA_ODT0 AD30 MA_DATA[52] AL22 DDRA_SDQ53 11 DDRB_CKE1 MB_CKE[1] MB_DATA[51] AP26 DDRB_SDQ52
3 10 DDRA_ODT0 AG28 MA0_ODT[0] MA_DATA[53] AJ20 AF31 MB_DATA[52] AR26 3
DDRA_ODT1 DDRA_SDQ54 DDRB_ODT0 DDRB_SDQ53
10 DDRA_ODT1 AE26 MA0_ODT[1] MA_DATA[54] AL19 11 DDRB_ODT0 AH31 MB0_ODT[0] MB_DATA[53] AN22
DDRA_SDQ55 DDRB_ODT1 DDRB_SDQ54
AG29 MA1_ODT[0] MA_DATA[55] 11 DDRB_ODT1 AE32 MB0_ODT[1] MB_DATA[54] AP22 DDRB_SDQ55
MA1_ODT[1] AK17 DDRA_SDQ56 AH33 MB1_ODT[0] MB_DATA[55]
DDRA_SCS0# AD26 MA_DATA[56] AJ17 DDRA_SDQ57 MB1_ODT[1] AR20 DDRB_SDQ56
10 DDRA_SCS0# DDRA_SCS1# AE29 MA0_CS_L[0] MA_DATA[57] AK14 DDRA_SDQ58 DDRB_SCS0# AD31 MB_DATA[56] AP19 DDRB_SDQ57
10 DDRA_SCS1# AB30 MA0_CS_L[1] MA_DATA[58] AH14 DDRA_SDQ59 11 DDRB_SCS0# DDRB_SCS1# AF32 MB0_CS_L[0] MB_DATA[57] AP16 DDRB_SDQ58
AF30 MA1_CS_L[0] MA_DATA[59] AM18 DDRA_SDQ60 11 DDRB_SCS1# AC32 MB0_CS_L[1] MB_DATA[58] AR16 DDRB_SDQ59
MA1_CS_L[1] MA_DATA[60] AL17 DDRA_SDQ61 AG32 MB1_CS_L[0] MB_DATA[59] AN20 DDRB_SDQ60
DDRA_SRAS# AB29 MA_DATA[61] AH15 DDRA_SDQ62 MB1_CS_L[1] MB_DATA[60] AP20 DDRB_SDQ61
10 DDRA_SRAS# DDRA_SCAS# AD29 MA_RAS_L MA_DATA[62] AL14 DDRA_SDQ63 DDRB_SRAS# AB32 MB_DATA[61] AP17 DDRB_SDQ62
10 DDRA_SCAS# AD28 MA_CAS_L MA_DATA[63] 11 DDRB_SRAS# AD32 MB_RAS_L MB_DATA[62] AN16
DDRA_SWE# DDRB_SCAS# DDRB_SDQ63
10 DDRA_SWE# MA_WE_L 11 DDRB_SCAS# DDRB_SWE# AD33 MB_CAS_L MB_DATA[63]
MEM_MA_RST# J28 11 DDRB_SWE# MB_WE_L
10 MEM_MA_RST# AA26 MA_RESET_L H31
MEM_MA_EVENT# MEM_MB_RST#
10 MEM_MA_EVENT# MA_EVENT_L 11 MEM_MB_RST# MEM_MB_EVENT# Y31 MB_RESET_L
G32 11 MEM_MB_EVENT# MB_EVENT_L
+MEM_VREF M_VREF
TRINITY-A8-SERIES_BGA813
1 2 M_ZVDDIO AJ32
+1.5V M_ZVDDIO
RC3 39.2_0402_1%
TRINITY-A8-SERIES_BGA813 A8@
Place them close to APU within 1"
15mil
A8@
EVENT# pull high 0.75V reference voltage +1.5V
+1.5V
2
4 RC4 4
1K_0402_1%
RC5 1 2 1K_0402_5% MEM_MA_EVENT# 15mil
1
RC6 1 2 1K_0402_5% MEM_MB_EVENT# +MEM_VREF
2
1 2
RC7
1K_0402_1% CC92 CC93 Security Classification Compal Secret Data Compal Electronics, Inc.
1000P_0402_50V7K 0.1U_0402_16V7K Issued Date 2012/09/11 2014/03/12 Title
2 1 Deciphered Date
FP2 DDRIII Memory I/F
1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9103P
Date: Wednesday, July 10, 2013 Sheet 6 of 52
A B C D E
A B C D E
Place near APU Place near APU If not used, pins are left unconnected (DG ref.)
U1D
20101111
CC94 1 2 0.1U_0402_16V7K DP0_TXP0 H2 M5 DP0_AUXP CC96 1 2 0.1U_0402_16V7K To LVDS
17 DP0_TXP0_C DP0_TXP[0] DP0_AUXP DP0_AUXP_C 17
CC95 1 2 0.1U_0402_16V7K DP0_TXN0 H1 M6 DP0_AUXN CC97 1 2 0.1U_0402_16V7K
Translater DP0_AUXP RC8 2 1 1.8K_0402_5%
17 DP0_TXN0_C DP0_TXN[0] DP0_AUXN DP0_AUXN_C 17
LVDS
CC98 1 2 0.1U_0402_16V7K DP0_TXP1 H3 L5 DP0_AUXN RC9 2 1 1.8K_0402_5%
DISPLAY PORT 0
17 DP0_TXP1_C DP0_TXP[1] DP1_AUXP
CC99 1 2 0.1U_0402_16V7K DP0_TXN1 H4 L6
17 DP0_TXN1_C DP0_TXN[1] DP1_AUXN
F4 J5
F3 DP0_TXP[2] DP2_AUXP J6 HDMI_CLK 19
DP0_TXN[2] DP2_AUXN HDMI_DATA 19 To HDMI
F1 P5
F2 DP0_TXP[3] DP3_AUXP P6
DP0_TXN[3] DP3_AUXN
DISPLAY PORT MISC.
E2 R5
1 E1 DP1_TXP[0] DP4_AUXP R6 +1.5V +3VS 1
DP1_TXN[0] DP4_AUXN Asserted as an input to force the
D4 U5 processor into the HTC-active state
DISPLAY PORT 1
D3 DP1_TXP[1] DP5_AUXP U6
DP1_TXN[1] DP5_AUXN
1
D1 M7 RC12 RC13
D2 DP1_TXP[2] DP0_HPD L7 LVDS_HPD_R 9
1K_0402_5% 10K_0402_5%
DP1_TXN[2] DP1_HPD J7
C1 DP2_HPD P7 HDMI_DET 19 Q1 DEL
2
C2 DP1_TXP[3] DP3_HPD R7 2011/11/28
DP1_TXN[3] DP4_HPD U7
DP2_TXP0 CV62 2 1 0.1U_0402_16V7K DP2_TXP0_R B2 DP5_HPD
19 DP2_TXP0 DP2_TXP[0]
DP2_TXN0 CV60 2 1 0.1U_0402_16V7K DP2_TXN0_R A2 C6 APU_PROCHOT#
19 DP2_TXN0 DP2_TXN[0] DP_BLON D7 12,42,49 APU_PROCHOT# H_PROCHOT#_EC 36
DP2_TXP1 CV64 2 1 0.1U_0402_16V7K DP2_TXP1_R B3 DP_DIGON A6 2N7002K_SOT23-3
DISPLAY PORT 2
19 DP2_TXP1 DP2_TXP[1] DP_VARY_BL DP_INT_PWM 9
1
DP2_TXN1 CV61 2 1 0.1U_0402_16V7K DP2_TXN1_R A3 D QC1
19 DP2_TXN1 DP2_TXN[1] B6 DP_AUX_ZVSS RC14 1 2 150_0402_1% 2
DP2_TXP2 CV66 2 1 0.1U_0402_16V7K DP2_TXP2_R B4 DP_AUX_ZVSS
HDMI 19 DP2_TXP2 DP2_TXP[2]
G
DP2_TXN2 CV63 2 1 0.1U_0402_16V7K DP2_TXN2_R A4 AL6 S
19 DP2_TXN2
3
DP2_TXN[2] TEST6 Y23
TEST9 T85
DP2_TXP3 CV65 2 1 0.1U_0402_16V7K DP2_TXP3_R B5 V23
T86
19 DP2_TXP3 DP2_TXP[3] TEST10
DP2_TXN3 CV59 2 1 0.1U_0402_16V7K DP2_TXN3_R A5 G9
T87 RPC1
19 DP2_TXN3 DP2_TXN[3] TEST14 F9 APU_TEST24 1 8
TEST15 T88 +1.5V
AL9 E9 APU_TEST18 2 7 Indicates to the FCH that a thermal trip
12 APU_CLK CLKIN_H TEST16 T89
AK9 G8 APU_TEST20 3 6 THERMTRIP shutdown has occurred. Its assertion will cause the FCH to
12 APU_CLK# CLKIN_L TEST17 T90
F12 APU_TEST18 APU_TEST19 4 5 temperature: 125 degree transition the system to S5 immediately
TEST
AL7 TEST18 E12 APU_TEST19
CLK
12 APU_DISP_CLK DISP_CLKIN_H TEST19
1
AK7 F14 APU_TEST20 1K_0804_8P4R_5%
12 APU_DISP_CLK# DISP_CLKIN_L TEST20 G12 APU_TEST24 RC21 RC19
E5 TEST24 AJ8 TEST25_H RC20 1 2 510_0402_1% 1K_0402_5% 10K_0402_5%
49 APU_SVC E6 SVC TEST25_H AH8 TEST25_L RC22 1 2 510_0402_1%
+1.2VS
49 APU_SVD SVD TEST25_L G14
T91
2 2
TEST28_H
SER.
2 D6 H14 2
49 APU_SVT SVT TEST28_L T92
B
V25
TEST30_H T110
APU_SIC AJ11 Y25 QC2
SIC TEST30_L T109
E
APU_SID AH11 AH32 APU_TEST31 RC23 1 2 39.2_0402_1% APU_THERMTRIP# 3 1
SID TEST31 H_THERMTRIP# 14
C
R25
TEST32_H T112
AK11 T25 TEST35 change to PU for MMBT3904_NL_SOT23-3 1
12 APU_RST# RESET_L TEST32_L T111
1000P_0402_50V7K
CC156
AH9 AL5 APU_TEST35 RC24 1 2 300_0402_5% HDMI can not output
12,49 APU_PWRGD PWROK TEST35 +1.5V
RC25 1 @ 2 300_0402_5% 20110126 NEMC@
APU_PROCHOT# AL12 AP10
CTRL
APU_THERMTRIP# AK5 PROCHOT_L DMAACTIVE_L ALLOW_STOP 12 2
ALERT_L AR10 THERMTRIP_L T23
T126 ALERT_L TEST4 T93
R23
TEST5 T94
APU_TDI E11
APU_TDO G11 TDI
APU_TCK H12 TDO
APU_TMS F11 TCK JTAG L8
APU_TRST# H11 TMS RSVD P8
APU_DBRDY E8 TRST_L RSVD AH12
APU_DBREQ# E7 DBRDY RSVD RSVD AJ12
DBREQ_L RSVD AK12
G6 RSVD
49 APU_VDD_SEN_L H6 VSS_SENSE
H5 VDDP_SENSE
49 APU_VDDNB_SEN_H G7 VDDNB_SENSE
SENSE
Route as differential VDDIO_SENSE
G5
with VSS_SENSE 49 APU_VDD_SEN_H H7 VDD_SENSE
VDDR_SENSE
TRINITY-A8-SERIES_BGA813
A8@
3 3
+3VS
CPU TSI interface level shift
1
RC36
+1.5V +5VS 31.6K_0402_1%
BSH111, the Vgs is: +1.5V HDT Debug conn
2
1
CC100 min = 0.4V
RC29 1 2 1K_0402_5% APU_SVT R17 1 2 0.1U_0402_16V7K +1.5V
@ 10K_0402_5% Max = 1.3V JHDT1
RC30 1 2 1K_0402_5% APU_SVC 1 2 APU_TCK
1 2
2
@ 1 RC37 2
2
RC38 1 2 1K_0402_5% APU_SVD RC32 3 4 APU_TMS
@ 30K_0402_1% 3 4 +1.5V
1K_0402_5%
RC34 1 2 1K_0402_5% APU_SIC 5 6 APU_TDI
5 6 RPC2
1
RC35 1 2 1K_0402_5% APU_SID @ 7 8 APU_TDO APU_TCK 1 8
7 8
2
2
G
Q78A QC4 @ ShortPad APU_TMS 2 7
RC40 1 2 1K_0402_5% ALERT_L ShortPad APU_TRST# RC41 1 2 0_0402_5% 9 10 APU_PWRGD APU_TDI 3 6
APU_SID 6 1 APU_SID_R 3 1 EC_SMB_DA 1 2 9 10 APU_DBREQ# 4 5
EC_SMB_DA2 22,36 To EC
RC43 1 2 1K_0402_5% ALLOW_STOP RC42 0_0402_5% RC44 1 2 10K_0402_5% 11 12 APU_RST#
S
DMN66D0LDW-7_SOT363-6 11 12 1K_0804_8P4R_5%
To FCH
+1.5VS MESS138-G 1N SOT23-3 RC46 1 2 10K_0402_5% 13 14 APU_DBRDY
Allow_STOP leakage issue RC45 13 14
RC47 1 2 10K_0402_5% 15 16 APU_DBREQ#
RC49 1 @ 2 1K_0402_5% SID_G 15 16
17 18
@
RC50 1ShortPad 2 0_0402_5% APU_TEST19
RC51 1 2 300_0402_5% APU_RST# 17 18
5
2
G
QC5 @ To EC 19 20 RC53 1ShortPad 2 0_0402_5% APU_TEST18
RC54 1 2 300_0402_5% APU_PWRGD ShortPad 19 20
4 APU_SIC 3 4 APU_SIC_R 3 1 EC_SMB_CK 1 2
@ 4
EC_SMB_CK2 22,36 To FCH
RC52 0_0402_5%
S
+3VS SAMTE_ASP-136446-07-B
Q78B MESS138-G 1N SOT23-3 CONN@
DMN66D0LDW-7_SOT363-6 RC55
RC56 1 2 4.7K_0402_5% HDMI_CLK
RC57 1 2 4.7K_0402_5% HDMI_DATA Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/09/11 Deciphered Date 2014/03/12 Title
Aux signal are re-configured as I2C signals for DDC. APU AUX pin are 3.3V tolerant THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
FP2 DDRIII Memory I/F
Size Document Number Rev
Default follow PAWGX setting for pull-high resistor value AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9103P
Date: Wednesday, July 10, 2013 Sheet 7 of 52
A B C D E
A B C D E
Power Name Consumption
VDD U1F
+APU_CORE 60A A17 Y11
A19 VSS VSS Y12
VDDNB VSS VSS
+APU_CORE A21 Y14
+APU_CORE_NB 29A A23 VSS VSS Y15
A25 VSS VSS Y17
VDDIO VSS VSS
A27 Y19
+1.5V 3.2A VSS VSS
CC101
0.22U_0402_6.3V6K
CC108
0.22U_0402_6.3V6K
CC102
0.01U_0402_16V7K
CC103
0.01U_0402_16V7K
CC109
0.01U_0402_16V7K
CC110
180P_0402_50V8J
CC104
180P_0402_50V8J
A29 Y20
A31 VSS VSS Y22
VDDP / VDDR 1 1 1 1 1 1 1 VSS VSS
+APU_CORE +APU_CORE B1 AA4
+1.2VS 5A / 3.5A U1E C3 VSS VSS AA5
J12 V17 C4 VSS VSS AB7
VDDA VDD VDD 2 2 2 2 2 2 2 VSS VSS
1 J14 V19 C33 AB8 1
+2.5VS 0.5A J15 VDD VDD V20 D5 VSS VSS AC1
J17 VDD VDD V22 D9 VSS VSS AC2
J19 VDD VDD W8 D11 VSS VSS AC4
J20 VDD VDD AA8 D13 VSS VSS AC9
J22 VDD VDD AA9 D15 VSS VSS AC11
M11 VDD VDD AA11 +APU_CORE_NB D17 VSS VSS AC12
M12 VDD VDD AA12 D19 VSS VSS AC14
M14 VDD VDD AA14 D21 VSS VSS AC15
M15 VDD VDD AA15 D23 VSS VSS AC17
VDD VDD VSS VSS
CC105
0.22U_0402_6.3V6K
CC106
0.22U_0402_6.3V6K
CC111
180P_0402_50V8J
CC107
180P_0402_50V8J
CC112
180P_0402_50V8J
M17 AA17 D25 AC19
M19 VDD VDD AA19 D30 VSS VSS AC20
VDD VDD 1 1 1 1 1 VSS VSS
M20 AA20 E4 AC22
M22 VDD VDD AA22 E27 VSS VSS AC23
R8 VDD VDD AD9 E29 VSS VSS AC25
R9 VDD VDD AD11 2 2 2 2 2 E30 VSS VSS AE4
R11 VDD VDD AD12 E33 VSS VSS AF9
R12 VDD VDD AD14 F5 VSS VSS AF11
R14 VDD VDD AD15 F6 VSS VSS AF12
R15 VDD VDD AD17 F7 VSS VSS AF14
R17 VDD VDD AD19 F8 VSS VSS AF15
R19 VDD VDD AD20 +1.5V F17 VSS VSS AF17
R20 VDD VDD AD22 F20 VSS VSS AF19
R22 VDD VDD AG12 F23 VSS VSS AF20
U8 VDD VDD AG14 F28 VSS VSS AF22
VDD VDD VSS VSS
CC113
22U_0603_6.3V6M
CC114
22U_0603_6.3V6M
CC115
22U_0603_6.3V6M
CC116
22U_0603_6.3V6M
CC117
22U_0603_6.3V6M
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
CC122
0.22U_0402_6.3V6K
CC123
0.22U_0402_6.3V6K
CC124
0.22U_0402_6.3V6K
CC125
0.22U_0402_6.3V6K
CC126
0.22U_0402_6.3V6K
CC127
0.22U_0402_6.3V6K
CC128
180P_0402_50V8J
V9 AG15 F29 AF23
VDD VDD VSS VSS
CC118
CC119
CC120
CC121
V11 AG17 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 G1 AF25
V12 VDD VDD AG19 G2 VSS VSS AG1
V14 VDD VDD AG20 @ G4 VSS VSS AG2
V15 VDD VDD AG22 G15 VSS VSS AG4
VDD VDD 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 G19 VSS VSS AG9
G25 VSS VSS AG11
2 A7 B11 G26 VSS VSS AG26 2
+APU_CORE_NB VDDNB VDDNB +APU_CORE_NB VSS VSS
A8 B12 G27 AH7
A9 VDDNB VDDNB B13 G33 VSS VSS AH17
A10 VDDNB VDDNB B14 H8 VSS VSS AH20
A11 VDDNB VDDNB B15 H9 VSS VSS AH23
A12 VDDNB VDDNB C8 H22 VSS VSS AH26
A13 VDDNB VDDNB C10 H26 VSS VSS AH30
VDDNB VDDNB
across VDDIO and VSS VSS VSS
A14 C12 +1.5V J4 AJ4
VDDNB VDDNB +APU_CORE_NB
split VSS VSS
A15 C14 J8 AJ5
B7 VDDNB VDDNB D8 J9 VSS VSS AJ6
B8 VDDNB VDDNB D10 J11 VSS VSS AJ7
VDDNB VDDNB VSS VSS
CC130
0.22U_0402_6.3V6K
CC131
0.22U_0402_6.3V6K
CC132
180P_0402_50V8J
CC133
180P_0402_50V8J
B9 D12 J23 AJ9
VDDNB VDDNB VSS VSS
CC151
22U_0603_6.3V6M
CC149
22U_0603_6.3V6M
CC152
22U_0603_6.3V6M
CC150
22U_0603_6.3V6M
CC153
180P_0402_50V8J
B10 D14 1 1 1 1 J25 AJ14
VDDNB VDDNB J26 VSS VSS AJ15
1 1 1 1 1 VSS VSS
M9 J27 AJ19
VDDNB_CAP +APU_CORE_NB VSS VSS
N9 J30 AJ22
VDDNB_CAP 2 2 2 2 K9 VSS VSS AJ27
J33 W33 2 2 2 2 2 K11 VSS VSS AJ28
+1.5V VDDIO VDDIO +1.5V VSS VSS
K23 AA23 K12 AJ33
K25 VDDIO VDDIO AA25 K14 VSS VSS AK6
L28 VDDIO VDDIO AA27 K15 VSS VSS AK8
L30 VDDIO VDDIO AA30 K17 VSS VSS AK25
L33 VDDIO VDDIO AA33 K19 VSS VSS AK28
M27 VDDIO VDDIO AB28 K20 VSS VSS AK30
N23 VDDIO VDDIO AC30 K22 VSS VSS AL1
N25 VDDIO VDDIO AC33 L1 VSS VSS AL2
N30 VDDIO VDDIO AD23 L2 VSS VSS AL4
N33 VDDIO VDDIO AD25 L4 VSS VSS AL8
P28 VDDIO VDDIO AD27 M8 VSS VSS AL11
R27 VDDIO VDDIO AE28 M23 VSS VSS AL27
R30 VDDIO VDDIO AE30 M25 VSS VSS AL28
R33 VDDIO VDDIO AE33 N4 VSS VSS AL33
3 U28 VDDIO VDDIO AG23 +1.5V N11 VSS VSS AM5 3
U30 VDDIO VDDIO AG25 N12 VSS VSS AM7
U33 VDDIO VDDIO AG27 N14 VSS VSS AM9
W28 VDDIO VDDIO AG30 N15 VSS VSS AM11
+1.2VS W30 VDDIO VDDIO AG33 N17 VSS VSS AM15
VDDP decoupling VDDIO VDDIO VSS VSS
CC129
330U_2.5V_M
1 N19 AM17
AM12 AN14 N20 VSS VSS AM19
AN12 VDDP VDDR AP14 + N22 VSS VSS AM21
VDDP VDDR VSS VSS
180P_0402_50V8J
180P_0402_50V8J
AP12 AP15 VDDR decoupling R1 AM23
VDDP VDDR VSS VSS
CC134
CC135
CC136
0.22U_0402_6.3V6K
CC137
0.22U_0402_6.3V6K
AP13 AR14 R2 AM25
AR12 VDDP VDDR AR15 2 R4 VSS VSS AM29
1 1 1 1 VDDP VDDR +1.2VS VSS VSS
AR13 T9 AM30
VDDP VSS VSS
CC138
180P_0402_50V8J
CC139
180P_0402_50V8J
CC140
1000P_0402_50V7K
CC141
1000P_0402_50V7K
CC142
1000P_0402_50V7K
CC143
1000P_0402_50V7K
CC144
0.22U_0402_6.3V6K
CC145
0.22U_0402_6.3V6K
T11 AN3
AA6 T12 VSS VSS AN4
2 2 2 2 VDDP_CAP 1 1 1 1 1 1 1 1 VSS VSS
AA7 T14 AN33
VDDP_CAP T15 VSS VSS AP5
AM13 T17 VSS VSS AP9
AM14 VDDA 2 2 2 @2 @2 @2 2 2 T19 VSS VSS AR2
VDDA T20 VSS VSS AR5
+VDDP_CAP T22 VSS VSS AR9
TRINITY-A8-SERIES_BGA813 (330uF_6.3V_4.2L_ESR17m)*1=(SF000002Z00) U4 VSS VSS AR17
W1 VSS VSS AR19
W2 VSS VSS AR21
A8@ VSS VSS
CC155
22U_0603_6.3V6M
CC154
22U_0603_6.3V6M
W4 AR23
+VDDP_CAP VSS VSS
1 1 W5 AR25
W6 VSS VSS AR27
W7 VSS VSS AR29
Y9 VSS VSS AR31
2 2 Demo Board Capacitor VSS VSS
TRINITY-A8-SERIES_BGA813
APU_CORE CORE_NB CORE_NB_CAP VDDIO_SUS
4 22uF x 10 22uF x 2 22uF x 2 (CPU side) A8@
4
+2.5VS L60 40mil 0.22uF x 2 10uF x 1 180pF x 1 22uF x 4
FBMA-L11-201209-221LMA30T_0805
2 1 +VDDA 0.01uF x 3 0.22uF x 2 4.7uF x 4
180pF x 2 180pF x 3 0.22uF x 6 +2(split)
CC146
3300P_0402_50V7K
CC147
0.22U_0402_6.3V6K
CC148
4.7U_0402_6.3V6M
1 1 180pF x 1 + 2(split)
1
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/09/11 Deciphered Date 2014/03/12 Title
2
2 2
VDDP VDDR VDDA VDDIO_SUS FP2 DDRIII Memory I/F
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
0.22uF x 2 0.22uF x 2 4.7uF x 1 (DIMM x2) Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom 1.0
180pF x 2 1nF x 4 0.22uF x 1 100uF x 2 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9103P
180pF x 2 3.3nF x 1 0.1uF x 12 Date: Wednesday, July 10, 2013 Sheet 8 of 52
A B C D E
5 4 3 2 1
D D
HPD Panel PWM +3VS
1
RC58 RC59
47K_0402_5% 4.7K_0402_5%
2
APU_INVT_PWM 17
Translator HPD
1
D
2
G QC6
MMBT3904_NL_SOT23-3
@ S 2N7002K_SOT23-3
3
1
C ShortPad QC8 C C
1 2 1 2 2
17 LVDS_HPD LVDS_HPD_R 7 7 DP_INT_PWM
RC67 0_0402_5% RC62 2.2K_0402_5% B
E
3
1
RC64
4.7K_0402_5%
2
B B
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/09/11 Deciphered Date 2014/03/12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
FP2 DDRIII Memory I/F
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9103P
Date: Wednesday, July 10, 2013 Sheet 9 of 52
5 4 3 2 1
A B C D E
+1.5V +1.5V
+VREF_DQ
JDIMM1 CONN@
1 2
3 VREF_DQ VSS 4 DDRA_SDQ4 DDRA_SDQ[0..63]
DDRA_SDQ0 5 VSS DQ4 6 DDRA_SDQ5 DDRA_SDQ[0..63] 6
DDRA_SDQ1 7 DQ0 DQ5 8 DDRA_SDM[0..7]
DQ1 VSS DDRA_SDM[0..7] 6
9 10 DDRA_SDQS0#
DDRA_SDM0 11 VSS DQS0# 12 DDRA_SDQS0 DDRA_SDQS0# 6 DDRA_SMA[0..15]
DM0 DQS0 DDRA_SDQS0 6 DDRA_SMA[0..15] 6
13 14
DDRA_SDQ2 15 VSS VSS 16 DDRA_SDQ6
DDRA_SDQ3 17 DQ2 DQ6 18 DDRA_SDQ7
19 DQ3 DQ7 20
1 DDRA_SDQ8 21 VSS VSS 22 DDRA_SDQ12 1
DDRA_SDQ9 23 DQ8 DQ12 24 DDRA_SDQ13
25 DQ9 DQ13 26
DDRA_SDQS1# 27 VSS VSS 28 DDRA_SDM1
6 DDRA_SDQS1# DDRA_SDQS1 29 DQS1# DM1 30 MEM_MA_RST#
6 DDRA_SDQS1 31 DQS1 RESET# 32 MEM_MA_RST# 6
DDRA_SDQ10 33 VSS VSS 34 DDRA_SDQ14
DDRA_SDQ11 35 DQ10 DQ14 36 DDRA_SDQ15 +1.5V
Place near DIMM1
37 DQ11 DQ15 38
DDRA_SDQ16 39 VSS VSS 40 DDRA_SDQ20 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K
DDRA_SDQ17 41 DQ16 DQ20 42 DDRA_SDQ21
DQ17 DQ21 2 2 2 2 2 2 2 2 2 2
43 44
DDRA_SDQS2# 45 VSS VSS 46 DDRA_SDM2 C120 C121 C122 C123 C124 C125 C168 C169 C172 C173
6 DDRA_SDQS2# 47 DQS2# DM2 48
DDRA_SDQS2
6 DDRA_SDQS2 49 DQS2 VSS 50 DDRA_SDQ22 1 1 1 1 1 1 1 1 1 1
DDRA_SDQ18 51 VSS DQ22 52 DDRA_SDQ23 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K
DDRA_SDQ19 53 DQ18 DQ23 54
55 DQ19 VSS 56 DDRA_SDQ28 NewAdd 20110818
DDRA_SDQ24 57 VSS DQ28 58 DDRA_SDQ29
DDRA_SDQ25 59 DQ24 DQ29 60
61 DQ25 VSS 62 DDRA_SDQS3#
DDRA_SDM3 63 VSS DQS3# 64 DDRA_SDQS3 DDRA_SDQS3# 6
65 DM3 DQS3 66 DDRA_SDQS3 6
DDRA_SDQ26 67 VSS VSS 68 DDRA_SDQ30
DDRA_SDQ27 69 DQ26 DQ30 70 DDRA_SDQ31
71 DQ27 DQ31 72
VSS VSS
DDRA_CKE0 73 74 DDRA_CKE1
6 DDRA_CKE0 75 CKE0 CKE1 76 DDRA_CKE1 6
77 VDD VDD 78 DDRA_SMA15
DDRA_SBS2# 79 NC A15 80 DDRA_SMA14
2 6 DDRA_SBS2# 81 BA2 A14 82 2
DDRA_SMA12 83 VDD VDD 84 DDRA_SMA11
DDRA_SMA9 85 A12/BC# A11 86 DDRA_SMA7
87 A9 A7 88
DDRA_SMA8 89 VDD VDD 90 DDRA_SMA6
DDRA_SMA5 91 A8 A6 92 DDRA_SMA4
93 A5 A4 94
DDRA_SMA3 95 VDD VDD 96 DDRA_SMA2
DDRA_SMA1 97 A3 A2 98 DDRA_SMA0
99 A1 A0 100 +1.5V +1.5V
DDRA_CLK0 101 VDD VDD 102 DDRA_CLK1
6 DDRA_CLK0 103 CK0 CK1 104 DDRA_CLK1 6
DDRA_CLK0# DDRA_CLK1#
6 DDRA_CLK0# CK0# CK1# DDRA_CLK1# 6
2
105 106
DDRA_SMA10 107 VDD VDD 108 DDRA_SBS1# R80 R81
DDRA_SBS0# 109 A10/AP BA1 110 DDRA_SRAS# DDRA_SBS1# 6 +VREF_DQ +VREF_CA
1K_0402_1% 1K_0402_1%
6 DDRA_SBS0# 111 BA0 RAS# 112 DDRA_SRAS# 6
DDRA_SWE# 113 VDD VDD 114 DDRA_SCS0#
DDRA_SCS0# 6 15mil 15mil
1
6 DDRA_SWE# DDRA_SCAS# 115 WE# S0# 116 DDRA_ODT0 +VREF_DQ +VREF_CA
6 DDRA_SCAS# 117 CAS# ODT0 118 DDRA_ODT0 6
VDD VDD
1000P_0402_50V7K
1000P_0402_50V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
DDRA_SMA13 119 120 DDRA_ODT1
DDRA_SCS1# 121 A13 ODT1 122 DDRA_ODT1 6
6 DDRA_SCS1# S1# NC
2
123 124 1 1 1 1
125 VDD VDD 126 C126 C129 R82 C127 C128 R83
TEST VREF_CA +VREF_CA
127 128 1K_0402_1% 1K_0402_1%
DDRA_SDQ32 129 VSS VSS 130 DDRA_SDQ36
DDRA_SDQ33 131 DQ32 DQ36 132 DDRA_SDQ37 2 2 2 2
1
133 DQ33 DQ37 134
DDRA_SDQS4# 135 VSS VSS 136 DDRA_SDM4
6 DDRA_SDQS4# DDRA_SDQS4 137 DQS4# DM4 138
6 DDRA_SDQS4 139 DQS4 VSS 140 DDRA_SDQ38
DDRA_SDQ34 141 VSS DQ38 142 DDRA_SDQ39
DDRA_SDQ35 143 DQ34 DQ39 144
3 145 DQ35 VSS 146 DDRA_SDQ44 3
DDRA_SDQ40 147 VSS DQ44 148 DDRA_SDQ45
DDRA_SDQ41 149 DQ40 DQ45 150
151 DQ41 VSS 152 DDRA_SDQS5#
153 VSS DQS5# 154 DDRA_SDQS5# 6
DDRA_SDM5 DDRA_SDQS5
155 DM5 DQS5 156 DDRA_SDQS5 6
DDRA_SDQ42 157 VSS VSS 158 DDRA_SDQ46
DDRA_SDQ43 159 DQ42 DQ46 160 DDRA_SDQ47
161 DQ43 DQ47 162
DDRA_SDQ48 163 VSS VSS 164 DDRA_SDQ52
DDRA_SDQ49 165 DQ48 DQ52 166 DDRA_SDQ53
167 DQ49 DQ53 168
DDRA_SDQS6# 169 VSS VSS 170 DDRA_SDM6
6 DDRA_SDQS6# DDRA_SDQS6 171 DQS6# DM6 172
6 DDRA_SDQS6 173 DQS6 VSS 174 DDRA_SDQ54
DDRA_SDQ50 175 VSS DQ54 176 DDRA_SDQ55
DDRA_SDQ51 177 DQ50 DQ55 178
179 DQ51 VSS 180 DDRA_SDQ60
DDRA_SDQ56 181 VSS DQ60 182 DDRA_SDQ61
DDRA_SDQ57 183 DQ56 DQ61 184
185 DQ57 VSS 186 DDRA_SDQS7#
187 VSS DQS7# 188 DDRA_SDQS7# 6
DDRA_SDM7 DDRA_SDQS7
189 DM7 DQS7 190 DDRA_SDQS7 6
DDRA_SDQ58 191 VSS VSS 192 DDRA_SDQ62
DDRA_SDQ59 193 DQ58 DQ62 194 DDRA_SDQ63
ShortPad 195 DQ59 DQ63 196
1 2 197 VSS VSS 198 MEM_MA_EVENT#
SA0 EVENT# MEM_MA_EVENT# 6
R84 0_0402_5% 199 200
+3VS 201 VDDSPD SDA 202 FCH_SDATA0 11,14,35
203 SA1 SCL 204 FCH_SCLK0 11,14,35
@ VTT VTT +0.75VS
1
1
205 206
4 C131 ShortPad R85 207 GND1 GND2 208 4
0.1U_0402_16V7K 0_0402_5% BOSS1 BOSS2
2
2
@ LCN_DAN06-K4406-0103
Security Classification Compal Secret Data Compal Electronics, Inc.
2012/09/11 2014/03/12 Title
Reverse H:4mm Issued Date Deciphered Date
DDRIII SO-DIMM 1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
<Address: 00> AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9103P
Date: Wednesday, July 10, 2013 Sheet 10 of 52
A B C D E
A B C D E
+1.5V +1.5V
+VREF_DQ JDIMM2 CONN@
1 2
3 VREF_DQ VSS1 4 DDRB_SDQ4 DDRB_SDQ[0..63]
DDRB_SDQ0 5 VSS2 DQ4 6 DDRB_SDQ5 DDRB_SDQ[0..63] 6
DDRB_SDQ1 7 DQ0 DQ5 8 DDRB_SDM[0..7]
DQ1 VSS3 DDRB_SDM[0..7] 6
9 10 DDRB_SDQS0#
DDRB_SDM0 11 VSS4 DQS#0 12 DDRB_SDQS0 DDRB_SDQS0# 6 DDRB_SMA[0..15]
DM0 DQS0 DDRB_SDQS0 6 DDRB_SMA[0..15] 6
13 14
DDRB_SDQ2 15 VSS5 VSS6 16 DDRB_SDQ6
DDRB_SDQ3 17 DQ2 DQ6 18 DDRB_SDQ7
19 DQ3 DQ7 20
1 DDRB_SDQ8 21 VSS7 VSS8 22 DDRB_SDQ12 +VREF_DQ 1
DDRB_SDQ9 23 DQ8 DQ12 24 DDRB_SDQ13 +VREF_CA
25 DQ9 DQ13 26
DDRB_SDQS1# 27 VSS9 VSS10 28 DDRB_SDM1
15mil 15mil
6 DDRB_SDQS1# DDRB_SDQS1 29 DQS#1 DM1 30 MEM_MB_RST# +VREF_DQ +VREF_CA
6 DDRB_SDQS1 31 DQS1 RESET# 32 MEM_MB_RST# 6
VSS11 VSS12
1000P_0402_50V7K
1000P_0402_50V7K
DDRB_SDQ10 33 34 DDRB_SDQ14
DQ10 DQ14
0.1U_0402_16V7K
0.1U_0402_16V7K
DDRB_SDQ11 35 36 DDRB_SDQ15
37 DQ11 DQ15 38
VSS13 VSS14 1 1 1 1
C132
C133
C134
DDRB_SDQ16 39 40 DDRB_SDQ20 C135
DDRB_SDQ17 41 DQ16 DQ20 42 DDRB_SDQ21
43 DQ17 DQ21 44
DDRB_SDQS2# 45 VSS15 VSS16 46 DDRB_SDM2 2 2 2 2
6 DDRB_SDQS2# 47 DQS#2 DM2 48
DDRB_SDQS2
6 DDRB_SDQS2 49 DQS2 VSS17 50 DDRB_SDQ22
DDRB_SDQ18 51 VSS18 DQ22 52 DDRB_SDQ23
DDRB_SDQ19 53 DQ18 DQ23 54
55 DQ19 VSS19 56 DDRB_SDQ28
DDRB_SDQ24 57 VSS20 DQ28 58 DDRB_SDQ29
DDRB_SDQ25 59 DQ24 DQ29 60
61 DQ25 VSS21 62 DDRB_SDQS3#
DDRB_SDM3 63 VSS22 DQS#3 64 DDRB_SDQS3 DDRB_SDQS3# 6
65 DM3 DQS3 66 DDRB_SDQS3 6
DDRB_SDQ26 67 VSS23 VSS24 68 DDRB_SDQ30
DDRB_SDQ27 69 DQ26 DQ30 70 DDRB_SDQ31
71 DQ27 DQ31 72
VSS25 VSS26
DDRB_CKE0 73 74 DDRB_CKE1
Place near DIMM2
6 DDRB_CKE0 75 CKE0 CKE1 76 DDRB_CKE1 6
+1.5V
77 VDD1 VDD2 78 DDRB_SMA15
2 DDRB_SBS2# 79 NC1 A15 80 DDRB_SMA14 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 2
6 DDRB_SBS2# 81 BA2 A14 82
VDD3 VDD4 2 2 2 2 2 2 2 2 2 2
DDRB_SMA12 83 84 DDRB_SMA11
DDRB_SMA9 85 A12/BC# A11 86 DDRB_SMA7 C234 C175 C235 C174 C136 C137 C138 C139 C140 C141
87 A9 A7 88
DDRB_SMA8 89 VDD5 VDD6 90 DDRB_SMA6 1 1 1 1 1 1 1 1 1 1
DDRB_SMA5 91 A8 A6 92 DDRB_SMA4 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K
93 A5 A4 94
DDRB_SMA3 95 VDD7 VDD8 96 DDRB_SMA2 NewAdd 20110818
DDRB_SMA1 97 A3 A2 98 DDRB_SMA0
99 A1 A0 100
DDRB_CLK0 101 VDD9 VDD10 102 DDRB_CLK1
6 DDRB_CLK0 103 CK0 CK1 104 DDRB_CLK1 6
DDRB_CLK0# DDRB_CLK1#
6 DDRB_CLK0# 105 CK0# CK1# 106 DDRB_CLK1# 6
DDRB_SMA10 107 VDD11 VDD12 108 DDRB_SBS1#
DDRB_SBS0# 109 A10/AP BA1 110 DDRB_SRAS# DDRB_SBS1# 6
6 DDRB_SBS0# 111 BA0 RAS# 112 DDRB_SRAS# 6
+0.75VS
DDRB_SWE# 113 VDD13 VDD14 114 DDRB_SCS0#
6 DDRB_SWE# 115 WE# S0# 116 DDRB_SCS0# 6
DDRB_SCAS# DDRB_ODT0
6 DDRB_SCAS# 117 CAS# ODT0 118 DDRB_ODT0 6
DDRB_SMA13 119 VDD15 VDD16 120 DDRB_ODT1
A13 ODT1 DDRB_ODT1 6 2 1
DDRB_SCS1# 121 122
6 DDRB_SCS1# 123 S1# NC2 124 C142 C143
125 VDD17 VDD18 126 0.1U_0402_16V7K 4.7U_0603_6.3V6K
NCTEST VREF_CA +VREF_CA 1 2
127 128
DDRB_SDQ32 129 VSS27 VSS28 130 DDRB_SDQ36
DDRB_SDQ33 131 DQ32 DQ36 132 DDRB_SDQ37
133 DQ33 DQ37 134
DDRB_SDQS4# 135 VSS29 VSS30 136 DDRB_SDM4
6 DDRB_SDQS4# DDRB_SDQS4 137 DQS#4 DM4 138
6 DDRB_SDQS4 139 DQS4 VSS31 140 DDRB_SDQ38
DDRB_SDQ34 141 VSS32 DQ38 142 DDRB_SDQ39
3 DDRB_SDQ35 143 DQ34 DQ39 144 3
145 DQ35 VSS33 146 DDRB_SDQ44
DDRB_SDQ40 147 VSS34 DQ44 148 DDRB_SDQ45
DDRB_SDQ41 149 DQ40 DQ45 150
151 DQ41 VSS35 152 DDRB_SDQS5#
DDRB_SDM5 153 VSS36 DQS#5 154 DDRB_SDQS5 DDRB_SDQS5# 6
155 DM5 DQS5 156 DDRB_SDQS5 6
DDRB_SDQ42 157 VSS37 VSS38 158 DDRB_SDQ46
DDRB_SDQ43 159 DQ42 DQ46 160 DDRB_SDQ47
161 DQ43 DQ47 162
DDRB_SDQ48 163 VSS39 VSS40 164 DDRB_SDQ52
DDRB_SDQ49 165 DQ48 DQ52 166 DDRB_SDQ53
167 DQ49 DQ53 168
DDRB_SDQS6# 169 VSS41 VSS42 170 DDRB_SDM6
6 DDRB_SDQS6# 171 DQS#6 DM6 172
DDRB_SDQS6
6 DDRB_SDQS6 173 DQS6 VSS43 174 DDRB_SDQ54
DDRB_SDQ50 175 VSS44 DQ54 176 DDRB_SDQ55
DDRB_SDQ51 177 DQ50 DQ55 178
179 DQ51 VSS45 180 DDRB_SDQ60
DDRB_SDQ56 181 VSS46 DQ60 182 DDRB_SDQ61
DDRB_SDQ57 183 DQ56 DQ61 184
185 DQ57 VSS47 186 DDRB_SDQS7#
DDRB_SDM7 187 VSS48 DQS#7 188 DDRB_SDQS7 DDRB_SDQS7# 6
189 DM7 DQS7 190 DDRB_SDQS7 6
DDRB_SDQ58 191 VSS49 VSS50 192 DDRB_SDQ62
DDRB_SDQ59 193 DQ58 DQ62 194 DDRB_SDQ63
R86 10K_0402_5% 195 DQ59 DQ63 196
1 2 197 VSS51 VSS52 198 MEM_MB_EVENT#
SA0 EVENT# MEM_MB_EVENT# 6
199 200
+3VS 201 VDDSPD SDA 202 FCH_SDATA0 10,14,35
203 SA1 SCL 204 FCH_SCLK0 10,14,35
VTT1 VTT2 +0.75VS
1
4 205 206 4
R87 ShortPad G1 G2
0_0402_5% LCN_DAN06-K4806-0103
2
@
Security Classification Compal Secret Data Compal Electronics, Inc.
2012/09/11 2014/03/12 Title
Reserve H:8mm Issued Date Deciphered Date
DDRIII SO-DIMM 2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
<Address: 01> AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9103P
Date: Wednesday, July 10, 2013 Sheet 11 of 52
A B C D E
A B C D E
RH1 100K_0402_5%
2 1 U2A
R90/ C146 close to FCH CH6 HUDSON-2
1 2 APU_PCIE_RST#_C AE2 AF3
PLT_RST# 1 RH3 2 33_0402_5% A_RST# AD5 PCIE_RST# PCICLK0 AF1
PCI CLKS
A_RST# PCICLK1/GPO36 AF5 PCI_CLK1 16
150P_0402_50V8J
CH7 1 2 0.1U_0402_16V7K UMI_RXP0_C AE30 PCICLK2/GPO37 AG2
5 UMI_RXP0 1 2 UMI_RXN0_C AE32 UMI_TX0P PCICLK3/GPO38 AF6 PCI_CLK3 16
CH1 0.1U_0402_16V7K
5 UMI_RXN0 1 2 UMI_RXP1_C AD33 UMI_TX0N PCICLK4/14M_OSC/GPO39 PCI_CLK4 16
CH8 0.1U_0402_16V7K
5 UMI_RXP1 1 2 UMI_RXN1_C AD31 UMI_TX1P AB5
CH2 0.1U_0402_16V7K
5 UMI_RXN1 1 2 UMI_RXP2_C AD28 UMI_TX1N PCIRST#
CH9 0.1U_0402_16V7K
5 UMI_RXP2 1 2 UMI_RXN2_C AD29 UMI_TX2P
CH3 0.1U_0402_16V7K
5 UMI_RXN2 1 2 UMI_RXP3_C AC30 UMI_TX2N AJ3
CH4 0.1U_0402_16V7K
5 UMI_RXP3 1 2 AC32 UMI_TX3P AD0/GPIO0 AL5
CH5 0.1U_0402_16V7K UMI_RXN3_C
1 5 UMI_RXN3 UMI_TX3N AD1/GPIO1 AG4 1
AB33 AD2/GPIO2 AL6
5 UMI_TXP0 AB31 UMI_RX0P AD3/GPIO3 AH3 CH10 1 2
NGCLK@ 32K_X1
5 UMI_TXN0 UMI_RX0N AD4/GPIO4
PCI EXPRESS INTERFACES
AB28 AJ5
5 UMI_TXP1 AB29 UMI_RX1P AD5/GPIO5 AL1 18P_0402_50V8JNGCLK@
5 UMI_TXN1 UMI_RX1N AD6/GPIO6
1
Y33 AN5
5 UMI_TXP2 UMI_RX2P AD7/GPIO7
1
Y31 AN6 RH4
5 UMI_TXN2 Y28 UMI_RX2N AD8/GPIO8 AJ1 32.768KHZ_12.5PF_9H03200019
20M_0402_5%
5 UMI_TXP3 Y29 UMI_RX3P AD9/GPIO9 AL8 Y2
5 UMI_TXN3 UMI_RX3N AD10/GPIO10 AL3
NGCLK@
CH11
2
RH5 1 2 590_0402_1% PCIE_CALRP AF29 AD11/GPIO11 AM7
RH2 1 2 2K_0402_1% PCIE_CALRN AF31 PCIE_CALRP AD12/GPIO12 AJ6 1 2 32K_X2
+VDDAN_11_PCIE PCIE_CALRN AD13/GPIO13 AK7
V33 AD14/GPIO14 AN8
GPP_TX0P AD15/GPIO15
18P_0402_50V8J Close to HUDSON-M2/3
V31 AG9
W30 GPP_TX0N AD16/GPIO16 AM11
NGCLK@
W32 GPP_TX1P AD17/GPIO17 AJ10
AB26 GPP_TX1N AD18/GPIO18 AL12
Move PCIE device to APU. 20110819 GPP_TX2P AD19/GPIO19
AB27 AK11
AA24 GPP_TX2N AD20/GPIO20 AN12
AA23 GPP_TX3P AD21/GPIO21 AG12
GPP_TX3N AD22/GPIO22 AE12
AA27 AD23/GPIO23 AC12 PCI_AD23 16
AA26 GPP_RX0P AD24/GPIO24 AE13 PCI_AD24 16
W27 GPP_RX0N AD25/GPIO25 AF13 PCI_AD25 16
V27 GPP_RX1P AD26/GPIO26 AH13 PCI_AD26 16
PCI INTERFACE
V26 GPP_RX1N AD27/GPIO27 AH14 PCI_AD27 16
W26 GPP_RX2P AD28/GPIO28 AD15
W24 GPP_RX2N AD29/GPIO29 AC15
W23 GPP_RX3P AD30/GPIO30 AE16
CLOSE TO Y1 RH6
GPP_RX3N AD31/GPIO31 AN3 1 2 32K_X1
CBE0# AJ8 20 FCH_RTCX1
2 RH7 CBE1# AN10 0_0402_5% 2
1 2 2K_0402_1% CLK_CALRN F27 CBE2# AD12
+1.1VS_CKVDD CLK_CALRN CBE3# AG10
@
FRAME# AK9
DEVSEL# AL10
G30 IRDY# AF10
G28 PCIE_RCLKP TRDY# AE10
SS For "EXT" CLK mode, input to PCIE, PCIE_RCLKN PAR AH1
R26 STOP# AM9
7 APU_DISP_CLK T26 DISP_CLKP PERR# AH8
APU DISP U2 BolR1@
7 APU_DISP_CLK# DISP_CLKN SERR# AG15
H33 REQ0# AG13
NSS H31 DISP2_CLKP REQ1#/GPIO40 AF15 SA000066K1L
DISP2_CLKN REQ2#/CLK_REQ8#/GPIO41 AM17
REQ3#/CLK_REQ5#/GPIO42 T95
T24 AD16
7 APU_CLK T23 APU_CLKP GNT0# AD13
APU 7 APU_CLK# APU_CLKN GNT1#/GPO44 T107 218-0844012 A1 BOLTON-M3 FCH 0FD
AD21
GNT2#/SD_LED/GPO45 T108
RH10 1@ ShortPad2 0_0402_5% CLK_PCIE_VGA_R J30 AK17
21 CLK_PCIE_VGA SLT_GFX_CLKP GNT3#/CLK_REQ7#/GPIO46
VGA RH11 1 ShortPad2 0_0402_5% CLK_PCIE_VGA#_R K29 AD19 U2 BolR3@
21 CLK_PCIE_VGA# SLT_GFX_CLKN CLKRUN# AH9
@
H27 LOCK#
H28 GPP_CLK0P AF18
GPP_CLK0N INTE#/GPIO32 AE18
INTF#/GPIO33 SA000066K2L
J27 AC16
K26 GPP_CLK1P INTG#/GPIO34 AD18
GPP_CLK1N INTH#/GPIO35 218-0844012 A1 BOLTON-M3 FCH A31!
RH12 1@ ShortPad2 0_0402_5% CLK_PCIE_WLAN_R F33
35 CLK_PCIE_WLAN GPP_CLK2P
WLAN RH13 1 ShortPad2 0_0402_5% CLK_PCIE_WLAN#_R F31
CLOCK GENERATOR
35 CLK_PCIE_WLAN# GPP_CLK2N B25 CLK_EC33M 1 RH14 2 22_0402_5%
@
SS RH15 1@ ShortPad2 0_0402_5% CLK_PCIE_LAN_R E33 LPCCLK0 CLK_PCI_EC 16,36
29 CLK_PCIE_LAN GPP_CLK3P
LAN RH16 1 ShortPad2 0_0402_5% CLK_PCIE_LAN#_R E31 D25
29 CLK_PCIE_LAN# GPP_CLK3N LPCCLK1 D27 LPC_CLK1 16
@
3 M23 LAD0 C28 LPC_AD0 36 3
M24 GPP_CLK4P LAD1 A26 LPC_AD1 36
GPP_CLK4N LAD2 LPC_AD2 36 APU_PG/APU_RST#/LDT_STP# : OD pin
A29 LPC_AD3 36 DMA_ACTIVE# : IN/OD, 0.8V threshold
M27 LAD3 A31 PROCHOT# : IN, 0.8V threshold
LPC
M26 GPP_CLK5P LFRAME# B27 LPC_FRAME# 36
GPP_CLK5N LDRQ0# LDT_STP : No use, NC
AE27 DMA active. The FCH drives the DMA_ACTIVE# to
N25 LDRQ1#/CLK_REQ6#/GPIO49 AE19
N26 GPP_CLK6P SERIRQ/GPIO48 SERIRQ 36 APU to notify DMA activity. This will cause the APU
GPP_CLK6N to reestablish the UMI link quicker.
R23
R24 GPP_CLK7P G25
GPP_CLK7N DMA_ACTIVE# E28 APU_PROCHOT#_R ALLOW_STOP 7
RH18 1 2 0_0402_5%
N27 PROCHOT# E26 APU_PROCHOT# 42,49,7
@
R27 GPP_CLK8P APU_PG G26 APU_PWRGD 49,7 +VCOIN +VCOIN_RTC
GPP_CLK8N LDT_STP# F26 DH1 RB751V40_SC76-2
APU
APU_RST# APU_RST# 7 1 2 +VCOIN 2 1 +VCOIN_RTC
+RTCBATT
J26 RH19 510_0402_5%
14M_25M_48M_OSC H7 2 1
RH21 S5_CORE_EN F1
+3VLP
1 2 25M_X1
NGCLK@
CH12 10P_0402_50V8J RTCCLK F3 RTC_CLK 16,36
DH2 RB751V40_SC76-2
20 PCH_X1 1 2 C31 INTRUDER_ALERT# E6 1 2
25M_X1 +VDDBT_RTC W=20mils W=20mils
0_0402_5% 25M_X1 VDDBT_RTC_G RH22 510_0402_5%
1U_0402_6.3V6K
X1 G2 32K_X1
CLOSE TO X1 @ NGCLK@
S5 PLUS
32K_X1 1
1
25MHZ_10PF_7V25000014
2 1 RH23 C33
25M_X2 CH13 CLRP1 @ RH24
GND OSC 25M_X2 SHORT PADS 10M_0402_5%
For PCIE device reset on FS1 1M_0402_5%
2
+3VALW 4 3 G4 32K_X2 2 @
(GFX,GLAN,WLAN,LVDS Travis) GND OSC NGCLK@ 32K_X2
CH14 @ for Clear CMOS
2
APU_PCIE_RST #: Reset PCIE device on APU 1 2 CH15 10P_0402_50V8J
1 2
0.1U_0402_16V7K NGCLK@ 21807-A13-HUDSON-M3_FCBGA656
5
MC74VHC1G08DFT2G SC70 5P Hud@
4 @ RH25 2 4
P
APU_PCIE_RST#_C 1 2 B 4
1 Y APU_PCIE_RST# 21
33_0402_5%
A
G
8.2K_0402_5%
UH1 QCL10 LAN-APU,WLAN&ExCARD-FCH 20110803
2
150P_0402_50V8J
1 @
3
1
CH16
RH26
@
RH27
@ @
2
0_0402_5% Security Classification Compal Secret Data Compal Electronics, Inc.
ShortPad
1
Issued Date 2012/09/11 Deciphered Date 2014/03/12 Title
2
@ RH28
1 2 PLT_RST# 29,35,36
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
FCH PCIE/CLK/PCI/LPC/RTC
0_0402_5% Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
R692/ C790 close to FCH
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9103P
Date: Wednesday, July 10, 2013 Sheet 12 of 52
A B C D E
A B C D E
4MB SPI ROM
& Non-share ROM.
SPI_CLK_FCH
1
+3VALW RH29
33_0402_5%
NEMC@
2
Place near CONN RH31 1 2 SPI_WP#
FCH: U2B 3.3K_0402_5%
Gen2<6" +3VALW CH20
1 HUDSON-2 RH30 1 2 SPI_HOLD# 1
22P_0402_50V8J
CH17 1 2 0.01U_0402_16V7K SATA_FTX_C_DRX_P0 AK19 AL14 3.3K_0402_5% CH21 NEMC@
32 SATA_FTX_DRX_P0 SATA_TX0P SD_CLK/SCLK_2/GPIO73
CH18 1 2 0.01U_0402_16V7K SATA_FTX_C_DRX_N0AM19 AN14 1 2
32 SATA_FTX_DRX_N0 SATA_TX0N SD_CMD/SLOAD_2/GPIO74 AJ12
HDD SD_CD/GPIO75 @
AL20 AH12 ShortPad UH2 0.1U_0402_16V7K
32 SATA_FRX_C_DTX_N0 AN20 SATA_RX0N SD_WP/GPIO76 AK13 SPI_SB_CS0#_R 1 2 SPI_SB_CS0# 1 8 @
32 SATA_FRX_C_DTX_P0 SATA_RX0P SD_DATA0/SDATI_2/GPIO77 CS# VCC
SD CARD
AM13 SPI_SO_R RH32 1 0_0402_5% 2 SPI_SO_L 2 7 SPI_HOLD# ShortPad
SATA_FTX_C_DRX_P1AN22 SD_DATA1/SDATO_2/GPIO78 AH15 SPI_WP# 3 SO/SIO1 HOLD# 6 SPI_CLK_FCH 1 2 SPI_CLK_FCH_R
32 SATA_FTX_DRX_P1 SATA_FTX_C_DRX_N1 AL22 SATA_TX1P SD_DATA2/GPIO79 AJ14 33_0402_5% 4 WP# SCLK 5 SPI_SI 1 0_0402_5%
2 SPI_SI_R
RH34
32 SATA_FTX_DRX_N1 SATA_TX1N SD_DATA3/GPIO80 RH33 GND SI/SIO0
ODD 33_0402_5%
AH20 AC4 Check CS# PU R 1kor10k and pop/nopop MX25L3206EM2I-12G_SO8
32 SATA_FRX_C_DTX_N1 AJ20 SATA_RX1N GBE_COL AD3 RH35
32 SATA_FRX_C_DTX_P1 SCL v1.20 : If an SPI ROM is shared between
SATA_RX1P GBE_CRS AD9
GBE_MDCK the FCH and the Embedded Controller
AJ22 W10 a 10-K pull-up resistor to +3.3V_S5 is installed.
AH22 SATA_TX2P GBE_MDIO AB8
SATA_TX2N GBE_RXCLK AH7
AM23 GBE_RXD3 AF7 GBE_PHY_INTR
AK23 SATA_RX2N GBE_RXD2 AE7 Pulled-up to +3.3V_S5 with a 10-KΩ 5% resistor.
SATA_RX2P GBE_RXD1 AD7 +3VALW
GBE_RXD0 FCH SCL v1.20 #19-85
AH24 AG8
AJ24 SATA_TX3P GBE_RXCTL/RXDV AD1 GBE_PHY_INTR RH36 1 2 10K_0402_5%
SATA_TX3N GBE_RXERR AB7
AN24 GBE_TXCLK AF9
GBE LAN
AL24 SATA_RX3N GBE_TXD3 AG6 Removed RGMII/MII support and updated termination
SATA_RX3P GBE_TXD2 AE8 requirements for GBE_COL, GBE_CRS, GBE_RXERR
AL26 GBE_TXD1 AD8
SATA_TX4P GBE_TXD0 and GBE_MDIO when RGMII/MII interface is not used.
AN26 AB9 FCH DGv1.20 / SCL v1.20
SATA_TX4N GBE_TXCTL/TXEN AC2
SERIAL ATA
AJ26 GBE_PHY_PD AA7
AH26 SATA_RX4N GBE_PHY_RST# W9 GBE_PHY_INTR
SATA_RX4P GBE_PHY_INTR
AN29
2 AL28 SATA_TX5P V6 SPI_SO_R 2
SATA_TX5N SPI_DI/GPIO164 V5 SPI_SI_R
AK27 SPI_DO/GPIO163 V3 SPI_CLK_FCH_R
SATA_RX5N SPI_CLK/GPIO162
SPI ROM
AM27 T6 SPI_SB_CS0#_R
SATA_RX5P SPI_CS1#/GPIO165 V1 T96
AL29 ROM_RST#/SPI_WP#/GPIO161
AN31 NC6
NC7 L30
AL31 VGA_RED
AL33 NC8
NC9 L32
AH33 VGA_GREEN
AH31 NC10
NC11 M29
AJ33 VGA_BLUE
AJ31 NC12
VGA DAC
NC13 M28
VGA_HSYNC/GPO68 N30
VGA_VSYNC/GPO69
M33
1K_0402_1% 2 1 RH37 SATA_CALRP AF28 VGA_DDC_SDA/GPO70 N32
SATA_CALRP VGA_DDC_SCL/GPO71
+AVDD_SATA 931_0402_1%2 1 RH38 SATA_CALRN AF27
SATA_CALRN K31
VGA_DAC_RSET
AD22
35 HDD_LED# SATA_ACT#/GPIO67 V28
RH39 1 2 10K_0402_5% AUX_VGA_CH_P V29
+3VS AUX_VGA_CH_N
AF21
VGA MAINLINK
SATA_X1 U28
AUXCAL
T31
3 ML_VGA_L0P T33 3
AG21 ML_VGA_L0N T29
SATA_X2 ML_VGA_L1P T28
ML_VGA_L1N R32
ML_VGA_L2P R30
ML_VGA_L2N P29
ML_VGA_L3P P28
ML_VGA_L3N
+3VALW
C29
ML_VGA_HPD/GPIO229
AH16 N2 GPIO175 RPH1 RPH3
AM15 FANOUT0/GPIO52 VIN0/GPIO175 USB_OC5# 1 8 GPIO182 1 8
AJ16 FANOUT1/GPIO53 M3 14 USB_OC5# 2 7 2 7
BT_ON# HW MONITOR GPIO176 GPIO180 GPIO177
35 BT_ON# FANOUT2/GPIO54 VIN1/GPIO176 GPIO179 3 6 GPIO172 3 6
AK15 L2 GPIO177 4
APU_ALERT#_FCH 5 GPIO173 4 5
WL_OFF# AN16 FANIN0/GPIO56 VIN2/SDATI_1/GPIO177
35 WL_OFF# AL16 FANIN1/GPIO57 N4 GPIO178 10K_0804_8P4R_5% 10K_0804_8P4R_5%
R136 2 1 100K_0402_5% FANIN2/GPIO58 VIN3/SDATO_1/GPIO178
+3VALW
@ P1 GPIO179
ODD_EN K6 VIN4/SLOAD_1/GPIO179 RPH2
32 ODD_EN TEMPIN0/GPIO171 P3 GPIO180 GPIO175 1 8
VIN5/SCLK_1/GPIO180 GPIO178 2 7
GPIO172 K5 M1 GPIO181 GPIO181 3 6
TEMPIN1/GPIO172 VIN6/GBE_STAT3/GPIO181 GPIO176 4 5
M5 GPIO182
GPIO173 K3 VIN7/GBE_LED3/GPIO182 10K_0804_8P4R_5%
TEMPIN2/GPIO173
AG16
APU_ALERT#_FCH M6 NC1 AH10 Need to enable internal
T127 TEMPIN3/TALERT#/GPIO174 NC2 A28 pull down to leave
4 NC3 G27 4
NC4 unconnected
L4
NC5
21807-A13-HUDSON-M3_FCBGA656
Hud@
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/09/11 Deciphered Date 2014/03/12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
FCH SATA/SPI/VGA/HWM/SD
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9103P
Date: Wednesday, July 10, 2013 Sheet 13 of 52
A B C D E
A B C D E
U2D
PCIE_RST2 : Reset PCIE device on Hudson2/3
HUDSON-2
RH51 2 @ 1 0_0402_5% T97 AB6 G8 CLK_USB30_48M T98
USB MISC
VGATE 49 R2 PCIE_RST2#/PCI_PME#/GEVENT4# USBCLK/14M_25M_48M_OSC
@
2 ShortPad1 36 EC_LID_OUT# W7 RI#/GEVENT22# B9
FCH_PWRGD USB_RCOMP RH54 1 2 11.8K_0402_1%
FCH_POK 36 T3 SPI_CS3#/GBE_STAT1/GEVENT21# USB_RCOMP
0_0402_5% RH52
36 PM_SLP_S3# W2 SLP_S3# H1
36 PM_SLP_S5# J4 SLP_S5# USB_FSD1P/GPIO186 H3
36 PBTN_OUT# PWR_BTN# USB_FSD1N Hudson-M2/M3
FCH_PWRGD N7 OHCI CTL
PWR_GOOD H6 DEV 20, Fn 5
USB 1.1
TEST0 T9 USB_FSD0P/GPIO185 H5 <Disable CTL>
ACPI / WAKE UP EVENTS
NEMC@ TEST1 T10 TEST0 USB_FSD0N
CH23 100P_0402_50V8J TEST2 V9 TEST1/TMS H10
2 1 FCH_PWRGD TEST2 USB_HSD13P
USB_HSD13N
G10 USB2P13_P1
USB2P13_N1
33
33
LP1
1
AE22 1
36 GATEA20 GA20IN/GEVENT0# K10
CE26 close to U2
36 KB_RST#
AG19
KBRST#/GEVENT1#
USB_HSD12P
USB_HSD12N
J12 Root
EC_SCI# R9 Hudson-M2 Hudson-M3
36 EC_SCI# C26 LPC_PME#/GEVENT3# G12
36 EC_SMI# LPC_SMI#/GEVENT23# USB_HSD11P EHCI CTL xHCI CTL
T5 F12 DEV 22, Fn 2 DEV 16, Fn 1
EC_SCI# RH53 1 @ 2 10K_0402_5% SYS_RESET# U4 LPC_PD#/GEVENT5# USB_HSD11N
+3VALW SYS_RESET#/GEVENT19# <Disable CTL of M2> xHCI CTL
THERMTRIP: K1 K12 DEV 16, Fn 0
29,36 FCH_PCIE_WAKE# WAKE#/GEVENT8# USB_HSD10P USB2P10_P2 33 LP2
10U_0603_6.3V6M
0.1U_0402_16V7K
V7 K13
Need level shift from +3VALW to +1.5V R10 IR_RX1/GEVENT20# USB_HSD10N USB2P10_N2 33
Note: Ensure FCH internal pull-up resistor 1 1 7 H_THERMTRIP# THRMTRIP#/SMBALERT#/GEVENT2#
WD_PWRGD AF19 B11
WD_PWRGD USB_HSD9P USB20_P12 18
CH91
CH92
to +3.3V S5 is disabled to prevent leakage NEMC@ D11
when APU is powered down. 2 2 36 EC_RSMRST#
U2
RSMRST#
USB_HSD9N USB20_N12 18 CAM
NEMC@ E10
AG24
CLK_REQ4#/SATA_IS0#/GPIO64
USB_HSD8P
USB_HSD8N
F10 Root
ODD_DA# AE24 Hudson-M2/M3
29 LAN_CLKREQ# AE26 CLK_REQ3#/SATA_IS1#/GPIO63 C10
SMARTVOLT1/SATA_IS2#/GPIO50 USB_HSD7P EHCI CTL
10U_0603_6.3V6M
0.1U_0402_16V7K
AF22 A10 DEV 19, Fn 2
AH17 CLK_REQ0#/SATA_IS3#/GPIO60 USB_HSD7N
USB 2.0
1 1 HDD_DET#
32 HDD_DET# AG18 SATA_IS4#/FANOUT3/GPIO55 H9
SATA_IS5#/FANIN3/GPIO59 USB_HSD6P USB20_P6 31 CR
CH94
CH93
NEMC@ AF24 G9
+3VS 30 FCH_SPKR AD26 SPKR/GPIO66 USB_HSD6N USB20_N6 31
FCH_SCLK0
GPIO
2 2 10,11,35 FCH_SCLK0 AD25 SCL0/GPIO43 A8
NEMC@ SM bus 0-->S0 PWR domain FCH_SDATA0 T99
10,11,35 FCH_SDATA0 T7 SDA0/GPIO47 USB_HSD5P C8
FCH_SCLK1
SM bus 1-->S5 PWR domain FCH_SDATA1 R7 SCL1/GPIO227 USB_HSD5N T100
SDA1/GPIO228
2
AG25 F8
35 WLAN_CLKREQ# AG22 CLK_REQ2#/FANIN4/GPIO62 USB_HSD4P E8
RH55
J2 CLK_REQ1#/FANOUT4/GPIO61 USB_HSD4N
100K_0402_5% IR_LED#/LLB#/GPIO184
2
G
QH1 AG26 C6
47 VGA_PWRGD V8 SMARTVOLT2/SHUTDOWN#/GPIO51 USB_HSD3P A6 Root
1
ODD_DA# 3 1 ODD_DA#_FCH KB_DET# W8 DDR3_RST#/GEVENT7#/VGA_PD USB_HSD3N
32,36 ODD_DA# 38 KB_DET# GBE_LED0/GPIO183 Hudson-M2/M3
Y6 C5 EHCI CTL
S
V10 SPI_HOLD#/GBE_LED1/GEVENT9#
GBE_LED2/GEVENT10#
USB_HSD2P
USB_HSD2N
A5 USB2P2_P4
USB2P2_N4
34
34
RP1 DEV 18, Fn 2
SSM3K7002FU_SC70-3 AA8 <Support Wakeup>
RH56 2 @ 1 0_0402_5% PEG_CLKREQ#_R AF25 GBE_STAT0/GEVENT11# C1
22 PEG_CLKREQ# CLK_REQG#/GPIO65/OSCIN/IDLEEXIT# USB_HSD1P
USB_HSD1N
C3 USB20_P4
USB20_N4
35
35
WLAN
ODD_DETECT#
M7 E1
2
+3VALW BLINK/USB_OC7#/GEVENT18# USB_HSD0P USB2P0_P3 34
DEBUG LP3 2
10U_0603_6.3V6M
0.1U_0402_16V7K
For FCH internal debug use ODD_DA#_FCH R8 E3
T1 USB_OC6#/IR_TX1/GEVENT6# USB_HSD0N USB2P0_N3 34
USB_OC5#
USB OC
1 1 13 USB_OC5# USB_OC5#/IR_TX0/GEVENT17#
RH57 1 @ 2 2.2K_0402_5% TEST0 ODD_DETECT# P6 C16 USBSS_CALRP RH58 1 2 1K_0402_1%
32 ODD_DETECT# USB_OC4#/IR_RX0/GEVENT16# USBSS_CALRP
CH96
CH95
NEMC@ USB_OC3# F5 A16 USBSS_CALRN RH59 1 2 1K_0402_1%
34 USB_OC3# USB_OC3#/AC_PRES/TDO/GEVENT15# USBSS_CALRN +FCH_VDD_11_SSUSB_S
RH60 1 @ 2 2.2K_0402_5% TEST1 USB_OC2# P5
2 2 33 USB_OC2# J7 USB_OC2#/TCK/GEVENT14# A14
NEMC@ USB_OC1# USB3P3TP1
34 USB_OC1# USB_OC1#/TDI/GEVENT13# USB_SS_TX3P USB3P3TP1 33
RH61 1 @ 2 2.2K_0402_5% TEST2 USB_OC0# T8 C14 USB3P3TN1
33 USB_OC0# USB_OC0#/SPI_TPM_CS#/TRST#/GEVENT12# USB_SS_TX3N USB3P3TN1 33 LP1
C12 USB3P3RP1
+3VALW USB_SS_RX3P A12 USB3P3RP1 33
USB3P3RN1
USB_SS_RX3N USB3P3RN1 33
RH62 1 2 33_0402_5% HDA_BITCLK AB3 D15
30 HDA_BITCLK_AUDIO AZ_BITCLK USB_SS_TX2P
RH63 1 2 33_0402_5% HDA_SDOUT AB1 B15
30 HDA_SDOUT_AUDIO AA2 AZ_SDOUT USB_SS_TX2N
RPH4 HDA_SDIN0
HD AUDIO
1 8 30 HDA_SDIN0 Y5 AZ_SDIN0/GPIO167 E14
USB_OC2#
2 7 Y3 AZ_SDIN1/GPIO168 USB_SS_RX2P F14
USB 3.0
USB_OC1#
3 6 USB_OC0# Y1 AZ_SDIN2/GPIO169 USB_SS_RX2N
4 5 USB_OC3# RH66 1 2 33_0402_5% HDA_SYNC AD6 AZ_SDIN3/GPIO170 F15
30 HDA_SYNC_AUDIO AZ_SYNC USB_SS_TX1P
RH68 1 2 33_0402_5% HDA_RST# AE4 G15
30 HDA_RST_AUDIO# AZ_RST# USB_SS_TX1N
10K_0804_8P4R_5%
H13
RH73 1 @ 2 100K_0402_5% EC_LID_OUT# @ USB_SS_RX1P G13
D6 USB_SS_RX1N
RH88 1 2 10K_0402_5% FCH_PCIE_WAKE# RB751V40_SC76-2 T101 K19 J16 USB3P0TP2
PS2_DAT/SDA4/GPIO187 USB_SS_TX0P USB3P0TP2 33
RH89 1 2 10K_0402_5% H_THERMTRIP# 1 2 FCH_GPIO192 T102 J19 H16 USB3P0TN2
J21 PS2_CLK/CEC/SCL4/GPIO188 USB_SS_TX0N USB3P0TN2 33
36 VGA_ON 1 2 FCH_GPIO191 SPI_CS2#/GBE_STAT2/GPIO166
USB_SS_RX0P
J15 USB3P0RP2
USB3P0RP2 33
LP2
K15 USB3P0RN2
USB_SS_RX0N USB3P0RN2 33
@ D7
RB751V40_SC76-2 GPIO189 D21 Hudson-M3
GPIO190 C20 PS2KB_DAT/GPIO189 H19 RH72 1 2 10K_0402_5%
PS2KB_CLK/GPIO190 SCL2/GPIO193 xHCI CTL
0_0402_5% 2 DIS@ 1 RH74 D23 G19 RH75 1 2 10K_0402_5% DEV 16, Fn 1
21 PXS_RST# C22 PS2M_DAT/GPIO191 EMBEDDED CTRL SDA2/GPIO194 G22
PS2M_CLK/GPIO192 SCL3_LV/GPIO195 T114 xHCI CTL
PXS_PWREN 0_0402_5% 2 @ 1 RH76 G21 DEV 16, Fn 0
23,45,47 PXS_PWREN SDA3_LV/GPIO196 T118
E22
+3VS FCH_GPIO192 EC_PWM0/EC_TIMER0/GPIO197 H22
F21 EC_PWM1/EC_TIMER1/GPIO198 J22 EC_PWM2
3
+3VS +3VALW E20 KSO_0/GPIO209 EC_PWM2/EC_TIMER2/WOL_EN/GPIO199 H21 EC_PWM2 16 strap pin 3
KSO_1/GPIO210 EC_PWM3/EC_TIMER3/GPIO200
1
RH78 F20
2.2K_0402_5% A22 KSO_2/GPIO211 K21
DIS@ E18 KSO_3/GPIO212 KSI_0/GPIO201 K22
RH79 1 2 2.2K_0402_5% FCH_SCLK0 A20 KSO_4/GPIO213 KSI_1/GPIO202 F22
KSO_5/GPIO214 KSI_2/GPIO203
1
RH81 J18 F24
2
RH80 1 2 2.2K_0402_5% FCH_SDATA0 PXS_PWREN 10K_0402_5% H18 KSO_6/GPIO215 KSI_3/GPIO204 E24
DIS@ G18 KSO_7/GPIO216 KSI_4/GPIO205 B23
KSO_8/GPIO217 KSI_5/GPIO206
3
RH82 1 2 10K_0402_5% WD_PWRGD B21 C24
QH2B K18 KSO_9/GPIO218 KSI_6/GPIO207 F18
2
RH83 1 @ 2 10K_0402_5% ODD_DETECT# +3VALW +3VALW D19 KSO_10/GPIO219 KSI_7/GPIO208
DMN66D0LDW-7_SOT363-6 KSO_11/GPIO220
DIS@ 5F_192- A18 +3VS
C18 KSO_12/GPIO221
KSO_13/GPIO222 G-EVENT[2:23]: VDDIO_33_S, S5 domain
6
DIS@ B19 +3VALW RPH5
GPIO[0:80]: VDDIO_33_PCIGP, S0 domain
4
KSO_14/GPIO223
2 UMA@ 1
2 UMA@ 1
RH84 1 2 8.2K_0402_5% WLAN_CLKREQ# B17 4 5FCH_SDATA1_TP
10K_0402_5%
10K_0402_5%
QH2A
A24 KSO_15/GPIO224 GPIO[161:229]: VDDIO_33_S, S5 domain 3 6FCH_SCLK1_TP
DMN66D0LDW-7_SOT363-6 KSO_16/GPIO225
RH87 1 2 8.2K_0402_5% LAN_CLKREQ# 2 FCH_GPIO192 D17 2 7FCH_SDATA1
RH85
RH86
KSO_17/GPIO226 1 8FCH_SCLK1
1
21807-A13-HUDSON-M3_FCBGA656 2.2K_0804_8P4R_5%
GPIO189
GPIO190 Hud@
BOARD
GPIO189 GPIO190 Function +3VS
RH90 1 2 2.2K_0402_5% Config.
FCH_SCLK1_TP
EC_RSMRST#
DIS@ 1
2 DIS@ 1
10K_0402_5%
10K_0402_5%
0 0 DIS-PX4
FCH_SCLK1
RH91 1 @ 2 10K_0402_5% HDA_BITCLK_AUDIO
RH92
RH93
0 1 Reserved
FCH_SDATA1_TP
2
RH94 1 @ 2 10K_0402_5% HDA_SDIN0
FCH_SDATA1
1 0 DIS-PURE
2
RH95 1 2 10K_0402_5% PEG_CLKREQ#_R FCH_SCLK1_TP 1 6 FCH_SCLK1
38 FCH_SCLK1_TP
1 1 UMA
5
QH31A
DMN66D0LDW-7_SOT363-6
FCH_SDATA1_TP 4 3 FCH_SDATA1
38 FCH_SDATA1_TP
4 4
QH31B
DMN66D0LDW-7_SOT363-6
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/09/11 Deciphered Date 2014/03/12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
FCH-ACPI/USB/HDA/GPIO
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-9103P
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, July 10, 2013 Sheet 14 of 52
A B C D E
A B C D E
+3VS
@ +1.1VS
LH1 U2C ShortPad
1 2 +VDDPL_33_SYS @ 50mils, +VCC_VDDCR_11 1 2
MBK1608221YZF_2P 10mils, 102mA HUDSON-2 1007mA RH98 0_0805_5%
CH31
2.2U_0402_6.3V6M
CH25
0.1U_0402_16V7K
CH32
0.1U_0402_16V7K
CH33
0.1U_0402_16V7K
CH34
1U_0402_6.3V6K
CH26
1U_0402_6.3V6K
CH35
10U_0603_6.3V6M
220 ohm 1ShortPad 2 +VDDIO_33_PCIGP AB17 T14
+3VS VDDIO_33_PCIGP_1 VDDCR_11_1
22U_0603_6.3V6M
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
1 1 RH96 0_0603_5% AB18 T17 1 1 1 1 1
VDDIO_33_PCIGP_2 VDDCR_11_2
CH30
CH36
CH27
CH37
AE9 T20
PCI/GPIO I/O
AD10 VDDIO_33_PCIGP_3 VDDCR_11_3 U16
1 1 1 1 VDDIO_33_PCIGP_4 VDDCR_11_4
AG7 U18
2 2 AC13 VDDIO_33_PCIGP_5 VDDCR_11_5 V14 2 2 2 2 2
VDDIO_33_PCIGP_6 VDDCR_11_6
CORE S0
AB12 V17
2 2 2 2 AB13 VDDIO_33_PCIGP_7 VDDCR_11_7 V20
+FCH_VDDAN_33_DAC AB14 VDDIO_33_PCIGP_8 VDDCR_11_8 Y17
1 AB16 VDDIO_33_PCIGP_9 VDDCR_11_9 +1.1VS_CKVDD +1.1VS 1
VDDIO_33_PCIGP_10 20mils,
10mils, 47mA 340mA 42ohm @ 100MHz
1
@ 2 +VDDPL_33_MLDAC H24 H26 +1.1VS_CKVDD 1 2
+VDDPL_33_SYS VDDPL_33_SYS VDDAN_11_CLK_1
RH99 ShortPad0_0402_5% @ 10mils, 20mA J25 RH100 0_0603_5%
+3VS RH1011 ShortPad2 0_0402_5% VDDAN_11_CLK_2 @
CH39
0.1U_0402_16V7K
CH40
0.1U_0402_16V7K
CH41
1U_0402_6.3V6K
CH29
1U_0402_6.3V6K
CH42
22U_0603_6.3V6M
+VDDPL_33_DAC V22 K24
0.1U_0402_16V7K
0.1U_0402_16V7K
CLKGEN I/O
+VDDPL_33_MLDAC VDDPL_33_DAC VDDAN_11_CLK_3
CH28
CH38
10mils, 12mA L22 1 1 1 1 1 ShortPad
1 @ 2 @ RH1021 ShortPad2 0_0402_5% +VDDPL_33_ML U22 VDDAN_11_CLK_4 M22
1 1 VDDPL_33_ML VDDAN_11_CLK_5
LH2 0_0805_5% @ 10mils, 30mA N21
@ +FCH_VDDAN_33_DAC T22 VDDAN_11_CLK_6 N22
VDDAN_33_DAC VDDAN_11_CLK_7 P22 2 2 2 2 2
2 2
VDDPL_33_SSUSB_S 10mils, 11mA VDDAN_11_CLK_8
For Hudson3 USB3.0 only RH97 2 @ 1 0_0402_5% +VDDPL_33_SSUSB_S L18
VDDPL_33_SSUSB_S
For Hudson2, connect to GND 10mils, 14mA 50mils,
+VDDPL_33_USB_S D7 1088mA +1.1VS
VDDPL_33_USB_S AB24 +VDDAN_11_PCIE 42ohm @ 100MHz
10mils, 11mA VDDAN_11_PCIE_1
+VDDPL_33_PCIE AH29 Y21 +VDDAN_11_PCIE 1 2
VDDPL_33_PCIE VDDAN_11_PCIE_2 AE25 RH103 0_0805_5%
10mils, 12mA VDDAN_11_PCIE_3
PCI EXPRESS
CH44
0.1U_0402_16V7K
CH45
1U_0402_6.3V6K
CH46
22U_0603_6.3V6M
+VDDPL_33_SATA AG28 AD24
VDDPL_33_SATA VDDAN_11_PCIE_4 AB23 1 1 1
@
@ VDDAN_11_PCIE_5 AA22
LDO_CAP: Internally generated 1.8V For A11: Cap = 1nF VDDAN_11_PCIE_6 ShortPad
1 2 M31 AF26
supply for the RGB outputs For A12, Cap = DNI LDO_CAP VDDAN_11_PCIE_7 AG27
CH43 2.2U_0603_6.3V6K
+1.1VS LH3 VDDAN_11_PCIE_8 2 2 2
10mils, 7mA
1 2 +1_1V_L RH1041 ShortPad2 0_0402_5% +VDDPL_11_DAC V21 60mils,
MBK1608221YZF_2P VDDPL_11_DAC +1.1VS
@ 1337mA
220 ohm/2A +VDDAN_11_ML
20mils, AA21 +AVDD_SATA 42ohm @ 100MHz
RH1051 ShortPad2 0_0603_5% VDDAN_11_SATA_1 Y20 1 2
226mA VDDAN_11_SATA_4
+3VS +FCH_VDDAN_33_DAC Y22 AB21 RH106 0_0805_5%
@ VDDAN_11_ML_1 VDDAN_11_SATA_2
CH47
4.7U_0402_6.3V6M
CH48
0.1U_0402_16V7K
CH49
0.1U_0402_16V7K
CH50
0.1U_0402_16V7K
CH51
1U_0402_6.3V6K
CH52
1U_0402_6.3V6K
CH53
22U_0603_6.3V6M
@ 30mil V23 AB22
SERIAL ATA
@
MAIN LINK
1 2 V24 VDDAN_11_ML_2 VDDAN_11_SATA_3 AC22
1 1 1 VDDAN_11_ML_3 VDDAN_11_SATA_5 1 1 1 1
LH4 ShortPad0_0805_5% V25 AC21 ShortPad
VDDAN_11_ML_4 VDDAN_11_SATA_6
CH54
2.2U_0603_6.3V6K
CH55
0.1U_0402_16V7K
220 ohm AA20
VDDAN_11_SATA_7 AA18
1 1 2 2 2 VDDAN_11_SATA_8 2 2 2 2
2 @ AB20 2
@ VDDAN_11_SATA_9 AC19
AB10 VDDAN_11_SATA_10 @ +3VALW
2 2 VDDIO_33_GBE_S 10mils,
59mA ShortPad
AB11 N18 +VDDIO_33_S 1 2
AA11 VDDCR_11_GBE_S_1 VDDIO_33_S_1 L19 RH107 0_0402_5%
GBE LAN
VDDCR_11_GBE_S_2 VDDIO_33_S_2
CH56
1U_0402_6.3V6K
CH57
1U_0402_6.3V6K
CH58
2.2U_0402_6.3V6M
M18
RH1081 ShortPad2 0_0402_5% AA9 VDDIO_33_S_3 V12
VDDIO_GBE_S_1 VDDIO_33_S_4 1 1 1
3.3V_S5 I/O
@ AA10 V13
+3VALW VDDIO_GBE_S_2 VDDIO_33_S_5 Y12
LH5 VDDIO_33_S_6 Y13
30mils, 470mA VDDIO_33_S_7 2 2 2
1 2 +VDDAN_33_USB G7 W11
VDDAN_33_USB_S_1 VDDIO_33_S_8
10U_0603_6.3V6M
10U_0603_6.3V6M
FBMA-L11-201209-221LMA30T_0805 H8
+3VALW VDDAN_33_USB_S_2 +3VALW
CH59
CH60
CH61
1U_0402_6.3V6K
CH62
1U_0402_6.3V6K
CH63
0.1U_0402_16V7K
220 ohm/2A J8 10mils, +VDDXL_3.3V
LH6 K8 VDDAN_33_USB_S_3 LH7
1 1 1 1 1 VDDAN_33_USB_S_4 5mA Tie to +3.3V_S5 rail if USB3 Wake
1 2 +VDDPL_33_SSUSB_S K9 G24 +VDDXL_3.3V 1 2 is supported; otherwise, tie to
MBK1608221YZF_2P M9 VDDAN_33_USB_S_5 VDDXL_33_S MBK1608221YZF_2P
VDDAN_33_USB_S_6 +3.3V_S0 rail.
CH64
2.2U_0402_6.3V6M
CH65
0.1U_0402_16V7K
CH66
2.2U_0402_6.3V6M
M10 220 ohm
2 2 2 2 2 N9 VDDAN_33_USB_S_7 +3VS Hudson-2 designs: Tie to +3.3V_S0
220 ohm 1 1 VDDAN_33_USB_S_8 1
N10 LH8 M2@ rail.
M12 VDDAN_33_USB_S_9 1 2
N12 VDDAN_33_USB_S_10 MBK1608221YZF_2P
2 2 M11 VDDAN_33_USB_S_11 2
+1.1VALW VDDAN_33_USB_S_12
LH9 10mils, 140mA 10mils, +1.1VALW
1 2 +VDDAN_11_USB_S U12 187mA
@
USB
MBK1608221YZF_2P U13 VDDAN_11_USB_S_1 N20 +VDDCR_1.1V 1 ShortPad2
VDDAN_11_USB_S_2 VDDCR_11_S_1
CH67
2.2U_0402_6.3V6M
CH68
0.1U_0402_16V7K
CH69
0.1U_0402_16V7K
220 ohm M20 RH109 0_0603_5%
+VDDAN_33_USB VDDCR_11_S_2
CH70
1U_0402_6.3V6K
CH71
1U_0402_6.3V6K
1 1 1
LH10 1 1
1 2 +VDDPL_33_USB_S
MBK1608221YZF_2P @
2 2 2
CH72
2.2U_0402_6.3V6M
CH73
0.1U_0402_16V7K
3 3
220 ohm 2 2
1 1
+1.1VALW
LH11 10mils, 42mA 10mils, +1.1VALW
2 2 1 2 +VDDCR_11_USB T12 LH12
VDDCR_11_USB_S_1 70mA
MBK1608221YZF_2P T13 J24 +VDDPL_11_SYS_S 1 2
VDDCR_11_USB_S_2 VDDPL_11_SYS_S
CH74
10U_0603_6.3V6M
CH75
0.1U_0402_16V7K
CH76
0.1U_0402_16V7K
220 ohm MBK1608221YZF_2P
0.1U_0402_16V7K
CH77
2.2U_0402_6.3V6M
CH78
1 1 1 220 ohm
1 1
+3VS
LH13 2 2 2
1 2 +VDDPL_33_PCIE 2 2
MBK1608221YZF_2P
220 ohm 10mils, +3VALW
+FCH_VDD_11_SSUSB_S
CH79
2.2U_0402_6.3V6M
20mils, 282mA 12mA @
P16 M8 +VDDAN_33_HWM 1 2
1
1
@ 2 +VDDAN_11_SSUSB M14 VDDAN_11_SSUSB_S_1 VDDAN_33_HWM_S RH110 ShortPad0_0402_5% AMD reply:
40mils VDDAN_11_SSUSB_S_2
CH83
2.2U_0402_6.3V6M
CH84
0.1U_0402_16V7K
RH111 0_0603_5% N14 VDDAN_33_HWM_S: Please connect
VDDAN_11_SSUSB_S_3
CH80
1U_0402_6.3V6K
CH81
0.1U_0402_16V7K
CH82
0.1U_0402_16V7K
ShortPad P13 1 1 it to +3.3V_S5 directly if HWM is not used.
2 P14 VDDAN_11_SSUSB_S_4
1 1 1 VDDAN_11_SSUSB_S_5
USB SS
30mils, @ @
2 2
2 2 2
424mA
N16
+3VS N17 VDDCR_11_SSUSB_S_1 @ +3VS
VDDCR_11_SSUSB_S_2 10mils,
LH14 P17 26mA ShortPad
1 2 +VDDPL_33_SATA M17 VDDCR_11_SSUSB_S_3 AA4 +VDDIO_AZ 1 2 VDDIO_AZ_S should be tied to
MBK1608221YZF_2P VDDCR_11_SSUSB_S_4 VDDIO_AZ_S RH112 0_0402_5% +3.3/1.5V_S5 rail if Wake on Ring
@
CH86
2.2U_0402_6.3V6M
220 ohm POWER CH85 1 2 2.2U_0402_6.3V6M is supported
1 ShortPad
4 2 LH15 1 1 2 +VDDCR_11_SSUSB 4
+1.1VALW 21807-A13-HUDSON-M3_FCBGA656
RH113 0_0603_5%
CH87
10U_0603_6.3V6M
CH88
1U_0402_6.3V6K
CH89
0.1U_0402_16V7K
CH90
0.1U_0402_16V7K
FBMA-L11-201209-221LMA30T_0805
2
42 ohm/4A 1 1 1 1 Hud@
For FCH M2 - BOM option
VDDAN_11_SSUSB_S / VDDCR_11_SSUSB_S
2 2 2 2
Connected to VSS. Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/09/11 Deciphered Date 2014/03/12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
FCH-PWR
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9103P
Date: Wednesday, July 10, 2013 Sheet 15 of 52
A B C D E
5 4 3 2 1
DEBUG STRAPS
U2E
HUDSON-2
STRAP PINS FCH HAS 15K INTERNAL PU FOR PCI_AD[27:23]
A3 T25
A33 VSS VSS T27
B7 VSS VSS U6
VSS VSS PCI_CLK1 PCI_CLK3 PCI_CLK4 CLK_PCI_EC LPC_CLK1 EC_PWM2 RTC_CLK PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 PCI_AD23
B13 U14
D9 VSS VSS U17
D D13 VSS VSS U20 D
VSS VSS PULL ALLOW USE NON_FUSION EC CLKGEN LPC ROM S5 PLUS USE PCI DISABLE USE FC USE DEFAULT DISABLE PCI
E5 U21 PULL
E12 VSS VSS U30 HIGH PCIE GEN2 DEBUG CLOCK MODE ENABLED ENABLED MODE PLL ILA PLL PCIE STRAPS MEM BOOT
E16 VSS VSS U32 STRAPS DISABLED HIGH AUTORUN
E29 VSS VSS V11 DEFAULT DEFAULT DEFAULT DEFAULT DEFAULT DEFAULT DEFAULT DEFAULT
F7 VSS VSS V16
F9 VSS VSS V18
F11 VSS VSS W4
VSS VSS PULL FORCE IGNORE FUSION EC CLKGEN SPI ROM S5 PLUS PULL BYPASS ENABLE BYPASS USE EEPROM ENABLE PCI
F13 W6
F16 VSS VSS W25 LOW PCIE GEN1 DEBUG CLOCK DISABLED DISABLE MODE LOW PCI PLL ILA FC PLL PCIE STRAPS MEM BOOT
F17 VSS VSS W28 STRAP MODE ENABLED AUTORUN
F19 VSS VSS Y14 DEFAULT DEFAULT DEFAULT DEFAULT
F23 VSS VSS Y16
F25 VSS VSS Y18
F29 VSS VSS AA6
G6 VSS VSS AA12
G16 VSS VSS AA13 +3VS +3VS +3VS +3VALW +3VALW +3VALW +3VALW
G32 VSS VSS AA14
VSS VSS
RH114 10K_0402_5%
RH115 10K_0402_5%
RH116 10K_0402_5%
RH117 10K_0402_5%
RH118 10K_0402_5%
RH119 10K_0402_5%
RH120 10K_0402_5%
H12 AA16
H15 VSS VSS AA17
VSS VSS
1
H29 AA25
GROUND
J6 VSS VSS AA28
J9 VSS VSS AA30 @ @ @ @
VSS VSS 12 PCI_AD27
J10 AA32
C VSS VSS C
J13 AB25
12 PCI_AD26
2
J28 VSS VSS AC6
J32 VSS VSS AC18
K7 VSS VSS AC28 12 PCI_AD25
VSS VSS 12 PCI_CLK1
K16 AD27
K27 VSS VSS AE6 12 PCI_AD24
VSS VSS 12 PCI_CLK3
K28 AE15
L6 VSS VSS AE21 12 PCI_AD23
L12 VSS VSS AE28 12 PCI_CLK4
L13 VSS VSS AF8
VSS VSS 12,36 CLK_PCI_EC
RH121 2.2K_0402_5%
RH122 2.2K_0402_5%
RH123 2.2K_0402_5%
RH124 2.2K_0402_5%
RH125 2.2K_0402_5%
L15 AF12
VSS VSS
1
L16 AF16
L21 VSS VSS AF33 12 LPC_CLK1
M13 VSS VSS AG30 @ @ @ @ @
VSS VSS 14 EC_PWM2
M16 AG32
M21 VSS VSS AH5
12,36 RTC_CLK
2
M25 VSS VSS AH11
VSS VSS RH126 10K_0402_5%
RH127 10K_0402_5%
RH128 10K_0402_5%
RH129 10K_0402_5%
RH130 10K_0402_5%
RH131 2.2K_0402_5%
RH132 2.2K_0402_5%
N6 AH18
N11 VSS VSS AH19
VSS VSS
1
1
N13 AH21
N23 VSS VSS AH23
N24 VSS VSS AH25 @ @ @
P12 VSS VSS AH27
P18 VSS VSS AJ18
B B
2
2
P20 VSS VSS AJ28
P21 VSS VSS AJ29
P31 VSS VSS AK21
P33 VSS VSS AK25
R4 VSS VSS AL18
R11 VSS VSS AM21
R25 VSS VSS AM25
R28 VSS VSS AN1
T11 VSS VSS AN18
T16 VSS VSS AN28
T18 VSS VSS AN33
VSS VSS
N8 T21
VSSAN_HWM VSSPL_DAC L28
K25 VSSAN_DAC K33
VSSXL VSSANQ_DAC N28
H25 VSSIO_DAC
VSSPL_SYS R6
EFUSE
21807-A13-HUDSON-M3_FCBGA656
A A
Hud@
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/09/11 Deciphered Date 2014/03/12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
FCH-VSS/Strap
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9103P
Date: Wednesday, July 10, 2013 Sheet 16 of 52
5 4 3 2 1
5 4 3 2 1
Power Consumption:
Pin22 (DPV33) < 20mA
Pin 11 (DP_V12) < 100mA
+AVCC33 +3VS +3VS_RT
Pin 15 (SWR_VCCK) < 100mA (layout trace > 60 mil)
@ Pin 17 (SWR_LX) < 600mA (layout trace > 60 mil)
10U_0603_6.3V6M
0.1U_0402_16V7K
0.1U_0402_16V7K
30mil 30mil
D
1 1 1 ShortPad Pin 18 (SWR_VDD) < 200mA (layout trace > 40 mil) D
1 2
Pin 22 (PVCC) < 50 mA
CT1
CT3
CT2
RT1 0_0805_5%
2 2 2 Pin 43 (VCCK) < 50mA
+DVCC33 +DVCC33
Close to LT2 Close to 5 pin
2
UT2 @
+DVCC33 RT2 RT20
+3VS_RT RTD2136R 4.7K_0402_5% EEPROM 4.7K_0402_5%
+DVCC33 35
change footprint LVDS_ACLK 18
1
60 mils 22 TXOC+ 36 MIIC_SCL MIIC_SDA
PVCC TXOC- LVDS_ACLK# 18
10U_0603_6.3V6M
0.1U_0402_16V7K
10U_0603_6.3V6M
22U_0805_6.3V6M
0.1U_0402_16V7K
0.1U_0402_16V7K
1 1 1 1 1 1 LT2 2 1 +AVCC33 60 mils 18 41
LVDS_A0 18
SWR_VDD TXO0+
2
FBMA-L11-201209-221LMA30T_0805 42
TXO0- LVDS_A0# 18
CT4
CT5
CT14
CT6
CT7
CT8
PWR
LT1 2 1 +DVCC33 40 mils 5 RT3 RT12
DP_V33 39
FBMA-L11-201209-221LMA30T_0805 LVDS_A1 18 4.7K_0402_5% ROMLESS 4.7K_0402_5%
2 2 2 2@ 2 2 +SWR_V12 LT3 1 2 S@+SW_LX 17 TXO1+ 40
60 mils
SWR_LX TXO1- LVDS_A1# 18 1:RevD W EEPROM @
4.7UH_PG031B-4R7MS_1.1A_20%
0:RevE W/O EEPROM
1
60 mils 15 37
SWR_VCCK TXO2+ LVDS_A2 18
38
TXO2- LVDS_A2# 18
Close to LT1 Close to 22 pin Close to 18 pin +SWR_V12 1 2 +SW_LX 60 mils 43
RT331 0_0603_5% VCCK 33
R@ 60 mils 11 TXO3+ 34 +DVCC33
電電電電電CPU端
DP_V12 TXO3-
LT3 and RT331 EDID_DATA 1 2 4.7K_0402_5%
DP 0.1u RT6
Co-lay 25
LVDS_BCLK 18
LVDS
DP0_TXP0_C 7 TXEC+ 26 EDID_CLK RT7 1 2 4.7K_0402_5%
C 7 DP0_TXP0_C LANE0P TXEC- LVDS_BCLK# 18 C
DP0_TXN0_C 8
7 DP0_TXN0_C LANE0N 31
LVDS_B0 18 CSCL RT10 1 2 4.7K_0402_5%
DP0_TXP1_C 9 TXE0+ 32
7 DP0_TXP1_C LANE1P TXE0- LVDS_B0# 18
DP0_TXN1_C 10 CSDA RT13 1 2 4.7K_0402_5%
7 DP0_TXN1_C LANE1N
DP
29
TXE1+ LVDS_B1 18
DP0_AUXP_C 4 30
7 DP0_AUXP_C AUX-CH_P TXE1- LVDS_B1# 18
DP0_AUXN_C 3
7 DP0_AUXN_C AUX-CH_N 27
TXE2+ LVDS_B2 18 Pin47 MIIC_SDA
LVDS_HPD 1 28
9 LVDS_HPD DP_HPD TXE2- LVDS_B2# 18
0 1
23
TXE3+ 24
60 mils TXE3- Pin48 0 x EP MODE
+SWR_V12 21 MIIC_SCL 1 EEPROM
9 APU_INVT_PWM 2 PWMIN
TESTMODE MIICSCL1
46 EDID_CLK
EDID_CLK 18
ROM
10U_0603_6.3V6M
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
1 2 12 45 EDID_DATA
DP_REXT MIICSDA1 EDID_DATA 18
OTHERS
1 1 1 1 RT5 12K_0402_1%
20 TL_ENVDD
PANEL_VCC TL_ENVDD 18
CT9
CT10
CT11
CT12
19 TL_INVT_PWM
PWMOUT TL_INVT_PWM 18
MIIC_SCL 48 44 TL_BKOFF#_R
2 2 2 2 MIIC_SDA 47 MODE_CFG1 BL_EN
MODE_CFG0 LVDS_HPD TL_BKOFF#_R
CSCL
@
1 ShortPad2 0_0402_5% CIICSCL 13 6
RT9
CIICSCL1 DP_GND
1
Close to LT3 Close to 43 pin Close to 11 pin CSDA RT11 1 ShortPad2 0_0402_5% CIICSDA 14
CIICSDA1
GND
@ 16
GND RT16 RT19
49 100K_0402_5% 100K_0402_5%
PAD
2
RTD2136R-CG_QFN48_6x6
B B
+3VS_RT
Pull-Low 100K
1
@
RT17
100K_0402_5%
Vendor advise reserve it
和 TL_SMB_CK在EC端端Pull high
2
DP0_AUXN_C
DP0_AUXP_C TL_SMB_DA
@
RT14 1 2 0_0402_5% +3VS_RT
ENBAKL 36
1
RT18
100K_0402_5%
2
TL_BKOFF#_R RT15 1 2 0_0402_5% @QT1A
@ QT1A
TL_BKOFF# 18
2
CT13 CSDA 1 6 TL_SMB_DA
TL_SMB_DA 36
+3VS_RT 0.1U_0402_16V7K
AUX termination 1 2 DMN66D0LDW-7_SOT363-6
5
@ QT1B
5
@
2 CSCL 4 3 TL_SMB_CK
P
B 4 TL_SMB_CK 36
1 Y DMN66D0LDW-7_SOT363-6
36 BKOFF# A
G
@
UT3 Short Pad
3
@ MC74VHC1G08DFT2G SC70 5P @ 1 2
Short Pad RT21 0_0402_5%
A 1 2 A
RT22 0_0402_5%
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/09/11 Deciphered Date 2014/03/12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LVDS Translator - RTD2132R
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9103P
Date: Wednesday, July 10, 2013 Sheet 17 of 52
5 4 3 2 1
5 4 3 2 1
JLVDS CONN@
+3VS @
LCD PWR CTRL LVDS Conn. 17 LVDS_A0#
LVDS_A0- 1
STARC_107K40-000001-G2
1
W=40mils CV22 need to close to Pin4 of U3 LVDS_A0+ 2 41
RV299 17 LVDS_A0 2 G1
3 42
2 1 +LCDVDD_IN LVDS_A1- 4 3 G2 43
17 LVDS_A1# 4 G3
1 LVDS_A1+ 5 44
17 LVDS_A1 5 G4
0.1U_0402_16V7K
0_0603_5% 6 45
6 G5
CV22
@ LVDS_A2- 7 46
17 LVDS_A2# 7 G6
LVDS_A2+ 8
2 17 LVDS_A2 8
9
LVDS_ACLK- 10 9
17 LVDS_ACLK# 10
LVDS_ACLK+ 11
17 LVDS_ACLK 11
+LCDVDD_IN 1 @ 2 U3_SS @ 12
0_0402_5% RV32 +LCDVDD LVDS_B0- 13 12
D 17 LVDS_B0# 13 D
U3 LVDS_B0+ 14
17 LVDS_B0 14
+LCDVDD_IN 5 1 +LCDVDD 15
VIN VOUT W=40mils LVDS_B1- 16 15
17 LVDS_B1# 16
1 1 LVDS_B1+ 17
17 LVDS_B1 17
TL_ENVDD TL_ENVDD_U3 3 CV21 CE_EN_R 18
17 TL_ENVDD EN CV20 18
0.1U_0402_16V7K LVDS_B2- 19
17 LVDS_B2# 19
4.7U_0805_10V4Z LVDS_B2+ 20
17 LVDS_B2 20
1
U3_SS 4 2 2@ 2 DBC_EN_R 21
@ RV300 SS GND LVDS_BCLK- 22 21
17 LVDS_BCLK# 22
100K_0402_5% APL3512ABI-TRG_SOT23-5 LVDS_BCLK+ 23
17 LVDS_BCLK 23
2 @ 24
CV19 25 24
W=60mils +LCDVDD
2
26 25
+3VS 26
0.1U_0402_16V7K 2 1 USB20_P12_R 27
1 14 USB20_P12 2 0_0402_5%
1 USB20_N12_R 28 27
RV210
14 USB20_N12 29 28
RV30 @ RV208 0_0402_5%
@ +3VS_CAM
MIC_CLK 2ShortPad 1 MIC_CLK_R 30 29
30 MIC_CLK @ 30
31
RV302 @ 1
MIC_DATA 32 31
0_0402_5% NEMC@
TL_ENVDD 2 1 +LCDVDD 30 MIC_DATA LCD_TEST 33 32
CV29 36 LCD_TEST
ShortPad 470P_0402_50V7K 2ShortPad@1 EDID_CLK_LCD 34 33
2 17 EDID_CLK 34
17 EDID_DATA 2 1
0_0402_5% ShortPad RV19 EDID_DATA_LCD 35
0_0603_5% 0_0402_5% INVTPWM 36 35
@ RV20 DISPOFF# 37 36
38 37
39 38
40 39
W=60mils +INV_PWR_SRC 40
LCD backlight PWR CTRL CIS Symbol
C C
40mil QV6 40mil
B+ SI3457CDV-T1-GE3_TSOP6
+INV_PWR_SRC_R 1 2
+INV_PWR_SRC
* Reserved for EMI/ESD/RF
D
6 RV24 @ 0_0603_5%
S
4 5
ShortPad
100K_0402_5%
2
need to close to JLVDS
1000P_0402_50V7K
CV25
RV25
1
1
1 1
3
CV26 LV24 NEMC@ DV8
0.1U_0603_25V7K DLW21SN900SQ2L_0805_4P MIC_CLK_R 6 1 USB20_P12_R
2 2 USB20_P12 1 2 USB20_P12_R V I/O V I/O
2
1 2 5 2
+5VS V BUS Ground
PWR_SRC_ON
USB20_N12 4 3 USB20_N12_R MIC_DATA 4 3 USB20_N12_R
4 3 V I/O V I/O
1
RV26 SC30000110L-->main IP4223CZ6_SO6
100K_0402_5% NEMC@
SC300001G00-->2nd
1
RV328
2
300_0402_5%
1
RV31@ D INVTPWM
2
2 ShortPad1 +LCDVDD_R 2 QV7 1
+LCDVDD
G SSM3K7002FU_SC70-3 CV368
0_0402_5% S 15P_0402_50V8J
3
470P_0402_50V7K
470P_0402_50V7K
DISPOFF#
2
B
1 NEMC@ 1 NEMC@ B
AMD request 5/16 CV30 C799
2 2
Wedcam PWR CTRL RV29 @
For EMI
INV_PWM 2 ShortPad1 INVTPWM
17 TL_INVT_PWM
0_0402_5%
1
RV230
+3VS +3VS_CAM
@ 100K_0402_5%
1ShortPad 2
2
RV231 0_0603_5%
+3VS
1
@ RV315 @
CE_EN RV62 1 2 0_0402_5% CE_EN_R 4.7K_0402_5%~D
36 CE_EN
DBC_EN RV99 1 2 0_0402_5% DBC_EN_R RV318 @ DV15
36 DBC_EN
2
2 ShortPad1 2 1 DISPOFF#
17 TL_BKOFF#
1
1
0_0402_5% RB751V40_SC76-2
@
RV100 RV216 10K_0402_5%
0_0402_5% 0_0402_5% RV319
@
2
2
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/09/11 Deciphered Date 2014/03/12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LVDS/CAMERA
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9103P
Date: Wednesday, July 10, 2013 Sheet 18 of 52
5 4 3 2 1
5 4 3 2 1
W=40mils
Place close to JHDMI1 @ ShortPad
D D
RV36 0_0805_5%
2 1
RV35 1 2 0_0402_5%
NEMC@ +VDISPLAY_VCC
KINGCORE_WCM-2012HS-900T DV9 FV1
TMDS_TXCP 4 3 TMDS_L_TXCP 2 1 2 1
10U_0603_6.3V6M
0.1U_0402_16V7K
4 3 +5VS
@ShortPad 3 NC 1 1
CV34
7 DP2_TXN3 CV32 1@ShortPad2 0_0402_5% TMDS_TXCN @ 1.5A_6V_1206L150PR
7 DP2_TXP3 CV33 1 2 0_0402_5% TMDS_TXCP TMDS_TXCN 1 2 TMDS_L_TXCN BAT1000-7-F_SOT23-3 CV35
1 2
@ShortPad LV7 EMC@ 2 2
7 DP2_TXN2 CV36 1@ShortPad2 0_0402_5% TMDS_TX0N +3VS
CV37 1
7 DP2_TXP2 @ShortPad2 0_0402_5% TMDS_TX0P
RV37 1 2 0_0402_5%
NEMC@
7 DP2_TXN1 CV38 1@ShortPad2 0_0402_5% TMDS_TX1N
7 DP2_TXP1 CV39 1 2 0_0402_5% TMDS_TX1P
1
@ShortPad RV38 1 2 0_0402_5%
NEMC@
7 DP2_TXN0 CV40 1@ShortPad2 0_0402_5% TMDS_TX2N RV39
CV41 1 2 0_0402_5% TMDS_TX2P KINGCORE_WCM-2012HS-900T 10K_0402_5%
7 DP2_TXP0
TMDS_TX0P 4 3 TMDS_L_TX0P
4 3
2
JHDMI
TMDS_TX0N 1 2 TMDS_L_TX0N HDMI_HPLUG 19
1 2 18 HP_DET
LV8 EMC@ 17 +5V
DDC_DAT_HDMI 16 DDC/CEC_GND
RV40 1 2 0_0402_5%
NEMC@ DDC_CLK_HDMI 15 SDA
14 SCL
13 Reserved
CEC
1
RV42
604_0402_1%
RV43
604_0402_1%
RV44
604_0402_1%
RV45
604_0402_1%
RV46
604_0402_1%
RV47
604_0402_1%
RV48
604_0402_1%
RV49
604_0402_1%
RV41 1 2 0_0402_5%
NEMC@ TMDS_L_TXCN 12 20
11 CK- GND 21
KINGCORE_WCM-2012HS-900T TMDS_L_TXCP 10 CK_shield GND 22
TMDS_TX1P 4 3 TMDS_L_TX1P TMDS_L_TX0N 9 CK+ GND 23
4 3 8 D0- GND
2
TMDS_L_TX0P 7 D0_shield
TMDS_TX1N 1 2 TMDS_L_TX1N TMDS_L_TX1N 6 D0+
1 2 5 D1-
LV9 EMC@ TMDS_L_TX1P 4 D1_shield
C D1+ C
TMDS_L_TX2N 3
RV50 1 2 0_0402_5%
NEMC@ 2 D2-
D2_shield
1
D TMDS_L_TX2P 1
2 QV11 D2+
+3VS
G LOTES_ABA-HDM-022-K01
1
S RV52 1 2 0_0402_5%
NEMC@ CONN@
3
RV53 2N7002K 1N SOT23-3
100K_0402_5% KINGCORE_WCM-2012HS-900T
TMDS_TX2P 4 3 TMDS_L_TX2P
4 3
2
TMDS_TX2N 1 2 TMDS_L_TX2N 46@ ROYALTY HDMI W/LOGO
1 2
LV10 EMC@ Part Number Description
RO0000002HM HDMI W/Logo:RO0000002HM
RV54 1 2 0_0402_5%
NEMC@
EMC@
TMDS_TXCN NEMC@CV358 1 2 1P_0402_50V8J TMDS_L_TXCN CV349 1 2 1P_0402_50V8J
EMC@
TMDS_TXCP NEMC@CV360 1 2 1P_0402_50V8J TMDS_L_TXCP CV350 1 2 1P_0402_50V8J
EMC@
TMDS_TX0N NEMC@CV362 1 2 1P_0402_50V8J TMDS_L_TX0N CV351 1 2 1P_0402_50V8J
EMC@
TMDS_TX0P NEMC@CV363 1 2 1P_0402_50V8J TMDS_L_TX0P CV352 1 2 1P_0402_50V8J
EMC@
TMDS_TX1N NEMC@CV359 1 2 1P_0402_50V8J TMDS_L_TX1N CV353 1 2 1P_0402_50V8J
EMC@
TMDS_TX1P NEMC@CV357 1 2 1P_0402_50V8J TMDS_L_TX1P CV354 1 2 1P_0402_50V8J
EMC@
B TMDS_TX2N NEMC@CV361 1 2 1P_0402_50V8J TMDS_L_TX2N CV355 1 2 1P_0402_50V8J B
EMC@
TMDS_TX2P NEMC@CV364 1 2 1P_0402_50V8J TMDS_L_TX2P CV356 1 2 1P_0402_50V8J
20121127 EMI ADD
+3VS
1
C RV57
QV13 2 1 2 HDMI_HPLUG
+3VS MMBT3904_NL_SOT23-3 B 150K_0402_5%
E 1
2
7 HDMI_DET EMC@
@ CV42
1
RV59 220P_0402_50V8J
1
200K_0402_5% 2
RV55 DV11
1
QV12A 100K_0402_5% BAV99-7-F_SOT23-3
2
@ DMN66D0LDW-7_SOT363-6 NEMC@
2
1ShortPad 2 HDMI_CLK_R 1 6 DDC_CLK_HDMI 1 2 +VDISPLAY_VCC
7 HDMI_CLK
3
RV329 0_0603_5% RV58 2.2K_0402_5%
5
@
1ShortPad 2 HDMI_DATA_R 4 3 DDC_DAT_HDMI 1 2 +3VS
7 HDMI_DATA
RV330 0_0603_5% RV60 2.2K_0402_5%
QV12B
3
DMN66D0LDW-7_SOT363-6
@ @
0.1U_0402_16V7K
0.1U_0402_16V7K
1 1 D20
CV369
CV370
A PESD24VS2UT_SOT23-3 A
NEMC@
1
2 2
CV365, CV367
Please close APU side
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/09/11 Deciphered Date 2014/03/12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDMI
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9103P
Date: Wednesday, July 10, 2013 Sheet 19 of 52
5 4 3 2 1
5 4 3 2 1
D D
SLG3NB244VTR SA000057I00 Intel-UMA
SLG3NB300VTR SA00005RS00 Intel-DIS
SLG3NB302VTR SA00006D500 AMD-DIS
C9 --> Close to UG1.Pin2 SLG3NB238VTR SA00005DO00 AMD-UMA
+1.8VGS +3VALW +LAN_IO +3VALW
GCLK@ 1 1 GCLK@ 1 GCLK@ 1 GCLK@
Depop if GCLK
C6 C7 C8 C9
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
with UMA
2 2 2 2
+VCOIN +VCOIN_RTC
+VCOIN_RTC
1
GCLK@ @
C7 --> Close to UG1.Pin3 R796 R787
1
330_0402_5% 0_0402_5% @
R790
0_0402_5%
2.2U_0603_6.3V6K
C 2 C
C5 GCLK@ 1
C10
22U_0805_6.3V6M GCLK@
GCLK@ 1 reserved circuit in VGA_X1 for EMI
1 2 UG1 2
+3VLP
R793 0_0402_5% NEMC@
10 14 C15 10P_0402_50V8J~D
@ VBAT VDD_RTC_OUT VGA_X1 1 2
1 2 +3VALW_15 15
+3VALW +V3.3A
R791 0_0402_5%
2
+3VALW VDD 9
32kHz FCH_RTCX1 12
GCLK@
11 12 VGA_X1_R 1 2 R785 VGA_X1
+1.8VGS VDDIO_27M 27MHz VGA_X1 22
CLK_X1 10_0402_1%
C11 GCLK@ 8 6
+LAN_IO VDDIO_25M_A 25MHz_A
2 1
3 5 PCH_X1_R 1 GCLK@ 2 R783
+3VALW VDDIO_25M_B 25MHz_B PCH_X1 12
12P_0402_50V8J Y1 GCLK@ 33_0402_5%
1 2 CLK_X1 1
OSC GND CLK_X2 16 XTAL_IN
XTAL_OUT
GND1
GND2
GND3
GND4
3 4
OSC GND
C12 GCLK@ 25MHZ_10PF_7V25000014
2 1 SLG3NB302VTR _TQFN16_2X3
4
7
13
17
DGCLK@
12P_0402_50V8J CLK_X2
UG1 UGCLK@
B B
SLG3NB238VTR_TQFN16_2X3
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/09/11 Deciphered Date 2014/03/12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
GCLK
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9103P
Date: Wednesday, July 10, 2013 Sheet 20 of 52
5 4 3 2 1
5 4 3 2 1
PCIE_CRX_GTX_P[7..0]
PCIE_CTX_GRX_P[7..0] PCIE_CRX_GTX_P[7..0] 5
5 PCIE_CTX_GRX_P[7..0]
D
PCIE_CRX_GTX_N[7..0] D
PCIE_CTX_GRX_N[7..0] PCIE_CRX_GTX_N[7..0] 5
5 PCIE_CTX_GRX_N[7..0]
GFX PCIE LANE REVERSAL
UV1A
PCIE_CTX_GRX_P0 AA38 Y33 PCIE_CRX_C_GTX_P0 0.1U_0402_16V7K 2 1 CV43 DIS@ PCIE_CRX_GTX_P0
PCIE_CTX_GRX_N0 Y37 PCIE_RX0P PCIE_TX0P Y32 PCIE_CRX_C_GTX_N0 0.1U_0402_16V7K 2 1 CV44 DIS@ PCIE_CRX_GTX_N0
PCIE_CTX_GRX_P1 Y35
PCIE_RX0N PCIE_TX0N
W33 PCIE_CRX_C_GTX_P1 0.1U_0402_16V7K 2 1 CV45 DIS@ PCIE_CRX_GTX_P1
LVDS Interface
PCIE_CTX_GRX_N1 W36 PCIE_RX1P PCIE_TX1P W32 PCIE_CRX_C_GTX_N1 0.1U_0402_16V7K 2 1 CV46 DIS@ PCIE_CRX_GTX_N1
PCIE_RX1N PCIE_TX1N UV1G
PCIE_CTX_GRX_P2 W38 U33 PCIE_CRX_C_GTX_P2 0.1U_0402_16V7K 2 1 CV47 DIS@ PCIE_CRX_GTX_P2
PCIE_CTX_GRX_N2 V37 PCIE_RX2P PCIE_TX2P U32 PCIE_CRX_C_GTX_N2 0.1U_0402_16V7K 2 1 CV48 DIS@ PCIE_CRX_GTX_N2
PCIE_RX2N PCIE_TX2N LVDS CONTROL AK27
VARY_BL AJ27
PCIE_CTX_GRX_P3 V35 U30 PCIE_CRX_C_GTX_P3 0.1U_0402_16V7K 2 1 CV49 DIS@ PCIE_CRX_GTX_P3 DIGON
PCIE_CTX_GRX_N3 U36 PCIE_RX3P PCIE_TX3P U29 PCIE_CRX_C_GTX_N3 0.1U_0402_16V7K 2 1 CV50 DIS@ PCIE_CRX_GTX_N3
PCIE_RX3N PCIE_TX3N
PCIE_CTX_GRX_P4 U38 T33 PCIE_CRX_C_GTX_P4 0.1U_0402_16V7K 2 1 CV51 DIS@ PCIE_CRX_GTX_P4 AK35
PCIE_CTX_GRX_N4 T37 PCIE_RX4P PCIE_TX4P T32 PCIE_CRX_C_GTX_N4 0.1U_0402_16V7K 2 1 CV52 DIS@ PCIE_CRX_GTX_N4 TXCLK_UP_DPF3P AL36
PCIE_RX4N PCIE_TX4N TXCLK_UN_DPF3N
PCI EXPRESS INTERFACE
AJ38
PCIE_CTX_GRX_P5 T35 T30 PCIE_CRX_C_GTX_P5 0.1U_0402_16V7K 2 1 CV53 DIS@ PCIE_CRX_GTX_P5 TXOUT_U0P_DPF2P AK37
PCIE_CTX_GRX_N5 R36 PCIE_RX5P PCIE_TX5P T29 PCIE_CRX_C_GTX_N5 0.1U_0402_16V7K 2 1 CV54 DIS@ PCIE_CRX_GTX_N5 TXOUT_U0N_DPF2N
PCIE_RX5N PCIE_TX5N AH35
TXOUT_U1P_DPF1P AJ36
PCIE_CTX_GRX_P6 R38 P33 PCIE_CRX_C_GTX_P6 0.1U_0402_16V7K 2 1 CV55 DIS@ PCIE_CRX_GTX_P6 TXOUT_U1N_DPF1N
PCIE_CTX_GRX_N6 P37 PCIE_RX6P PCIE_TX6P P32 PCIE_CRX_C_GTX_N6 0.1U_0402_16V7K 2 1 CV56 DIS@ PCIE_CRX_GTX_N6 AG38
C PCIE_RX6N PCIE_TX6N TXOUT_U2P_DPF0P C
AH37
TXOUT_U2N_DPF0N
PCIE_CTX_GRX_P7 P35 P30 PCIE_CRX_C_GTX_P7 0.1U_0402_16V7K 2 1 CV57 DIS@ PCIE_CRX_GTX_P7 AF35
PCIE_CTX_GRX_N7 N36 PCIE_RX7P PCIE_TX7P P29 PCIE_CRX_C_GTX_N7 0.1U_0402_16V7K 2 1 CV58 DIS@ PCIE_CRX_GTX_N7 TXOUT_U3P AG36
PCIE_RX7N PCIE_TX7N TXOUT_U3N
N38 N33 LVTMDP
M37 PCIE_RX8P PCIE_TX8P N32
PCIE_RX8N PCIE_TX8N AP34
TXCLK_LP_DPE3P AR34
M35 N30 TXCLK_LN_DPE3N
L36 PCIE_RX9P PCIE_TX9P N29 AW37
PCIE_RX9N PCIE_TX9N TXOUT_L0P_DPE2P AU35
TXOUT_L0N_DPE2N
L38 L33 AR37
K37 PCIE_RX10P PCIE_TX10P L32 TXOUT_L1P_DPE1P AU39
PCIE_RX10N PCIE_TX10N TXOUT_L1N_DPE1N
AP35
K35 L30 TXOUT_L2P_DPE0P AR35
J36 PCIE_RX11P PCIE_TX11P L29 TXOUT_L2N_DPE0N
PCIE_RX11N PCIE_TX11N AN36
TXOUT_L3P AP37
J38 K33 TXOUT_L3N
H37 PCIE_RX12P PCIE_TX12P K32
PCIE_RX12N PCIE_TX12N
H35 J33
G36 PCIE_RX13P PCIE_TX13P J32 THAMES XT M2 @
PCIE_RX13N PCIE_TX13N
G38 K30
F37 PCIE_RX14P PCIE_TX14P K29
PCIE_RX14N PCIE_TX14N
F35 H33
E37 PCIE_RX15P PCIE_TX15P H32
PCIE_RX15N PCIE_TX15N RV61 2 @ 1 0_0402_5%
B B
+3VGS
CLOCK
MARS@
CLK_PCIE_VGA AB35 1 2
12 CLK_PCIE_VGA PCIE_REFCLKP +1.0VGS
CLK_PCIE_VGA# AA36 RV198 1.69K_0402_1%~D
12 CLK_PCIE_VGA# PCIE_REFCLKN
5
VCC
CALIBRATION
TH@ 1
Y30 14 PXS_RST# IN1
1.27K_0402_1% 1 RV63 2 4 GPU_RST#
PCIE_CALRP 2 OUT
DIS@ TH@
GND
1 2 AH16 Y29 12 APU_PCIE_RST# IN2
2K_0402_1% 1 RV65 2
+1.0VGS 2
RV64 1K_0402_5% PWRGOOD PCIE_CALRN UV13
1K_0402_1% 1 RV203 2 CV326 MC74VHC1G08DFT2G_SC70-5
3
GPU_RST# AA30 MARS@ 0.1U_0402_16V7K DIS@
PERSTB 1
DIS@
1
DIS@ Install 2K for Thames/Seymour SA00000OH00
RV66 THAMES XT M2 THR1@
100K_0402_5%
2
UV1 MSR1@ UV1 SUNXTR1@
SA00005X10L SA00006G60L
MARS-PRO_FCBGA962~D SUN XT M2_FCBGA962
MARS Pro
UV1 SUNXTR3@
SA00006G61L
SUN XT M2_FCBGA962
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/09/11 Deciphered Date 2014/03/12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ATI_ThamesXT_M2_PCIE/LVDS
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9103P
Date: Wednesday, July 10, 2013 Sheet 21 of 52
5 4 3 2 1
5 4 3 2 1
UV1B
OPTIONAL FOR MEMORY ID ON HEATHROW/CHELSEA/VENUS/THAMES/SEYMOUR ONLY CONFIGURATION STRAPS RECOMMENDED SETTINGS
No DVO or GPIO function on Mars ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE 0= DO NOT INSTALL RESISTOR
AU24 1 = INSTALL 10K RESISTOR
TXCAP_DPA3P AV23 GPIOS ARE USED, THEY MUST NOT CONFLICT DURING RESET ACIN_65W 1 2 AC_BATT
X = DESIGN DEPENDANT
+1.8VGS TXCAM_DPA3N RV250 DIS@ 0_0402_5%
NA = NOT APPLICABLE
AT25
RV67 1 2 @ 10K_0402_5% VRAM_ID0 MUTI GFX TX0P_DPA2P AR24 +3VGS
RV68 1 2 @ 10K_0402_5% DPA TX0M_DPA2N RECOMMENDED
RV69 1 2 @ 10K_0402_5% VRAM_ID1 AU26 STRAPS PIN DESCRIPTION OF DEFAULT SETTINGS SETTINGS
TX1P_DPA1P
1
RV70 1 2 @ 10K_0402_5% AV25
RV71 1 2 @ 10K_0402_5% VRAM_ID2 TX1M_DPA1N 0: 50% swing
RV72 1 2 @ 10K_0402_5% AR8 AT27 TX_PWRS_ENB GPIO0 PCIE FULL TX OUTPUT SWING 1: Full swing X +3VGS RV73
AU8 DVPCNTL_MVP_0 TX2P_DPA0P AR26
@ 10K_0402_5%
AP8 DVPCNTL_MVP_1 TX2M_DPA0N 0: disable
2
DVPCNTL_0
1
AW8 AR30 TX_DEEMPH_EN GPIO1 PCIE TRANSMITTER DE-EMPHASIS 1: enable X AC_BATT
AR3 DVPCNTL_1 TXCBP_DPB3P AT29 RV74
DVPCNTL_2 TXCBM_DPB3N
3
AR1 Advertises PCIE speed 0: 2.5GT/s @ 4.7K_0402_5%
VRAM_ID0 AU1 DVPCLK AV31 RSVD GPIO2 when compliance test 1: 5GT/s 0
VRAM_ID1 AU3 DVPDATA_0 TX3P_DPB2P AU30
D @ D
2
VRAM_ID2 AW3 DVPDATA_1 DPB TX3M_DPB2N PACIN# 5
AP6 DVPDATA_2 AR32 RSVD GPIO8 RESERVED 0 QV14B
DVPDATA_3 TX4P_DPB1P
6
AW5 AT31 2N7002DW-7-F_SOT363-6
4
AU5 DVPDATA_4 TX4M_DPB1N
AR6 DVPDATA_5 AT33 BIF_VGA DIS GPIO9 VGA ENABLED 0
@
AW6 DVPDATA_6 TX5P_DPB0P AU32 ACIN_65W 2 QV14A
DVPDATA_7 TX5M_DPB0N 36 ACIN_65W
AU6 2N7002DW-7-F_SOT363-6
AT7 DVPDATA_8 AU14 RSVD GPIO21 RESERVED 0
1
AV7 DVPDATA_9 TXCCP_DPC3P AV13
AN7 DVPDATA_10 TXCCM_DPC3N 0: disable
AV9 DVPDATA_11 AT15 BIOS_ROM_EN GPIO_22_ROMCSB ENABLE EXTERNAL BIOS ROM 1: enable X
AT9 DVPDATA_12 TX0P_DPC2P AR14
AR10 DVPDATA_13 TX0M_DPC2N
AW10 DVPDATA_14 DPC AU16 ROMIDCFG(2:0) GPIO[13:11] SERIAL ROM TYPE OR MEMORY APERTURE SIZE SELECT XXX
AU10 DVPDATA_15 TX1P_DPC1P AV15
AP10 DVPDATA_16 TX1M_DPC1N
AV11 DVPDATA_17 AT17 VIP_DEVICE_STRAP_ENA V2SYNC IGNORE VIP DEVICE STRAPS 0
AT11 DVPDATA_18 TX2P_DPC0P AR16
MLPS Setting please refer Page 24
AR12 DVPDATA_19 TX2M_DPC0N
AW12 DVPDATA_20 AU20 RSVD H2SYNC 0 +1.8VGS +1.8VGS +1.8VGS
AU12 DVPDATA_21 TXCDP_DPD3P AT19
AP12 DVPDATA_22 TXCDM_DPD3N
DVPDATA_23 AT21 RSVD GENERICC 0
TX3P_DPD2P
1
AJ21 AR20
AK21 SWAPLOCKA TX3M_DPD2N AUD[1] AUD[0] RV237 RV239 RV241
SWAPLOCKB DPD AU22 AUD[1] HSYNC 0 0 No audio function 11 8.45K_0402_1% 10K_0402_1% 10K_0402_1%
TX4P_DPD1P AV21 0 1 Audio for DisplayPort and HDMI if dongle is detected
TX4M_DPD1N @ @ @
AUD[0] VSYNC 1 0 Audio for DisplayPort only
2
I2C AT23 1 1 Audio for both DisplayPort and HDMI PS_1 PS_2 PS_3
TX5P_DPD0P AR22
TX5M_DPD0N
1
AK26 @ @
SUN GPU GPIO1, 2, 7, 11, 12, 13, 14, 18 - NC pin AJ26 SCL AMD RESERVED CONFIGURATION STRAPS 1 RV238 1 RV240 1 RV242
0.68U_0402_10V
0.68U_0402_10V
0.68U_0402_10V
SDA
AD39
ALLOW FOR PULLUP PADS FOR THESE STRAPS BUT DO NOT INSTALL CV329
4.75K_0402_1%
CV331
4.75K_0402_1%
CV333
4.75K_0402_1%
GENERAL PURPOSE I/O R AD37 RESISTOR. IF THESE GPIOS ARE USED, THEY MUST KEEP "LOW" AND MARS@ MARS@ MARS@
2
GPU_GPIO0 AH20 RB @ 2 2 2
GPU_GPIO1 AH18 GPIO_0 AE36
NOT CONFLICT DURING RESET
GPU_GPIO2 AN16 GPIO_1 G AD35
VGA_SMB_DA2 1 RV251 2 0_0402_5% AH23
VGA_SMB_DA2_R GPIO_2 GB GPIO21 H2SYNC GENERICC GPIO2 GPIO8
VGA_SMB_CK2 1 RV252 2 0_0402_5% AJ23
VGA_SMB_CK2_R GPIO_3_SMBDATA AF37
AC_BATT AH17 GPIO_4_SMBCLK B AE38
Add 12/6 for MLPS
GPU_VID4 AJ17 GPIO_5_AC_BATT DAC1 BB
+3VGS STRAPS 47 GPU_VID4
AK17 GPIO_6
GPIO_7_BLON HSYNC
AC36 Transmitter Power Saving Enable
GPU_GPIO8 AJ13 AC38 TX_PWRS_ENB GPIO0 0: 50% Tx output swing for mobile mode
C
GPU_GPIO9 AH15 GPIO_8_ROMSO VSYNC C
DIS@ GPIO_9_ROMSI 1: full Tx output swing (Default setting for Desktop)
10K_0402_5% 1 2 RV75 GPU_GPIO0 GPU_VID5 AJ16 +1.8VGS
47 GPU_VID5
GPU_GPIO11 AK16 GPIO_10_ROMSCK AB34 RV84 1
@ 2 499_0402_1%
@ GPIO_11 RSET 65mA PCI Express Transmitter De-emphasis Enable
10K_0402_5% 1 2 RV76 GPU_GPIO1 RV76-SUN GPIO1- NC pin GPU_GPIO12 AL16 TX_DEEMPH_EN GPIO1 0: Tx de-emphasis diabled for mobile mode
10K_0402_5% 1 @ 2 RV77 GPU_GPIO2 GPU_GPIO13 AM16 GPIO_12 AD34
10mil
+AVDD (1.8V@65mA AVDD) 1 2 1: Tx de-emphasis enabled (Defailt setting for desktop)
GPU_GPIO14 AM14 GPIO_13 AVDD AE34 LV12
T125 GPU_VID3 AM13 GPIO_14_HPD2 AVSSQ BLM15BD121SN1D_0402
CV75
CV76
CV77
10mil 100mA
1U_0402_6.3V6K
10U_0603_6.3V6M
0.1U_0402_16V7K
47 GPU_VID3 GPIO_15_PWRCNTL_0
10K_0402_5% 1 @ 2 RV78 AC_BATT GPU_VID2 AK14 AC33 (1.8V@100mA VDD1DI) 1
+VDD1DI 2 +1.8VGS 1 1 1 @
47 GPU_VID2 GPIO_16 VDD1DI
THM_ALERT# AG30 AC34 LV13
AN14 GPIO_17_THERMAL_INT VSS1DI BLM15BD121SN1D_0402 AMD recommended setting
CV78
CV79
CV80
1U_0402_6.3V6K
10U_0603_6.3V6M
0.1U_0402_16V7K
10K_0402_5% 1 @ 2 RV79 GPU_GPIO8 RV89 1 @ 2 10K_0402_5% AM17 GPIO_18_HPD3
GPIO_19_CTF 1 1 1 @ 2 2 2 MLPS Bit
@
10K_0402_5% 1 @ 2 RV80 GPU_GPIO9 GPU_VID1 AL13 AC30 strap R_PU R_PD C
47 GPU_VID1 GPIO_20_PWRCNTL_1 R2/NC
GPIO21_BBEN AJ14 AC31
T78 AK13 GPIO_21_BB_EN R2B/NC
@ GPIO_22_ROMCSB 2 2 2 PS0: 11001 RV243=8.45K RV201=2K CV335=NC
@
10K_0402_5% 1 2 RV81 GPU_GPIO11 RV81-SUN GPIO11- NC pin VGA_CLKREQ#_R AN13 AD30
10K_0402_5% 1 @ 2 RV82 GPU_GPIO12 GPIO24_TRSTB AM23 GPIO_23_CLKREQB G2/NC AD31 PS_1
JTAG_TRSTB G2B/NC PS1: 11000 RV237=NC RV238=4.75K CV329=NC
10K_0402_5% 1 @ 2 RV83 GPU_GPIO13 GPIO25_TDI AN23
GPIO26_TCK AK23 JTAG_TDI AF30
JTAG_TCK B2/NC PS2: 00000 RV239=NC RV240=4.75K CV331=0.68u
GPIO27_TMS AL24 AF31
T79 GPIO28_TDO AM24 JTAG_TMS B2B/NC RV246
AJ19 JTAG_TDO 1 2 +DPLL_PVDD
AK19 GENERICA AC32 @ 0_0402_5%
AJ20 GENERICB C/NC AD32 RV247
+3VGS AK20 GENERICC Y/NC AF32 1 2 DPLL_PVSS
Add 12/8
AJ24 GENERICD COMP/NC @ 0_0402_5%
10K_0402_5% 1 @ 2 RV85 GPIO24_TRSTB AH26 GENERICE_HPD4 DAC2
10K_0402_5% 1 @ 2 RV86 GPIO25_TDI AH24 GENERICF_HPD5 AD29 GENLK_CLK T80
10K_0402_5% 1 @ 2 RV87 GPIO27_TMS GENERICG_HPD6 H2SYNC/GENLK_CLK AC29 GENLK_VSYNC T81
V2SYNC/GENLK_VSYNC
10K_0402_5% 1 @ 2 RV88 GPIO26_TCK AK24
HPD1 AG31 PS_2
VDD2DI/NC AG32 SUN_GPIO29 T123
VSS2DI/NC
0.60 V level, Please
AG33 SUN_GPIO30 T124
+1.8VGS
VREFG Divider ans A2VDD/NC
cap close to ASIC 20mil AD33 PS_3
+1.8VGS @
2 RV93 1 499_0402_1% +VREFG_GPU AH13 A2VDDQ/NC RV207
VREFG AF33 1 2
LV14
(Thames 75mA) 2
@
RV95 1 249_0402_1% A2VSSQ/TSVSSQ
2 1 +DPLL_PVDD
TH@ 0_0402_5%
BLM15BD121SN1D_0402 2 1 20mil AA29 NC_TSVSSQ should be tied to GND on Thames/Seymour
CV81 0.1U_0402_16V7K@ +DPLL_PVDD AM32 R2SET/NC
CV82
CV83
CV84
DIS@
1U_0402_6.3V6K
10U_0603_6.3V6M
0.1U_0402_16V7K
1 2 DPLL_PVSS AN32 DPLL_PVDD
1 1 1 @ RV248 DPLL_PVSS
ShortPad 0_0402_5%
B
20mil DDC/AUX AM26
B
+DPLL_VDDC AN31 PLL/CLOCK DDC1CLK AN26
2 2 2 +3VGS DPLL_VDDC DDC1DATA
DIS@
DIS@
DIS@
AM27
XTALIN AV33 AUX1P AL27
XTALIN XTALIN AUX1N
1
XTALOUT AU34
RV235
Voltage Swing: 1.8 V XTALOUT AM19
+1.0VGS (Thames 125mA) DDC2CLK AL19
10K_0402_5%
LV15 AW34 DDC2DATA
0.935V@Mars Pro @ XO_IN
2 1 +DPLL_VDDC AN20
2
BLM15BD121SN1D_0402 TS_FDO AW35 AUX2P AM20
XO_IN2 AUX2N
CV86
CV87
CV88
DIS@
1U_0402_6.3V6K
10U_0603_6.3V6M
0.1U_0402_16V7K
1 1 1 AL30
RV236 DDCCLK_AUX3P AM30
DDCDATA_AUX3N
10K_0402_5%
AL29
2 2 2 MARS@ GPU_THERMAL_D+ AF29 DDCCLK_AUX4P AM29
DIS@
DIS@
DIS@
GPU_THERMAL_D- AG29 DPLUS THERMAL DDCDATA_AUX4N
DMINUS AN21
Add 12/6 for MLPS DDCCLK_AUX5P AM21
TS_FDO AK32 DDCDATA_AUX5N
TS_FDO AJ30
RV97 (Thames 5mA) AL31 DDC6CLK AJ31
XTALOUT
DIS@ XTALIN TS_A/NC DDC6DATA
(1.8V@20mA TSVDD)
LV16 AK30
1M_0402_5% 1 2 +TSVDD
10mil
AJ32 DDCCLK_AUX7P AK29
YV1 +1.8VGS TSVDD DDCDATA_AUX7N
BLM15BD121SN1D_0402 AJ33
1U_0402_6.3V6K
10U_0603_6.3V6M
0.1U_0402_16V7K
TSVSS
CV91
CV92
CV93
DIS@ 1 1 1
3 1 VGA Thermal Sensor ADM1032ARMZ
DIS@
3
GND GND
1
DIS@ +3VGS
Internal VGA Thermal Sensor
1
THAMES XT M2
Closed to GPU
DIS@
DIS@
DIS@
CV94 CV95 2 2 2 +3VGS +3VGS
10P_0402_50V8J 4 2 10P_0402_50V8J @
2
27MHZ_10PF_7V27000050 +3VGS
@ @
1
MARS@ 2 MARS@
2
DIS@ CV85 RV96
RV90 RV91
10K_0402_5% 10K_0402_5%
0.1U_0402_16V7K 4.7K_0402_5%
1
2
2
2
UV14
1
+3VGS 1 8 VGA_SMB_CK2 VGA_SMB_CK2 1 6
VDD SCLK EC_SMB_CK2 36,7
@
5
close to YV1 GPU_THERMAL_D+ 2 7 VGA_SMB_DA2 QV15A
CV89 D+ SDATA
@ DMN66D0LDW-7_SOT363-6
1
A +3VGS A
1 2 XTALIN 1 2 3 6 THM_ALERT# VGA_SMB_DA2 4 3
20 VGA_X1 D- ALERT# EC_SMB_DA2 36,7
RV199 RV232 0_0402_5%
2.2K_0402_5% GPU_THERMAL_D- 2200P_0402_50V7K 4 5 @
QV15B
@ THERM# GND
@ DMN66D0LDW-7_SOT363-6
2
G
@
2
EMC1402-2-ACZL-TR MSOP 1 2
1 3 VGA_CLKREQ#_R +3VGS
14 PEG_CLKREQ# @ RV92 ShortPad
@0_0402_5%
MARS@2 1 2
D
@
2N7002_SOT23-3
1
RV98 4.7K_0402_5%
Address:100_1101 RV94 ShortPad 0_0402_5%
QV28 SA00001Z710 12/12 Update
2 RV200 1
0_0402_5%
@
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/09/11 Deciphered Date 2014/03/12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ATI_ThamesXT_M2_Main_MSIC
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9103P
Date: Wednesday, July 10, 2013 Sheet 22 of 52
5 4 3 2 1
5 4 3 2 1
PX_MODE=1 for Normal Operation
PX_MODE=0 for BACO mode to shut down power rails expcept VDDR3,PCIE_VDDC and 1.8V rail Switch circuits in BACO desingns for Thanes/Seymour only
[email protected], in BACO mode
+3VGS
+1.0VGS +BIF_VDDC +VGA_CORE
D 60mil D
60mil 60mil
1
@ MARS@
RV105 1 2 1 RV234 2
20K_0402_5% RV103 0_0805_5% TH@ 0_0603_5%
1 for PX5.0
CV97
2
PXS_PWREN 1
@ 2 PX_MODE DIS@ 22U_0805_6.3V6M
14,45,47 PXS_PWREN PX_MODE 36,44,47,48 2
RV233 ShortPad 0_0402_5%
1
CV100
for PX4.0 and PX5.0 1U_0603_10V6K
2
@
+3.3VS TO +3.3VGS
+3VS +3VGS
10U_0603_6.3V6M 1U_0603_10V6K
1
1 1
CV101 CV102 RV106
DIS@ DIS@ 470_0603_5%
@
3 1 2 2
2
DIS@
1
QV22 D
+5VALW DIS@ DIS@ AP2301GN-HF_SOT23-3 2
2
G
C RV107 PXS_PWREN# RV108 S QV23 C
3
2N7002K_SOT23-3
20K_0402_5% 1.1K_0402_1% @
DIS@
1
1
D CV103 PXS_PWREN#
PXS_PWREN 2 0.1U_0603_16V7K
G
2
DIS@ S
3
QV24
2N7002K_SOT23-3
+1.5V TO +1.5VGS
+1.5V +1.5VGS
+1.5VGPU 與+1.5VP共共共
DIS@
UV17
10U_0603_6.3V6M AO4304L_SO8
8 1 10U_0603_6.3V6M
10U_0603_6.3V6M 1 1 7 2 1 1
1
CV309 CV104 6 3 CV105 CV106
DIS@ DIS@ 5 DIS@ 1U_0603_10V6K RV111 @
470_0603_5%
2 2 2 2 DIS@
1 2
B
Note: B+_BIAS D
B
PX4.0 +VGA_CORE,VDDCI,+1.5VGS OFF 2
G
1
PX4.0 +3VGS, +1.0VGS,+1.8VGS ON S QV26 @
3
RV112 2N7002K_SOT23-3
PX5.0 +3VGS,+VGA_CORE,VDDCI,+1.5VGV,+1.0VGS,+1.8VGS OFF 300K_0402_5%
+3VALW DIS@ DIS@
2
20K_0402_5%
RV113
1
DIS@ PX_MODE#
6
RV114
2
100K_0402_5% DIS@ 1 DIS@
RV115 DIS@
3 2
PX_MODE# 2 QV27A CV107
DMN66D0LDW-7_SOT363-6
2M_0402_5%~D 0.1U_0603_25V7K
2
DIS@
Power Seguence of Thames and Chelsea
1
PX_MODE 5 QV27B
1
DMN66D0LDW-7_SOT363-6
4
RV117
100K_0402_5%
+3VGS DIS@
2
+VGA_CORE
+VDDCI
A
+1.8VGS A
+1.0VGS
+1.5VGS <20ms
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/09/11 Deciphered Date 2014/03/12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ATI_ThamesXT_M2_BACO POWER
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9103P
Date: Wednesday, July 10, 2013 Sheet 23 of 52
5 4 3 2 1
5 4 3 2 1
UV1F
AB39 A3
E39 PCIE_VSS#1 GND#1 A37
F34 PCIE_VSS#2 GND#2 AA16
F39 PCIE_VSS#3 GND#3 AA18
G33 PCIE_VSS#4 GND#4 AA2
G34 PCIE_VSS#5 GND#5 AA21
H31 PCIE_VSS#6 GND#6 AA23
H34 PCIE_VSS#7 GND#7 AA26
D PCIE_VSS#8 GND#8 D
H39 AA28
J31 PCIE_VSS#9 GND#9 AA6
J34 PCIE_VSS#10 GND#10 AB12
K31 PCIE_VSS#11 GND#11 AB15
K34 PCIE_VSS#12 GND#12 AB17
K39 PCIE_VSS#13 GND#13 AB20
(Thames 330mA) L31 PCIE_VSS#14 GND#14 AB22
+DPAB_VDD18 +1.8VGS L34 PCIE_VSS#15 GND#15 AB24
M34 PCIE_VSS#16 GND#16 AB27
1.8V@300mA DPAB_VDD18) PCIE_VSS#17 GND#17
+DPAB_VDD18 1 RV118 2 M39 AC11
N31 PCIE_VSS#18 GND#18 AC13
1 1 1 PCIE_VSS#19 GND#19
CV108
CV109
CV110
0_0402_5% N34 AC16
10U_0603_6.3V6M
0.1U_0402_16V7K
1U_0402_6.3V6K
UV1H P31 PCIE_VSS#20 GND#20 AC18
(Thames 330mA) 20mil @ P34 PCIE_VSS#21 GND#21 AC2
+1.8VGS +DPCD_VDD18 DP C/D POWER @ 2@ 2@ 2 P39 PCIE_VSS#22 GND#22 AC21
1.8V@300mA DPCD_VDD18) DP A/B POWER 20mil PCIE_VSS#23 GND#23
130mA R34 AC23
1 RV119 2 +DPCD_VDD18 AP20 AN24 T31 PCIE_VSS#24 GND#24 AC26
AP21 DPCD/DPC_VDD18#1 DPAB/DPA_VDD18#1 AP24 T34 PCIE_VSS#25 GND#25 AC28
DPCD/DPC_VDD18#2 DPAB/DPA_VDD18#2 (Thames 330mA) PCIE_VSS#26 GND#26
CV111
CV112
CV113
0_0402_5% T39 AC6
10U_0603_6.3V6M
1U_0402_6.3V6K
0.1U_0402_16V7K
+DPCD_VDD10 +DPAB_VDD10 +1.0VGS U31 PCIE_VSS#27 GND#27 AD15
@ 1 1 1 20mil (1.0V@220mA DPAB_VDD10) PCIE_VSS#28 GND#28
20mil 110mA 0.935V@Mars Pro U34 AD17
@ @ @ AP13 AP31 +DPAB_VDD10 1 RV120 2 V34 PCIE_VSS#29 GND#29 AD20
AT13 DPCD/DPC_VDD10#1 DPAB/DPA_VDD10#1 AP32 V39 PCIE_VSS#30 GND#30 AD22
10U_0603_6.3V6M
0.1U_0402_16V7K
1U_0402_6.3V6K
2 2 2 DPCD/DPC_VDD10#2 DPAB/DPA_VDD10#2 PCIE_VSS#31 GND#31
CV114
CV115
CV116
0_0402_5% W31 AD24
W34 PCIE_VSS#32 GND#32 AD27
1 1 1
AN17 AN27 @ Y34 PCIE_VSS#33 GND#33 AD9
AP16 DP/DPC_VSSR#1 DP/DPA_VSSR#1 AP27 @ @ @ Y39 PCIE_VSS#34 GND#34 AE2
AP17 DP/DPC_VSSR#2 DP/DPA_VSSR#2 AP28 PCIE_VSS#35 GND#35 AE6
AW14 DP/DPC_VSSR#3 DP/DPA_VSSR#3 AW24 2 2 2 GND#36 AF10
(Thames 220mA) +DPCD_VDD10 AW16 DP/DPC_VSSR#4 DP/DPA_VSSR#4 AW26 GND#37 AF16
+1.0VGS DP/DPC_VSSR#5 DP/DPA_VSSR#5 GND#38 AF18
1.0V@220mA DPCD_VDD10) GND#39
0.935V@Mars Pro +DPCD_VDD18 +DPAB_VDD18 AF21
1 RV121 2
0_0402_5%
+DPCD_VDD10 20mil
AP22
DPCD/DPD_VDD18#1 DPAB/DPB_VDD18#1
20mil
AP25 130mA F15
GND#100
GND GND#40
GND#41
GND#42
AG17
AG2
@ CV117
@ CV118
@ CV119
AP23 AP26 F17 AG20
10U_0603_6.3V6M
@
1U_0402_6.3V6K
0.1U_0402_16V7K
DPCD/DPD_VDD18#2 DPAB/DPB_VDD18#2 F19 GND#101 GND#43 AG22
1 1 1 GND#102 GND#44
C +DPCD_VDD10 +DPAB_VDD10 F21 AG6 C
F23 GND#103 GND#45 AG9
20mil 20mil GND#104 GND#46
AP14 AN33 110mA F25 AH21
2 2 2 AP15 DPCD/DPD_VDD10#1 DPAB/DPB_VDD10#1 AP33 F27 GND#105 GND#47 AJ10
DPCD/DPD_VDD10#2 DPAB/DPB_VDD10#2 F29 GND#106 GND#48 AJ11
F31 GND#107 GND#49 AJ2
F33 GND#108 GND#50 AJ28
AN19 AN29 F7 GND#109 GND#51 AJ6
AP18 DP/DPD_VSSR#1 DP/DPB_VSSR#1 AP29 F9 GND#110 GND#52 AK11
AP19 DP/DPD_VSSR#2 DP/DPB_VSSR#2 AP30 G2 GND#111 GND#53 AK31
AW20 DP/DPD_VSSR#3 DP/DPB_VSSR#3 AW30 G6 GND#112 GND#54 AK7
AW22 DP/DPD_VSSR#4 DP/DPB_VSSR#4 AW32 H9 GND#113 GND#55 AL11
DP/DPD_VSSR#5 DP/DPB_VSSR#5 J2 GND#114 GND#56 AL14
J27 GND#115 GND#57 AL17
J6 GND#116 GND#58 AL2
150_0402_1% 2
@ 1 RV122 AW18 AW28 RV123 1
@ 2 150_0402_1% J8 GND#117 GND#59 AL20
DPCD_CALR DPAB_CALR K14 GND#118 GND#60 AL21
+1.8VGS (Thames 330mA) +DPEF_VDD18 +DPAB_VDD18 K7 GND#119 GND/PX_EN#61 AL23
L11 GND#120 GND#62 AL26
1.8V@300mA DPEF_VDD18) 20mil DP E/F POWER DP PLL POWER 20mA 10mil GND#121 GND#63
1 RV124 2 +DPEF_VDD18 AH34 AU28 L17 AL32
DPEF/DPE_VDD18#1 DPAB_VDD18/DPA_PVDD GND#122 GND#64
1
AJ34 AV27 L2 AL6
DPEF/DPE_VDD18#2 DP_VSSR/DPA_PVSS GND#123 GND#65
@ CV120
@ CV121
@ CV122
0_0402_5% L22 AL8 RV125
10U_0603_6.3V6M
1U_0402_6.3V6K
0.1U_0402_16V7K
+DPEF_VDD10 +DPAB_VDD18 L24 GND#124 GND#66 AM11 4.7K_0402_5%
1 1 1
@ 20mil 20mA 10mil L6 GND#125 GND#67 AM31 DIS@
AL33 AV29 M17 GND#126 GND#68 AM9
2
AM33 DPEF/DPE_VDD10#1 DPAB_VDD18/DPB_PVDD AR28 M22 GND#127 GND#69 AN11
2 2 2 DPEF/DPE_VDD10#2 DP_VSSR/DPB_PVSS M24 GND#128 GND#70 AN2
+DPCD_VDD18 N16 GND#129 GND#71 AN30
N18 GND#130 GND#72 AN6
20mA 10mil GND#131 GND#73
AN34 AU18 N2 AN8
AP39 DP/DPE_VSSR#1 DPCD_VDD18/DPC_PVDD AV17 N21 GND#132 GND#74 AP11
+DPEF_VDD10 AR39 DP/DPE_VSSR#2 DP_VSSR/DPC_PVSS N23 GND#133 GND#75 AP7
(Thames 220mA) AU37 DP/DPE_VSSR#3 +DPCD_VDD18 N26 GND#134 GND#76 AP9
+1.0VGS DP/DPE_VSSR#4 N6 GND#135 GND#77 AR5
1.0V@240mA DPEF_VDD10) 20mA 10mil GND#136 GND#78
0.935V@Mars Pro AV19 R15 B11
1 RV126 2 +DPEF_VDD10 +DPEF_VDD18 DPCD_VDD18/DPD_PVDD AR18 R17 GND#137 GND#79 B13
DP_VSSR/DPD_PVSS R2 GND#138 GND#80 B15
20mil GND#139 GND#81
@ CV123
@ CV124
@ CV125
0_0402_5% AF34 +DPEF_VDD18 R20 B17
10U_0603_6.3V6M
1U_0402_6.3V6K
0.1U_0402_16V7K
B DPEF/DPF_VDD18#1 GND#140 GND#82 B
1 1 1 AG34 20mA 10mil R22 B19
@ DPEF/DPF_VDD18#2 AM37 R24 GND#141 GND#83 B21
+DPEF_VDD10 DPEF_VDD18/DPE_PVDD AN38 R27 GND#142 GND#84 B23
DP_VSSR/DPE_PVSS R6 GND#143 GND#85 B25
2 2 2 20mil GND#144 GND#86
AK33 +DPEF_VDD18 T11 B27
AK34 DPEF/DPF_VDD10#1 T13 GND#145 GND#87 B29
DPEF/DPF_VDD10#2
20mA 10mil GND#146 GND#88
AL38 T16 B31
DPEF_VDD18/DPF_PVDD AM35 T18 GND#147 GND#89 B33
DP_VSSR/DPF_PVSS T21 GND#148 GND#90 B7
AF39 T23 GND#149 GND#91 B9
AH39 DP/DPF_VSSR#1 T26 GND#150 GND#92 C1
AK39 DP/DPF_VSSR#2 U15 GND#151 GND#93 C39
AL34 DP/DPF_VSSR#3 U17 GND#153 GND#94 E35
PS_0 AM34 DP/DPF_VSSR#4 U2 GND#154 GND#95 E5
DP/DPF_VSSR#5 U20 GND#155 GND#96 F11
U22 GND#156 GND#97 F13
+1.8VGS U24 GND#157 GND#98
AM39 U27 GND#158
DPEF_CALR U6 GND#159
V11 GND#160
GND#161
1
THAMES XT M2 V16
GND#163
1
RV127 @ V18
RV243 150_0402_1% V21 GND#164
V23 GND#165
8.45K_0402_1% @ V26 GND#166
MARS@
2
W2 GND#167
2
W6 GND#168
PS_0 Y15 GND#169
RV201 Y17 GND#170
Y20 GND#171
GND#172
1
Y22 A39 MECH#1
0.68U_0402_10V
1 GND#173 VSS_MECH#1
RV201 Y24 AW1 MECH#2 T82 PAD
MARS@ CV335 Y27 GND#174 VSS_MECH#2 AW39MECH#3 T83 PAD
0_0402_5% GND#175 VSS_MECH#3
U13 T84 PAD
2K_0402_1% TH@ @ 2 V13 GND#152
2
GND#162
A Thames/Seymour Only THAMES XT M2 A
@
Do not install for Heathrow/Chelsea
PS_0 Should be tied to GND on Thames/Seymour
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/09/11 Deciphered Date 2014/03/12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ATI_ThamesXT_M2_PWR_GND
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-9103P
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, July 10, 2013 Sheet 24 of 52
5 4 3 2 1
5 4 3 2 1
(Thames 440mA) +1.8VGS
(1.8V@504mA PCIE_VDDR) @ LV17
+PCIE_VDDR 2 1
MBK1608121YZF_0603
CV126
CV127
CV128
CV129
CV130
CV131
10U_0603_6.3V6M
0.1U_0402_16V7K
0.1U_0402_16V7K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 1 1 1
2 2 2 2 2 2
For Thames/Seymour
@
UV1E
40mA +1.8VGS BIF_VDDC is connected to VDDC in non BACO designsIn
For DDR3 MVDDQ = 1.5V (1.8V@40mA PCIE_PVDD) DIS@ LV18 BACO designs, switch circuits is required so that
+1.5VGS MEM I/O 2 1
D (Thames 1.7)A 40mil when GPU is operating, BIF_VDDC is connected to VDDC, D
CV132
CV133
CV134
PCIE MBK1608121YZF_0603
10U_0603_6.3V6M
Add 12/8
0.1U_0402_16V7K
1U_0402_6.3V6K
AC7 AA31 while in BACO mode, BIF_VDDC is connected to +1.0V
VDDR1#1 PCIE_VDDR#1 1 1 1
330U_D2_2VM_R6M
330U_D2_2VM_R6M
AD11 AA32 RV244
VDDR1#2 PCIE_VDDR#2
330U_2.5V_M
CV136
CV137
CV138
CV139
CV140
CV141
CV142
CV143
CV144
CV145
AF7 AA33 1 2 +PCIE_VDDR For MARS/VENUS/HEATHROW/CHELSEA
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
CV332 1 1 1 VDDR1#3 PCIE_VDDR#3
1 1 1 1 1 1 1 1 1 1 AG10 AA34 TH@ 0_0402_5%
VDDR1#4 PCIE_VDDR#4 2 2 2 BIF_VDDC should be connectted with 0.95V
CV330
CV135
@
@
+ + + AJ7 V28
DIS@
DIS@
DIS@
+BIF_R RV245
AK8 VDDR1#5 PCIE_VDDR#5 W29 1 2
VDDR1#6 PCIE_VDDR#6 +BIF_VDDC
AL9 W30
DIS@
@ 0_0402_5%
2 2 2 2 2 2 2 2 2 2 2 2 2 G11 VDDR1#7 PCIE_VDDR#7 Y31 +1.0VGS
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
G14 VDDR1#8 PCIE_VDDR#8 AB37 +PCIE_PVDD
G17 VDDR1#9 PCIE_VDDR/PCIE_PVDD
G20 VDDR1#10 G30
G23 VDDR1#11 PCIE_VDDC#1 G31
VDDR1#12 PCIE_VDDC#2
CV146
CV147
CV148
CV149
CV150
CV151
G26 H29
(Thames 1.1A)
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
G29 VDDR1#13 PCIE_VDDC#3 H30
VDDR1#14 PCIE_VDDC#4 1 1 1 1 1 1
H10 J29 (1.0V@1920mA PCIE_VDDC)
+1.5VGS J7 VDDR1#15 PCIE_VDDC#5 J30
J9 VDDR1#16 PCIE_VDDC#6 L28
K11 VDDR1#17 PCIE_VDDC#7 M28 2 2 2 2 2 2 (Chelsea) On Heathrow/Chelsea/Venus/Mars only
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
K13 VDDR1#18 PCIE_VDDC#8 N28
VDDR1#19 PCIE_VDDC#9 ([email protected] PCIE_VDDC for GEN3) PCIE_VDDC : 0.95V @ 1.3A (GEN3.0)
CV152
CV153
CV154
CV155
CV156
K8 R28
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
L12 VDDR1#20 PCIE_VDDC#10 T28
1 1 1 1 1 VDDR1#21 PCIE_VDDC#11
L16 U28
L21 VDDR1#22 PCIE_VDDC#12 +VGA_CORE
L23 VDDR1#23
2 2 2 2 2 L26 VDDR1#24 AA15
(Thames 20.5A)
DIS@
DIS@
DIS@
DIS@
DIS@
VDDR1#25 VDDC#1
330U_D2_2VM_R6M
L7 CORE AA17
VDDR1#26 VDDC#2
CV157
CV158
CV159
CV160
CV161
CV162
CV163
CV164
CV165
CV166
CV167
CV168
CV169
M11 AA20
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
VDDR1#27 VDDC#3 1
N11 AA22 1 1 1 1 1 1 1 1 1 1 1 1 1
VDDR1#28 VDDC#4
CV327
P7 AA24 +
DIS@
R11 VDDR1#29 VDDC#5 AA27
U11 VDDR1#30 VDDC#6 AB16
+1.8VGS +VDDC_CT U7 VDDR1#31 VDDC#7 AB18 2 2 2 2 2 2 2 2 2 2 2 2 2 2
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
(Thames 250mA) Y11 VDDR1#32 VDDC#8 AB21
DIS@ LV19 Y7 VDDR1#33 VDDC#9 AB23
(1.8V@110mA VDD_CT) VDDR1#34 VDDC#10
1 2 AB26
BLM15BD121SN1D_0402 VDDC#11 AB28
C VDDC#12 C
+VGA_CORE
CV170
CV171
CV172
CV173
CV174
10U_0603_6.3V6M AC17
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0402_16V7K
VDDC#13 AC20
1 1 1 1 1 VDDC#14
LEVEL AC22
+3VGS 20mil TRANSLATION VDDC#15 AC24
VDDC#16
POWER
CV175
CV176
CV177
CV178
CV179
CV180
CV181
CV182
CV183
CV184
CV185
CV186
AF26 AC27
(Thames 60mA)
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
2 2 2 2 2 AF27 VDD_CT#1 VDDC#17 AD18
DIS@
DIS@
DIS@
DIS@
DIS@
VDD_CT#2 VDDC#18 1 1 1 1 1 1 1 1 1 1 1 1
AG26 AD21
VDD_CT#3 VDDC#19
CV187
CV188
CV189
CV190
AG27 AD23
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
VDD_CT#4 VDDC#20 AD26
1 1 1 1 VDDC#21 AF17 2 2 2 2 2 2 2 2 2 2 2 2
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
10mil I/O VDDC#22 AF20
AF23 VDDC#23 AF22
2 2 2 2 AF24 VDDR3#1 VDDC#24 AG16
DIS@
DIS@
DIS@
DIS@
AG23 VDDR3#2 VDDC#25 AG18
AG24 VDDR3#3 VDDC#26 AG21 +VGA_CORE
+1.8VGS VDDR3#4 VDDC#27 AH22
LV20 @
20mil VDDC#28 AH27
1 2 +VDDR4 AF13 VDDC#29 AH28
VDDR4#4 VDDC#30
CV365
CV366
CV367
CV191
CV192
BLM15BD121SN1D_0402 AF15 M26
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
22U_0603_6.3V6M
VDDR4#5 VDDC#31
CV193
CV194
AG13 N24
1U_0402_6.3V6K
0.1U_0402_16V7K
VDDR4#7 VDDC#32 1 1 1 1 1
1 1 AG15 N27
VDDR4#8 VDDC/BIF_VDDC#33 R18
VDDC#34 R21
AD12 VDDC#35 R23 2 2 2 2 2
DIS@
DIS@
DIS@
DIS@
DIS@
2 2 VDDR4#1 VDDC#36
@
AF11 R26
AF12 VDDR4#2 VDDC#37 T17
AG11 VDDR4#3 VDDC#38 T20
VDDR4#6 VDDC#39 T22 +BIF_VDDC
VDDC#40 T24
+1.8VGS (M97, (Thames 150mA)
Broadway and Madison: 1.8V@150mA MPV18)
VDDC#41 T27 55mA
VDDC/BIF_VDDC#42 U16
VDDC#43
CV195
CV196
LV21 DIS@ M20 U18 For non-BACO designs, connect BIF_VDDC to VDDC.
1U_0402_6.3V6K
1U_0402_6.3V6K
1 2 M21 NC_VDDRHA VDDC#44 U21 1 1
MCK1608471YZF 0603 NC_VSSRHA VDDC#45 U23 For BACO designs - see BACO reference schematics
+1.8VGS (Thames 50mA) VDDC#46 U26
VDDC#47
CV197
CV198
CV199
LV22
DIS@ (1.8V@75mA SPV18) V12 V17
10U_0603_6.3V6M
1U_0402_6.3V6K
0.1U_0402_16V7K
1 2 U12 NC_VDDRHB VDDC#48 V20 2 2
DIS@
DIS@
B 1 1 1 NC_VSSRHB VDDC#49 B
BLM15BD121SN1D_0402 V22
VDDC#50
CV200
CV201
CV202
V24
10U_0603_6.3V6M
1U_0402_6.3V6K
0.1U_0402_16V7K
VDDC#51 V27
1 1 1 VDDC#52
2 2 2 Y16
DIS@
DIS@
DIS@
PLL VDDC#53 Y18
VDDC#54 Y21
2 2 2 20mil VDDC#55 Y23
DIS@
DIS@
DIS@
+MPV18 H7 VDDC#56 Y26
H8 MPV18#1 VDDC#57 Y28
MPV18#2 VDDC#58
(GDDR3/DDR3 1.12V@4A VDDCI)
+VDDCI +VGA_CORE
+1.0VGS (Thames 100mA) 10mil +SPV18 AM10
0.935V@Mars Pro
LV23 DIS@ SPV18 AA13
(GDDR5 1.12V@16A VDDCI) 16A 1 LV25 2
1 2
(120mA SPV10) 20mil +SPV10 AN9 VDDCI#1 AB13 0_0402_5%
SPV10 VDDCI#2 DIS@
CV203
CV204
CV205
CV206
CV207
CV208
CV209
CV210
CV211
CV212
CV213
CV214
MCK1608471YZF 0603 AC12
10U_0603_6.3V6M
22U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
+VDDCI +VGA_CORE VDDCI#3
CV215
CV216
CV217
AN10 AC15 1 LV26 2
10U_0603_6.3V6M
1U_0402_6.3V6K
0.1U_0402_16V7K
SPVSS VDDCI#4 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 AD13 DIS@ 0_0402_5%
VDDCI#5 AD16
VDDCI#6
1
M15
VDDCI#7 M16 2 2 2 2 2 2 2 2 2 2 2 2
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
RV215 RV202
2 2 2 VDDCI#8 M18
DIS@
DIS@
DIS@
10_0402_1% 10_0402_1% VOLTAGE
DIS@ DIS@ SENESE VDDCI#9 M23
VDDCI#10 N13
10mil
2
VGA_CORE_SEN AF28 VDDCI#11 N15
47 VCCSENSE_VGA FB_VDDC VDDCI#12 N17
VDDCI#13
CV325
CV324
CV322
CV323
10mil N20
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1U_0402_6.3V6K
VDDCI_SEN AG28 VDDCI#14 N22
48 VDDCI_SEN FB_VDDCI 1 1 1 1
ISOLATED VDDCI#15 R12
CORE I/O VDDCI#16 R13
VSSSENSE_VGA AH29 VDDCI#17 R16
47 VSSSENSE_VGA FB_GND VDDCI#18 T12 2 2 2 2
DIS@
DIS@
DIS@
DIS@
VDDCI#19
1
T15
RV204 VDDCI#20 V15
DIS@ 10_0402_1% VDDCI#21 Y13
VDDCI#22
VDDCI and VDDC should have seperate regulators with a merge option on PCB
2
A THAMES XT M2 A
@
For Madison, Park, Capilano, Robson, Seymour and Whistler, VDDCI and VDDC can share one common regulator
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/09/11 Deciphered Date 2014/03/12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ATI_ThamesXT_M2_Power
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-9103P
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, July 10, 2013 Sheet 25 of 52
5 4 3 2 1
5 4 3 2 1
UV1C MDA[0..63] UV1D MDB[0..63]
DDR2 DDR2 27 MDA[0..63] DDR2 DDR2 28 MDB[0..63]
GDDR3/GDDR5 GDDR5/GDDR3 GDDR3/GDDR5 GDDR5/GDDR3
DDR3 DDR3 MAA[12..0] DDR3 DDR3 MAB[12..0]
C37 G24 MAA[12..0] 27 C5 P8 MAB[12..0] 28
MDA0 MAA0 MDB0 MAB0
MDA1 C35 DQA0_0/DQA_0 MAA0_0/MAA_0 J23 MAA1 A_BA[2..0] MDB1 C3 DQB0_0/DQB_0 MAB0_0/MAB_0 T9 MAB1 B_BA[2..0]
A35 DQA0_1/DQA_1 MAA0_1/MAA_1 H24 A_BA[2..0] 27 E3 DQB0_1/DQB_1 MAB0_1/MAB_1 P9 B_BA[2..0] 28
MDA2 MAA2 MDB2 MAB2
MDA3 E34 DQA0_2/DQA_2 MAA0_2/MAA_2 J24 MAA3 MDB3 E1 DQB0_2/DQB_2 MAB0_2/MAB_2 N7 MAB3
MDA4 G32 DQA0_3/DQA_3 MAA0_3/MAA_3 H26 MAA4 MDB4 F1 DQB0_3/DQB_3 MAB0_3/MAB_3 N8 MAB4
MEMORY INTERFACE A
MDA5 D33 DQA0_4/DQA_4 MAA0_4/MAA_4 J26 MAA5 MDB5 F3 DQB0_4/DQB_4 MAB0_4/MAB_4 N9 MAB5
MEMORY INTERFACE B
MDA6 F32 DQA0_5/DQA_5 MAA0_5/MAA_5 H21 MAA6 MDB6 F5 DQB0_5/DQB_5 MAB0_5/MAB_5 U9 MAB6
MDA7 E32 DQA0_6/DQA_6 MAA0_6/MAA_6 G21 MAA7 MDB7 G4 DQB0_6/DQB_6 MAB0_6/MAB_6 U8 MAB7
MDA8 D31 DQA0_7/DQA_7 MAA0_7/MAA_7 H19 MAA8 MDB8 H5 DQB0_7/DQB_7 MAB0_7/MAB_7 Y9 MAB8
MDA9 F30 DQA0_8/DQA_8 MAA1_0/MAA_8 H20 MAA9 MDB9 H6 DQB0_8/DQB_8 MAB1_0/MAB_8 W9 MAB9
MDA10 C30 DQA0_9/DQA_9 MAA1_1/MAA_9 L13 MAA10 MDB10 J4 DQB0_9/DQB_9 MAB1_1/MAB_9 AC8 MAB10
D DQA0_10/DQA_10 MAA1_2/MAA_10 DQB0_10/DQB_10 MAB1_2/MAB_10 D
MDA11 A30 G16 MAA11 MDB11 K6 AC9 MAB11
MDA12 F28 DQA0_11/DQA_11 MAA1_3/MAA_11 J16 MAA12 MDB12 K5 DQB0_11/DQB_11 MAB1_3/MAB_11 AA7 MAB12
MDA13 C28 DQA0_12/DQA_12 MAA1_4/MAA_12 H16 A_BA2 MDB13 L4 DQB0_12/DQB_12 MAB1_4/MAB_12 AA8 B_BA2
MDA14 A28 DQA0_13/DQA_13 MAA1_5/MAA_13_BA2 J17 A_BA0 MDB14 M6 DQB0_13/DQB_13 MAB1_5/BA2 Y8 B_BA0
MDA15 E28 DQA0_14/DQA_14 MAA1_6/MAA_14_BA0 H17 A_BA1 MDB15 M1 DQB0_14/DQB_14 MAB1_6/BA0 AA9 B_BA1
MDA16 D27 DQA0_15/DQA_15 MAA1_7/MAA_A15_BA1 MDB16 M3 DQB0_15/DQB_15 MAB1_7/BA1
F26 DQA0_16/DQA_16 A32 DQMA#[7..0] 27 M5 DQB0_16/DQB_16 H3 DQMB#[7..0] 28
MDA17 DQMA#0 MDB17 DQMB#0
MDA18 C26 DQA0_17/DQA_17 WCKA0_0/DQMA_0 C32 DQMA#1 MDB18 N4 DQB0_17/DQB_17 WCKB0_0/DQMB_0 H1 DQMB#1
MDA19 A26 DQA0_18/DQA_18 WCKA0B_0/DQMA_1 D23 DQMA#2 MDB19 P6 DQB0_18/DQB_18 WCKB0B_0/DQMB_1 T3 DQMB#2
MDA20 F24 DQA0_19/DQA_19 WCKA0_1/DQMA_2 E22 DQMA#3 MDB20 P5 DQB0_19/DQB_19 WCKB0_1/DQMB_2 T5 DQMB#3
MDA21 C24 DQA0_20/DQA_20 WCKA0B_1/DQMA_3 C14 DQMA#4 MDB21 R4 DQB0_20/DQB_20 WCKB0B_1/DQMB_3 AE4 DQMB#4
MDA22 A24 DQA0_21/DQA_21 WCKA1_0/DQMA_4 A14 DQMA#5 MDB22 T6 DQB0_21/DQB_21 WCKB1_0/DQMB_4 AF5 DQMB#5
MDA23 E24 DQA0_22/DQA_22 WCKA1B_0/DQMA_5 E10 DQMA#6 MDB23 T1 DQB0_22/DQB_22 WCKB1B_0/DQMB_5 AK6 DQMB#6
MDA24 C22 DQA0_23/DQA_23 WCKA1_1/DQMA_6 D9 DQMA#7 MDB24 U4 DQB0_23/DQB_23 WCKB1_1/DQMB_6 AK5 DQMB#7
MDA25 A22 DQA0_24/DQA_24 WCKA1B_1/DQMA_7 MDB25 V6 DQB0_24/DQB_24 WCKB1B_1/DQMB_7
F22 DQA0_25/DQA_25 GDDR5/DDR2/GDDR3 C34 QSA[7..0] 27 V1 DQB0_25/DQB_25 GDDR5/DDR2/GDDR3 F6 QSB[7..0] 28
MDA26 QSA0 MDB26 QSB0
MDA27 D21 DQA0_26/DQA_26 EDCA0_0/QSA_0/RDQSA_0 D29 QSA1 MDB27 V3 DQB0_26/DQB_26 EDCB0_0/QSB_0/RDQSB_0 K3 QSB1
MDA28 A20 DQA0_27/DQA_27 EDCA0_1/QSA_1/RDQSA_1 D25 QSA2 MDB28 Y6 DQB0_27/DQB_27 EDCB0_1/QSB_1/RDQSB_1 P3 QSB2
MDA29 F20 DQA0_28/DQA_28 EDCA0_2/QSA_2/RDQSA_2 E20 QSA3 MDB29 Y1 DQB0_28/DQB_28 EDCB0_2/QSB_2/RDQSB_2 V5 QSB3
MDA30 D19 DQA0_29/DQA_29 EDCA0_3/QSA_3/RDQSA_3 E16 QSA4 MDB30 Y3 DQB0_29/DQB_29 EDCB0_3/QSB_3/RDQSB_3 AB5 QSB4
MDA31 E18 DQA0_30/DQA_30 EDCA1_0/QSA_4/RDQSA_4 E12 QSA5 MDB31 Y5 DQB0_30/DQB_30 EDCB1_0/QSB_4/RDQSB_4 AH1 QSB5
MDA32 C18 DQA0_31/DQA_31 EDCA1_1/QSA_5/RDQSA_5 J10 QSA6 MDB32 AA4 DQB0_31/DQB_31 EDCB1_1/QSB_5/RDQSB_5 AJ9 QSB6
MDA33 A18 DQA1_0/DQA_32 EDCA1_2/QSA_6/RDQSA_6 D7 QSA7 MDB33 AB6 DQB1_0/DQB_32 EDCB1_2/QSB_6/RDQSB_6 AM5 QSB7
F18 DQA1_1/DQA_33 EDCA1_3/QSA_7/RDQSA_7 QSA#[7..0] 27 AB1 DQB1_1/DQB_33 EDCB1_3/QSB_7/RDQSB_7 QSB#[7..0] 28
MDA34 MDB34
MDA35 D17 DQA1_2/DQA_34 A34 QSA#0 MDB35 AB3 DQB1_2/DQB_34 G7 QSB#0
MDA36 A16 DQA1_3/DQA_35 DDBIA0_0/QSA_0B/WDQSA_0 E30 QSA#1 MDB36 AD6 DQB1_3/DQB_35 DDBIB0_0/QSB_0B/WDQSB_0 K1 QSB#1
MDA37 F16 DQA1_4/DQA_36 DDBIA0_1/QSA_1B/WDQSA_1 E26 QSA#2 MDB37 AD1 DQB1_4/DQB_36 DDBIB0_1/QSB_1B/WDQSB_1 P1 QSB#2
MDA38 D15 DQA1_5/DQA_37 DDBIA0_2/QSA_2B/WDQSA_2 C20 QSA#3 MDB38 AD3 DQB1_5/DQB_37 DDBIB0_2/QSB_2B/WDQSB_2 W4 QSB#3
MDA39 E14 DQA1_6/DQA_38 DDBIA0_3/QSA_3B/WDQSA_3 C16 QSA#4 MDB39 AD5 DQB1_6/DQB_38 DDBIB0_3/QSB_3B/WDQSB_3 AC4 QSB#4
MDA40 F14 DQA1_7/DQA_39 DDBIA1_0/QSA_4B/WDQSA_4 C12 QSA#5 MDB40 AF1 DQB1_7/DQB_39 DDBIB1_0/QSB_4B/WDQSB_4 AH3 QSB#5
MDA41 D13 DQA1_8/DQA_40 DDBIA1_1/QSA_5B/WDQSA_5 J11 QSA#6 MDB41 AF3 DQB1_8/DQB_40 DDBIB1_1/QSB_5B/WDQSB_5 AJ8 QSB#6
MDA42 F12 DQA1_9/DQA_41 DDBIA1_2/QSA_6B/WDQSA_6 F8 QSA#7 MDB42 AF6 DQB1_9/DQB_41 DDBIB1_2/QSB_6B/WDQSB_6 AM3 QSB#7
MDA43 A12 DQA1_10/DQA_42 DDBIA1_3/QSA_7B/WDQSA_7 MDB43 AG4 DQB1_10/DQB_42 DDBIB1_3/QSB_7B/WDQSB_7
MDA44 D11 DQA1_11/DQA_43 J21 ODTA0 MDB44 AH5 DQB1_11/DQB_43 T7 ODTB0
F10 DQA1_12/DQA_44 ADBIA0/ODTA0 G19 ODTA0 27 AH6 DQB1_12/DQB_44 ADBIB0/ODTB0 W7 ODTB0 28
MDA45 ODTA1 MDB45 ODTB1
A10 DQA1_13/DQA_45 ADBIA1/ODTA1 ODTA1 27 AJ4 DQB1_13/DQB_45 ADBIB1/ODTB1 ODTB1 28
MDA46 MDB46
MDA47 C10 DQA1_14/DQA_46 H27 CLKA0 MDB47 AK3 DQB1_14/DQB_46 L9 CLKB0
C DQA1_15/DQA_47 CLKA0 CLKA0 27 DQB1_15/DQB_47 CLKB0 CLKB0 28 C
MDA48 G13 G27 CLKA0# MDB48 AF8 L8 CLKB0#
H13 DQA1_16/DQA_48 CLKA0B CLKA0# 27 AF9 DQB1_16/DQB_48 CLKB0B CLKB0# 28
MDA49 MDB49
MDA50 J13 DQA1_17/DQA_49 J14 CLKA1 MDB50 AG8 DQB1_17/DQB_49 AD8 CLKB1
H11 DQA1_18/DQA_50 CLKA1 H14 CLKA1 27 AG7 DQB1_18/DQB_50 CLKB1 AD7 CLKB1 28
MDA51 CLKA1# MDB51 CLKB1#
G10 DQA1_19/DQA_51 CLKA1B CLKA1# 27 AK9 DQB1_19/DQB_51 CLKB1B CLKB1# 28
MDA52 MDB52
MDA53 G8 DQA1_20/DQA_52 K23 RASA0# MDB53 AL7 DQB1_20/DQB_52 T10 RASB0#
K9 DQA1_21/DQA_53 RASA0B K19 RASA0# 27 AM8 DQB1_21/DQB_53 RASB0B Y10 RASB0# 28
MDA54 RASA1# MDB54 RASB1#
K10 DQA1_22/DQA_54 RASA1B RASA1# 27 AM7 DQB1_22/DQB_54 RASB1B RASB1# 28
MDA55 MDB55
MDA56 G9 DQA1_23/DQA_55 K20 CASA0# MDB56 AK1 DQB1_23/DQB_55 W10 CASB0#
A8 DQA1_24/DQA_56 CASA0B K17 CASA0# 27 AL4 DQB1_24/DQB_56 CASB0B AA10 CASB0# 28
MDA57 CASA1# MDB57 CASB1#
C8 DQA1_25/DQA_57 CASA1B CASA1# 27 AM6 DQB1_25/DQB_57 CASB1B CASB1# 28
MDA58 MDB58
MDA59 E8 DQA1_26/DQA_58 K24 CSA0#_0 MDB59 AM1 DQB1_26/DQB_58 P10 CSB0#_0
A6 DQA1_27/DQA_59 CSA0B_0 K27 CSA0#_0 27 AN4 DQB1_27/DQB_59 CSB0B_0 L10 CSB0#_0 28
MDA60 MDB60
MDA61 C6 DQA1_28/DQA_60 CSA0B_1 MDB61 AP3 DQB1_28/DQB_60 CSB0B_1
MDA62 E6 DQA1_29/DQA_61 M13 CSA1#_0 MDB62 AP1 DQB1_29/DQB_61 AD10 CSB1#_0
A5 DQA1_30/DQA_62 CSA1B_0 K16 CSA1#_0 27 AP5 DQB1_30/DQB_62 CSB1B_0 AC10 CSB1#_0 28
MDA63 MDB63
DQA1_31/DQA_63 CSA1B_1 DQB1_31/DQB_63 CSB1B_1
+VDD_MEM15_REFDA L18 K21 CKEA0 U10 CKEB0
+1.5VGS L20 MVREFDA CKEA0 J20 CKEA0 27 CKEB0 CKEB0 28
+VDD_MEM15_REFSA CKEA1 +VDD_MEM15_REFDB Y12 AA11 CKEB1
MVREFSA CKEA1 CKEA1 27 MVREFDB CKEB1 CKEB1 28
+VDD_MEM15_REFSB AA12
RV129 1 TH@ 2 240_0402_1% L27 K26 WEA0# MVREFSB N10 WEB0#
MEM_CALRN0 WEA0B WEA0# 27 WEB0B WEB0# 28
RV130 1 @ 2 240_0402_1% N12 L15 WEA1# AB11 WEB1#
MEM_CALRN1 WEA1B WEA1# 27 WEB1B WEB1# 28
RV131 1 TH@ 2 240_0402_1% AG12
MEM_CALRN2 DIS@
RV132 1 @ 2 240_0402_1% M12 H23 MAA13 RV133 1 2 TESTEN AD28 T8 MAB13
MEM_CALRP1 MAA0_8 MAA13 27 TESTEN MAB0_8 MAB13 28
RV134 1 TH@ 2 240_0402_1% M27 J19 MAA14 5.11K_0402_1% W8 MAB14
MEM_CALRP0 MAA1_8 MAA14 27 MAB1_8 MAB14 28
RV135 1 TH@ 2 240_0402_1% AH12 AK10
GDDR5
RV206 1 MARS@ 2 120_0402_5% MEM_CALRP2 AL10 CLKTESTA AH11 DRAM_RST#_R
GDDR5
RV205 1 CH@ 2 120_0402_5% CLKTESTB DRAM_RST
THAMES XT M2 THAMES XT M2
@ @
B B
1
@ @
CV218 CV219
0.1U_0402_16V7K 0.1U_0402_16V7K
2
route 50ohms single-ended/100ohms diff
Co-lay Thames/Mars Pro/Chelsea This basic topology should be used for DRAM_RST for DDR3/GDDR5.These
Capacitors and Resistor values are an example only. The Series R and and keep short
1
Thames M2 Mars Pro Chelsea M2 || Cap values will depend on the DRAM load and will have to be Debug only, for clock observation, if not needed, DNI
@ @
RV129 POP @ @ calculated for different Memory ,DRAM Load and board to pass Reset RV136 RV137 5mil 5mil
Signal Spec. 51.1_0402_1% 51.1_0402_1%
RV130 @ @ @ Place all these components very close to GPU (Within
2
25mm) and keep all component close to each Other (within
RV131 POP @ @ 5mm) except Rser2
RV132 @ @ @
RV134 POP @ @ +1.5VGS
RV135 POP @ @
1
RV206 @ MARS@ @ RV138
+1.5VGS +1.5VGS
4.7K_0402_5%
RV205 @ @ POP @
2
1
RV141 RV142
40.2_0402_1% 40.2_0402_1%
+1.5VGS +1.5VGS 1 RV143 2 1 RV144 2 DRAM_RST#_R DIS@ DIS@
27,28 DRAM_RST#
51.1_0402_1% 10_0402_1%
2
DIS@ DIS@
1
+VDD_MEM15_REFDB +VDD_MEM15_REFSB
2
RV139 RV140
1
40.2_0402_1% 40.2_0402_1% DIS@ DIS@
1
@ @ CV222 RV145 CV223 CV224
120P_0402_50V9 4.99K_0402_1% RV148 0.1U_0402_16V7K RV149 0.1U_0402_16V7K
2
100_0402_1% DIS@ 100_0402_1% DIS@
1
2
A +VDD_MEM15_REFDA +VDD_MEM15_REFSA DIS@ A
DIS@
2
1
CV220 CV221
RV146 0.1U_0402_16V7K RV147 0.1U_0402_16V7K
100_0402_1% @ 100_0402_1% @
2
@ @
2
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/09/11 Deciphered Date 2014/03/12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ATI_ThamesXT_M2_MEM IF
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-9103P
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, July 10, 2013 Sheet 26 of 52
5 4 3 2 1
5 4 3 2 1
CHANNEL A: 256MB/512MB DDR3
UV18 UV19 UV20 UV21
VREFC_A1 M8 E3 MDA29 VREFC_A2 M8 E3 MDA18 VREFC_A3 M8 E3 MDA38 VREFC_A4 M8 E3 MDA55
VREFD_Q1 H1 VREFCA DQL0 F7 MDA27 VREFD_Q2 H1 VREFCA DQL0 F7 MDA23 VREFD_Q3 H1 VREFCA DQL0 F7 MDA36 VREFD_Q4 H1 VREFCA DQL0 F7 MDA51
VREFDQ DQL1 F2 MDA30 VREFDQ DQL1 F2 MDA19 VREFDQ DQL1 F2 MDA39 VREFDQ DQL1 F2 MDA50
MAA0 N3 DQL2 F8 MDA26 MAA0 N3 DQL2 F8 MDA20 MAA0 N3 DQL2 F8 MDA34 MAA0 N3 DQL2 F8 MDA52
MAA1 P7 A0 DQL3 H3 MDA28 MAA1 P7 A0 DQL3 H3 MDA17 MAA1 P7 A0 DQL3 H3 MDA35 MAA1 P7 A0 DQL3 H3 MDA48
MAA2 P3 A1 DQL4 H8 MDA24 MAA2 P3 A1 DQL4 H8 MDA21 MAA2 P3 A1 DQL4 H8 MDA33 MAA2 P3 A1 DQL4 H8 MDA53
D A2 DQL5 A2 DQL5 A2 DQL5 A2 DQL5 D
MAA3 N2 G2 MDA31 MAA3 N2 G2 MDA16 MAA3 N2 G2 MDA37 MAA3 N2 G2 MDA49
MAA4 P8 A3 DQL6 H7 MDA25 MAA4 P8 A3 DQL6 H7 MDA22 MAA4 P8 A3 DQL6 H7 MDA32 MAA4 P8 A3 DQL6 H7 MDA54
MAA5 P2 A4 DQL7 MAA5 P2 A4 DQL7 MAA5 P2 A4 DQL7 MAA5 P2 A4 DQL7
MAA6 R8 A5 MAA6 R8 A5 MAA6 R8 A5 MAA6 R8 A5
MDA[0..63] MAA7 R2 A6 D7 MDA0 MAA7 R2 A6 D7 MDA15 MAA7 R2 A6 D7 MDA42 MAA7 R2 A6 D7 MDA60
26 MDA[0..63] T8 A7 DQU0 C3 T8 A7 DQU0 C3 T8 A7 DQU0 C3 T8 A7 DQU0 C3
MAA8 MDA5 MAA8 MDA10 MAA8 MDA44 MAA8 MDA58
MAA9 R3 A8 DQU1 C8 MDA1 MAA9 R3 A8 DQU1 C8 MDA14 MAA9 R3 A8 DQU1 C8 MDA40 MAA9 R3 A8 DQU1 C8 MDA63
MAA10 L7 A9 DQU2 C2 MDA6 MAA10 L7 A9 DQU2 C2 MDA11 MAA10 L7 A9 DQU2 C2 MDA46 MAA10 L7 A9 DQU2 C2 MDA56
MAA11 R7 A10/AP DQU3 A7 MDA3 MAA11 R7 A10/AP DQU3 A7 MDA13 MAA11 R7 A10/AP DQU3 A7 MDA43 MAA11 R7 A10/AP DQU3 A7 MDA61
MAA12 N7 A11 DQU4 A2 MDA4 MAA12 N7 A11 DQU4 A2 MDA9 MAA12 N7 A11 DQU4 A2 MDA45 MAA12 N7 A11 DQU4 A2 MDA59
MAA[14..0] MAA13 T3 A12/BC DQU5 B8 MDA2 MAA13 T3 A12/BC DQU5 B8 MDA12 MAA13 T3 A12/BC DQU5 B8 MDA41 MAA13 T3 A12/BC DQU5 B8 MDA62
26 MAA[14..0] T7 A13 DQU6 A3 T7 A13 DQU6 A3 T7 A13 DQU6 A3 T7 A13 DQU6 A3
MAA14 MDA7 MAA14 MDA8 MAA14 MDA47 MAA14 MDA57
A14 DQU7 A14 DQU7 A14 DQU7 A14 DQU7
+1.5VGS +1.5VGS +1.5VGS +1.5VGS
M2 B2 A_BA0 M2 B2 A_BA0 M2 B2 A_BA0 M2 B2
26 A_BA0 N8 BA0 VDD D9 N8 BA0 VDD D9 N8 BA0 VDD D9 N8 BA0 VDD D9
A_BA1 A_BA1 A_BA1
DQMA#[7..0] 26 A_BA1 M3 BA1 VDD G7 M3 BA1 VDD G7 M3 BA1 VDD G7 M3 BA1 VDD G7
A_BA2 A_BA2 A_BA2
26 DQMA#[7..0] 26 A_BA2 BA2 VDD K2 BA2 VDD K2 BA2 VDD K2 BA2 VDD K2
VDD K8 VDD K8 VDD K8 VDD K8
VDD N1 VDD N1 VDD N1 VDD N1
J7 VDD N9 CLKA0 J7 VDD N9 J7 VDD N9 CLKA1 J7 VDD N9
26 CLKA0 K7 CK VDD R1 K7 CK VDD R1 26 CLKA1 K7 CK VDD R1 K7 CK VDD R1
CLKA0# CLKA1#
QSA[7..0] 26 CLKA0# K9 CK VDD R9 K9 CK VDD R9 26 CLKA1# K9 CK VDD R9 K9 CK VDD R9
CKEA0 CKEA1
26 QSA[7..0] 26 CKEA0 CKE VDD +1.5VGS CKE VDD +1.5VGS 26 CKEA1 CKE VDD +1.5VGS CKE VDD +1.5VGS
K1 A1 ODTA0 K1 A1 K1 A1 ODTA1 K1 A1
26 ODTA0 L2 ODT VDDQ A8 L2 ODT VDDQ A8 26 ODTA1 L2 ODT VDDQ A8 L2 ODT VDDQ A8
CSA0#_0 CSA1#_0
26 CSA0#_0 J3 CS VDDQ C1 J3 CS VDDQ C1 26 CSA1#_0 J3 CS VDDQ C1 J3 CS VDDQ C1
RASA0# RASA1#
26 RASA0# K3 RAS VDDQ C9 K3 RAS VDDQ C9 26 RASA1# K3 RAS VDDQ C9 K3 RAS VDDQ C9
CASA0# CASA1#
QSA#[7..0] 26 CASA0# L3 CAS VDDQ D2 L3 CAS VDDQ D2 26 CASA1# L3 CAS VDDQ D2 L3 CAS VDDQ D2
WEA0# WEA1#
26 QSA#[7..0] 26 WEA0# WE VDDQ E9 WE VDDQ E9 26 WEA1# WE VDDQ E9 WE VDDQ E9
VDDQ F1 VDDQ F1 VDDQ F1 VDDQ F1
QSA3 F3 VDDQ H2 QSA2 F3 VDDQ H2 QSA4 F3 VDDQ H2 QSA6 F3 VDDQ H2
QSA0 C7 DQSL VDDQ H9 QSA1 C7 DQSL VDDQ H9 QSA5 C7 DQSL VDDQ H9 QSA7 C7 DQSL VDDQ H9
DQSU VDDQ DQSU VDDQ DQSU VDDQ DQSU VDDQ
C C
DQMA#3 E7 A9 DQMA#2 E7 A9 DQMA#4 E7 A9 DQMA#6 E7 A9
DQMA#0 D3 DML VSS B3 DQMA#1 D3 DML VSS B3 DQMA#5 D3 DML VSS B3 DQMA#7 D3 DML VSS B3
DMU VSS E1 DMU VSS E1 DMU VSS E1 DMU VSS E1
VSS G8 VSS G8 VSS G8 VSS G8
QSA#3 G3 VSS J2 QSA#2 G3 VSS J2 QSA#4 G3 VSS J2 QSA#6 G3 VSS J2
QSA#0 B7 DQSL VSS J8 QSA#1 B7 DQSL VSS J8 QSA#5 B7 DQSL VSS J8 QSA#7 B7 DQSL VSS J8
DQSU VSS M1 DQSU VSS M1 DQSU VSS M1 DQSU VSS M1
VSS M9 VSS M9 VSS M9 VSS M9
VSS P1 VSS P1 VSS P1 VSS P1
T2 VSS P9 DRAM_RST# T2 VSS P9 DRAM_RST# T2 VSS P9 DRAM_RST# T2 VSS P9
26,28 DRAM_RST# RESET VSS T1 RESET VSS T1 RESET VSS T1 RESET VSS T1
L8 VSS T9 L8 VSS T9 L8 VSS T9 L8 VSS T9
ZQ VSS ZQ VSS ZQ VSS ZQ VSS
1
1
J1 B1 J1 B1 J1 B1 J1 B1
RV150 L1 NC VSSQ B9 RV151 L1 NC VSSQ B9 RV152 L1 NC VSSQ B9 RV153 L1 NC VSSQ B9
J9 NC VSSQ D1 J9 NC VSSQ D1 J9 NC VSSQ D1 J9 NC VSSQ D1
240_0402_1% NC VSSQ 240_0402_1% NC VSSQ 240_0402_1% NC VSSQ 240_0402_1% NC VSSQ
@ L9 D8 @ L9 D8 @ L9 D8 @ L9 D8
M7 NC VSSQ E2 M7 NC VSSQ E2 M7 NC VSSQ E2 M7 NC VSSQ E2
2
2
NC VSSQ E8 NC VSSQ E8 NC VSSQ E8 NC VSSQ E8
VSSQ F9 VSSQ F9 VSSQ F9 VSSQ F9
VSSQ G1 VSSQ G1 VSSQ G1 VSSQ G1
VSSQ G9 VSSQ G9 VSSQ G9 VSSQ G9
VSSQ VSSQ VSSQ VSSQ
96-BALL 96-BALL 96-BALL 96-BALL
SDRAM DDR3L SDRAM DDR3L SDRAM DDR3L SDRAM DDR3L
@ K4W2G1646E-BC11 FBGA 96P K4W2G1646E-BC11 FBGA 96P K4W2G1646E-BC11 FBGA 96P K4W2G1646E-BC11 FBGA 96P
CLKA0 1 2
RV154 56_0402_1% @ @ @ @
@
CLKA0# 1 2
RV155 56_0402_1%
1
CV225
0.01U_0402_16V7K
@ +1.5VGS +1.5VGS +1.5VGS +1.5VGS +1.5VGS +1.5VGS +1.5VGS +1.5VGS
B B
2
1
RV156 RV157 RV158 RV159 RV160 RV161 RV162 RV163
4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1%
@ @ @ @ @ @ @ @
@
15mil 15mil 15mil 15mil 15mil 15mil 15mil 15mil
2
2
CLKA1 1 2
RV164 56_0402_1% VREFD_Q1 VREFC_A1 VREFC_A2 VREFD_Q2 VREFC_A3 VREFD_Q3 VREFC_A4 VREFD_Q4
1
1
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
CV226
CV227
CV228
CV229
CV230
CV231
CV232
@
1
1
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
CV233
CLKA1# 1 2 RV166 RV167 RV168 RV169 RV170 RV171 RV172 RV173
RV165 56_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1%
1
CV234 @ @ @ @ @ @ @ @ @ @ @ @ @
2
2
0.01U_0402_16V7K @ @ @
2
2
@
2
+1.5VGS
+1.5VGS
+1.5VGS +1.5VGS
CV235
CV236
CV237
CV238
CV239
CV240
CV241
CV242
CV243
CV244
CV245
CV246
CV247
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
CV248
CV249
CV250
CV251
CV252
CV253
CV254
CV255
CV256
CV257
CV258
CV259
CV260
CV261
CV262
CV263
CV264
CV265
CV266
CV267
CV268
CV269
CV270
CV271
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2 2 2 2 2 2
@
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
@
@
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/09/11 Deciphered Date 2014/03/12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ATI_ThamesXT_M2_VRAM_A
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-9103P
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, July 10, 2013 Sheet 27 of 52
5 4 3 2 1
5 4 3 2 1
CHANNEL B: 256MB/512MB DDR3
UV22 UV23 UV24 UV25
VREFC_A1_B M8 E3 MDB29 VREFC_A2_B M8 E3 MDB16 VREFC_A3_B M8 E3 MDB33 VREFC_A4_B M8 E3 MDB55
VREFD_Q1_B H1 VREFCA DQL0 F7 MDB26 VREFD_Q2_B H1 VREFCA DQL0 F7 MDB19 VREFD_Q3_B H1 VREFCA DQL0 F7 MDB37 VREFD_Q4_B H1 VREFCA DQL0 F7 MDB50
MDB[0..63] VREFDQ DQL1 F2 MDB30 VREFDQ DQL1 F2 MDB20 VREFDQ DQL1 F2 MDB35 VREFDQ DQL1 F2 MDB54
26 MDB[0..63] N3 DQL2 F8 N3 DQL2 F8 N3 DQL2 F8 N3 DQL2 F8
MAB0 MDB27 MAB0 MDB22 MAB0 MDB39 MAB0 MDB51
MAB1 P7 A0 DQL3 H3 MDB31 MAB1 P7 A0 DQL3 H3 MDB17 MAB1 P7 A0 DQL3 H3 MDB32 MAB1 P7 A0 DQL3 H3 MDB53
MAB2 P3 A1 DQL4 H8 MDB25 MAB2 P3 A1 DQL4 H8 MDB21 MAB2 P3 A1 DQL4 H8 MDB36 MAB2 P3 A1 DQL4 H8 MDB49
D A2 DQL5 A2 DQL5 A2 DQL5 A2 DQL5 D
MAB3 N2 G2 MDB28 MAB3 N2 G2 MDB18 MAB3 N2 G2 MDB34 MAB3 N2 G2 MDB52
MAB4 P8 A3 DQL6 H7 MDB24 MAB4 P8 A3 DQL6 H7 MDB23 MAB4 P8 A3 DQL6 H7 MDB38 MAB4 P8 A3 DQL6 H7 MDB48
MAB[14..0] MAB5 P2 A4 DQL7 MAB5 P2 A4 DQL7 MAB5 P2 A4 DQL7 MAB5 P2 A4 DQL7
26 MAB[14..0] R8 A5 R8 A5 R8 A5 R8 A5
MAB6 MAB6 MAB6 MAB6
MAB7 R2 A6 D7 MDB0 MAB7 R2 A6 D7 MDB15 MAB7 R2 A6 D7 MDB44 MAB7 R2 A6 D7 MDB56
MAB8 T8 A7 DQU0 C3 MDB4 MAB8 T8 A7 DQU0 C3 MDB10 MAB8 T8 A7 DQU0 C3 MDB41 MAB8 T8 A7 DQU0 C3 MDB59
MAB9 R3 A8 DQU1 C8 MDB1 MAB9 R3 A8 DQU1 C8 MDB14 MAB9 R3 A8 DQU1 C8 MDB47 MAB9 R3 A8 DQU1 C8 MDB63
MAB10 L7 A9 DQU2 C2 MDB6 MAB10 L7 A9 DQU2 C2 MDB11 MAB10 L7 A9 DQU2 C2 MDB43 MAB10 L7 A9 DQU2 C2 MDB62
MAB11 R7 A10/AP DQU3 A7 MDB3 MAB11 R7 A10/AP DQU3 A7 MDB12 MAB11 R7 A10/AP DQU3 A7 MDB45 MAB11 R7 A10/AP DQU3 A7 MDB57
DQMB#[7..0] MAB12 N7 A11 DQU4 A2 MDB7 MAB12 N7 A11 DQU4 A2 MDB9 MAB12 N7 A11 DQU4 A2 MDB40 MAB12 N7 A11 DQU4 A2 MDB61
26 DQMB#[7..0] T3 A12/BC DQU5 B8 T3 A12/BC DQU5 B8 T3 A12/BC DQU5 B8 T3 A12/BC DQU5 B8
MAB13 MDB2 MAB13 MDB13 MAB13 MDB46 MAB13 MDB58
MAB14 T7 A13 DQU6 A3 MDB5 MAB14 T7 A13 DQU6 A3 MDB8 MAB14 T7 A13 DQU6 A3 MDB42 MAB14 T7 A13 DQU6 A3 MDB60
A14 DQU7 A14 DQU7 A14 DQU7 A14 DQU7
+1.5VGS +1.5VGS +1.5VGS +1.5VGS
QSB[7..0] M2 B2 B_BA0 M2 B2 B_BA0 M2 B2 B_BA0 M2 B2
26 QSB[7..0] 26 B_BA0 N8 BA0 VDD D9 N8 BA0 VDD D9 N8 BA0 VDD D9 N8 BA0 VDD D9
B_BA1 B_BA1 B_BA1
26 B_BA1 M3 BA1 VDD G7 M3 BA1 VDD G7 M3 BA1 VDD G7 M3 BA1 VDD G7
B_BA2 B_BA2 B_BA2
26 B_BA2 BA2 VDD K2 BA2 VDD K2 BA2 VDD K2 BA2 VDD K2
VDD K8 VDD K8 VDD K8 VDD K8
VDD N1 VDD N1 VDD N1 VDD N1
J7 VDD N9 CLKB0 J7 VDD N9 J7 VDD N9 CLKB1 J7 VDD N9
QSB#[7..0] 26 CLKB0 K7 CK VDD R1 K7 CK VDD R1 26 CLKB1 K7 CK VDD R1 K7 CK VDD R1
CLKB0# CLKB1#
26 QSB#[7..0] 26 CLKB0# K9 CK VDD R9 K9 CK VDD R9 26 CLKB1# K9 CK VDD R9 K9 CK VDD R9
CKEB0 CKEB1
26 CKEB0 CKE VDD +1.5VGS CKE VDD +1.5VGS 26 CKEB1 CKE VDD +1.5VGS CKE VDD +1.5VGS
K1 A1 ODTB0 K1 A1 K1 A1 ODTB1 K1 A1
26 ODTB0 L2 ODT VDDQ A8 L2 ODT VDDQ A8 26 ODTB1 L2 ODT VDDQ A8 L2 ODT VDDQ A8
CSB0#_0 CSB1#_0
26 CSB0#_0 J3 CS VDDQ C1 J3 CS VDDQ C1 26 CSB1#_0 J3 CS VDDQ C1 J3 CS VDDQ C1
RASB0# RASB1#
26 RASB0# K3 RAS VDDQ C9 K3 RAS VDDQ C9 26 RASB1# K3 RAS VDDQ C9 K3 RAS VDDQ C9
CASB0# CASB1#
26 CASB0# L3 CAS VDDQ D2 L3 CAS VDDQ D2 26 CASB1# L3 CAS VDDQ D2 L3 CAS VDDQ D2
WEB0# WEB1#
26 WEB0# WE VDDQ E9 WE VDDQ E9 26 WEB1# WE VDDQ E9 WE VDDQ E9
VDDQ F1 VDDQ F1 VDDQ F1 VDDQ F1
DIS@ QSB3 F3 VDDQ H2 QSB2 F3 VDDQ H2 QSB4 F3 VDDQ H2 QSB6 F3 VDDQ H2
CLKB0 1 2 QSB0 C7 DQSL VDDQ H9 QSB1 C7 DQSL VDDQ H9 QSB5 C7 DQSL VDDQ H9 QSB7 C7 DQSL VDDQ H9
RV174 56_0402_1% DQSU VDDQ DQSU VDDQ DQSU VDDQ DQSU VDDQ
C C
DIS@ DQMB#3 E7 A9 DQMB#2 E7 A9 DQMB#4 E7 A9 DQMB#6 E7 A9
CLKB0# 1 2 DQMB#0 D3 DML VSS B3 DQMB#1 D3 DML VSS B3 DQMB#5 D3 DML VSS B3 DQMB#7 D3 DML VSS B3
RV175 56_0402_1% DMU VSS E1 DMU VSS E1 DMU VSS E1 DMU VSS E1
VSS G8 VSS G8 VSS G8 VSS G8
VSS VSS VSS VSS
1
CV272 QSB#3 G3 J2 QSB#2 G3 J2 QSB#4 G3 J2 QSB#6 G3 J2
0.01U_0402_16V7K QSB#0 B7 DQSL VSS J8 QSB#1 B7 DQSL VSS J8 QSB#5 B7 DQSL VSS J8 QSB#7 B7 DQSL VSS J8
DIS@ DQSU VSS M1 DQSU VSS M1 DQSU VSS M1 DQSU VSS M1
2
VSS M9 VSS M9 VSS M9 VSS M9
VSS P1 VSS P1 VSS P1 VSS P1
T2 VSS P9 DRAM_RST# T2 VSS P9 DRAM_RST# T2 VSS P9 DRAM_RST# T2 VSS P9
26,27 DRAM_RST# RESET VSS T1 RESET VSS T1 RESET VSS T1 RESET VSS T1
L8 VSS T9 L8 VSS T9 L8 VSS T9 L8 VSS T9
ZQ VSS ZQ VSS ZQ VSS ZQ VSS
DIS@
1
1
CLKB1 1 2 J1 B1 J1 B1 J1 B1 J1 B1
RV180 56_0402_1% RV176 L1 NC VSSQ B9 RV177 L1 NC VSSQ B9 RV178 L1 NC VSSQ B9 RV179 L1 NC VSSQ B9
J9 NC VSSQ D1 J9 NC VSSQ D1 J9 NC VSSQ D1 J9 NC VSSQ D1
240_0402_1% NC VSSQ 240_0402_1% NC VSSQ 240_0402_1% NC VSSQ 240_0402_1% NC VSSQ
DIS@ DIS@ L9 D8 DIS@ L9 D8 DIS@ L9 D8 DIS@ L9 D8
CLKB1# 1 2 M7 NC VSSQ E2 M7 NC VSSQ E2 M7 NC VSSQ E2 M7 NC VSSQ E2
2
2
RV181 56_0402_1% NC VSSQ E8 NC VSSQ E8 NC VSSQ E8 NC VSSQ E8
VSSQ VSSQ VSSQ VSSQ
1
CV273 F9 F9 F9 F9
0.01U_0402_16V7K VSSQ G1 VSSQ G1 VSSQ G1 VSSQ G1
DIS@ VSSQ G9 VSSQ G9 VSSQ G9 VSSQ G9
2
VSSQ VSSQ VSSQ VSSQ
96-BALL 96-BALL 96-BALL 96-BALL
SDRAM DDR3L SDRAM DDR3L SDRAM DDR3L SDRAM DDR3L
K4W2G1646E-BC11 FBGA 96P K4W2G1646E-BC11 FBGA 96P K4W2G1646E-BC11 FBGA 96P K4W2G1646E-BC11 FBGA 96P
@ @ @ @
+1.5VGS +1.5VGS +1.5VGS +1.5VGS +1.5VGS +1.5VGS +1.5VGS +1.5VGS
B B
1
1
RV182 RV183 RV184 RV185 RV186 RV187 RV188 RV189
4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1%
DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@
15mil 15mil 15mil 15mil 15mil 15mil 15mil 15mil
2
2
VREFD_Q1_B VREFC_A1_B VREFC_A2_B VREFD_Q2_B VREFC_A3_B VREFD_Q3_B VREFC_A4_B VREFD_Q4_B
CV274
CV275
CV276
CV277
CV278
CV279
CV280
CV281
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
1
1
1 1 1 1 1 1 1 1
RV190 RV191 RV192 RV193 RV194 RV195 RV196 RV197
4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1%
DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@
2 2 2 2 2 2 2 2
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
2
2
+1.5VGS
+1.5VGS
+1.5VGS +1.5VGS
CV282
CV283
CV284
CV285
CV286
CV287
CV288
CV289
CV290
CV291
CV292
CV293
CV294
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
CV295
CV296
CV297
CV298
CV299
CV300
CV301
CV302
CV303
CV304
CV305
CV306
CV307
CV308
CV310
CV311
CV312
CV313
CV314
CV315
CV316
CV317
CV318
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2 2 2 2 2 2
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/09/11 Deciphered Date 2014/03/12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ATI_ThamesXT_M2_VRAM_B
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-9103P
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, July 10, 2013 Sheet 28 of 52
5 4 3 2 1
5 4 3 2 1
JP3 @
2 1
W=40mils 2MM
+LAN_IO rising time : >1ms and <100ms
W=40mils
+3VALW
@ W=40mils +LAN_IO 1.5A
RL18
CL38 U5
2 1 2 1 +LAN_PWR 5 1
1U_0402_6.3V6K VIN VOUT
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0_0603_5% 1 1 1 1 1 1
3
36 WOL_EN EN
D CL15 CL19 CL16 CL17 CL18 CL27 D
@ @
U5_SS 4 2 2 2 2 2 2 2
SS GND
2
0.1U_0603_50V_X7R
RL27 APL3512ABI-TRG_SOT23-5 MCT0 1 RL19 2 75_0603_5%
100K_0402_5% 1
CL39
@ MCT1 1 RL20 2 75_0603_5%
1
2 These caps close to Pin 12,27,39,42,47,48
1
For 8105E-VD pop the capacitor close pin 27,39,47,48
2
Place close to TCT pin EMC@
CL33
100P_1206_2KV8J NEMC@
2
DL11
+LAN_VDD
PESD5V0U2BT_SOT23-3
1
+LAN_PWR 2 1 U5_SS
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
RL22 0_0402_5% 1 1 1 1 1 1 1
@
CL20 CL21 CL22 CL23 CL24 CL25 CL26 TL1
@ @ @ @
2 2 2 2 2 2 2 MDI1- 1 16 MDO1-
MDI1+ 2
3
RD+
RD-
RX+
RX-
15
14
MDO1+ DL11 as close as
MCT0
4
5
CT
NC
CT
NC
13
12
possible to C27
NC NC
MDI0-
6
7 CT
TD+
CT
TX+
11
10
MCT1
MDO0- and C32
MDI0+ 8 9 MDO0+
TD- TX-
2
X'FORM_ NS0014
C C
These caps close to Pin 3,6,9,13,29,41,45 CL41
CL28,C30 Close UL1 0.01U_0402_16V7K
UL1 For 8105E-VD pop capacitor close to pin 13,29,45 1
CL28 1 2 0.1U_0402_16V7K PCIE_CRX_C_DTX_P0 22 31
5 PCIE_CRX_DTX_P0 HSOP LED3/EEDO 37 T105 MDI1-
CL30 1 2 0.1U_0402_16V7K PCIE_CRX_C_DTX_N0 23 LED1/EESK 40
5 PCIE_CRX_DTX_N0 HSON LED0
17 30 RL23 1 @ 2 10K_0402_5% MDI1+
5 PCIE_CTX_DRX_P0 HSIP EECS/SCL
18 32 RL24 1 2 10K_0402_5% Place Close to TL1
5 PCIE_CTX_DRX_N0 HSIN EEDI/SDA @
16 1 MDI0+
10
14 LAN_CLKREQ# CLKREQB MDIP0
6
7
8
9
2 MDI0-
25 MDIN0 4 MDI1+ NGCLK@
6
7
8
9
10
12,35,36 PLT_RST# PERSTB MDIP1 5 MDI1- 11 NEMC@
MDIN1 CL36 GND
19 7
12 CLK_PCIE_LAN REFCLK_P NC/MDIP2 RCLAMP3304N.TCT_SLP2626P10-10
20 8 1 2 XTLI
12 CLK_PCIE_LAN# REFCLK_N NC/MDIN2 DL9
5
4
3
2
1
10
NC/MDIP3 11 15P_0402_50V8J YL2
5
4
3
2
1
XTLO 43 NC/MDIN3 1 2
CKXTAL1 OSC GND NGCLK@
XTLI 44 13 +LAN_VDD NGCLK@ 3 4
CKXTAL2 DVDD10 29 OSC GND MDI0-
DVDD10 CL37
41 25MHZ_10PF_7V25000014
FCH_PCIE_WAKE# 28 DVDD10 1 2 XTLO
14,36 FCH_PCIE_WAKE# LANWAKEB MDI0+
ISOLATEB 26 27 15P_0402_50V8J
ISOLATEB DVDD33 39
DVDD33 reserve for China Go-rural
14 12 +LAN_IO
15 NC/SMBCLK AVDD33 42
38 NC/SMBDATA AVDD33 47
GPO/SMBALERT AVDD33 48
B
AVDD33 B
ENSWREG 33
ENSWREG 21 +LAN_EVDD10
+LAN_VDDREG
34
35 VDDREG
EVDD10
3
RJ45 Conn.
VDDREG AVDD10 +LAN_VDD
6 JLAN
AVDD10 9
1 RL31 2 2.49K_0402_1% 46 AVDD10 45 8
RSET AVDD10 PR4-
24 36 7
49 GND REGOUT PR4+
PGND MDO1- 6
PR2-
S IC RTL8105E-VD-CGT QFN 48P LAN CTRL 5
PR3-
+3VS SA00003PO40 W=20mils 4
+LAN_VDD PR3+
@ MDO1+ 3
PR2+
1
1ShortPad 2 +LAN_EVDD10
RL33 RL26 0_0603_5% MDO0- 2
PR1-
1K_0402_5%
1U_0402_6.3V6K
0.1U_0402_16V7K
1 1 MDO0+ 1
PR1+
2
CL34 CL35 9
ENSWREG ISOLATEB SHLD1
2 2 10
SHLD2
@
1
ShortPad
2
SANTA_130456-311
0_0402_5% RL35 CONN@
RL36 15K_0402_5%
2
SP011207090
1
A DC234004V00 (OLD) A
3.3V : Enable switching regulator
0V : Disable switching regulator
10/100 ：100@ (LDO mode used) Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/09/11 Deciphered Date 2014/03/12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LAN RTL8105E
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-9103P
Date: Wednesday, July 10, 2013 Sheet 29 of 52
5 4 3 2 1
5 4 3 2 1
JACK_PLUG Delay circutis
Line1-VREFO-L
Line1-VREFO-R +3VS +3VS
CA71, CA51 place close to Pin 26
1
+5V_PVDD +5VS RC60 RC61 @ @ JACK_SENSE#
4.7K_0402_5% 4.7K_0402_5% RA1 RA2
+5V_PVDD +5V_PVDD +5VA
100K_0402_5% 100K_0402_5%
RA203 2 @ 1 0_0603_5%
3
@
2
+5VA +5VS
4.7U_0603_6.3V6K
CA55
4.7U_0603_6.3V6K
CA53
4.7U_0603_6.3V6K
CA71
1 1 1 QA5B
1 1 1 LINE1-L CA67 1 2 1 2 Line-IN-L @
0.1U_0402_16V7K
CA56
0.1U_0402_16V7K
CA54
0.1U_0402_16V7K
CA51
D 4.7U_0603_6.3V6K RA80 1K_0402_1%~D QA5A 5 DMN66D0LDW-7_SOT363-6 D
6
RA204 2 @ 1 0_0603_5% LINE1-R CA68 1 2 1 2 Line-IN-R DMN66D0LDW-7_SOT363-6
2 2 2 4.7U_0603_6.3V6K RA82 1K_0402_1%~D
4
2 2 2
JACK_PLUG# 1 @ 2 2
10K_0402_5% RA3
+3VS
1
1 1
UA1 CA2
CA58 1 1 CA1
12 CA65 1 2 PC_BEEP 10U_0603_6.3V6M 10U_0603_6.3V6M
PCBEEP 2 2
0.1U_0402_16V7K
4.7U_0603_6.3V6K
26 0.1U_0402_16V7K @ @
CA57 41 AVDD1 16
2 2 +3VS PVDD1 MONO-OUT
CA59 1 CA60 1 46 @ CA365 1 2 100P_0402_50V8J
PVDD2 24
CA59, CA60 4.7U_0603_6.3V6K 0.1U_0402_16V7K 1 LINE2-L(PORT-E-L) 23
DVDD LINE2-R(PORT-E-R)
Close to UA1 2 2
36
CPVDD 22 LINE1-L
@ RA81 2 1 10K_0402_5% @
Pin36 @ 9 LINE1-L(PORT-C-L) 21 LINE1-R
@3223 JACK_PLUG# 1 ShortPad2 0_0402_5% JACK_SENSE#
RA4
RA9 1 ShortPad2 0_0402_5% CA61 1 40 DVDD-IO LINE1-R(PORT-C-R) CA74 10U_0603_6.3V6M~D
+1.5VS AVDD2 MIC1-L 1 2 Reserve for cancel Delay circutis
20 @3221
4.7U_0603_6.3V6K MIC1-R(PORT-B-R) 19 RA1108
RA130 1 2 22_0402_5% 2 8 MIC1-L(PORT-B-L) 1 2 22K_0402_1%~D
14 HDA_SDIN0
5 SDATA-IN 18
@
14 HDA_SDOUT_AUDIO RA11 1 2 0_0402_5%
HDA_BITCLK_AUDIO 6 SDATA-OUT MIC2-R(PORT-F-R) 17 CA66 1 2 4.7U_0603_6.3V6K MIC_IN
14 HDA_BITCLK_AUDIO BCLK MIC2-L(PORT-F-L)
14 HDA_SYNC_AUDIO
10 @3221 RA1108, RA33 place close to Jack Conn
11 SYNC 1 2 RING2
14 HDA_RST_AUDIO# RESETB RA27 0_0402_5% @
14 RA33 1 2 0_0402_5%
CA23 1 2 2.2U_0603_6.3V6K 28 SENSE B 13 RA51 1 2 39.2K_0402_1% JACK_SENSE#
RA153 1 2 15 VREF SENSE A @3221
20K_0402_1%
JDREF RA51, RA33 place close to UA1 @
RA29 1 2 0_0603_5%~D
37 45 INT-SPK-R+
CA24 1 2 1U_0402_6.3V6K 35 CBP SPK-OUT-R+ 44 INT-SPK-R- RA30 1 @ 2 0_0603_5%~D
CA25 1 2 1U_0402_6.3V6K 34 CBN SPK-OUT-R- 43 INT-SPK-L-
CPVEE SPK-OUT-L- 42 INT-SPK-L+ RA31 1 2 0_0603_5%~D
Line1-VREFO-L 31 SPK-OUT-L+ @
C @
Line1-VREFO-R 30 MIC1-VREFO-L C
+MIC2-VREFO RA50 1 ShortPad2 0_0402_5% 29 MIC1-VREFO-R 33 HPOUT-R
+MIC2-VREFO MIC2-VREFO HPOUT-R(PORT-I-R) 32 HPOUT-L
HPOUT-L(PORT-I-L)
CA62 1 2 10U_0603_6.3V6M 27 RA1107 RA25 1 2 0_0603_5%~D
LDO1-CAP @3221222K_0402_1%~D
CA63 1 2 10U_0603_6.3V6M 39 48 1 MIC_IN @
CA64 1 2 10U_0603_6.3V6M 7 LDO2-CAP SPDIF-OUT/GPIO2
LDO3-CAP 2
GPIO0/DMIC-DATA MIC_DATA 18 1
+MIC2-VREFO
10U_0603_6.3V6M
CA70
HDA_BITCLK_AUDIO 4 3 MIC_CLK_C
25 DVSS GPIO1/DMIC-CLK
38 AVSS1 47 EC_MUTE#
@3221
1 AVSS2 PDB EC_MUTE# 36 2
NEMC@ CA21
49
22P_0402_50V8J Thermal PAD 2 1 MIC_IN
GNDA GND
2 RA53 2.2K_0402_5%
ALC3223-CG_MQFN48_6X6~D RA131 EMI@ 2 1 RING2 Place on the moat between GND & GNDA.
MIC_CLK_C 1 2 MIC_CLK RA1109 2.2K_0402_5%
MIC_CLK 18
BLM15BB221SN1D_2P
@3223
1
CA22 NEMC@
22P_0402_50V8J DA8
2 2
EC Beep 36 BEEP#
+VCOIN_RTC SM01000BV00 1 PC_BEEP
need CIS symbol 3
FCH Beep 14 FCH_SPKR
1
1
MIC_IN BAT54C-7-F_SOT23-3
RA5 @ RA19
100K_0402_5% 10K_0402_5%
PC Beep
2
3
2
QA6B
B B
QA6A 5 DMN66D0LDW-7_SOT363-6
6
DMN66D0LDW-7_SOT363-6
4
1 @ 2 2
+3VS
10K_0402_5% RA6
SP02000H300
HDA_RST_AUDIO# 1 2
close to Codec
1
10K_0402_5% RA7 JSPK
INT-SPK-R- 1
INT-SPK-R+ 2 1
INT-SPK-L- 3 2 5
INT-SPK-L+ 4 3 GND 6
4 GND
2
E-T_3703-Q04N-11R
Trace width for SPK-L+/SPK-L-/SPK-R+/SPK-R-
AZ5125-02S.R7G_SOT23-3
DA5
AZ5125-02S.R7G_SOT23-3
DA6
CONN@
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
1 1 1 1
CA29
CA30
CA31
CA32
NEMC@ NEMC@
Speaker 4 ohm : 40mil
2 2 2 2
LA7
FBMA-L10-160808-800LMT_2P iPhone and Nokia type Combo Jack Speaker 8 ohm : 20mil
1
2 1MIC_IN 40mil MIC_IN_R
FBMA-L10-160808-800LMT_2P LA10
RING2 2 1 40mil RING2_R JHP CONN@
8.2_0402_1% LA8 FBMA-L10-160808-800LMT_2P RING2_R 3
HPOUT-L RA55 1 2 AUD_HP_OUT_LL 2 1 AUD_HP_OUT_L_CN AUD_HP_OUT_L_CN 1
8.2_0402_1% LA9 FBMA-L10-160808-800LMT_2P
HPOUT-R RA56 1 2 AUD_HP_OUT_RL 2 @ 11 AUD_HP_OUT_R_CN
JACK_PLUG# 2 AUD_HP_NB_SENSE_R AUD_HP_NB_SENSE_R 5
0_0402_5%ShortPad RA21
Line-IN-R 6
AUD_HP_OUT_R_CN 2
Line-IN-L MIC_IN_R 4
A
7 A
1
EMC@
AZ5125-02S.R7G_SOT23-3
DA10
AZ5125-02S.R7G_SOT23-3
DA12
RA58
RA57
10K_0402_5%
10K_0402_5%
@ @ 1 1 EMC@ SINGA_2SJ3080-000111F
100P_0402_50V8J
CA38
100P_0402_50V8J
CA40
2
2 2
1
Security Classification Compal Secret Data Compal Electronics, Inc.
CA33 and CA39 change to 9.31K Issued Date 2012/09/11 Deciphered Date 2014/03/12 Title
SD03493118L (S RES 1/16W 9.31K +-1% 0402) THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Audio Codec ALC3221
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1.0
Audio Vender request DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
LA-9103P
Wednesday, July 10, 2013 Sheet 30 of 52
5 4 3 2 1
5 4 3 2 1
拉MS_D2_SD_CLK到Conn pin 14 SD_CLK
D
14 USB20_P6
USB20_P6 4
DLW21SN900SQ2L_0805_4P
4 3
3 USB20_P6_R
再再Via拉到pin 10 MS_D2 D
USB20_N6 1 2 USB20_N6_R +VCC_3IN1
14 USB20_N6 1 2
LR2 EMC@
拉MS_CLK_SD_WP到Conn pin 5 MS_CLK
1 2
Trace width:40mil +3VS
NEMC@ RR8 0_0402_5%
NEMC@ RR7
1 2
0_0402_5% 再再Via拉到pin 22 SD_W +VCC_3IN1
5
UR1
USB20_N6
CARD_3V3
3V3_IN
RR1 2 1 6.19K_0402_1% RREF 1 22 MS_BS JREAD
RREF SP14
1
21 SD_D2 SD_D2 1
R808 +3VS SP13 20 MS_D1_SD_D3 2 SD-DAT2
300_0402_5% USB20_N6_R 2 SP12 19 MS_D1_SD_D3 3 MS-VSS1
USB20_P6_R 3 DM
DP
SP11
SP10
18 SD_CMD close to chip side 4 SD-CD/DAT3 MMC-RSV
MS-VCC
16 MS_D0 MS_CLK_SD_WP 5
2
SP9 15 MS_D2_SD_CLK_R RR2 1 2 0_0402_5% MS_D2_SD_CLK SD_CMD 6 MS-SCLK
1 SP8 SD-CMD MMC-CMD
C155 @ MS_D3 7
15P_0402_50V8J MS_INS# 8 MS-DATA3
1 1 MS-INS
CR1
CR2
RTS5170-GR_QFN24 9
2 14 MS_D2_SD_CLK 10 SD-VSS MMC-VSS1
7 SP7 13 SD_CD# 11 MS-DATA2
2 2 23 XD_CD# SP6 12 MS_D3 MS_D0 12 SD-VDD MMC-VDD
AMD request 5/16 XD_D7 SP5 MS-DATA0
0.1U_0402_16V7K
4.7U_0603_6.3V6K
17 11 SD_D0 MS_D1_SD_D3 13
GPIO0 SP4 10 SD_D1 MS_D2_SD_CLK 14 MS-DATA1
Thermal pad
6 SP3 9 MS_INS# MS_BS 15 SD-CLK MMC-CLK
V18 24 SDREG SP2 8 MS_CLK_SD_WP_R RR3 1 @ 2 0_0402_5% MS_CLK_SD_WP 16 MS-BS
V18 SP1 17 MS-VSS2
SD-VSS MMC-VSS2
CR3
CR4
SD_D0 18
SD_D1 19 SD-DAT0 MMC-DAT
2 2 SD-DAT1
SD_CD# 20
CR5
CR6
C RTS5170-GR_QFN24_4X4 C
25
21 SD-CD 23
SA00005T300 1 1 SD-GND GND1
EMC@ MS_CLK_SD_WP 22 24
1 1 EMC@ SD-WP(SW) GND2
5P_0402_50V8C
5P_0402_50V8C
1U_0402_6.3V6K
1U_0402_6.3V6K
T-SOL_143-2300302602_RV
2 2 CONN@
SP071204100
LTCX004AK00
SD_CMD
1
CR10
EMC@ +VCC_3IN1
22P_0402_50V8J
2
close to chip side 1 1
CR8
CR7
RR4
@
2 2
1
4.7U_0603_6.3V6K
0.1U_0402_16V7K
10K_0402_5%
MS_INS# SD_CD#
1 1
22P_0402_50V8J
CR11
22P_0402_50V8J
CR9
B B
EMC@
2 2 EMC@
close to chip side Close to JREAD1
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/09/11 Deciphered Date 2014/03/12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Card Reader RTS5179
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9103P
Date: Wednesday, July 10, 2013 Sheet 31 of 52
5 4 3 2 1
A B C D E F G H
SATA HDD Conn.
JHDD
1
SATA_FTX_DRX_P0 2 GND
13 SATA_FTX_DRX_P0 3 A+
SATA_FTX_DRX_N0
13 SATA_FTX_DRX_N0 4 A-
CN3 1 2 0.01U_0402_16V7K SATA_PRX_DTX_N0_C 5 GND
13 SATA_FRX_C_DTX_N0 1 2 0.01U_0402_16V7K 6 B-
CN4 SATA_PRX_DTX_P0_C +5V_HDD
13 SATA_FRX_C_DTX_P0 7 B+
GND
1 1
1000P_0402_50V7K
0.1U_0402_16V7K
10U_0805_10V6K
8
+5V_HDD Source +3VS
9 V33
V33 1 1 1
CN6
10
11 V33 CN5 CN7
HDD_DET# 12 GND
14 HDD_DET# 13 GND 2 2 2
14 GND
15 V5
+5V_HDD V5
16
17 V5
18 GND
19 Reserved
+5V_HDD +5VS 20 GND
@ JP13 21 V12 24
1 2 22 V12 GND 23
1 2 V12 GND
JUMP_43X79
SHORT DEFAULT SANTA_194301-1
CONN@
DC010003V00
DC010003Y00 (OLD)
2 2
ODD BTB Conn.
+5VS_ODD
JBTB1
1 2
@ 3 1 2 4 ODD_DETECT#
RN8 1 ShortPad2 0_0402_5% ODD_DA#_R 5 3 4 6 ODD_DETECT# 14
14,36 ODD_DA# 5 6
RN13 1 2 0_0402_5% SATA_FRX_C_DTX_N1_C 7 8 SATA_FTX_DRX_P1_C RH43 2 1 0_0402_5%
RX 13
13
SATA_FRX_C_DTX_N1
SATA_FRX_C_DTX_P1
RN14 1 2 0_0402_5% SATA_FRX_C_DTX_P1_C 9
11
7
9
11
8
10
12
10
12
SATA_FTX_DRX_N1_C RH42 2 1 0_0402_5%
SATA_FTX_DRX_P1
SATA_FTX_DRX_N1
13
13 TX
13 16
14 GND GND 17
15 GND GND 18
GND GND
E-T_1133-Q12C-01R
3 3
SP02000MJ00
SP02000G800 (OLD)
+5VS_ODD
Pleace near ODD CONN
1000P_0402_50V7K
0.1U_0402_16V7K
10U_0805_10V6K
+5VS_ODD
1 1 1
CN11
RX TX
CN10
CN12
ACES_50100-0127N-001
JBTB @
1 2 2 2 2
SATA_FRX_C_DTX_P1_C 3 1 2 4 SATA_FTX_DRX_N1_C
SP02000WP00
ODD Power Control SATA_FRX_C_DTX_N1_C
ODD_DA#_R
5 3
7 5
4 6
6 8
SATA_FTX_DRX_P1_C
( 2nd connector
9 7 8 10 ODD_DETECT#
@ JP7 11 9 10 12
11 12
co-layout with
1 2
1 2 13 14 JBTB1 Main )
15 G1 G2 16
JUMP_43X79 17 G3 G4 18
G5 G6
+5VS +5VS_ODD
CN13 U4
2 1 +5VS 5 1
1U_0402_6.3V6K VIN VOUT
3
13 ODD_EN EN
ODD_EN (Hi Active) U4_SS 4 2
SS GND
2
4 4
RN7 APL3512ABI-TRG_SOT23-5
100K_0402_5% 1
CN16
1
0.1U_0402_16V7K
2
@
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/09/11 Deciphered Date 2014/03/12 Title
+5VS 1 2 U4_SS
0_0402_5%~D @ RN9
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDD/ODD
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9103P
Date: Wednesday, July 10, 2013 Sheet 32 of 52
A B C D E F G H
5 4 3 2 1
9/20 OAK Intel USB3.0 issue
Change LI1, LI3, LI4, LI6 Part
PN: from SM01002080L (S SUPPRE_ MURATA DLW21SN900SQ2L 0805)
To SM070000S80 (S COM FI_ CHENG HANN WCM2012F2SF-670T04)
1/22 Change LI1, LI3, LI4, LI6 Part
PN: from SM070000S80 (S COM FI_ CHENG HANN WCM2012F2SF-670T04)
To SM070001E00 (S COM FI_ MURATA DLW21SN900HQ2L)--Main
To SM070001S00 (S COM FI_ KINGCORE WCM-2012HS-900T )--2nd
EMC@
LI1 +5VALW
USB3P3RN1 1 2 USB3P3RN1_L
14 USB3P3RN1 1 2
D D
USB3P3RP1 4 3 USB3P3RP1_L 1 1
14 USB3P3RP1 4 3 CI12 CI14
FI_ MURATA DLW21SN900HQ2L
1 2 4.7U_0805_10V4Z
2 2
0.1U_0402_16V7K 2.0A +5V_USB_PWR1
USB conn.1
NEMC@ RI1 0_0402_5%
1 2 UI3
NEMC@ RI2 0_0402_5% 1 8 +5V_USB_PWR1
2 GND VOUT 7
80mil JUSB1
3 VIN VOUT 6 USB3P3TP1_L 9
VIN VOUT SSTX+
EPAD
USB_EN# 4 5 1
34,36 USB_EN# EN FLG USB_OC0# 14 8 VBUS
USB3P3TN1_L
LI3 EMC@ USB2P13_P1_LR 3 SSTX-
1 1 1 D+
0.1U_0402_16V7K
USB3P3TN1 2 1 USB3P3TN1_C 1 2 USB3P3TN1_L CI13 CI15 @ 1 7
14 USB3P3TN1
9
1 2 GND
CI2
CI3 0.1U_0402_16V7K @ AP2301MPG-13_MSOP8 CI1 + USB2P13_N1_LR 2 10
D- GND
0.1U_0402_16V7K
0.1U_0402_16V7K USB3P3RP1_L 6 11
SSRX+ GND
2
USB3P3TP1 2 1 USB3P3TP1_C 4 3 USB3P3TP1_L 2 2 220U_6.3V_M 4 12
14 USB3P3TP1 4 3 2 2 GND GND
PESD5V0U2BT_SOT23-3
DI2
CI4 0.1U_0402_16V7K USB3P3RN1_L 5 13
FI_ MURATA DLW21SN900HQ2L SSRX- GND
1 2 ACON_TARA4-9K1311
NEMC@ RI4 0_0402_5% EMC@ CONN@
1 2
NEMC@ RI6 0_0402_5% EMC@
DI1
1
USB3P3RN1_L 1 10 USB3P3RN1_L
LI2 EMC@
USB2P13_N1 1 2 USB2P13_N1_LR USB3P3RP1_L 2 9 USB3P3RP1_L
14 USB2P13_N1 1 2
USB3P3TN1_L 4 7 USB3P3TN1_L
USB2P13_P1 4 3 USB2P13_P1_LR
14 USB2P13_P1 4 3 5 6
USB3P3TP1_L USB3P3TP1_L
DLW21SN900SQ2L_0805_4P
1 2 3
NEMC@ RI3 0_0402_5%
C
8 C
1 2
NEMC@ RI5 0_0402_5% IP4292CZ10-TBR_XSON10_2.5X1
LI4 EMC@
USB3P0RN2 1 2 USB3P0RN2_L +5VALW
14 USB3P0RN2 1 2
USB3P0RP2 4 3 USB3P0RP2_L
14 USB3P0RP2 4 3
1 1
FI_ MURATA DLW21SN900HQ2L CI6 CI7
1 2
NEMC@ RI13 0_0402_5% 4.7U_0805_10V4Z
2 2
0.1U_0402_16V7K 2.0A +5V_USB_PWR2
1 2
NEMC@ RI14 0_0402_5% UI2
1 8 80mil
2 GND VOUT 7
B VIN VOUT B
3 6
VIN VOUT
EPAD
USB_EN# 4 5
14 USB3P0TN2
USB3P0TN2 2 1 USB3P0TN2_C 1
LI6 EMC@
1 2
2 USB3P0TN2_L 1
EN FLG
1
USB_OC2# 14
USB conn.2
CI10 0.1U_0402_16V7K CI26 CI17 @
9
@ AP2301MPG-13_MSOP8
0.1U_0402_16V7K
USB3P0TP2 2 1 USB3P0TP2_C 4 3 USB3P0TP2_L 0.1U_0402_16V7K
14 USB3P0TP2 4 3 2 2
CI11 0.1U_0402_16V7K
FI_ MURATA DLW21SN900HQ2L +5V_USB_PWR2
1 2 JUSB2 CONN@
NEMC@ RI17 0_0402_5% USB3P0TP2_L 9
1 SSTX+
1 2 USB3P0TN2_L 8 VBUS
NEMC@ RI18 0_0402_5% USB2P10_P2_LR 3 SSTX-
1 D+
0.1U_0402_16V7K
1 7
GND
CI9
CI8 + USB2P10_N2_LR 2 10
USB3P0RP2_L 6 D- GND 11
SSRX+ GND
2
220U_6.3V_M 4 12
2 2 GND GND
PESD5V0U2BT_SOT23-3
DI5
USB3P0RN2_L 5 13
LI5 EMC@ EMC@ SSRX- GND
USB2P10_N2 1 2 USB2P10_N2_LR DI4 EMC@ ACON_TARA4-9K1311
14 USB2P10_N2 1 2 1 10
USB3P0RN2_L USB3P0RN2_L
USB2P10_P2 4 3 USB2P10_P2_LR USB3P0RP2_L 2 9 USB3P0RP2_L
14 USB2P10_P2 4 3
DLW21SN900SQ2L_0805_4P USB3P0TN2_L 4 7 USB3P0TN2_L
1
1 2
NEMC@RI15 0_0402_5% USB3P0TP2_L 5 6 USB3P0TP2_L
1 2 3
NEMC@ RI16 0_0402_5%
8
IP4292CZ10-TBR_XSON10_2.5X1
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/09/11 Deciphered Date 2014/03/12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
USB3.0
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9103P
Date: Wednesday, July 10, 2013 Sheet 33 of 52
5 4 3 2 1
5 4 3 2 1
+5VALW
1 1
CI23 CI22
4.7U_0805_10V4Z
2 2
0.1U_0402_16V7K 2.0A +5V_USB_PWR3
D D
UI4
1 8 80mil
2 GND VOUT 7
3 VIN VOUT 6
VIN VOUT
EPAD
USB_EN# 4 5
33,36 USB_EN# EN FLG USB_OC3# 14
1 1 @
CI16 CI24
9
@ AP2301MPG-13_MSOP8
USB conn.3
0.1U_0402_16V7K
0.1U_0402_16V7K
2 2
+5V_USB_PWR3
JUSB3
1
USB2P0_N3_LR 2 VBUS
USB2P0_P3_LR 3 D-
1 D+
0.1U_0402_16V7K
1 4
GND
CI19
CI20 + 5
6 GND
GND
2
EMC@ 220U_6.3V_M 7
2 2 GND
PESD5V0U2BT_SOT23-3
DI7
LI7 8
USB2P0_N3 1 2 USB2P0_N3_LR GND
14 USB2P0_N3 1 2 EMC@ ACON_UARBG-4K1926
CONN@
USB2P0_P3 4 3 USB2P0_P3_LR
14 USB2P0_P3 4 3
Place close to JUSB3
DLW21SN900SQ2L_0805_4P USB 2.0 Port 2
1 2
1
NEMC@ RI25 0_0402_5%
DC233007P00
1 2
NEMC@ RI21 0_0402_5%
DC233007P00(OLD)
C C
+5VALW
1 1
CI31 CI30
4.7U_0805_10V4Z
2 2
0.1U_0402_16V7K 2.0A +5V_USB_PWR4
B B
UI5
EMC@ 1 8 80mil
LI10 2 GND VOUT 7
14 USB2P2_N4
USB2P2_N4 1
1 2
2 USB2P2_N4_LR
USB_EN#
3
4
VIN
VIN
EN
EPAD
VOUT
VOUT
FLG
6
5
USB_OC1# 14
USB conn.4
USB2P2_P4 4 3 USB2P2_P4_LR 1 1
14 USB2P2_P4 4 3 CI25 CI32 @
9
DLW21SN900SQ2L_0805_4P @ AP2301MPG-13_MSOP8 +5V_USB_PWR4
0.1U_0402_16V7K
1 2 0.1U_0402_16V7K
@ RI32 0_0402_5% 2 2
JDB
1 2 1
@ RI28 0_0402_5% 2 1
3 2
USB2P2_P4_LR 4 3
USB2P2_N4_LR 5 4
6 5 9
7 6 G1 10
7 G2
2
8
8
PESD5V0U2BT_SOT23-3
DI8
EMC@ ACES_51524-0080N-001
CONN@
SP01001A900
1
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/09/11 Deciphered Date 2014/03/12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MB to USB2.0 DB
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9103P
Date: Wednesday, July 10, 2013 Sheet 34 of 52
5 4 3 2 1
5 4 3 2 1
+1.5VS +1.5VS_WLAN
2
ShortPad 1
0_0402_5% @ R21
+3VS +3VS_WLAN
Mini WLAN/WIMAX H=6.7
2
ShortPad 1
0_0402_5% @ R20
+3VS_WLAN +3VS_WLAN
D D
JMINI +1.5VS_WLAN
WLAN_WAKE# 1 2 +3VS
36 WLAN_WAKE# 3 1 2 4
5 3 4 6 +3VS
5 6
1
WLAN_CLKREQ# 7 8
14 WLAN_CLKREQ# 9 7 8 10 R110
CLK_PCIE_WLAN# 11 9 10 12
12 CLK_PCIE_WLAN# 11 12 10K_0402_5%
12 CLK_PCIE_WLAN CLK_PCIE_WLAN 13 14
13 14
2
15 16
G
2
@ 17 15 16 18
BT_ON# 2 1 19 17 18 20 1 3
R12 0_0402_5% 21 19 20 22 2
@ WLAN_RADIO_DIS#_R
1 PLT_RST#
WL_OFF# WL_OFF# 13
S
21 22 PLT_RST# 12,29,36
PCIE_FRX_DTX_N1 23 24 R16 ShortPad 0_0402_5% QV30
5 PCIE_FRX_DTX_N1 25 23 24 26
PCIE_FRX_DTX_P1 2N7002K 1N SOT23-3
5 PCIE_FRX_DTX_P1 27 25 26 28
29 27 28 30 FCH_SCLK0_R R18 2 @ 10_0402_5% FCH_SCLK0
31 29 30 32 2 1 FCH_SCLK0 10,11,14
5 PCIE_FTX_DRX_N1 PCIE_FTX_DRX_N1 FCH_SDATA0_R FCH_SDATA0
33 31 32 34 FCH_SDATA0 10,11,14
5 PCIE_FTX_DRX_P1 PCIE_FTX_DRX_P1 R19 @ 0_0402_5%
35 33 34 36 USB20_N4
37 35 36 38 USB20_N4 14
USB20_P4
39 37 38 40 USB20_P4 14
41 39 40 42
43 41 42 44 WLAN_LED_EC_R 2 1 WLAN_LED_EC
45 43 44 46 WLAN_LED_EC 36
BT_LED_EC_R R22 2 10_0402_5% BT_LED_EC
47 45 46 48 BT_LED_EC 36
@ R23 0_0402_5%
1 47 48
36 EC_TX
EC_TX
EC_RX
@ 2
R14 1 ShortPad20_0402_5%
49
51 49 50
50
52
36 EC_RX 51 52
R15 ShortPad 0_0402_5%
BT_ON# R13 2 1 1K_0402_1% 53 54 +3VS +3VS +3VALW +3VALW
13 BT_ON# GND1 GND2
2
R11
1
CONCR_525B01BE17A @ @
100K_0402_5% CONN@ R111 R112 R113 R114
10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%
1
2
靠靠wlan connector
C C
WLAN_LED_EC_R BT_LED_EC_R WLAN_LED_EC_R BT_LED_EC_R
+1.5VS +3VS CC47
R111, R112
0.047U_0402_16V4Z
0.047U_0402_16V4Z
0.047U_0402_16V4Z
0.047U_0402_16V4Z
0.1U_0402_16V7K
0.1U_0402_16V7K
4.7U_0603_6.3V6K
47PF_0402_50V8
0.1U_0402_16V7K
C87
1
@
1 1 1 @ 1 1 2 2 1 1 Please Close to JMINI
C47
C46
C48
47PF_0402_50V8
C50
C45
C40
C42
C43
C88
@
2 2 @ 2 @ 2 2 2 1 1 2 2
HDD LED Battery LED
LED2
B LTW-110DC5-C 3.2X1 WHITE White B
R2 R3
HDD_LED# 1 2 1 2 BATT_CHG_LED# 1 2 2
13 HDD_LED# +5VS 36 BATT_CHG_LED#
680_0402_1%
390_0402_5% R4 1 +5VALW
3
BATT_LOW_LED# 1 2 3
36 BATT_LOW_LED#
390_0402_5%
Amber
Power LED LED3
LTW-S115KFDS-5A 1204 WHITE/ORANGE
10mils, All pins LED1
LTW-110DC5-C 3.2X1 WHITE
R1
PWR_LED# 1 2 1 2 +5VALW
390_0402_5%
Wireless LED
3
1
D
2 Q1 LED4
36 PWR_PWM_LED#
G LTW-110DC5-C 3.2X1 WHITE
S 2N7002K 1N SOT23-3 R9
3
1
WL_BT_LED# 1 2 1 2
36 WL_BT_LED# +5VALW
R786 680_0402_1%
100K_0402_5%
3
2
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/09/11 Deciphered Date 2014/03/12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Mini Card/LED
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9103P
Date: Wednesday, July 10, 2013 Sheet 35 of 52
5 4 3 2 1
5 4 3 2 1
+3VALW LE1
@ FBMA-L11-160808-800LMT_0603 Board ID
1 2 0.1U_0402_16V7K 0.1U_0402_16V7K +3VALW_EC 1 2 +EC_VCCA +3VALW
RE1 ShortPad 0_0805_5%
1 1 1 1 2 2 1
CE1 CE2 CE3 CE4 CE5 CE6 @ 0.1U_0402_16V7K
2
D @ CE7 D
1000P_0402_50V7K RE3
2 2 2 2 1 1 2 ECAGND 1 @ 2 ECAGND_EC 100K_0402_5%
ECAGND_EC 41 Ra
0.1U_0402_16V7K 0.1U_0402_16V7K 1000P_0402_50V7K RE7 0_0402_5%
@
1
1 2 +3VLP AD_BID0
RE4 ShortPad 0_0402_5%
2
1
111
125
Reserved for KB9012 RE5 CE8
22
33
96
67
9
UE1 Rb 0_0402_5%
EC_VDD0
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/AVCC
2
1
0.1U_0402_16V7K
GATEA20 1 21 KB_LED_PWM
14 GATEA20 2 GATEA20/GPIO00 GPIO0F 23 KB_LED_PWM 38
KB_RST# BEEP# Analog Board ID definition,
14 KB_RST# 3 KBRST#/GPIO01 BEEP#/GPIO10 26 BEEP# 30
SERIRQ ECPWM1 T103
12 SERIRQ LPC_FRAME# 4 SERIRQ GPIO12 27 ACOFF Please see page 4.
12
LPC_FRAME# 5 LPC_FRAME# ACOFF/GPIO13 ACOFF 42 2 1
CE10 LPC_AD3 ECAGND
12 LPC_AD3 7 LPC_AD3
NEMC@ 22P_0402_50V8J NEMC@ LPC_AD2 PWM Output CE9 100P_0402_50V8J
2 1 2 1 12 LPC_AD2 8 LPC_AD2 63
RE6 33_0402_5% LPC_AD1 BATT_TEMP
+3VALW 12 LPC_AD1 10 LPC_AD1 BATT_TEMP/GPIO38 64 BATT_TEMP 41,42
LPC_AD0 LPC & MISC
12 LPC_AD0 LPC_AD0 GPIO39 65 ADP_I
12 ADP_I/GPIO3A 66 ADP_I 41,42
AD Input AD_BID0
1 2 12,16 CLK_PCI_EC 13 CLK_PCI_EC GPIO3B 75
KSO1
2 1 47K_0402_5% 12,29,35 PLT_RST# 37 PCIRST#/GPIO05 GPIO42 76
RE62 @ 47K_0402_5% +3VALW RE8 EC_RST# #ECAD5 T104 +5VS
EC_SCI# 20 EC_RST# IMON/GPIO43
1 2 2 1 14 EC_SCI# 38 EC_SCII#/GPIO0E
KSO2 CE11 0.1U_0402_16V7K
RE63 @ 47K_0402_5% GPIO1D 68 TP_CLK 2 1
DAC_BRIG/GPIO3C T122
70 EN_DFAN1 4.7K_0402_5% RE9
1 2 EN_DFAN1/GPIO3D 71 EN_DFAN1 38 2 1
LID_SW# DA Output T113 TP_DATA
RE71 10K_0402_5% KSI0 55 IREF/GPIO3E 72 4.7K_0402_5% RE10
56 KSI0/GPIO30 CHGVADJ/GPIO3F LCD_TEST 18
KSI1
1 2 WLAN_WAKE# KSI2 57 KSI1/GPIO31
RE70 10K_0402_5% KSI3 58 KSI2/GPIO32 83 EC_MUTE# +5VALW
59 KSI3/GPIO33 EC_MUTE#/GPIO4A 84 EC_MUTE# 30
KSI4 USB_EN#
1 2 60 KSI4/GPIO34 USB_EN#/GPIO4B 85 USB_EN# 33,34
@ EC_SMI# KSI5 TL_SMB_CK
KSI[0..7] 61 KSI5/GPIO35 CAP_INT#/GPIO4C 86 TL_SMB_CK 17
C RE16 1K_0402_1% KSI6 PS2 Interface TL_SMB_DA USB_EN# RE504 1 2 10K_0402_5% C
38 KSI[0..7] 62 KSI6/GPIO36 EAPD/GPIO4D 87 TL_SMB_DA 17
KSI7 TP_CLK
1 2 KSO[0..16] 39 KSI7/GPIO37 TP_CLK/GPIO4E 88 TP_CLK 38
EC_PME# KSO0 TP_DATA
38 KSO[0..16] 40 KSO0/GPIO20 TP_DATA/GPIO4F TP_DATA 38
RE21 10K_0402_5% KSO1 CE18 100P_0402_50V8J
KSO2 41 KSO1/GPIO21 ACIN 2 1
KSO3 42 KSO2/GPIO22 97
KSO3/GPIO23 CPU1.5V_S3_GATE/GPXIOA00 T115
KSO4 43 98 WOL_EN
44 KSO4/GPIO24 WOL_EN/GPXIOA01 99 WOL_EN 29 WOL_EN (Hi Active)
KSO5 APU_ALERT#_EC CE21 100P_0402_50V8J
+3VALW PM_SLP_S5# PM_SLP_S3# KSO6 45 KSO5/GPIO25 Int. K/B ME_EN/GPXIOA02 109 1 2
T128
BATT_TEMP 2 1
+3VS KSO7 46 KSO6/GPIO26 Matrix VCIN0_PH/GPXIOD00 RE15@ 0_0402_5%
VCIN0_PH 41
KSO7/GPIO27 SPI Device Interface
RPE1 1 NEMC@ 1 NEMC@ KSO8 47 ShortPad
1 8 EC_SMB_CK1_R CE14 CE15 KSO9 48 KSO8/GPIO28 119 5V_EC_ON EC_LID_OUT# 1 2 NEMC@
KSO9/GPIO29 SPIDI/GPIO5B T119
2 7 EC_SMB_DA1_R KSO10 49 120 CE27 1000P_0402_50V7K
KSO10/GPIO2A SPIDO/GPIO5C T116
3 6 EC_SMB_CK2_R KSO11 50 SPI Flash ROM 126
2 2 KSO11/GPIO2B SPICLK/GPIO58 T117
4 5 EC_SMB_DA2_R KSO12 51 128 1 2 WL_BT_LED# EC_RSMRST# 1 2 NEMC@
52 KSO12/GPIO2C SPICS#/GPIO5A WL_BT_LED# 35 +3VLP
0.1U_0402_16V7K 0.1U_0402_16V7K KSO13 RE67 @ 0_0402_5% CE26 1000P_0402_50V7K
2.2K_0804_8P4R_5% KSO14 53 KSO13/GPIO2D ShortPad
KSO15 54 KSO14/GPIO2E 73 ENBAKL
KSO15/GPIO2F ENBKL/GPIO40 ENBAKL 17 Reserve for ESD
1
ESD Request at SSI KSO16 81 74 PECI_KB930 CE26, CE27 please close to UE1
82 KSO16/GPIO48 PECI_KB930/GPIO41 89 RE30
KSO17/GPIO49 FSTCHG/GPIO50 90 PX_MODE 23,44,47,48
BATT_CHG_LED# @ 47K_0402_5%
BATT_CHG_LED#/GPIO52 91 BATT_CHG_LED# 35
CAPS_LED
CAPS_LED#/GPIO53 CAPS_LED 38
EC_SMB_CK1 1 RE26 2 0_0402_5% EC_SMB_CK1_R 77 GPIO 92 PWR_PWM_LED#
41,42 EC_SMB_CK1 PWR_PWM_LED# 35
2
EC_SMB_DA1 1 RE27 2 0_0402_5% EC_SMB_DA1_R 78 EC_SMB_CK1/GPIO44 PWR_LED#/GPIO54 93 BATT_LOW_LED#
41,42 EC_SMB_DA1 79 EC_SMB_DA1/GPIO45 BATT_LOW_LED#/GPIO55 95 BATT_LOW_LED# 35
EC_SMB_CK2_R SM Bus SYSON VCIN1_PH
+3VS 1 RE28@ 2 0_0402_5% EC_SMB_DA2_R 80 EC_SMB_CK2/GPIO46 SYSON/GPIO56 121 VR_ON
SYSON 39,44
22,7 EC_SMB_CK2 1 RE29@ 2 0_0402_5%
ShortPad EC_SMB_DA2/GPIO47 VR_ON/GPIO57 127 VGA_ON
VR_ON 49
reserve for KB9012 Rev.A2
22,7 EC_SMB_DA2 PM_SLP_S4#/GPIO59 VGA_ON 14
ShortPad
ShortPad
@ ShortPad
1 2 EC_SCI#
14 PM_SLP_S3#
@
1 RE31 2 0_0402_5% PM_SLP_S3#_R 6 100 EC_RSMRST#
EC_RSMRST# 14
PECI_KB930 1 @ 2
WLAN_WAKE# 35
RE32 10K_0402_5% @
1 RE33 2 0_0402_5% PM_SLP_S5#_R 14 PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXIOA03 101 EC_LID_OUT# RE69 0_0402_5%
1 2 14 PM_SLP_S5# 15 PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXIOA04 102 EC_LID_OUT# 14
@ TL_SMB_CK EC_SMI# VCIN1_PH
RE35 1 2
10K_0402_5% TL_SMB_DA @14 EC_SMI# 16 EC_SMI#/GPIO08 PROCHOT_IN/GPXIOA05 103 VCOUT1_PH
VCIN1_PH 41
GPU_AC_LIGHT 1 2
RE36 @ 10K_0402_5% CE_EN @ 41 PS_ID
ShortPad 17 GPIO0A H_PROCHOT#_EC/GPXIOA06 104 VCOUT0 2 RE37 10_0402_5% RE80 @ 0_0402_5%
ACIN_65W 22
18 CE_EN 18 GPIO0B VCOUT0_PH/GPXIOA07 105 VCOUT0_PH 43
ShortPad GPO BKOFF# @ ShortPad ShortPad
19 GPIO0C BKOFF#/GPXIOA08 106 BKOFF# 17
ODD_DA# GPIO PBTN_OUT#
14,32 ODD_DA# 25 GPIO0D PBTN_OUT#/GPXIOA09 107 PBTN_OUT# 14
@ DBC_EN GPU_AC_LIGHT T106
1 @ 2 18 DBC_EN 28 EC_INVT_PWM/GPIO11 PCH_APWROK/GPXIOA10 108
B WLAN_LED_EC FAN_SPEED1 B
RE34 1 2 10K_0402_5%
BT_LED_EC 38 FAN_SPEED1 EC_PME# 29 FAN_SPEED1/GPIO14 SA_PGOOD/GPXIOA11
RE38 10K_0402_5% EC_TX 30 EC_PME#/GPIO15
35 EC_TX 31 EC_TX/GPIO16 110
EC_RX
35 EC_RX 32 EC_RX/GPIO17 AC_IN/GPXIOD01 112 ACIN 41,42
FCH_POK
14 FCH_POK 34 PCH_PWROK/GPIO18 EC_ON/GPXIOD02 114 EC_ON 43
WLAN_LED_EC
RE34, RE38 35
35
WLAN_LED_EC
BT_LED_EC
BT_LED_EC 36 SUSP_LED#/GPIO19
NUM_LED#/GPIO1A GPI
ON/OFF/GPXIOD03
LID_SW#/GPXIOD04
115 LID_SW# ON/OFF 38
LID_SW# 38
116 SUSP#
Please Close to UE1 SUSP#/GPXIOD05
GPXIOD06
117 SUSP# 39,44,46
45W/65W# 41
118
@ 122 PECI_KB9012/GPXIOD07
AGND/AGND
1 ShortPad 2 EC_CRY2 123 XCLKI/GPIO5D 124 +V18R
GND/GND
GND/GND
GND/GND
GND/GND
12,16 RTC_CLK XCLKO/GPIO5E V18R
FAN_SPEED1 RE43 0_0402_5% 1
GND0
NEMC@ 2 RE45 1 100K_0402_5% CE16
1
CE29 1 2 4.7U_0805_10V4Z
CE17 20P_0402_50V8 KB9012QF-A4_LQFP128_14X14 2
11
24
35
94
113
69
0.1U_0402_16V7K NEMC@ 20mil
2 LE2
ECAGND 2 1
FBMA-L11-160808-800LMT_0603
Please close to EC
@
ShortPad
1 2 EC_PME#
14,29 FCH_PCIE_WAKE# RE61 0_0402_5%
@
7 H_PROCHOT#_EC H_PROCHOT#_EC 2 ShortPad 1 VCOUT1_PH
RE44 0_0402_5%
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/09/11 Deciphered Date 2014/03/12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
EC ENE-KB9012
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9103P
Date: Wednesday, July 10, 2013 Sheet 36 of 52
5 4 3 2 1
5 4 3 2 1
D D
Screw Hole
H3 H2 H5 H8 H9
H_2P8 H_2P8 H_2P8 H_2P8 H_2P8
@ @ @ @ @
1
H11 H12 H16 H17
H_2P8 H_2P8 H_2P8 H_2P8
@ @ @ @
1
C C
H31 H32 H33 H34
H_3P7 H_3P7 H_3P7 H_3P7
FD1
@ FIDUCAL
FD2
@ FIDUCIAL
FD3
@ FIDUCAL
FD4
@ FIDUCIAL
@ @ @ @
APU Screw Hole
1
1
1
H6 H7
H_3P3 H_3P3
@ @
GPU Screw Hole
1
H10
H_3P3
@
FAN Screw Hole
1
H4 H18
H_3P0X5P0N H_5P0N
@ @
1
H19
H_3P0N
@
1
B B
H13 H14
H_3P5 H_3P5
@ @
ODD Screw Hole
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/09/11 Deciphered Date 2014/03/12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Screw Hole
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9101P
Date: Wednesday, July 10, 2013 Sheet 37 of 52
5 4 3 2 1
5 4 3 2 1
+FAN_POWER
FAN Control circuit
D D
Power ON Circuit +3VLP
40mil +5VS
2.2U_0603_6.3V6K
1
@
1000P_0402_50V7K
1 1
RV301
ON/OFF switch
2
CE22 CE23 0_0603_5%
RE49
100K_0402_5% 2 2 CE25
TOP Side
2
2.2U_0603_6.3V6K
@ SW1 +FAN_PWR 1 2
1
SMT1-05-A_4P
1 3
ON/OFF 36
UE3
2 4 1 1 8
CE20 2 VEN GND 7
3 VIN GND 6
6
5
EN_DFAN1 4 VO GND 5
2 0.1U_0402_16V7K 36 EN_DFAN1 VSET GND
APE8875M SO 8P
Bottom Side
@ SW2 +3VS
SMT1-05-A_4P +FAN_POWER
1 3
1
2 4 RE50 40mil JFAN
10K_0402_5% 1
2 1
6
5
3 2
2
3
C
4 C
36 FAN_SPEED1 5 GND
GND
1 ACES_85204-0300N
Pop only for @ CONN@
CE24
SSI debug 0.01U_0402_16V7K
2
POWER/B INT_KBD Conn.
+3VALW 36 KSI[0..7]
KSI[0..7] * Key Board Back Light
KSO[0..16]
36 KSO[0..16]
JPWR
1
LID_SW# 2 1 JKB
36 LID_SW# 3 2
ON/OFF +5VS FE1 KBBL@ +5VS_KBL
4 3 CONN@
4 HB_A823020-SBHR21 0.75A_24V_1812L075-24DR
5 30 32
GND 30 GND 31
3
6 KSI7 29 2 1
GND 29 GND
10U_0603_6.3V6M
DE5 KSI6 28 20mil
28
1U_0603_10V6K
PESD24VS2UT_SOT23-3 HB_A090420-SAHR21 KSI4 27 1 2
NEMC@ CONN@ KSI2 26 27 RE59
B 26 1 1 B
CE56
KSI5 25 0_0805_5%
25
CE57
KSI1 24 KBBL@ KBBL@
SP01001G200 @
1
KSI3 23 24
KSI0 22 23 2 2
SP01000Z300 (OLD) KSO5 21 22
KSO4 20 21
KSO7 19 20
KSO6 18 19
KSO8 17 18
KSO3 16 17
KSO1 15 16 +3VS
KSO2 14 15
Touch pad KSO0
KSO12
13
12
14
13
12
KBBL@
RE68
KSO16 11 1 2
11 14 KB_DET#
KSO15 10
+3VS KSO13 9 10 10K_0402_5% +5VS_KBL
KSO14 8 9
JTP KSO9 7 8 JKBBL
7
1
1 +5VS KSO11 6 D 1
TP_CLK 2 1 RE60 KSO10 5 6 2 2 1
36 TP_CLK 3 2 1 2 4 5 3 2
TP_DATA KB_CAPS_PWR G
36 TP_DATA 4 3 3 4 4 3
QE4 KB_BL_PWM
SP01001H500 S
3
4 3 4
1
FCH_SCLK1_TP 5 7 240_0402_1% 2 2N7002BKW_SOT323-3
14 FCH_SCLK1_TP 6 5 G1 8 1 2 5
FCH_SDATA1_TP KB_CAPS_PWR- KBBL@ RE58
14 FCH_SDATA1_TP 6 G2 1 100K_0402_5%
20mil GND 6
GND
3
ACES_51524-0060N-001 KBBL@
PESD5V0U2BT_SOT23-3
DE3
CONN@ HB_A090420-SAHR21
1
2
5
6
CONN@
1
D D QE5
NEMC@ 2 QE3 G SI3456BDV-T1-E3 1N TSOP6
36 CAPS_LED 3
G SSM3K7002FU_SC70-3~D
36 KB_LED_PWM S
S KBBL@
3
4
1
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/09/11 Deciphered Date 2014/03/12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
FAN/TP/KB/PWR SW
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9103P
Date: Wednesday, July 10, 2013 Sheet 38 of 52
5 4 3 2 1
A B C D E
+1.1VALW to +1.1VS +1.5V To +1.5VS
+5VALW to +5VS +1.1VALW UZ36 +1.1VS
AP4800BGM-HF_SO-8
8 1 QZ55
+3VALW to +3VS 1 7 2 1 1
+1.5V SI3456BDV-T1-E3 1N TSOP6
1
6 3 +1.5VS
0.1U_0603_16V7K
D
CZ712 5 CZ713 CZ714 6
S
+5VALW +5VS 10U_0603_6.3V6M 1U_0603_10V6K RZ590 5 4
2 2 2
10U_0805_10V6K
470_0603_5% 2
Shape Shape
1
1U_0603_10V6K
U6 @ 1 1 1
CZ18
CZ19
1 14 +5VALW
G
2 VIN1 VOUT1 13 R581
1 1
3
VIN1 VOUT1
1
B+_BIAS D
1U_0603_10V6K
10U_0805_10V6K
1U_0603_10V6K
1 1 1 470_0603_5%
1
CZ1 SUSP# 3 12 CZ3 CZ4 QZ62 2 SUSP 2 2 @
2
ON1 CT1 G
2N7002K_SOT23-3
1
4 11 @ S RZ18
3
VBIAS GND
1
2 2 2 10K_0402_5% D
+3VALW 1 2 SUSP#_C 5 10 +3VS 75K_0402_5% Q58 2 SUSP
2
RZ25 0_0402_5% ON2 CT2 RZ594 RZ20 G
2N7002K_SOT23-3
6 9 RZ669 +1.5VS_GATE1 2 +1.5VS_GATE_R @ S
3
7 VIN2 VOUT2 8 1.1VS_GATE 1 2 1.1VS_GATE_R 7.5K_0402_5%
VIN2 VOUT2
1
47K_0402_5% D
10U_0805_10V6K
1U_0603_10V6K
1 1
1
D
Shape
1U_0603_10V6K
15 SUSP 2
CZ20
RZ596
0.1U_0603_16V7K
1
CZ2 1
GPAD Shape 1 1
SUSP 2 0_0402_5% CZ715 G QZ11
CZ13
CZ14
@ TPS22966DPUR_SON14_2X3 G QZ65 @ 0.1U_0603_25V7K S SSM3K7002FU_SC70-3
3
CZ5 S 2N7002K_SOT23-3 2 2
1
2 2 2
0.1U_0402_16V7K
2
1000P_0402_50V7K
470P_0402_50V7K
1 1
CZ15
CZ9
2 2
+3VLP +5VALW
+5VALW
1
RISE TIME (µs)
CTx(pF) @ RZ591 RZ10 @
5V 3.3V 100K_0402_5% 100K_0402_5% RZ19
100K_0402_5%
2
0 124 88 SUSP
2
2 SYSON# 2
1
220 481 323
1
QZ8 @
OUT
470 855 603 DDTC124EKA-7-F NPN SC59-3 QZ12
OUT
DDTC124EKA-7-F NPN SC59-3
1000 1724 1185 2
36,44,46 SUSP# IN 2
GND
36,44 SYSON IN
2200 3328 2240 @ @
GND
1 1
CZ16
CZ21
4700 7459 4950
0.1U_0603_16V7K
0.1U_0603_16V7K
3
3
10000 16059 10835 2 2
+0.75VS
+1.5V
1
@
RZ24
1
@
470_0402_5% RZ27
2
470_0402_5%
2
+VCCP_D
+1.5V_D
3 3
1
D D @
SUSP 2 @ SYSON# 2
G QZ13 G QZ15
S SSM3K7002FU_SC70-3 S SSM3K7002FU_SC70-3
3
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/09/11 Deciphered Date 2014/03/12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC/DC Interface
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9103P
Date: Wednesday, July 10, 2013 Sheet 39 of 52
A B C D E
5 4 3 2 1
Version Change List ( P. I. R. List ) Page 1
Request
Item Page# Title Date Issue Description Solution Description Rev.
Owner
The M3 traces are routed to the Sandy Bridge Processor reserved pins for DDR3
1 08,11,12 DIMM 11/07/28 COMPAL VREF Intel CHKLST Rev1.5 required 0.1
D D
10
11
12
13
C C
14
15
16
17
18
B B
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/09/11 Deciphered Date 2014/03/12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HW-PIR
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, July 10, 2013 Sheet 40 of 52
5 4 3 2 1
A B C D
PL901
VIN +3VALW
SMB3025500YA_2P
ADPIN 1 2
PR901
1000P_0402_50V7K
1000P_0402_50V7K
@ PJPDC @ 0_0402_5%
2.2K_0402_5%
100P_0402_50V8J
100P_0402_50V8J
1
1
1 1 2
1
2
2
PC901
PC902
PC903
PC904
2 3
2
3 4
PR902
4 5 PR903
5 33_0402_5%
1
6 PSID-6 1 3 PSID-3 1 2
S
1
GND 7 PQ901 PS_ID 36
1
GND FDV301N_G_SOT23-3
ACES_50299-00501-003
SMB3025500YA_2P
G
2
1
100K_0402_1%
2
PL903
JUMP_43X79
PJP900
PL902 +5VALW
PR904
TAI-TECH FCM1005KF-102T03 0402
PSID 2 1 PSID-2
10K_0402_1%
@
1
@
PR905
C
PSID-1 2 PQ900
B
15K_0402_1%
MMST3904-7-F_SOT323~D
2
E
2
PR900
1
1
PD901 PD902
1
TVNST52302AB0_SOT523-3 TVNST52302AB0_SOT523-3
BATT+ BATT++ @ @
3
BATT+
PL900
SMB3025500YA_2P
1 2 BATT++
PD900
100P_0402_50V8J
1
4 3
1000P_0402_50V7K
100P_0402_50V8J
0.01U_0402_25V7K
V I/O V I/O
1
PC900
PC907
PC905
PC906
5 2
2
V BUS Ground JRTC
2
6 1 @
2 V I/O V I/O 2
2 1 3 1
IP4223CZ6_SO6~D - + +RTCBATT B+ B+_BIAS
100K_0402_1%
0.1U_0402_25V6
0.22U_0603_25V7K
1
1
PR907
PC908
PC909
1
2
@ SUYIN_060003FA002G202NL
2
PR919 PQ902
0_0402_5% +5VALW PR908 TP0610K-T1-E3_SOT23-3
2
22K_0402_1%
PBATT @ BATT_TEMP 36,42 1 2 VSB_N_001
1VSB_N_003
1
1
2
2
2 3 PR910 PR911 PR909
3 4 SYS_PRES 100_0402_5% 10K_0402_1% 100K_0402_1%
4 5 BATT_PRS 1 2 1 2 PR912
5 6 DAT_SMB +3VALW @ 0_0402_5%~D D
1
6 7 CLK_SMB 1 2 2
VSB_N_002 PQ903
7 8 43,45 POK
PR914 G 2N7002W -T/R7_SOT323-3
8 9 100_0402_5%
.1U_0402_16V7K
S
3
9
1
10 1 2
PC910
GND 11 EC_SMB_CK1 36,42
GND PR913
2
SUYIN_200028MR009G502ZL 100_0402_5%
1 2
EC_SMB_DA1 36,42
PBATT1 battery connector (Follow E3)
3
SMART 3
Battery:
01.GND1 ADP_I 36,42 PH900 under CPU bottom side :
02.GND2 CPU thermal protection at 98 degree C
03.BAT_ALERT
04.SYS_PRES
05.BATT_PRS
2
06.DAT_SMB PR918 @ +3VALW +3VLP
1.02K_0402_1%
2
07.CLK_SMB
08.BATT1+
Erp lot6 Circuit VIN PR915
1 1
2
107K_0402_1% ADP_I-1
D
09.BATT2+ PR927 PR916 @
@ PQ904 2 10.2K_0402_1% 10.2K_0402_1%
3.3K_1206_5%~D
1
2N7002W -T/R7_SOT323-3 G 45W /65W # 36
1
1
PR931
PR929
ACIN 36,42 36 VCIN0_PH
2
1M_0402_1%
62
36 VCIN1_PH
1
<=45W:High
2
PQ905A PR917 PC915 @ >=65W:Low
1
1
2 DMN66D0LDW -7_SOT363-6~D
PR928 332K_0402_1% .1U_0402_16V7K PH900
1
2
3
100K_0402_1%_TSM0B104F4251RZ
1
200K_0402_1%
PQ905B PR930
2
4
5 DMN66D0LDW -7_SOT363-6~D 4
1M_0402_1% ECAGND_EC 36
1
1
PC916
4
0.1U_0402_25V6
2
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/03/14 Deciphered Date 2013/03/12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-DCIN / BATT CONN / OTP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-9103P
Date: W ednesday, July 10, 2013 Sheet 41 of 52
A B C D
A B C D
VIN
PQ101 Iada=0~4.62A(90W)/Iada=0~3.34A(65W)
PQ100 SI4483ADY_SO8 P3
AO4407AL_SO8 P2
8 1 1 8 ADP_I = Iadapter*Rsense*Current sense amplifier vlotage gain 3S2P:CV=13.3V CC=2.1A
7 2 2 7
6 3 3 6
5 5 4S1P: CV=17.7V CC=1A
PR102 B+ PQ102
0.01_1206_1% AO4407AL_SO8
4
1 8
1 4 2 7
1
3 6
0.1U_0603_25V7K
3
1
PQ103 2 3 CSIN 5
200K_0402_1%
PC101
PR101
PDTA144EU PNP_SOT323
5600P_0402_25V7K
1
1 1
CSIP
4
2
2
PC102
200K_0402_1%
2
CHG_B+
PR103
PL101
1UH_NRS4018T1R0NDGJ_3.2A_30%
1
1 2
2
2200P_0402_25V7K
0.1U_0603_25V7K
1
PQ104
4.7U_0805_25V6-K
4.7U_0805_25V6-K
DDTC115EUA-7-F_SOT323
PC103
PC104
10_0402_5%
10_0402_5%
1
V1 2 VIN
1
1
PR106
PR107
PC105
PC106
PR105
0.1U_0603_25V7K
2
150K_0402_1%
DMN66D0LDW-7 2N SOT363-6
PR108
0.1U_0603_25V7K
3
3
200K_0402_1%
2
2
1 2
VIN
2
PQ106B
PR109
DMN66D0LDW-7 2N SOT363-6
2
5
PC107
PC108
BATT_TEMP 10_1206_1%
6
2
1 2 PC112
0.1U_0402_10V7K
1
1
2
ISL88731_ICREF
PC109
PQ105A
PQ105B 0.047U_0603_25V7M PC110
1
1
5 DMN66D0LDW -7 2N SOT363-6 @ 1 2 1U_0603_10V6K PR110
1
2 PC111 47K_0402_1%
2
1 VDDP_LDO
@ 1U_0603_25V6K PR111
4
2
4.7_0603_5%
1
1 1
VIN 2 1
232K_0402_1%
PC113 PC135
DDTC115EUA-7-F_SOT323
2
0.01U_0402_50V7K @ PR114 0_0603_5% 0.1U_0603_25V7K
100K_0402_1%
28
27
PR115
PQ107
1 2
PR113
PU100 1 2 BST_CHGA 1 2
PR112
2 1 2 V1
ICREF
CSSP
CSSN
2
DCIN 22 26 2
PR116 DCIN ICOUT
1
1 2 ACSETIN 2 100K_0402_1%
2
ACIN
5
6
7
8
PR118 25 BST 1 2
3
BOOT
PQ108
200K_0402_5% ACIN 49.9K_0402_1% 13
MDS1528URH_SO8
ACIN 1 236,41 ACIN +5VALW ACOK PC115
1
11 1U_0603_10V6K
158K_0402_1%
VDDSMB
PR117
0.1U_0402_10V7K
DDTC115EUA-7-F_SOT323
@ PR119 0_0402_5%~D 10 4
36,41 EC_SMB_CK1 SCL
1
1
PC116
1 2
9 21 VDDP_LDO
2
SDA VDDP PR121
ACOFF 36
2
PR131 @ PR120 0_0402_5%~D 14
3
2
1
36,41 EC_SMB_DA1 NC
PQ109
1 2 2 1 2 24 DH_CHG PL100 0.01_1206_1%
UGATE
8
VICM
10UH_PCMB063T-100MS_4A_20% BATT+
23 LX_CHG 1 2 CHG
1 4
10K_0402_5% 6 PHASE
4.7_1206_5%
FBO 2 3
DMN66D0LDW-7 2N SOT363-6
1
5
EAI
6
5
6
7
8
PR124
PQ110
4 20
PQ112A
DL_CHG
2ISL88731_VREF
4.7K_0402_5%
MDS1528URH_SO8
EAO LGATE
10U_0805_25V5K~D
10U_0805_25V5K~D
10U_0805_25V5K~D
10U_0805_25V5K~D
2
10_0402_5%
@
1 2
1
PR126
PC122
PC118
PC119
PC120
PR125 SNB_CHG
100_0402_1% ISL88731_VREF 3 19 4
680P_0402_50V7K
41 BATT_TEMP
1
VREF PGND 18
PC121
PR127
2
CSOP @
221K_0402_1%
1
2
7 17
2
CE CSON
PR134
3
2
1
15 VFB 1 PR130 2
63.4K_0402_1% 287K_0402_1%
VFB BATT+
2
12
2200P_0402_25V7K
36,41 ADP_I GND
PR136
16 100_0402_5%
0.1U_0402_10V7K
1
NC
1
3 3
PC134
29 PC126
TP 1 2
12,49,7 APU_PROCHOT#
1
PC128
2
ISL88731_ICREF ISL88732HRTZ-T_TQFN28_5X5~D 0.22U_0603_25V7K
1
@ PC130
2
2
@ PC127 @ 1 2
28.7K_0402_1%
2
PR137
1U_0603_25V6K
0.01U_0402_25V7K
2
PR135
PC131 0.1U_0603_25V7K
1
PC132
.1U_0402_16V7K
1
1
2
1
1
D
BATT_TEMP 2 PQ111 @
G SSM3K7002FU_SC70-3
S
3
For DT Mode
VIN
3.3K_1206_5%~D
1
PR122
V1
DMN66D0LDW-7 2N SOT363-6
3 2
4 4
DMN66D0LDW-7 2N SOT363-6
6
PQ112B
PQ106A
ACOFF 5
BATT_TEMP 2
4
@
Security Classification Compal Secret Data Compal Electronics, Inc.
1
Issued Date 2012/03/14 Deciphered Date 2013/03/12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-Charger
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-9103P
Date: W ednesday, July 10, 2013 Sheet 42 of 52
A B C D
A B C D E
1 1
0.1U_0402_25V6
0.1U_0402_25V6
@ PC202 @ PC200
2
100P_0402_50V8J 100P_0402_50V8J
PC221
PC220
1 2 1 2
+3VLP
1
PR201 PR202
13K_0402_1% 30.1K_0402_1%
1 2 2 1
0_0603_5%
PR203 @ PR204
1U_0603_10V5K
2
20K_0402_1% 20K_0402_1%
1
PR212
PC206
1 2 2 1
2
B+ B++
1
B++
2
82.5K_0402_1%
84.5K_0402_1%
2
PL202
PR205
PR206
1UH_NRS4018T1R0NDGJ_3.2A_30%
1 2
FB_3V FB_5V
1
1
4.7U_0805_25V6-K
2
PC227
2200P_0402_50V7K
0.1U_0402_25V6
0.1U_0603_25V7K
4.7U_0805_25V6-K
1
1
VARIST_ CK0402101V05 0402 PC207
1
PC203
PC204
PC205
PC209
1 2
1
PU200
CS2
VFB2
VREG3
VFB1
CS1
2
2
2
0.1U_0402_25V6 21
@ PC208 3V_EN 6 PAD
EN2
5
14
POK 41,45
1
VO1
5
PQ202
MDV1528URH_PDFN33-8-5 7 PQ203
PGOOD 19 MDV1528URH_PDFN33-8-5
TPS51225CRUKR_QFN20_3X3 VCLK
2
4 UG_3V 10 2
PC210 PR207 DRVH2 16 UG_5V 4
0.1U_0603_25V7K~D @ 0_0603_5% DRVH1 PR208 PC211
1 2 1 2 BST_3V 9 @ 0_0603_5% 0.1U_0603_25V7K~D
VBST2 17 BST_5V 1 2 1 2
1
2
3
PL200 VBST1 PL201
3
2
1
3.3UH_PCMB063T-3R3MS_6.5A_20% SW2 8 3.3UH_PCMB063T-3R3MS_6.5A_20%
1 2 SW2 18 SW1 1 2
+5VALWP
VREG5
+3VALWP
DRVL2
DRVL1
SW1
EN1
1
1
VIN
4.7_1206_5%
4.7_1206_5%
PR209
PR210
PQ204 PQ205
1 MDV1525URH_PDFN33-8-5 MDV1525URH_PDFN33-8-5
11
12
13
20
15
0.1U_0603_25V7K
0.1U_0603_25V7K
0.1U_0603_25V7K
0.1U_0603_25V7K
1
1
1
+ PC212 @ @ PC213
2
2
+
PC222
PC223
PC224
PC225
330U_6.3V_M 4 LG_3V LG_5V 4
330U_6.3V_M
2
2
1 SNUB_3V
SNUB_5V
2
3.3VALWP 5V_EN 2
680P_0402_50V7K
TDC 5.4A
1
2
3
3
2
1
PC217 VARIST_ CK0402101V05 0402
Peak Current 7.7A
PC214
1 2
680P_0402_50V7K
1U_0603_10V5K
0.1U_0603_25V7K
OCP current 9.2A
1
PC215
1
1
PC218
PC216
@
TYP MAX
2
2
H/S Rds(on) :23.2mohm , 27.8mohm @
2
L/S Rds(on) :11.5mohm , 14mohm PC226
0.1U_0603_25V7K
5VALWP
1 2 B++ TDC 5.6A
+5VALWP +3VALWP
Peak Current 8A
OCP current 9.6A
PR216 TYP MAX
3
3V_EN
@ 0_0402_5%~D
1 2
H/S Rds(on) :23.2mohm , 27.8mohm 3
@ PD200 PR217
L/S Rds(on) :11.5mohm , 14mohm
RB751V-40_SOD323-2 @ 0_0402_5%~D
VCOUT0_PH 1 2 5V_EN 1 2
PJP202 @ PJP203 @
1 2 1 2 +3VALW
+5VALWP +5VALW +3VALWP
PAD-OPEN 4x4m PAD-OPEN 4x4m
PJP204 @ PJP200 @
PR213 1 2 1 2
2.2K_0402_5%
1 2
36 EC_ON PAD-OPEN 4x4m PAD-OPEN 4x4m
VCOUT0_PH 1 2 N_3_5V_002
36 VCOUT0_PH
@ PR215
0_0402_5%~D
4.7U_0603_10V6K
1
PC219
2
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/03/14 Deciphered Date 2013/03/12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR_3.3VALWP/5VALWP
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9103P
Date: Wednesday, July 10, 2013 Sheet 43 of 52
A B C D E
5 4 3 2 1
PJP301
VLDOIN_1.5V 2 1 +1.5VP
PR301
B+ @ PJP302 @ 0_0603_5% PAD-OPEN1x1m
2 1 1.5V_B+ BOOT_1.5V-1 1 2 BOOT_1.5V
2 1
JUMP_43X118
DH_1.5V
2200P_0402_50V7K
0.1U_0402_25V6
4.7U_0805_25V6-K
4.7U_0805_25V6-K
+0.75VSP
2
@
10U_0805_6.3V6M
10U_0805_6.3V6M
1
1
PC304 SW_1.5V
PC301
PC302
PC305
PC303
0.22U_0603_10V7K
1
D D
1
PC306
PC307
DL_1.5V
16
17
18
19
20
PQ300
PU300 @
MDV1528URH_PDFN33-8-5
PJP300
VLDOIN
BOOT
VTT
PHASE
UGATE
+0.75VS
2
PAD
21 +0.75VSP 1 2
4 15 1
LGATE VTTGND PAD-OPEN 3x3m
PR302 14 2
PL300 13K_0402_1% PGND VTTSNS
1
2
3
1UH_PCMB063T-1R0MS_12A_20% 1 2 CS_1.5V
1 2 13 3
0.75Volt +/- 5%
+1.5VP CS RT8207MZQW_WQFN20_3X3 GND
TDC 0.7A
5
4.7_1206_5%
Peak Current 1A
PQ301
PR304 1 2 PC309 12 4 VTTREF_1.5V
MDV1523URH 1N PDFN33-8
1U_0603_10V6K VDDP VTTREF
PR303
1 5.1_0603_5%
OCP Current 1.2A
+ PC308 +5VALW 1 2 VDD_1.5V 11 5
+1.5VP PC310
SNUB_1.5V 2
4 VDD VDDQ
PGOOD
330U_2.5V_M 0.033U_0402_16V7
TON
2 PC311
FB
S5
S3
1U_0603_10V6K
2
PC314 220P_0402_50V8J
1
2
3
10
6
1
PC316 1 2
+5VALW
680P_0402_50V7K
1000P_0402_50V7K
TON_1.5V
2
PC312
PR305
10.5K_0402_1%
2
1.5V_FB 2 1
@ PJP303
2 1 PR300
2 1 1M_0402_1%
+1.5VP +1.5V
2
JUMP_43X118 PR306 1.5V_B+ 1 2
1
@ 0_0402_5%~D PR307
@ PJP304 1 2 S5_1.5V 10K_0402_1% PC313
2 1 36,39 SYSON @.1U_0402_16V7K
0.1U_0603_25V7K
2
2 1
1
1
C PC300 @ PR308 C
1
PC317
JUMP_43X118 @ 0_0402_5%~D
1U_0402_6.3VX5R 1 2 S3_1.5V
2
0.1U_0402_10V7K
36,39,46 SUSP#
PC315
1
@
2
+1.5VP
1.5VP
TDC 11A
Peak Current 16A
OCP current 19A @ PJP1100
TYP MAX +V1.05SP_B+ 2 1
H/S Rds(on) :23.2mohm , 27.8mohm
2 1 B+
JUMP_43X118
L/S Rds(on) :7mohm , 8.4mohm
2200P_0402_50V7K
0.1U_0402_25V6
4.7U_0805_25V6-K
4.7U_0805_25V6-K
1
1
PC1100
@ PC1101
@ PC1102
@ PC1105
5
@ PQ1100
MDV1528URH_PDFN33-8-5
2
@
PR1100 @ PC1108 @
3
2
1
PU1100 @ 0_0603_5% 0.22U_0603_10V7K
B
1 10 BST_+1.5VGPU 1 2 BST_+1.5VGPU-1 2 1 B
@ PR1104 PGOOD VBST
1 2 TRIP_+1.5VGPU 2 9 UG_+1.5VGPU @ PL1100
TRIP DRVH 1UH_PCMB053T-1R0MS_7A_20%
80.6K_0402_1%
EN_+1.5VGPU 3
EN SW
8 SW_+1.5VGPU 1 2 +1.5VGPUP
@ PR1101
5
100K_0402_5% FB_+1.5VGPU 4 7 +1.5VGPU_5V
VFB V5IN +5VALW
1
@ PQ1101
1 2
4.7_1206_5%
MDV1525URH_PDFN33-8-5
23,36,47,48 PX_MODE 5 6
PR1102
RF_+1.5VGPU LG_+1.5VGPU 1
RF DRVL
2
11 + PC1103 @
TP
1
@ PR1107 PC1107 @ 4 330U_2.5V_M
2
1
1M_0402_5% @ PC1104 RT8237EZQW(2)_WDFN10_3X3 1U_0603_10V6K @
2
0.1U_0402_16V7K 2
2
@ PR1106 SNB_1.5VGPUP
1
470K_0402_1%
3
2
1
680P_0402_50V7K
2
PC1106
2
@
@ PR1105
11.5K_0402_1%
2 1
+1.5VGPU
2
PR1103 @
TDC 5.6A
10K_0402_1% Peak Current 8A
A
OCP current 9.6A A
1
PJP1102 @
+1.5VGPUP 2
2 1
1 +1.5VGPU
JUMP_43X118
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/03/14 Deciphered Date 2013/03/12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR_+1.5VP/+1.5VGPUP/0.75VSP
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9103P
Date: Wednesday, July 10, 2013 Sheet 44 of 52
5 4 3 2 1
A B C D
<Vo=1.8V> VFB=0.6V
Vo=VFB*(1+PR401/PR400)=0.6*(1+20K/10K)=1.8V
PU400 VGA@ PL400
4
PJP400 @ 1UH_NRS4018T1R0NDGJ_3.2A_30%
+3VALW 1 2 1.8VSP_VIN 10 2 1.8VSP_LX 1 2
PG
PVIN LX
+1.8VSP
9 3
22P_0402_50V8J
PVIN LX
1
PAD-OPEN 3x3m
4.7_0603_5%
+1.8VSP
1
1 1
8
VGA@ PC402
PC403
SVIN
TDC 1.4A
@ PR404
22U_0805_6.3VAM VGA@ PR403
VGA@ 6 1.8VSP_FB 20K_0402_1%
2
FB
5 Peak Current 2A
22U_0805_6.3VAM
22U_0805_6.3VAM
1SNUB_1.8VSP 2
2
EN
1
NC
NC
TP
OCP current 2.4A
VGA@ PC400
VGA@ PC404
11
2
1 2 EN_1.8VSP
14,23,47 PXS_PWREN
1
1
PR402 4.7K_0402_1%
1U_0402_16V6K
VGA@ PC405
VGA@ G5673RE1U_TDFN10_3X3 VGA@ PR400
1
PR401 VGA@ 10K_0402_1%
680P_0603_50V7K
@ PC401
47K_0402_5%
2
VGA@
2
PJP401 @
1 2
+1.8VSP +1.8VGS
PAD-OPEN 3x3m
2 2
SY8036LDBC_DFN10_3X3 PL401
PJP404 +1.1VALWP
4
+3VALW PU401 0.47UH_PCMB063T-R47MS_18A_20%
2 1 1.1V_PVIN 10 2 LX_1.1V 1 2
PG
2 1 PVIN LX
9 3
JUMP_43X79 PVIN LX
4.7_0603_5%
1
@ PC413 8
SVIN
PR409
47U_0805_6.3V6M PJP403
6 FB_1.1V 2 1
+1.1VALW P +1.1VALW
2
5 FB 2 1
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
2
EN
1
@ @ JUMP_43X118
SS
TP
LX
PC410
PC407
PC409
PC414
PR405
@ 0_0402_5%~D
11.1V_SS
11
2
1 2EN_1.1V
3
41,43 POK 3
SNUB_1.1V
1
PC408
0.1U_0402_10V7K
0.1U_0402_10V7K
PC406
200K_0402_5%
PR408
1
PR406
2 1
2
2
@ @
8.45K_0402_1%
1
680P_0603_50V7K
PC412
PC411
2
1
2 1
@
PR407
10K_0402_1% 22P_0402_50V8J
2
1.1V
TDC 3.5A
Peak Current 5A
OCP current 6A
TYP MAX
H/S Rds(on) :27mohm , 34mohm
L/S Rds(on) :11mohm , 14mohm
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/03/14 Deciphered Date 2013/03/12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-1.8VSP/1.1VALWP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-9103P
Date: W ednesday, July 10, 2013 Sheet 45 of 52
A B C D
5 4 3 2 1
@ PJ500
+1.2VSP_B+ 2 1
2 1 B+
JUMP_43X118
2200P_0402_50V7K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
0.1U_0402_25V6
D D
1
PC506
PC508
PC504
PC503
2
2
5
@
PQ500
MDV1528URH_PDFN33-8-5
4
PR500 PC500
PU500 @ 0_0603_5% .1U_0603_25V7K
1 10 BST_+1.2VSP 1 2 BST_+1.2VSP-1 2 1
3
2
1
PGOOD VBST
PR502
1 2 TRIP_+1.2VSP 2 9 UG_+1.2VSP PL500
TRIP DRVH 1UH_PCMB063T-1R0MS_12A_20%
SUSP# 36,39,44 80.6K_0402_1%
PR505 EN_+1.2VSP 3 8 SW _+1.2VSP 1 2
60.4K_0402_1% EN SW +1.2VSP
1 2 FB_+1.2VSP 4 7 +1.2VSP_5V
VFB V5IN
+5VALW
2
RF_+1.2VSP 5 6 LG_+1.2VSP
47K_0402_1%
0.1U_0402_16V7K
0.1U_0603_25V7K
RF DRVL
1
1
@
PR508
1
11
PQ501
PC507
220U_6.3V_M
TP
1
MDV1525URH_PDFN33-8-5
PC501 PR504 +
PC502
2
RT8237EZQW (2)_W DFN10_3X3 1U_0603_10V6K 4.7_1206_5%
PC505
1
2
@ PR503 4 SNB_1.2V 2
470K_0402_1% @
1
C PC509 C
2
1000P_0603_50V7K
3
2
1
2
PJ501 +1.2VS
PR501 +1.2VSP 2 1
2 1
7.15K_0402_1% @ JUMP_43X118
2 1
1.2V
2
PR506 TDC 6A
10K_0402_1%
Peak Current 8.5A
OCP current 10A
1
B B
TYP MAX
H/S Rds(on) :23.2mohm , 27.8mohm
L/S Rds(on) :11.5mohm , 14mohm
PU501
APL5508-25DC-TRL_SOT89-3
PJ502
+3VS PJ503
1 2 2.5V_VIN 2 3 +2.5VSP
1 2 IN OUT +2.5VSP 2 1 +2.5VS
@ JUMP_43X39 2 1
1
GND @ JUMP_43X39
4.7U_0805_6.3V6K
1
PR509
PC511
1 (0.5A,20mils ,Via NO.=1)
PC510 10K_1206_5%
1U_0603_10V6K
2
@
2
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/03/14 Deciphered Date 2013/03/12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-1.2VSP/2.5VSP
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9103P
Date: W ednesday, July 10, 2013 Sheet 46 of 52
5 4 3 2 1
5 4 3 2 1
VGA@ PR822
+5VALW
2 1 62881_VDD VGA_CORE_B+
1
1_0603_5%
0_0603_5%
@ @ PJP800
2
PC811 VGA@ VGA_CORE_B+ 2 1
B+
2
2 1
PR823
1U_0603_10V6K
JUMP_43X118
0.22U_0603_25V7K
PC847 VGA@
PC848 VGA@
PC816 VGA@
1 1
2200P_0402_50V7K
0.1U_0402_25V6
4.7U_0805_25V6-K
4.7U_0805_25V6-K
PC846 @
VGA@ PC810
1
2
FDMS7698_POWERDFN56-8-5
2
5
VGA@ PQ800
D D
PR833 @
2 1
+5VALW PR802 4
10_0402_5% 0_0402_5%~D PC812 VGA@ @ 0_0603_5%
12 62881_VIN
ISUM+
PR845 @ 1 2 BST_VGA_CORE 1 2 1 2
ISUM-
2 1
1
25 VSSSENSE_VGA 1000P_0402_50V7K PC805 VGA@
3
2
1
2 1 PC807 @ 0.1U_0603_25V7K VGA@ PL800
25 VCCSENSE_VGA 1 2 330P_0402_50V7K 0.36UH_PDME064T-R36MS_24A_20%
29
10
11
13
14
2
9
PR846 @
PR820 @ 0_0402_5%~D PC813 @ 1 4
AGND
RTN
ISUM+
VDD
VIN
IMON
BOOT
ISUM
+VGA_CORE
+VGA_CORE
2 1 330P_0402_50V7K
2 3
10_0402_5%
PC843 VGA@
PC849 VGA@
PC817 VGA@
PC850 VGA@
PC815 VGA@
7 15 UG_VGA_CORE
1000P_0603_50V7K 4.7_1206_5%
470U_D2_2VM_R4.5M
470U_D2_2VM_R4.5M
VSEN UGATE 1 1
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
VGA@ PQ802
VGA@ PQ801
+ +
PR821
62881_FB 6 PU800 VGA@ 16 SW_VGA_CORE
MDU1511RH_POWERDFN56-8-5
MDU1511RH_POWERDFN56-8-5
FB PHASE
1
PR829 VGA@
ISL62881CHRTZ-T_QFN28_4X4
0_0402_5%~D
3.65K_0402_1%
62881_COMP 5 17 @
COMP VSSP
1
@ 2 2
2
PR830
62881_VW 4 18 LG_VGA_CORE 4 4
VW LGATE @ PR814 0_0603_5%
1
PC841
3
62881_RBIAS 19 62881_VCCP 1 2 +5VALW
PR813 VGA@ PR819 VGA@ PC818 VGA@ RBIAS VCCP PH800
2
1
2.32K_0402_1% 226K_0402_1% 1000P_0402_50V7K 2 20 1 2ISUM-2
1 2
3
2
1
3
2
1
2
2 1 1 2GFX_FB-1
1 2 2 1 PGOOD VID0 @ PR809 VGA@
1
1 21
47K_0402_1%
PC801 VGA@ 2.61K_0402_1% 10K_0402_5%_ERTJ0ER103J
DPRSLPVR
2
VGA@ PC806 VGA@ PR812 CLK_EN# VID1 2.2U_0603_6.3V6K VGA@
390P_0402_50V7K
VR_ON
VID6
VID5
VID4
VID3
VID2
VGA@ PC814 1 2
2
62881_VID0
56P_0402_50V8 PR827 VGA@
2 1GFX_FB-2
2 1 1 2 2 1 11K_0402_1%
+VGA_CORE
62881_VID1
28
27
26
25
24
23
22
VGA@ PC808 PR818 VGA@ PR817 VGA@
TDC 22A
1000P_0402_50V7K 715_0402_1% 8.06K_0402_1% 1 2 Peak Current 30A
62881_VR_ON
PR842 VGA@
PC800 VGA@
C
OCP current 36A C
2
62881_VID6
62881_VID5
62881_VID4
62881_VID3
62881_VID2
.1U_0402_16V7K
ISUM-1
1
1K_0402_1%
PC809
.1U_0402_16V7K
FSW=350kHz
1
+3VS 1 2
VGA@ DCR 1.4mohm +/-5%
PC804 VGA@ Loadline = 1.5mohm
2
2
0.068U_0402_16V7K~N
1.1K_0402_1%
PR801 VGA@
VGA@ PR825
10K_0402_1%
PR828 @
100_0402_1%
1
2 PR811 @10_0402_5%~D PR824 @
2ISUM-4
2 PR810 @10_0402_5%~D 82.5_0402_1%
1
2 PR808 @10_0402_5%~D GPU_VID1 22 1 2ISUM-3
1 2
2 PR807 @10_0402_5%~D GPU_VID2 22
+3VS 2 PR806 @10_0402_5%~D GPU_VID3 22 ISUM+ @ PC802
2
2 PR805 @10_0402_5%~D GPU_VID4 22 0.01U_0402_25V7K PC803 @
2 PR804 @10_0402_5%~D GPU_VID5 22
180P_0402_50V8J
1
14 VGA_PWRGD
@ PR803 0_0402_5%~D
1 2 ISUM-
0.1U_0402_10V7K PX_MODE 23,36,44,48
VGA@ PC844
1
2
Mars Pro
GPU_VID5 GPU_VID4 GPU_VID3 GPU_VID2 GPU_VID1 +3VGS
(GPIO_10) (GPIO_14) (GPIO_15) (GPIO_16) (GPIO_20) Core Voltage Level
PR815 @
1 2 GPU_VID1
0 1 1 1 1 1.125V
10K_0402_1%
PR816 VGA@
1 0 0 0 0 1.1V 1 2
+VGA_PCIE
B
10K_0402_1%
TDC 3.6A B
1 0 0 0 1 1.075V PR826 @ Peak Current 5.2A
1 2 GPU_VID2
OCP current 6A
1 0 0 1 0 1.05V 10K_0402_1% VGA@
PR834 VGA@ @ VGA@ PL803
PJP807 +VGA_PCIEP
4
1 2 PU801 0.47UH_PCMB063T-R47MS_18A_20%
+3VALW
1 0 0 1 1 1.025V 2 1 PCIE_B+ 10 2 LX_PCIE 1 2
PG
10K_0402_1% 2 1 PVIN LX
PR835 @ 9 3
JUMP_43X79 PVIN LX
1
1 0 1 0 0 1V 1 2 GPU_VID3 VGA@
4.7_0603_5%
1
PC833 8
SVIN
@ PR841
10K_0402_1% 47U_0805_6.3V6M
1 0 1 0 1 0.975V PR836 VGA@ 6 FB_PCIE
2
1 2 5 FB
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
2
EN
1
SS
TP
LX
VGA@ PC835
VGA@ PC852
VGA@ PC837
VGA@ PC851
1 0 1 1 0 0.95V 10K_0402_1%
14,23,45 PXS_PWREN
SY8036LDBC_DFN10_3x3
PR843 VGA@
11
2
PR837 VGA@ 1 2EN_PCIE
SNUB_PCIE
PC832
1 0 1 1 1 0.925V 1 2 GPU_VID4 @
0.1U_0402_10V7K
1
1
4.7K_0402_5% PR832 VGA@
0.1U_0402_10V7K
PC842
10K_0402_1%
1
1 1 0 0 0 0.9V PR838 @ VGA@ PR844 5.9K_0402_1%
VGA@
1 2 47K_0402_5% 2 1
2
1 1 0 0 1 0.875V 10K_0402_1%
680P_0402_50V7K
PR839 VGA@
@ PC834
1 2 GPU_VID5
PC840
1 1 0 1 0 0.85V VGA@
2
1
10K_0402_1% 2 1
PR840 @
1 1 0 1 1 0.825V 1 2 VGA@ PR831
+VGA_PCIEP
10K_0402_1% 22P_0402_50V8J
10K_0402_1% Thames Mars Pro
2
1 1 1 0 0 0.8V
A PJP806
@ VGA_PCIE 1.0V 0.95V A
1 1 1 0 1 0.775V
2 1
+VGA_PCIEP 2 1 +1.0VGS PR832 6.81K 5.9K
JUMP_43X79
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/03/14 Deciphered Date 2013/03/12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR_VGA_CORE/VGA_PCIE
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9103P
Date: Wednesday, July 10, 2013 Sheet 47 of 52
5 4 3 2 1
5 4 3 2 1
D D
+VDDCI
TDC 1.5A
Peak Current 2.2A
@ OCP current 4A
PU1000 PL1000 @
PJP1002
4
@ G5673RE1U_TDFN10_3X3 1UH_NRS4018T1R0NDGJ_3.2A_30%
1 2 VDDCIP_IN 10 2 LX_VDDCIP 1 2
+3VALW
PG
1 2 PVIN LX +VDDCIP
JUMP_43X79 9 3
22P_0402_50V8J
PVIN LX
2
4.7_0603_5%
22U_0805_6.3V6M
1
1
PR1012 @
8
@ PC1007
PC1009 @ PR1011 @
22U_0805_6.3V6M
SVIN
1
22U_0805_6.3V6M 10_0402_5%
6
@ PC1010
@ PC1012
FB_VDDCIP
2
2
5 FB
1SNB_VDDCIP
EN_VDDCIP
2
EN
NC
NC
TP
C
1 2 C
FB=0.6Volt
11
VDDCI_SEN-1
1 2 @ PR1013
23,36,44,47 PX_MODE
680P_0402_50V7K
PR1020 @ 4.99K_0402_1%
0.1U_0402_10V7K
2
PC1008
@ PC1011
100K_0402_5% PR1014@
1
@ PR1021 0_0402_5%
2
1M_0402_5% 2 1 VDDCI_SEN 25
2
@
1
+3VGS
1
PR1015 @
1
29.4K_0402_1% PR1016 @
10K_0402_5%
2
@ PR1018
10K_0402_1% PR1017 @
2
1
D 10K_0402_5%
2
2 2 1
G
1
S
1
PQ1006 @
2N7002W-T/R7_SOT323-3 @ PC1013 PR1019 @
4700P_0402_25V7K 100K_0402_5%
2
VDDCI_VID0
B 0 0.9V B
+3VGS
1
1 1V
1
PR1024 @
29.4K_0402_1% PR1023 @
10K_0402_5%
2
PR1022 @
2
1
D 10K_0402_5%
2 2 1
G
1
S
3
1
PQ1007 @
2N7002W-T/R7_SOT323-3 @ PC1014 PR1025 @
4700P_0402_25V7K 100K_0402_5%
2
PJP1003
@
+VDDCIP 1
1 2
2 +VDDCI
JUMP_43X79
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/03/14 Deciphered Date 2013/03/12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR_+VDDCIP
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9103P
Date: Wednesday, July 10, 2013 Sheet 48 of 52
5 4 3 2 1
A B C D E
7 APU_VDD_SEN_L APU_VDD_SEN_H 7
0_0402_5%~D
1
0.01U_0402_50V7K @ PR790
PC728 1 2 ISEN2N
10_0402_5% 10_0402_5%
FDMS7698_POWERDFN56-8-5
2
1 2 1 2 0_0402_5%~D @ PJP701
+APU_CORE
@ PR754 APU_NB_B+ 2 1
2 1 B+
680P_0402_50V7K
PR748 PR749
0.1U_0603_25V7K
1 2 ISEN2P
+5VS
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
0_0402_5%~D
0_0402_5%~D
PR747
PR733
JUMP_43X118
PQ704
PC725
0_0402_5%~D
1
@ PR723
1
PC741
PC739
PC740
PC703
@ @ 1 2 ISEN3P
2
1
1
@
2
1 0_0402_5%~D UGATE_NB1 4 1
2
1
2K_0402_1%
1 2 @ PR757 @
PR745
1 2 ISENA2P
PC727 @ PR713 PL703
330P_0402_50V @ 0_0603_5% PC743 0.36UH_PDME064T-R36MS_24A_20%
3
2
1
PR769 @ 0_0402_5%~D PR766 BOOT_NB11 2BOOT_NB1-1
1 2 4 1
+APU_CORE_NB
2
10K_0402_1% @ PR744 100K_0402_1%
4.7_1206_5%
1 2 1 2 1 2 PR761 0.22U_0603_25V7K 3 2
CPU_B+
1
PR714
1 2 PR705
PQ705
PHASE_NB1 2.61K_0402_1%
MDU1511RH_POWERDFN56-8-5
PC726 PC723 178K_0402_1% 1 2 2 1
470P_0402_50V8J 68P_0402_50V8J
1 2 1 2 @ PR762 PC746
2
1 2 B+_BIAS LGATE_NB1 4 .1U_0402_16V7K
SNB_APU_NB
680P_0603_50V7K
PC742
178K_0402_1%
PR711 @
0_0402_5%
3
2
1
2
1 2
TONSET
COMP
ISEN3P
ISEN2P
VSEN
ISEN1N
ISEN2N
ISEN1P
FB
+5VS
ISENA1N-1
ISENA1P
PR755
PU700 910_0402_1%
13
12
11
10
1
RT8880AGQW_QFN52_6X6 ISENA1N 1 2
APU_CORE_NB
PWM3
BOOT2
UGATE2
TONSET
COMP
FB
ISEN3P
ISEN1P
ISEN2P
VSEN
ISEN3N
ISEN1N
ISEN2N
0.1U_0402_25V6
1
TDC 22A
PC736
53
RGND
GND
14 52 PR724 Peak Current 33 A
2
2 RGND PHASE2 @ 0_0402_5%~D 2
IMON 15 51 PVCC 1 2
+5VALW
OCP current > 33A
IMON LGATE2
VREF 16 50 PVCC Load line -4mV/A
V064 PVCC
PC745 IMONA 17 49 LGATE1
VCC 1 2 FSW=300kHz
IMONA LGATE1
DCR 1.4mohm +/-5%
2.2U_0603_10V7K
2.2U_0603_10V7K
1U_0402_6.3V6K+1.5VS PR726
1
PC712
PC711
1 2 VDDIO 18 48 PHASE1 10_0603_5%
0_0402_5%~D @ PR739 VDDIO PHASE1 TYP MAX
1 2APU_PWROK 19 47 UGATE1
12,7 APU_PWRGD H/S Rds(on) :11.7mohm , 14mohm
2
0_0402_5%~D @ PR728 PWROK UGATE1
1 2 SVC 20 46 BOOT1
7 APU_SVC
0_0402_5%~D @ PR735 SVC BOOT1 L/S Rds(on) :2.7mohm , 3.3mohm
1 2 SVD 21 45 LGATE_NB1
7 APU_SVD SVD LGATEA1
0_0402_5%~D @ PR737 @ PJP700
1 2 SVT 22 44 PHASE_NB1 2 1
7 APU_SVT SVT PHASEA1 CPU_B+ 2 1 B+
29.4K_0402_1%
5.76K_0402_1%
FDMS7698_POWERDFN56-8-5
1
0.1U_0603_25V7K
OFS 23 43 UGATE_NB1 JUMP_43X118
OFS UGATEA1
PR770
PR740
PC704
OFSA 24 42 BOOT_NB1
OFSA BOOTA1
2
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
1 1
2
100U_25V_M
100U_25V_M
PQ700
0_0402_5%~D
SET1 25 41
PR725
+5VS
2
2
SET1 PWMA2
1
0_0402_5%~D
0_0402_5%~D
0_0402_5%~D
PC700
PC722
PC701
PC702
+ +
PR727
PR763 174K_0402_1% @
PGOODA
ISENA2N
ISENA1N
ISENA2P
ISENA1P
1
PC708
PC706
PC705
SET2 26 40 1 2 APU_NB_B+
PGOOD
@ @
COMPA
VSENA
OCP_L
SET2 TONSETA
2
IBIAS
@
VCC
2
FBA
1
2 2
PR771
PR722
UGATE1 4 @
EN
2
1
@ PR764 174K_0402_1%
PR742 PR741 1 2 B+_BIAS PHASE1
27
28
29
100K_0402_5% COMPA 30
31
32
33
34
35
36
37
38
39
4.64K_0402_1% 13.3K_0402_1% PR707 PL701
1
1
22.6K_0402_1%
2 1 2 1 0_0402_5%~D @ 0_0603_5% 0.36UH_PDME064T-R36MS_24A_20%
3
2
1
ISENA1N
100K_0402_1%_TSM0B104F4251RZ
100K_0402_1%_TSM0B104F4251RZ
ISENA2P
ISENA1P
13.3K_0402_1%
PR734 @ BOOT1 1 2BOOT1-1
1 2 4 1
2 IBIAS
+APU_CORE
VSENA
1
VCC
FBA
1 2VR_HOT
VGATE 14
PH704
PR772
PR721
PH702
4.7_1206_5%
3 PR758 PC707 3 2 3
5
12,42,7 APU_PROCHOT# 2 1 0.22U_0603_25V7K
+3VS
1
PQ708
PQ707
PR736
PR701
MDU1511RH_POWERDFN56-8-5
MDU1511RH_POWERDFN56-8-5
PR708
100K_0402_5% 2.61K_0402_1%
2
1 2 VREF 1 2 1 2 2 1
VR_ON 36 @
1
PR765 @ PR716 @ 1 2 LGATE1 4 4 PC747
1 2
0.1U_0402_25V6
0.1U_0402_25V6
0_0402_5%~D 0_0402_5%~D SNB_APU .1U_0402_16V7K
1
680P_0603_50V7K
PC724
PC718
PC713
@PR738
@ PR738
0_0402_5%~D
2
3
2
1
3
2
1
2
1
PC731 PC734
68P_0402_50V8J 470P_0402_50V8J PR700 PR710 @
2 1 2 1 10K_0402_5% 4.12K_0402_1%
1 2
2
PR778 0_0402_5%~D PR773
56K_0402_1% @ PR776 10K_0402_1% ISEN1P
ISEN1N-1
2 1 1 2 2 1
APU_core
OFS
@ PR746
@PR746 @ PR752 @ PR759
@PR759 @ PR780 PR709
2
6.2K_0402_5%
1 2
120_0402_1%
1 2
20K_0402_5%
1 2
0_0402_5%
1 2 PC733 @
TDC 22A(1H1L) 26.4A(1H2L) ISEN1N 1
1.3K_0402_1%
2
@ PR775 2 1 Peak Current 35A
0.1U_0402_25V6
@PR750
@ PR750 @ PR753 @PR760
@ PR760 @ PR781 2K_0402_1%
+5VS OCP current > 35A
1
PC730
6.2K_0402_5% 120_0402_1% 20K_0402_5% 0_0402_5% 330P_0402_50V
1
1 2 1 2 1 2 1 2
Load line -2.1mV/A
OFSA
2
2
FSW=300kHz @
0_0402_5%~D
0_0402_5%~D
PR774
PR791
@ PC735
680P_0402_50V7K DCR 1.4mohm +/-5%
1
4 PR756 @ @ TYP MAX 4
1
1
SET1
2 1
0_0402_5%~D PR784 PR786 PR788
+APU_CORE_NB H/S Rds(on) :11.7mohm , 14mohm
2
RGND
2
PR782 @
1
35.7K_0402_1% 1K_0402_1%
1 2 1 2
124K_0402_1%
1 2 PC732
10_0402_5% L/S Rds(on) :2.7mohm , 3.3mohm
0.01U_0402_50V7K
1
0_0402_5%~D PR785 PR787 PR789 +5VS
PR783 @ 470_0402_1% 1K_0402_1% 124K_0402_1%
2 1 1 2 1 2 1 2 Security Classification Compal Secret Data Compal Electronics, Inc.
7 APU_VDDNB_SEN_H Issued Date 2012/03/14 2013/03/12 Title
SET2
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR_+APU_CORE/APU_CORE_NB
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9103P
Date: Wednesday, July 10, 2013 Sheet 49 of 52
A B C D E
A
B
C
D
5
5
PC1211 PC1206 PC1201
22U_0603_6.3V6K 22U_0603_6.3V6K 22U_0603_6.3V6K
2 1 2 1 2 1
2
1
+
PC1214
330U_D2_2V_Y
2 1 2 1 1 2
PC1047 PC1243 PC1238
180P_0402_50V8J 0.01U_0402_25V7K 0.22U_0402_10V6K
+APU_CORE
+APU_CORE
+APU_CORE
+APU_CORE
+APU_CORE
PC1212 PC1207 PC1202
22U_0603_6.3V6K 22U_0603_6.3V6K 22U_0603_6.3V6K
2 1 2 1 2 1
+APU_CORE
2
1
+
PC1215
330U_D2_2V_Y 2 1 2 1 1 2
PC1048 PC1244 PC1239
180P_0402_50V8J 0.01U_0402_25V7K 0.22U_0402_10V6K
PC1213 PC1208 PC1203
22U_0603_6.3V6K 22U_0603_6.3V6K 22U_0603_6.3V6K
2 1 2 1 2 1
2
1
+
PC1216
4
4
330U_D2_2V_Y
PC1218 PC1209 PC1204
22U_0603_6.3V6K 22U_0603_6.3V6K 22U_0603_6.3V6K
2 1 2 1 2 1
PC1235 PC1210 PC1205
22U_0603_6.3V6K 22U_0603_6.3V6K 22U_0603_6.3V6K
2 1 2 1 2 1
Issued Date
Security Classification
3
3
2012/03/14
PC1233
22U_0603_6.3V6K PC1219
2 1 22U_0603_6.3V6K
2 1
2
1
+
PC1217 PC1220
330U_D2_2V_Y 22U_0603_6.3V6K
PC1227 2 1
10U_0603_6.3V6K
+1.2VS
+1.2VS
2 1 PC1221
2
1
+
22U_0603_6.3V6K
PC1228 PC1225 2 1
Compal Secret Data
Deciphered Date
10U_0603_6.3V6K 330U_D2_2V_Y
2 1 PC1222
+APU_CORE_NB
22U_0603_6.3V6K
PC1229 2 1
10U_0603_6.3V6K
2 1 PC1223
22U_0603_6.3V6K
+APU_CORE_NB
PC1230 2 1
10U_0603_6.3V6K
2
2
2 1 PC1224
22U_0603_6.3V6K
2013/03/12
PC1231 2 1
10U_0603_6.3V6K
2 1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PC1232
10U_0603_6.3V6K
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
2 1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Title
Date:
Document Number
LA-9103P
W ednesday, July 10, 2013
1
1
Sheet
50
Compal Electronics, Inc.
of
52
PWR_PROCESSOR DECOUPLING
Rev
0.1
A
B
C
D
5 4 3 2 1
Power block
CPU OTP
Page 41
D Turn Off D
Input B+
DC IN +3VALWP: TDC:5.4A
Switch Page 42 +5VALWP: TDC:5.6A Always
TPS51225CRUKR Page 43
CHARGER
CC:2.1A +1.8VSP: TDC:1.4A PXS_PWREN
CV:13.3V(6cell)/17.7V(4cell) G5673RE1U
Page 45
ISL88732HRTZ-T Page 42
C C
+1.1VALWP: TDC:3.5A POK
Battery SY8036LDBC Page 45
+1.5VP/+0.75VSP: TDC:11A/0.7A SYSON
RT8207MZQW
Page 44
+1.2VSP: TDC:6A SUSP#
RT8237EZQW
Page 46
+VGA_CORE
PX_MODE
TDC:22A
B ISL62881C B
Page 47 +2.5VSP: TDC:0.5A
APL5508
Page 46
+1.0VGS: TDC:3.6A PXS_PWREN
+APU_CORE
VR_ON
TDC: 22A SY8036LDBC Page 47
RT8880AGQW
Page 49
+APU_CORE_NB
VR_ON
A TDC: 22A A
RT8880AGQW
Page 49
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/03/14 Deciphered Date 2013/03/12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR_POWER BLOCK DIAGRAM
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9103P
Date: Wednesday, July 10, 2013 Sheet 51 of 52
5 4 3 2 1
5 4 3 2 1
Version Change List ( P. I. R. List ) Page 1
Request
Item Page# Title Date Owner Issue Description Solution Description Rev.
1 42 Charger 2013/07/08 Compal EMI power noise. Pop PC106 0.1uF for EMI requesst. X01
D Pop PR303 4.7ohm and PC312 680pF for EMI requesst. D
2 44 +1.5VP 2013/07/08 Compal EMI power noise/ESD issue. Add PC317 0.1uF for ESD request. X01
Add PR703 0.1uF and PC704 0.1uF for EMI requesst.
3 49 +APU_CORE/APU_CORE_NB 2013/07/08 Compal EMI power noise/ESD issue. Pop PC736 0.1uF for ESD request. X01
4 46 +1.2VSP 2013/07/08 Compal ESD issue. Add PC505 0.1uF for ESD requesst. X01
5 47 3.3VALWP/5VALWP 2013/07/08 Compal ESD issue. Add PC222,PC223,PC224,PC225,PC226,PC227 0.1uF for ESD requesst. X01
C C
B B
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/03/14 Deciphered Date 2013/03/12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR_PIR
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9103P
Date: Wednesday, July 10, 2013 Sheet 52 of 52
5 4 3 2 1
www.s-manuals.com
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