Guru Nanak Institutions Technical Campus

(Autonomous)
Question Bank with Blooms
Taxonomy Level (BTL)
Subject Name with code : VLSI Design (EC0742) Class : IV/I/ECE
Academic Year : 2020-21 (I semester)
Blooms Taxonomy Levels (BTL)
1. Remembering 2.Understanding 3.Applying
4. Analyzing 5.Evaluating 6.Creating

BTL level Course

(Please Outcome
Questions mention (Please
Sl.No
L1 or L2 mention
or etc...) CO1 or
CO2 etc…)
Unit - I
Part – A (2 Marks)
1 Define figure of merit of MOS transistor. L1 CO1
2 Draw the CMOS inverter circuit. L2 CO1
3 Define threshold voltage of a MOS device. L1 CO1
4 What are the different types of pull-ups and explain about the resistor L2 CO1
pull-up and its usage.
5 Define gm of MOS transistor. L1 CO1
6 Explain about pass transistor logic L2 CO1
Part – B (5 Marks)
1 Derive the drain to source current equation for an NMOS enhancement L1 CO1
mode transistor.
2 Discuss the fabrication steps of an NMOS transistor and explain L2
its operation in detail.
3 Derive the expression for estimation of Pull-Up to Pull-Down ratio of L2 CO1
an n-MOS inverter driven by another n-MOS inverter.
4 Explain the operation of CMOS inverter and draw its transfer L4 CO1
characteristics.
5 Draw and explain the operation of BiCMOS inverter. L2 CO1
6 Distinguish between Bipolar and CMOS devices technologies in brief. L1 CO1
7 Discuss the fabrication steps of a CMOS transistor using n-well process L2 CO1
and explain its operation in detail.
UNIT-2
PART-A(2 Marks)
1 Differentiate Functional simulation and timing simulation. L2 CO2
2 Explain about the VLSI Design Flow. L2 CO2
3 Draw the stick diagram for two inputs NOR gates. L3 CO2
4 Explain about the contact cuts and its approaches. L1 CO2
5 Represent the stick diagram of a NMOS inverter. L3 CO2
6 Explain difference between stick diagram and layout diagram. L1 CO2
PART-B(5 Marks)
1 Draw the stick diagram and layout diagram for the following Boolean L3 CO2
expression using CMOS logic. F=[A(B+C)]’, Y=(AB+CD)’.
2 Explain in detail about the scaling concept in VLSI circuit Design. L2 CO2
3 Draw the Layout Diagrams for NAND Gate using CMOS design style. L3 CO2
4 Discuss about the stick diagrams and their corresponding mask layout L2 CO2
with examples.
5 Explain about λ-based design rules and discuss in detail with an L2 CO2
examples.
6 Explain the color code used for drawing stick diagram for NMOS and L2 CO2
PMOS designs and Design a Stick Diagram for 2-input n-MOS NAND
and NOR gates.
7 List and explain the scaling factors for device parameters briefly. L1/L2 CO2
UNIT-3
PART-A(2 Marks)
1 What is the importance of fan-in fan-out? L1 CO3
2 Differentiate between rise time and fall time? L2 CO3
3 What is switch logic? And explain its usage. L1 CO3
4 What are the issues involved in driving large capacitive loads in L2 CO3
VLSI circuits.
5 Explain about clocked CMOS logic and its usage. L1 CO3
6 Explain about the wiring capacitance and its need. L2 CO3
PART-B(5 Marks)
1 Implement 4: 1 multiplexer using switch logic L3 CO3
2 Explain the following L2 CO3
i. Fan-in
ii. Fan-out
iii. Choice of layers
3 Describe the following L2 CO3
a) Pseudo-nMOS logic
b) Domino Logic
4 Describe about the methods for driving large capacitive loads. L2 CO3
5 Explain different wiring capacitance used in Gate level design L3 CO3
with example.
6 Discuss the importance of timing delays in design of a system? L2 CO3
7 Explain the formal estimation of CMOS inverter delay rise time L2
estimation and fall time estimation.
UNIT-4
PART-A(2 Marks)
1 Draw the 1-bit SRAM cell. L1 CO4
2 What are the various serial access memories? L1 CO4
3 Design a 2-bit Parity generator. L2 CO4
4 Define Booth’s algorithm? L1 CO4
5 Write a note on Content Addressable Memory. L1 CO4
6 Explain the difference between EPROM and EEPROM. L2 CO4
PART-B(5 Marks)
1 Design a zero detector circuit. L3 CO4
2 Draw the schematic and logic diagram for a single bit adder and L4 CO4
explain its operation with truth table.
3 With neat circuit diagram, explain the operation of Barrel Shifter. L3 CO4
4 Explain about design of an ALU subsystem in brief. L2 CO4
5 Explain the working principle of Ripple carry adder using L4 CO4
transmission gates.
6 Draw the circuit diagram of three transistor DRAM cell with L3 CO4
storage nodes
7 Draw the basic circuit diagram of 6-T SRAM and explain its L3 CO4
operation.
UNIT-5
PART-A(2 Marks)
1 Implement 2:1 MUX using PAL. L3 CO5
2 Compare FPGA and CPLD architecture. L2 CO5
3 Explain about the principle of Built in Self Test. L2 CO5
4 Explain about the test principles used for testing. L2 CO5
5 Explain difference between PLA and PAL. L2 CO5
6 Define controllability and observability with respect to testing. L1 CO5
PART-B(5 Marks)
1 Discuss the various scan design techniques used? L2 CO5
2 Explain the Architecture of FPGA in detail. L2 CO5
3 Why stuck-at-faults occur in CMOS circuits? Explain with a L2/L1 CO5
suitable logical diagram.
4 What is the need for chip testing? And at what levels testing a L2 CO5
chip can occur?
5 Explain the following in detail L2 CO5
i. Boundary Scan Test Techniques.
ii. Testability and practices.
6 What is the drawback of serial scan and how it can be overcome? L2 CO5
7 What is CPLD? Draw the basic structure of a CPLD and give its L1/L3 CO5
application.
8 What is the need of Test and Testability in VLSI system design? L3 CO5