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DSD Lab Manuals: Design and Implementation of Multiplier in Fpga

This document describes designing and implementing an 8-bit signed multiplier in FPGA. The objectives are to design a pipelined multiplier that multiplies two 8-bit signed numbers in 2's complement format and implement it in FPGA. The document includes an introduction to multiplication algorithms and techniques. It provides Verilog code for an 8x8 signed multiplier module with testbench. The code is synthesized, simulated and tested on FPGA to multiply two 8-bit numbers and display the 16-bit result.

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56 views5 pages

DSD Lab Manuals: Design and Implementation of Multiplier in Fpga

This document describes designing and implementing an 8-bit signed multiplier in FPGA. The objectives are to design a pipelined multiplier that multiplies two 8-bit signed numbers in 2's complement format and implement it in FPGA. The document includes an introduction to multiplication algorithms and techniques. It provides Verilog code for an 8x8 signed multiplier module with testbench. The code is synthesized, simulated and tested on FPGA to multiply two 8-bit numbers and display the 16-bit result.

Uploaded by

AL RIZWAN
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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DSD lab Manuals Lab14

DESIGN AND IMPLEMENTATION OF MULTIPLIER IN FPGA.

OBJECTIVES

To design, synthesize, simulate pipelined multiplier to multiply two 8 bit signed


numbers in 2’s complement and to implement and program the same in FPGA.

INTRODUCTION

MULTIPLIER:

In many digital signal processing applications such as correlations,


convolutions, filtering and frequency analysis, one needs to
perform multiplication. Multiplication algorithms will be used to illustrate
methods of designing different cells so they fit into a larger structure. In
order to introduce these designs, simple serial and parallel multipliers will be
introduced. The appropriate tests should be consulted for more definite
system architecture. The most basic form of multiplication consists of
forming the products of two positive binary numbers. This may be
accomplished through the traditional technique ofSuccessive Addition and
shifts in which each additive is conditional on one of the multiplier bits.

The multiplication process may be viewed to consist of the following steps:


1. Evaluation of Partial Products,
2. Accumulation of the shifted partial products

It should be noted that binary multiplication is equal to partial AND


operations.Thus evaluation of partial products consists of the logical AND of
the Multiplicand and therelevant Multiplier bit. Each column of partial
products must then be added and if necessaryany carry values is passed to
the next column. There are a number of techniques that may be
used to perform multiplication. In general the choice is based on the factors
such as speed,throughput, numerical accuracy and area. As a rule,
multiplication may be classified by theformat, in which the words are
accessed namely,
1. Serial Form
2. Serial / Parallel Form
3. Parallel Form

1
DSD lab Manuals Lab14
Verilog Code:

module multiplier(clk,addr,load,clear,data_in,calc,result);

inputclk,clear,calc,load;
inputaddr;
input [7:0]data_in;
outputreg [15:0]result;
reg [7:0]ram[1:0];
always@(posedgeclk)
begin
if(~clear)
begin
ram[0]=8'b0;
ram[1]=8'b0;
end
else if(~load)
ram[addr]=data_in;
end
always@(posedgeclk)
begin
if(~load)
result={8'b0,data_in};
else if(~calc)
result= multiply_8x8_2sC (ram[0],ram[1]);
else
result={8'b0,ram[addr]};
end
function[15:0] multiply_8x8_2sC;
input[7:0] a,b;
reg[7:0] a_mag,b_mag;
reg[14:0] y_mag;
reg[14:0] y_neg;
begin
case (a[7])
0: a_mag = a[6:0];
1: a_mag = 128 - a[6:0]; // max(a_mag) = 128, thus 8 bits
endcase
case (b[7])
0: b_mag = b[6:0];
1: b_mag = 128 - b[6:0];
endcase
y_mag = a_mag * b_mag; // max(y_mag) = 16384, thus 15 bits
if ((a[7] ^ b[7]) & (y_mag != 0)) // if (a * b) is -ve AND non-zero
begin
// y_mag>=1, <= 16256, thus need only 14 bits
y_neg = 32768 - y_mag[13:0]; // max(y_neg) = 32767, thus need 15 bits

2
DSD lab Manuals Lab14
multiply_8x8_2sC = {1'b1,y_neg};
end
else
multiply_8x8_2sC = y_mag;
end
endfunction
endmodule

Simulation:

3
DSD lab Manuals Lab14
RTL Schematic:

RESULT:

Thus the onboard switches and LEDs were designed using Verilog HDL and it was
simulated and tested in the FPGA device.

4
Observations/Comments/Explanation of Results

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