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ITI1100A: Assignment # 4 Submission Deadline March 1, 2021@ 6:00PM Submit PDF File Format On Brightspace

This document contains an assignment for a digital logic design course. It includes 7 problems involving the design of combinational logic circuits using techniques like Boolean algebra, Karnaugh maps, decoders and minimization. Students are asked to derive logic expressions, design circuits with inputs and outputs, show equivalent forms, and implement circuits using decoders, NAND/NOR gates. The assignment is due on March 1, 2021 and should be submitted as a PDF file on Brightspace.

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123 views

ITI1100A: Assignment # 4 Submission Deadline March 1, 2021@ 6:00PM Submit PDF File Format On Brightspace

This document contains an assignment for a digital logic design course. It includes 7 problems involving the design of combinational logic circuits using techniques like Boolean algebra, Karnaugh maps, decoders and minimization. Students are asked to derive logic expressions, design circuits with inputs and outputs, show equivalent forms, and implement circuits using decoders, NAND/NOR gates. The assignment is due on March 1, 2021 and should be submitted as a PDF file on Brightspace.

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ITI1100A

Professor: Ahmed Karmouch

Assignment # 4
Submission Deadline March 1, 2021@ 6:00PM

Submit PDF file format on Brightspace

Solve the following problems.

4.1 Consider the combinational circuit shown in Fig. P4.1 .

Figure P4.1
(a)∗ Derive the Boolean expressions for T1 through T4 .
Evaluate the outputs F 1 and F 2 as a function of the four inputs.

(b) List the truth table with 16 binary combinations of the four
input variables. Then list the binary values for T1 through T4
and outputs F 1 and F 2 in the table.

(c) Plot the output Boolean functions obtained in part (b) on


maps and show that the simplified Boolean expressions are
equivalent to the ones obtained in part (a).

4.5 Design a combinational circuit with three inputs x, y, and z and


three outputs A, B, and C. When the binary input is 0, 1, 2, or 3, the
binary output is one greater than the input. When the binary input is
4, 5, 6, or 7, the binary output is two less than the input.

4.9 A BCD-to-seven-segment decoder is a combinational circuit that


converts a decimal digit in BCD to an appropriate code for the selection
of segments in an indicator used to display the decimal digit in a familiar
form. The seven outputs of the decoder (a, b, c, d, e, f, g) select the
corresponding segments in the display, as shown in Fig.P4.9(a). The
numeric display chosen to represent the decimal digit is shown in Fig.
P4.9(b). Using a truth table and Karnaugh maps, design the BCD-to-
seven-segment decoder using a minimum number of gates. The six
invalid combinations should result in a blank display. (HDL—see
Problem 4.51)

Figure 4.9

4.21 Design a combinational circuit that compares two 4-bit numbers


to check if they are equal. The circuit output is equal to 1 if the two
numbers are equal and 0 otherwise.

4.23 Draw the logic diagram of a 2-to-4-line decoder using (a) NOR
gates only and (b) NAND gates only. Include an enable input. (HDL—
see Problems 4.36 and 4.45 )

4.27 A combinational circuit is specified by the following three


Boolean functions:
F1( A , B , C ) = Σ ( 1 , 4 , 6 )
F2 ( A , B , C ) = Σ ( 3 , 5 )
F3( A , B , C ) = Σ ( 2 , 4 , 6 , 7 )
Implement the circuit with a decoder constructed with NAND gates
(similar to Fig. 4.19) and NAND or AND gates connected to the decoder
outputs. Use a block diagram for the decoder. Minimize the number of
inputs in the external gates.

4.28 Using a decoder and external gates, design the combinational


circuit defined by the following three Boolean functions:
(a)∗ F1= x ′ y z ′ + x z
F2= x y ′ z ′ + x ′ y
F3 = x ′ y ′ z ′ + x y
(b) F1 = ( y ′ + x ) z
F2 = y ′ z ′ + x ′ y + y z ′
F3 = ( x + y ) z

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