UNIT II

ARM7 BASED MICROCONTROLLER

Prof. M. N. Kakatkar
Sinhgad College of Engineering
 Syllabus
2

ARM7 Based Microcontroller

 Features
 Architecture (Block Diagram and Its Description)
 System Control Block (PLL and VPB divider)
 Memory Map
 GPIO
 Pin Connect Block
 Timer
 Instruction set
 Programming in Assembly language
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 Architecture…
3

ARM7TDMI-S processor:
 The ARM7TDMI-S is general purpose 32-bit microprocessor,

which offers high performance and very low power

consumption.
 Pipeline techniques are employed so that all parts of the

processing and memory systems can operate continuously.

 Due to their tiny size and low power consumption, LPC2148

are ideal for applications where miniaturization is a key

requirement.
 Impressive real-time interrupt response, Cost-effective
processor core.
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ARM7 Based Microcontroller LPC2148: Features
4
ARM7 Based Microcontroller LPC2148: Features
5
ARM7 Based Microcontroller LPC2148: Features
6
 Applications
7

 The ARM7TDMI-S: Thumb, makes it ideally suited for high-

volume applications with memory restrictions, or where code
density is an issue.

 Due to their tiny size and low power consumption, ideal for
applications where miniaturization is a key requirement.

 Communication gateways and Protocol converters

 Modems ,Voice recognition, Low end Imaging

 Industrial control and Medical systems.

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8
 ARM7 Based
Microcontroller
LPC2148:
9

Architecture

(1) Pins shared with GPIO.

(2) LPCC2144/6/8 only.

(3) USB DMA
controller with 8 kB of
RAM accessible as
general purpose RAM
and/or DMA is
available in LPC2146/8
only.
(4) LPC2142/4/6/8 only.

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 Buses
10

 In LPC2148, there are 3 type of buses

 The ARM7 Local Bus for interface to on-chip memory
controllers and fast GPIOs.
 The AMBA AHB (Advanced Microcontroller Bus
Architecture) for interface to the interrupt controller.
 The APB (ARM Peripheral Bus) or VLSI Peripheral Bus
(VPB) for connection to on-chip peripheral functions.
 The VPB can drive the peripheral at ¼ th CPU clock
frequency.
 The connection of on-chip peripherals to device pins is
controlled by a Pin Connect Block

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 ARM7 Based Microcontroller LPC2148:
system control block functions
11

The System Control Block includes several system features and

control registers for a number of functions. Not related to
specific peripheral devices. These include:
CrystalOscillator
External Interrupt Inputs

Miscellaneous System Controls and Status

Memory Mapping Control

PLL

Power Control

Reset

APB Divider

Wakeup Timer
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 system control block functions…
12

Phase Locked Loop (PLL)

 PLL is a closed loop system to generate high frequency by

multiplying with given factor to the input frequency.

 There are two PLL modules in the LPC2148 microcontroller.

 The PLL0 is used to generate the CCLK clock (system clock)

 The PLL1 has to supply the clock for the USB at the fixed
rate of 48 MHz.
 PLL interrupts are only available for PLL0 and not for PLL1.

 Input clock to both the PLLs must be between 10Mhz to

25Mhz strictly.

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 system control block functions…
PLL…
13

 The input frequency is multiplied: 10 MHz to

60 MHz for the CCLK and 48 MHz for the
USB clock using CCO.
 The multiplier can be an integer value
from 1 to 32
 The CCO range- 156 MHz to 320 MHz, so
there is an additional divider in the loop to keep
the CCO within its frequency range while the PLL is providing
the desired output frequency.

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 system control block functions…
PLL…
14

 ARM7 LPC2148 needs two clocks;

 one is for its peripherals and

 other for its CPU.

 CPU works faster with higher frequencies whereas peripheral

needs lower frequency to work with.
 The Peripheral Clock i.e. PCLK is derived from CPU Clock
i.e. CCLK.
 The input to APB Divider is CCLK and output is PCLK. By
Default PCLK runs at 1/4th the speed of CCLK.

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 system control block functions…
PLL…
15

 PLL activation is controlled via the PLLCON register. The

PLL multiplier and divider values are controlled by the
PLLCFG register.
 Since all chip operations, are dependent on the PLL0,
accidental changes in the PLL setup could result in
unexpected behavior, so these two registers are protected .
 The same concern is present with the PLL1 and the USB.
 Both PLLs are turned off and bypassed following a chip Reset
and when by entering Power-down mode.
 The program must configure and activate the PLL, wait for
the PLL to Lock, then connect to the PLL as a clock source.
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 PLL Registers in LPC2148
Protected

Activation

Multiplier &
divider values

Control and
Configuration

Loading
Control and
Configuration

16
PLL Control register: (PLL0CON & PLL1CON)
bit description
7 6 5 4 3 2 1 0
R R R R R R PLLC PLLE

Values
written
to this
register
do not
take
effect
until a
valid PLL
feed
Sequence
has taken
place.

17
 PLL Control register (PLL0CON - 0xE01F C080,
PLL1CON - 0xE01F C0A0)
18

 The PLLCON register contains the bits that enable

and connect the PLL.
 Enabling the PLL allows it to attempt to lock to the
current settings of the multiplier and divider values.
 Connecting the PLL causes the processor and all
chip functions to run from the PLL output clock.
 Changes to the PLLCON register do not take effect
until a correct PLL feed sequence has been given

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PLL Configuration register ( PLL0CFG & PLL1CHG ]
bit description
7 6 5 4 3 2 1 0
R19 PSEL PSEL MSEL MSEL MSEL MSEL MSEL
Values
written to
this
register
do not
take effect
until a valid
PLL feed
Sequence
has taken
place.
 PLL Configuration register (PLL0CFG - 0xE01F C084,
PLL1CFG - 0xE01F C0A4)
20

 The PLLCFG register contains the PLL multiplier

and divider values.
 Changes to the PLLCFG register do not take effect
until a correct PLL feed sequence has been given

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PLL Status register (PLL0STAT & PLL1STAT)
bit description

21
 PLL Status register (PLL0STAT - 0xE01F C088, PLL1STAT -
0xE01F C0A8)
22

 The read-only PLLSTAT register provides the

actual PLL parameters that are in effect at the time
it is read, as well as the PLL status.
 PLLSTAT may disagree with values found in
PLLCON and PLLCFG because changes to those
registers do not take effect until a proper PLL feed
has occurred

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 PLL Feed register (PLL0FEED - 0xE01F C08C, PLL1FEED -
0xE01F C0AC)
23

 A correct feed sequence must be written to the

PLLFEED register in order for changes to the
PLLCON and PLLCFG registers to take effect. The
feed sequence is:
 1. Write the value 0xAA to PLLFEED.
 2. Write the value 0x55 to PLLFEED.
 The two writes must be in the correct sequence, and
must be consecutive APB bus cycles.

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Elements Determining PLL’s frequency

Lets define some symbols which are used in

Datasheet
FOSC frequency from the crystal oscillator(XTAL)/external clock

FCCO frequency of the PLL Current Controlled Oscillator(CCO)

CCLK PLL output frequency (CPU Clock)

M PLL Multiplier value from the MSEL bits in the PLLCFG register

P PLL Divider value from the PSEL bits in the PLLCFG register

PCLK Peripheral Clock which is derived from CCLK

24
Formulae for determining clock

 The frequency of CPU clock or the output of the

PLL is CCLK = M x FOSC or CCLK = FCCO / (2 x P)

 The frequency of CCO is FCCO = CCLK x 2 x P or

FCCO = FOSC x M x 2 x P

Standard Values (when PLL is used)

1. The range of FOSC is 10 MHz to 25 MHz
2. The range of CCLK is 10 MHz to FMAX (60 MHz for
LPC214x MCUs)
3. The range of FCCO is 156 MHz to 320 MHz
25
 PROGRAMMING: PLL in LPC2148 ARM7
 While configuring clock and PLL in LPC2148 ARM7. We
have to follow general steps. It’s important to follow
sequence to perform configuration part of PLL
1. Select the desired operating
frequency for your system (CPU
Operating Frequency) CCLK
2. Check the oscillator connected to
the controller on board FOSC
3. Calculate the value of PLL Multiplier
‘M’; CCLK=M x FOSC
4. Find the value of PLL Divider ‘P’ in
such a way that is in the range of
156 MHz to 320 MHz,
156<FCCO<320 = CCLK x 2 x P
5. Write the value PLLCON and PLLCFG
6. Write
the PLLFEED values 0xAA and 0x55
7. Wait for PLL to lock
8. Connect the PLL
9. Write
the PLLFEED values 0xAA and 0x55
once again
26
 Example 1: an application not using
the USB - configuring the PLL0
Q. We have 12 MHz crystal connected to LPC2148 on our
microcontroller development board.

1. We can say FOSC=12 MHz and 6. So we found P = 2 meets

And we want core to be run at
60 MHz. FCCO requirements (156
2. In this case, we have to
multiply crystal frequency i.e.12 MHz Programming PLL has to
MHz by ‘5’, therefore CCLK
= M x FOSC = 5 x 12 = 60 MHz
be done in some sequence to
3. Also we have to keep FCCO make new PLL setting
(Frequency of the PLL Current
Controlled Oscillator) within its effective.
range i.e. [156 MHz – 320
MHz], 7. First of all we have to write
4. so we have to control another
constant ‘P’:FCCO = CCLK x 2 multiplier M and divider P
x P;
5. FCCO = 60 MHz x 2 x 2 = 240 values to PLLCFG Register.
MHz 27
NOTE: For PLLCFG register we have to use a value of (M-1) for MSEL Bits where M is
the value obtained from the equations. Say for example if we want to use M=5 from
the equation then we have to apply a value of (M-1) = (5-1) = 4 to the register.
Similarly, we have to use a specific value for PSEL bits as mentioned in table earlier.
Hence for P=2, we have to assign 01 to PSEL. Read a table carefully

7 6 5 4 3 2 1 0
R PSEL PSEL MSEL MSEL MSEL MSEL MSEL

0 0 1 0 0 1 0 0

•So for our calculation M = 5 and P = 2,

then PLLCFG = 0b00100100 = 0x24;
•Further, there has to follow some sequence to
activate PLL.
•After PLLCFG register is updated then
update PLLCON register and then we have to
write 0xAA and then 0x55 to PLLFEED register.
This value has to be written in consecutive
cycles. 28
Example Code: PLL in LPC2148 ARM7
void PLL_Init(void)
{ //Enable PLL
PLL0CON = 0x01; //Multiplier and divider
PLL0CFG = 0x24; setup
PLL0FEED = 0xAA; //Feed sequence
PLL0FEED = 0x55;
//is locked?
while(!(PLL0STAT & 0x00000400));
PLL0CON = 0x03; //Connect PLL after PLL is
locked
PLL0FEED = 0xAA;
PLL0FEED = 0x55; //Feed sequence
VPBDIV = 0x01; // PCLK is same as CCLK
} i.e.60 MHz
29
 VLSI Peripheral Bus Divider
• The Peripheral Clock i.e. PCLK is derived from CPU Clock i.e.
CCLK. The APB Divider decides the operating frequency of
PCLK. The input to APB Divider is CCLK and output is PCLK.
• By Default PCLK runs at 1/4th the speed of CCLK. To control
APB Divider we have a register called VPBDIV
• The value in VPBDIV controls the division of CCLK to
generate PCLK as shown below:
VPBDIV=0x00; APB bus clock (PCLK) = ¼th of the processor clock
(CCLK)
VPBDIV=0x01; APB bus clock (PCLK) = processor clock (CCLK)

VPBDIV=0x02; APB bus clock (PCLK) = ½th of the processor clock

(CCLK)
VPBDIV=0x03; Reserved. If this value is written to the APBDIV
register, it has no effect (the previous setting is
retained).
The APB Divider determines the relationship between the processor 30
clock (CCLK) and the clock used by peripheral devices (PCLK).
APB/VPB divider:
 The APB Divider serves two purposes.
1. The first is to provides peripherals with desired PCLK
via APB bus so that they can operate at the speed
chosen for the ARM processor.
2. APB Divider allow power savings when an application
does not require any peripherals to run at the full
processor rate.

31
32
 PLL Interrupt
33

•The PLOCK bit in the PLLSTAT register is

connected to the interrupt controller.
•This allows for software to turn on the PLL and
continue with other functions without having to
wait for the PLL to achieve lock.
•When the interrupt occurs (PLOCK = 1), the
PLL may be connected, and the interrupt
disabled.

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 GPIO…
34

 LPC2141/2/4/6/8 has two 32-bit General Purpose I/O ports.

 Total of 30 input/output and a one output only pin out of 32
pins are available on PORT0.
 PORT1 has up to 16 pins available for GPIO functions.
PORT0 and PORT1 are controlled via two groups of 4
registers
 Legacy registers shown in Table allow backward compatibility
with earlier family devices, using existing code.
 The functions and relative timing of older GPIO
implementations is preserved.

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 ARM7 Based Microcontroller LPC2148:
Pin connect block
35

 The pin connect block allows selected pins of the

microcontroller to have more than one function.
 Configuration registers control the multiplexers to allow
connection between the pin and the on chip peripherals.
 Peripherals should be connected to the appropriate pins prior
to being activated, and prior to any related interrupt(s) being
enabled.

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 Pin connect block…
36

Pin function Select register 0 (PINSEL0 - 0xE002 C000)

 The PINSEL0 register controls the functions of the pins as per

the settings listed in Table The direction control bit in the

IO0DIR register is effective only when the GPIO function is
selected for a pin. For other functions, direction is controlled
automatically

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 Pin connect block…
37

Pin function Select register 1 (PINSEL1 - 0xE002 C004)

 The PINSEL1 register controls the functions of the pins as per

the settings listed in following tables. The direction control bit

in the IO0DIR register is effective only when the GPIO
function is selected for a pin. For other functions direction is
controlled automatically

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 Pin connect block…
38

Pin function Select register 2 (PINSEL2 - 0xE002 C014)

 The PINSEL2 register controls the functions of the pins as per the
settings listed in Table. The direction control bit in the IO1DIR
register is effective only when the GPIO function is selected for a
pin. For other functions direction is controlled automatically

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 Pin connect block…
39

Warning: use read-modify-write operation when accessing

PINSEL2 register.
 Accidental write of 0 to bit 2 and/or bit 3 results in loss of
debug and/or trace functionality! Changing of either bit 2 or
bit 3 from 1 to 0 may cause an incorrect code execution!
 The Debug modes are entered as follows:

 During reset, if P1.26 is pulled low (weak bias resistor is

connected from P1.26 to Vss), JTAG pins will be

available.
 During reset, if P1.20 is pulled low (weak bias resistor is
connected from P1.20 to Vss), Trace port will be available.
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 GPIO…
40

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LPC 2148: System Memory Map
It has 4 GB address space (PC is 32
bit). LPC2148 has 32kB on chip SRAM
and 512 kB on chip FLASH memory. It
has inbuilt support up to 2kB end point
USB RAM also.

1. On chip FLASH memory system

The LPC2148 incorporates a 512 kB
Flash memory system. This memory may
be used for both code and data storage.

2. On chip SRAM
The LPC2148 provides 32 kB of static
RAM which may be used for code and/or
data storage. It may be accessed as 8-
bits, 16-bits, and 32-bits.
APB and AHB Peripherals
1. Both the AHB and APB peripheral
areas are 2 megabyte spaces which
are divided up into 128 peripherals
2. Each peripheral space is 16 kilobytes
Fig: System Memory Map in size 41
 2 MB space
for AHP
Peripherals.
Divided into
128
peripherals

2 MB space
for AHB
Peripherals.
Divided into
128
peripherals

16 KB 42
ARM7 Based
Microcontroller
LPC2148:
43

Memory maps

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 Memory maps…
44

 Both the AHB and APB peripheral areas are 2 megabyte

spaces which are divided up into 128 peripherals
 Each peripheral space is 16 kilobytes in size
 All peripheral register addresses are word aligned (to 32-bit
boundaries) regardless of their size.
 This eliminates the need for byte lane mapping hardware that
would be required to allow byte (8-bit) or half-word (16-bit)
accesses to occur at smaller boundaries

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45

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 ARM7 Based Microcontroller LPC2148:
Timer
46

Features:
 A 32-bit Timer/Counter with a programmable 32-bit Prescaler.

 Counter or Timer operation

Timer/Counter0 and Timer/Counter1 are functionally

identical except for the peripheral base address.
 Four 32-bit capture channels/ timer - Take a snapshot of the timer
value when an input signal transitions.
 Optionally generate an interrupt.
 Four 32-bit match registers- allow:
– Continuous operation with optional interrupt generation on
match.
– Stop / Reset timer on match with optional interrupt generation.

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 PCLK and VPDIV Register
• All of the timers are driven by PCLK which is the
Peripheral Clock. The system is generally driven by the
CCLK or Crystal Clock.
• PCLK is derived from CCLK which is the processor
clock.
• If CCLK = 60MHz, VPBDIV register determines the
rate of PCLK. VPBDIV is not the same as the prescaler
register although its action is similar.
• VPBDIV is an 8-bit register and only the lower two bits
of it are used as follows:
0x00; (PCLK) = ¼th (CCLK)
0x01; (PCLK) = (CCLK)
0x02; (PCLK) = ½th (CCLK)
VPBDIV register values 0x03; Reserved.

PCLK goes into a prescaler which further scales the clock going to the
timer. The output of the prescaler actually drives the timer register. 47
 Timer
• No of Timers : 2 (Timer 0 & Timer 1)
• The Timer/Counter is designed to count cycles of the
peripheral clock (PCLK) or externally-supplied clock, and
• Can optionally generate interrupts or perform other
actions at specified timer values

Functional Block Diagram

48
 Timer Features

• Two timer/counters named Timer0 and Timer1.

Each timer has the following features:
 A 32-bit Timer/Counter with a programmable 32-
bit Prescaler. The prescaler allows the user to
divide the clock.
 Counter or Timer operation.
 Four 32-bit capture channels per timer that
take a snapshot of the timer value when an
input signal transitions. A capture event may also
optionally generate an interrupt.

49
 Timer Registers Description
1) PR : Prescale Register (32 bit) – Stores the maximum value
of Prescale counter after which it is reset.

2) PC : Prescale Counter Register (32 bit) – This register

increments on every PCLK(Peripheral clock).
a. This register controls the resolution of the timer.
b. When PC reaches the value in PR , PC is reset back to
0 and Timer Counter is incremented by 1.
c. If PR=9 then Timer Counter Increments on every
10th cycle of PCLK. Hence by selecting an prescale
value we can control the resolution of the timer.

3) TC : Timer Counter Register (32 bit) – This is the main

counting register.
Timer Counter increments when PC reaches its maximum
value as specified by PR.
50
 Timer Registers
4) TCR : Timer Control Register – This register is used to
enable , disable and reset TC.
a. When bit0 =1, timer is enabled and when 0 it is
disabled.
b. When bit1 is set to 1 TC and PC are set to zero
together in sync on the next positive edge of PCLK.
Rest of the bits of TCR are reserved.

5) CTCR : Count Control register – Used to select

Timer/Counter Mode.
a. For our purpose we are always gonna use this in Timer
Mode. When the value of the CTCR is set to 0×0 Timer
Mode is selected.

51
 Timer Features
 Four 32-bit match registers that allow:
– Continuous operation with optional interrupt
generation on match.
– Stop timer on match with optional interrupt
generation.
– Reset timer on match with optional interrupt
generation
 Four external outputs corresponding to match
registers,
with the following capabilities:
– Set low on match.
– Set high on match.
– Toggle on match.
– Do nothing on match. 52
 Match Registers
• What is a Match Register anyways ?
• Ans: A Match Register is a Register which
contains a specific value set by the user.
• When the Timer starts – every time after TC
is incremented the value in TC is compared
with match register.
• If it matches then it can Reset the Timer or
can generate an interrupt as defined by the
user.
• Match Registers can be used to:
– Stop Timer on Match and trigger an optional
interrupt.
– Reset Timer on Match and trigger an optional
interrupt.
– To count continuously and trigger an interrupt on
match.
53
Match Register

Functional Block Diagram

54
 Timer Registers
MCR : Match Control register – This register is used to
control which all operations can be done when the value in
MR matches the value in TC. Bits 0,1,2 are for MR0 , Bits
3,4,5 for MR1 and so on. Heres a quick table which shows
the usage:

For MR0:
– Bit 0 : Interrupt on MR0 i.e trigger an interrupt when MR0 matches
TC. Interrupts are enabled when set to 1 and disabled when set to 0.
– Bit 1 : Reset on MR0. When set to 1 , TC will be reset when it
matched MR0. Disabled when set to 0.
– Bit 2 : Stop on MR0. When set to 1 , TC & PC will stop when MR0
matches TC.
– Similarly bits 3-5 , 6-8 , 9-11 are for MR1 , MR2 ,
MR3 respectively.

55
 Timer…
Pin description…

• MAT0.3..0 & MAT1.3..0 (Output)

• External Match Output 0/1- When a
match register 0/1 (MR3:0) equals the
timer counter (TC), this output can
either toggle, go low, go high, or do
nothing.
• The External Match Register (EMR)
controls the functionality of this output.

56
 Capture Registers
• What are Capture Registers ?
Ans: As the name suggests it is used to Capture
Input signal.
When a transition event occurs on a Capture pin
, it can be used to copy the value of TC into any
of the 4 Capture Register or to generate an
Interrupt.
• . CAP0.3..0 & CAP1.3..0 (Input)
Capture Signals- A transition on a this
(capture) pin is found, it loads one of the
Capture Registers with the value in the Timer
Counter and optionally generate an interrupt.

57
Capture Register

Functional Block Diagram

58
 Timer…
Pin description…

List of all CAPTURE signals, together with pins

on where they can be selected:
Capture 0:
• CAP0.0 (3 pins) : P0.2, P0.22 and P0.30
• CAP0.1 (1 pin) : P0.4
• CAP0.2 (3 pin) : P0.6, P0.16 and P0.28
• CAP0.3 (1 pin) : P0.29
Capture 1:
• CAP1.0 (1 pin) : P0.10
• CAP1.1 (1 pin) : P0.11
• CAP1.2 (2 pins) : P0.17 and P0.19
• CAP1.3 (2 pins) : P0.18 and P0.21

59
 Timer Register Description
7) IR : Interrupt Register – It contains the interrupt flags for 4 match
and 4 capture interrupts.
a. Bit0 to bit3 are for MR0 to MR3 interrupts respectively.
b. And similarly the next 4 for CR0-3 interrupts.
c. when an interrupt is raised the corresponding bit in IR will be set to
1 and 0 otherwise.
d. Writing a 1 to the corresponding bit location will reset the interrupt
– which is used to acknowledge the completion of the corresponding
ISR execution.
Setting up & Use the following sequence for Setting up
configuring Timers : Timers:
1. To use timers we 1. Set appropriate value in TxCTCR
need to first configure 2. Define the Prescale value in TxPR
them. 3. Set Value(s) in Match Register(s) if
2. We need to set required
appropriate values in 4. Set appropriate value in TxMCR if using
TxCTCR, TxIR, TxPR Match registers / Interrupts
and reset TxPC, TxTC. 5. Reset Timer – Which resets PR and TC
Finally we assign 6. Set TxTCR to 0×01 to Enable the Timer
TxTCR = 0×01 which when required
enables the timer. 7. Reset TxTCR to 0×00 to Disable the
60
Timer when required
Timer Registers Basics

61
 Implement of basic function required
for Timer Operation:
void initTimer0(void); Attention Plz! :
1. This function is used to
void initTimer0(void) setup and initialize the
{ Timer block.
/*Assuming that PLL0 has been 2. Timer blocks use
setup with CCLK = 60Mhz and peripheral clock as their
PCLK also = 60Mhz.*/ input and hence
peripheral clock must be
T0CTCR = 0x0; // Timer Mode initialized before Timer
Selected is initialized.
3. In our case it is
T0PR = PRESCALE-1;
assumed that LPC2148
//(Value in Decimal!) –
is connected to 12Mhz
// Increment T0TC at every 60000
XTAL and both CPU and
clock cycles//Count begins from zero
Peripheral Clocks have
hence subtracting 1//60000 clock
been setup to tick at
cycles @60Mhz = 1 mS
60Mhz.
T0TCR = 0x02; //Reset Timer & prescaler;
disable prescaler count; 0b0000 0010 62
}
 Timer Calculations
1. The delay or time required for 1 clock cycle at ‘X’ MHz is
given by :

2. Hence in our case when PR=0 i.e TC increments at every

PCLK, the delay required for TC to increment by 1 is:

3. Similarly when we set PR = 59999 the delay in this case

will be:

• which boils down to 1/1000 = 0.001 Seconds

• Hence the delay required for TC to increment by 1
will be 1mS.

63
 Delay program using timers
delayMS(unsigned int milliseconds);

void delayMS(unsigned int milliseconds) //Using Timer0

{
T0TCR = 0x02; //Reset Timer, 0b0000 0010

T0TCR = 0x01; //Enable timer or start counter 0,

0b 0000 0001

while(T0TC < milliseconds); //wait until timer counter

//reaches the desired delay

T0TCR = 0x00; //Disable timer, 0b0000 0000

}

Main Program 64
 ARM instruction set

65 5/18/2021
 ARM Instruction Set

66

ARM instruction set

Data processing
instructions
Data transfer
instructions
Block transfer
instructions
Branching instructions

Multiply instructions
Software interrupt
instructions

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 The ARM Register Set
Current Visible Registers
r0
Abort
Undef
SVC
IRQ
FIQ
User Mode
Mode
Mode
Mode r1
r2
r3 Banked out Registers
r4
r5
r6 User FIQ IRQ SVC Undef Abort
r7
r8 r8 r8
r9 r9 r9
r10 r10 r10
r11 r11 r11
r12 r12 r12
r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp)
r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr)
r15 (pc)

cpsr
spsr spsr spsr spsr spsr spsr
 Conditional Execution

 An unusual feature of the ARM instruction set is that conditional execution

applies no only to branches but to all ARM instructions

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 Data Processing Instruction

 Arithmetic (ADD, SUB, RSB)

 E.g. ADD r3,r1,r2 (Rd, Rm, Rn)
 For conditional execution, ADDEQ, ADDCS
etc.
 3-address instruction format

 2 source operands and 1 destination register

 One source is always a register, the second
may be a register, a shifted register or an
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immediate value 5/18/2021
 Data Processing Instruction

 All operands are 32-bit wide; come from

registers or literal in the instruction itself
 Second operand sent to ALU via barrel shifter

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 Using and Updating the condition Field

 To execute an instruction conditionally, simply postfix

it with the appropriate condition:

 For example and add instruction takes the form

 ADD r0, r1, r2 ; r0 = r1 + r2 (ADDAL)
 To execute this only if the zero flag is set
 ADDEQ r0, r1, r2 ; r0 = r1 + r2 iff zero flag set
 By default, data processing operations do not affect the
condition flags

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 Using and Updating the condition Field

 To cause the condition flags to be updated, the

instruction needs to be postfixed with an “S”.

 For
example to add two numbers and set the
condition flags:
ADDS r0, r1, r2 ; r0 = r1 + r2 and set flags
ADDEQS r1, r2,r3;
; r1 = r2 +r3 if equality condition satisfy
72 ; otherwise nop 5/18/2021
 Data Processing Instruction

 Arithmetic (ADD, SUB, RSB)

 Logical (BIC, AND)

 Compare (CMP, TST)

 Register movement (MOV, MVN)

 32-bit result placed in register

 3-address instruction format
 2 source operands and 1 destination register

 One source is always a register, the second may be a

register, a shifted register or an immediate value
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 Arithmetic Instructions

 Arithmetic Operations

ADD r0,r1,r2 ;r0:= r1+r2

ADC r0,r1,r2 ;r0:= r1+r2+C
SUB r0,r1,r2 ;r0:= r1–r2
SBC r0,r1,r2 ;r0:= r1–r2+C
RSB r0,r1,r2 ;r0:= r2–r1, reverse
subtraction
RSC r0,r1,r2 ;r0:= r2–r1+C
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 Logical Instructions

 Bit-wise Logical Operations

AND r0,r1,r2 ;r0:= r1 AND r2

ORR r0,r1,r2 ;r0:= r1 OR r2
EOR r0,r1,r2 ;r0:= r1 XOR r2
BIC r0,r1,r2 ;r0:= r1AND (NOT r2), bit clear

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 Use of Barrel Shifter
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 Barrel Shifter
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 Shift Register Operands
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 ADD r3,r1,r2,LSL#3 ;r3 := r1 + 8 * r2

 A single instruction executed in a single cycle

 LSL: Logical Shift Left by 0 to 31 places, 0 filled at the LSB.

 LSR, ASL (Arithmetic Shift Left), ASR, ROR (Rotate Right),

RRX (Rotate Right Extended by 1 place)

 ADD r5, r5 ,r3, LSL r2 ; r5 = r5 + r3 shifted left by r2

times

 MOV r12, r4, ROR r3 ;r12:=r4 rotated right by value of r3

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 Multiply Instructions
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• 32-bit product (Least Significant)

– MUL{<cond>}{S} Rd,Rm,Rs
– MLA{<cond>}{S} Rd,Rm,Rs,Rn

MUL r4,r3,r2; r4:=(r3*r2)[31:0]

MLA r4,r3,r2,r1; r4:=(r3*r2+r1)[31:0]
• 64-bit Product
– <mul>{<cond>}{S} RdHi,RdLo,Rm,Rs
– <mul> is UMULL,UMLAL,SMULL,SMLAL
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 Multiply Instructions
80

Opco de Mnemo ni c Meani ng Effect

[2 3 :2 1 ]
000 MUL Multiply (32-bit result) Rd := (Rm * Rs) [31:0]
001 MLA Multiply-accumulate (32-bit result) Rd := (Rm * Rs + Rn) [31:0]
100 UMULL Unsigned multiply long RdHi:RdLo := Rm * Rs
101 UMLAL Unsigned multiply-accumulate long RdHi:RdLo += Rm * Rs
110 SMULL Signed multiply long RdHi:RdLo := Rm * Rs
111 SMLAL Signed multiply-accumulate long RdHi:RdLo += Rm * Rs

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 Register Transfer Instruction

 Register Movement Operations

 Omit 1st source operand from the format
MOV r0, r2 ; r0:=r2
MVN r0,r2 ; r0:=NOT r2, move 1’s
complement

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 Comparison Instruction

 Comparison Operations
 Not produce result in registers; subtract the
destination from the source
 Just set the condition code bits (N, Z, C and V) in
CPSR
CMP r1,r2 ; set cc on r1 - r2, compare
CMN r1,r2 ; set cc on r1 + r2, compare negated
TST r1,r2 ; set cc on r1 AND r2, bit test
TEQ r1,r2 ; set cc on r1 XOR r2, test equal

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 Branch Instructions

 Syntax
 Branch: B{<cond>} Label
 Branch is like jump unconditional.
 Branch with Link: BL{<cond>}
subroutine_label
 BL is like a call to subroutine.

The PC-relative offset for branch instructions is

calculated by:
– Taking the difference between the branch instruction
and the target address minus 8 (to allow for the
pipeline)
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 Conditional Branch

 The branch has a condition associated with it and it

is only executed if the condition codes have the
correct value – taken or not taken
MOV r0,#0 ;initialize counter
Loop …
ADD r0,r0,#1 ;increment loop counter
CMP r0,#10 ;compare with limit
BNE Loop ;repeat if not equal
;else fail through

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 Examples of Branch Instructions

Call a subroutine
 Unconditional jump BL SUB
B LABEL …
… SUB …
LABEL … MOV PC,r14

Loop ten times Conditional subroutine

MOV r0,#10 call
Loop … CMP r0,#5
SUBS r0,#1 BLLT SUB1 ;if r0<5,
BNE Loop ;call sub1
… BLGE SUB2 ;else call
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 Example of Conditional Execution

CMP r0,#5
CMP r0,#5
BEQ Bypass ;if (r0!=5)
ADDNE r1,r1,r0
ADD r1,r1,r0 ;{r1=r1+r0}
SUBNE r1,r1,r2
SUB r1,r1,r2
Bypass …

 Whenever the conditional sequence is 3 instructions for fewer it is

better (smaller and faster) to exploit conditional execution than to
use a branch
CMP r0,r1
if((a==b)&&(c==d)) e++; CMPEQ r2,r3
ADDEQ r4,r4,#1

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 Example of conditional execution

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 Branch with Link and exchange

 B{L}X{<cond>} Rm

The branch target is specified in a register, Rm

 Bit[0] of Rm is copied into the T bit in CPSR; bit[31:1] is moved
into PC
 If Rm[0] is 1, the processor switches to execute Thumb
instructions and begins executing at the address in Rm aligned to
a half-word boundary
 If Rm[0] is 0, the processor continues executing ARM
instructions and begins executing at the address in Rm aligned to
a word boundary
 BLX <target address>
 Call Thumb subroutine from ARM
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Conditional Branch
B ran c h In t e rp re t at i o n No rmal us e s
B Unconditional Always take this branch
BAL Always Always take this branch
BEQ Equal Comparison equal or zero result
BNE Not equal Comparison not equal or non-zero result
BPL Plus Result positive or zero
BMI Minus Result minus or negative
BCC Carry clear Arithmetic operation did not give carry-out
BLO Lower Unsigned comparison gave lower
BCS Carry set Arithmetic operation gave carry-out
BHS Higher or same Unsigned comparison gave higher or same
BVC Overflow clear Signed integer operation; no overflow occurred
BVS Overflow set Signed integer operation; overflow occurred
BGT Greater than Signed integer comparison gave greater than
BGE Greater or equal Signed integer comparison gave greater or equal
BLT Less than Signed integer comparison gave less than
BLE Less or equal Signed integer comparison gave less than or equal
BHI Higher Unsigned comparison gave higher
BLS Lower or same Unsigned comparison gave lower or same
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 Branch Instructions

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 Loading Constants

 No single ARM instruction can load a 32-bit immediate constant

directly into a register
 All ARM instructions are 32-bit long

 The data processing instruction format has 12 bits available for

operand 2 .
 Instead it is used to store 8-bit constants, give a range of 0-255
 To load a constant, simply move the required value into a register –
the assembler will convert to the rotate form for us
 MOV r0,#4096

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 Loading 32-bit Constants

 To allow larger constants to be loaded, the assembler offers a

pseudo-instruction:
 LDR Rd,=const
 This will either:
 Produce a MOV or MVN instruction to generate the value (if possible)
or
 Generate a LDR instruction with a PC-relative address to read the
constant from a literal pool (constant data area embedded in the code)

 For example
 MOV r0,=&FF ;MOV r0,#0xFF

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 Load and Store Instructions

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 Load and Store Instructions

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 Indexing methods

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 Indexing methods

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 Multiple Register Data Transfer
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 The load and store multiple instructions (LDM/STM) allow

between 1 and 16 registers to be transferred to or from memory
 Lowest register number is always transferred to/form lowest memory
location accessed

 These instruction are very efficient for

 Moving block of data around memory
 Saving and restoring context – stack
 Base register used to determine where memory access should
occur
 4 different addressing modes
 Base register can be optionally updated following the transfer (using “!”)

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 Load/ Store multiple
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 Block Transfer Instructions with example
99

Mi
LDM Mi+1
R0 Mi+2
R1
R2
Mi+14
Mi+15
R14 STM
R15
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 Multiple Register Data Transfer

 The direction that the base pointer moves through memory is

given by the postfix to the STM/LDM instruction
 STMIA/ LDMIA: Increment After
 STMIB/ LDMIB: Increment Before
 STMDA/ LDMDA: Decrement After
 STMDB/ LDMDB: Decrement Before

 Load store pairs:

 STMIA - LDMDB
 STMIB - LDMDA
 STMDA - LDMIB
 STMDB - LDMIA

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 Stack operations

 This ARM instruction can be also used to carry out stack

operations.
 The pop instruction uses load multiple instruction.
 The push instruction uses store multiple instruction.
 Another interesting feature is that the stack can be made either
ascending or descending
 When uses full stack (F), the stack pointer points to last or full
location.(Top of the stack)
 When uses empty stack (E), the stack pointer points to bottom
or empty location.(Bottom of the stack)

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 Stack operations

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 Swap Memory and Register Instructions

 Syntax
 SWP{<cond>}{B} Rd,Rm,[Rn]

 Rd <- [Rn], [Rn] <- Rm

 Combine a load and a store of a word or an unsigned byte in a

single instruction

 Example
ADR r0,SEMAPHORE
SWPB r1,r1,[r0] ;exchange byte

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 Status Register to General Register
Transfer instructions

 Syntax
 MRS{<cond>} Rd, CPSR|SPSR

 The CPSR or the current mode SPSR is copied into the

destination register. All 32 bits are copied.

 Example
MRS r0,CPSR
MRS r3,SPSR

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 General Register to Status Register
Transfer instructions

 Syntax
 MSR{<cond>} CPSR_<field>|SPSR_<field>,#<32-bit
immediate>
 MSR{<cond>} CPSR_<field>|SPSR_<field>,Rm

 <field> is one of
 c – the control field PSR[7:0]
 x – the extension field PSR[15:8]
 s – the status field PSR[23:16]
 f – the flag field PSR[31:24]

 Example
 Set N, X, C, V flags
 MSR CPSR_f, #&f0000000
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 Coprocessor Instructions

 The ARM architecture supports 16 coprocessors

 The instructions for each coprocessor occupy a fixed part of the ARM
instruction set
 If the appropriate coprocessor is not present in the system, an undefined
instruction exception occurs.
 There are three types of coprocessor instruction
 Coprocessor data processing
 CDP: Initiate a coprocessor data processing operation
 Coprocessor register transfers
 MRC: Move to ARM register from coprocessor register
 MCR: Move to Coprocessor register from ARM register
 Coprocessor memory transfers
 LDC: Load coprocessor register from memory
 STC: Store from coprocessor register to memory

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 Software Interrupt (SWI)

 SWI{<cond>}<24-bit immediate>
 Used for calls to the operating system and is often called a “supervisor
call”
 The supervisor is a program which operates at a privileged level, which
means that it can do things that a use-level program cannot do directly
 It puts the processor into supervisor mode and begins executing
instruction from address 0x08 (refer to P.21)
 Save the address of the instruction after SWI in r14_svc
 Save the CPSR in SPSR_svc
 Enter supervisor mode and disable IRQs
 Set PC to 0816 and begin executing the instruction there

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 Addition Program

AREA SIMPLE_PROGRAM, CODE, READONLY

ENTRY
MOV R1, #0X05
MOV R2, #0X03
ADD R1, R1, R2
HERE B HERE
END

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 Subtraction Program

• Subtraction
• AREA Program, CODE, READONLY
ENTRY
MOV R1, #0X000000008; /GET 1st VALUE

MOV R2, #0X000000003; /GET 2nd VALUE

SUB R3, R1, R2; /R3=R1-R2

END

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 Loading numbers from memory

 AREA Program,CODE, readonly

 ENTRY
 LDR R1, NUM1
 LDR R2, NUM2
 ADD R3, R1, R2
 S BS
 AREA storage,data, readonly

 NUM1 DCD 0x10

 NUM2 DCD 0x15


 END
 110/70 5/18/2021
• Multiplication of numbers

• Multiplication :
AREA SIMPLE_PROGRAM, CODE, READONLY
ENTRY
MOV R1, #0X05
MOV R2, #0X03
MUL R1, R1, R2
HERE B HERE
END

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SERIES ADDITION OF 'N' 32 BIT NUMBERS

 AREA program, CODE, readwrite

 ENTRY
 LDR R1, N ;Load Counter
 LDR R2, NOS ;Initialize the address Pointer
 MOV R0, #0 ;Clear Register to hold result
 LOOP LDR R3,[R2],#4 ;Load the number to register
 ADD R0, R0, R3 ;Addition of nos.
 SUBS R1, R1,#1 ;Decerement counter
 BNZ LOOP ;Check counter = 0
 STR R0,RESULT ;Store result
 HERE B HERE
 AREA storage , data, readwrite
 N DCD 0x05
 NOS DCD 05,06,07,08,09
 RESULT DCD 0x0
 END 112/70 5/18/2021

To find the largest number from series of numbers

 AREA program, CODE, readwrite

 ENTRY
 LDR R1, N ;Load Counter
 LDR R2, NOS ;Initialize the address Pointer
 MOV R0, #0 ;Clear Register to hold result
 LOOP LDR R3,[R2],#4 ;Load the number to register
 CMP R3, R0 ;Compare the number
 BLO SKIP ;Skip if number is smaller
 MOV R0, R3 ;Load largest number in result register
 SKIP SUBS R1, R1,#1 ;Decrement Counter
 BNE LOOP ;Check Counter = 0
 STR R0,RESULT ;Store the result
 HERE B HERE
 AREA storage, data, readwrite
 N DCD 0x05
 NOS DCD 05, 10,09, 08, 07
 RESULT DCD 0x0
 END

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Program to find the Negative numbers from series of numbers

 AREA program, CODE, readwrite

 ENTRY
 LDR R1, N ;Load Counter
 LDR R2, =NOS ;Initialize the Pointer
 MOV R0, #0 ;Clear Register to hold result
 LOOP LDR R3,[R2],#4 ;Load the number to register
 ANDS R3,#0x80000000 ; Check for MSB = 1
 ADDEQ R0, R0, #1 ;if MSB=0 then increment
 SKIP SUBS R1, R1,#1 ;Decrement Counter
 BNE LOOP ;Check counter = 0
 STR R0,RESULT ;Store result
 HERE B HERE
 AREA storage, data, readwrite
 N DCD 0x05
 NOS DCD -5,6,-9,8,7
 RESULT DCD 0
 END
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