Design and Verification of AMBA AHB

Perumalla Giridhar Dr Priyanka Choudhury

Department of ECE, Department of ECE,
NIT Agartala NIT, Agartala,
Agartala, India Agartala, India
[email protected] [email protected]

Abstract: The AHB (Advanced High-performance Bus) is range. The bus slave signals back to the active master
a high-performance bus in AMBA (Advanced the success, failure or waiting of the data transfer. Bus
Microcontroller Bus Architecture) family. It is a standard transfer is read/write operation between master and
for intercommunication of modules in a system. AHB slave which may take one or more bus cycles. AHB
standards are defined by ARM and supports the decoder is used to decode the address of each transfer
communication of on-chip memories processors and and provide a select signal for the slave that is involved
interfaces of off-chip external memory. In this paper we in the transfer. A single centralized decoder is required
present, design and perform verification of AHB which in all AHB implementations.
support one master and four slaves. In this work, the
design of the AHB Protocol is developed comprising of the
basic blocks such as Master, Slave, decoder and After designing the AHB supporting one master and
multiplexers. This AMBA-AHB protocol can be used in four slave. We have developed a verification
any application provided the design should be an AHB environment in SV to verify the read/write transactions
compliant. The building blocks of the design master, between the master and slave for randomized address
slaves, decoder and multiplexers are developed in Verilog. and control signals in a given range and constraints so
The verification environment is developed in system that maximum space of the input output combinations
Verilog (SV). QuestaSim (Advanced verification tool from are verified. The intent of functional verification is to
Mentor Graphics) is used to simulate and verify the design make sure that the design is working as intended.
and calculate code and functional coverages. Functional verification is measured using coverage.
There are two coverages in functional verification, they
Keywords- AHB, AMBA-AHB, QuestaSim, ARM are code coverage and functional coverage. Code
I. INTRODUCTION coverage is the amount of code triggered during the
verification. It can help finding dead code and false
Advanced Microcontroller Bus Architecture defines the paths which is not triggered for any given combination
on-chip communication standard for designing high- of the inputs. Functional coverage tells the percentage
performance embedded microcontrollers. Three types of transactions which are successful.
of buses are defined in AHB specification by ARM,
The article is structured as follows. Section II contains
they are Advance High Performance Bus (AHB),
the design of the system. Section III the verification of
Advanced System Bus (ASB) and Advanced Peripheral
the design. Section IV shows the verification results.
Bus (APB). In this paper we limit our discussion to Section V explains the future scope of our system, and
AHB. concludes the article.
An AMBA-based microcontroller contains a high-
II. DESIGN
performance system bus (AMBA AHB or ASB), on-
chip memory, CPU cores, and DMA (Direct Memory A. AMBA AHB master
Access) devices. APB is a secondary bus or peripheral
bus that provide communication between low AMBA AHB master is designed using Finite State
bandwidth devices (peripheral devices). There is a Machines (FSM). It is three states FSM. Address and
bridge between high-performance bus and peripheral control signal information is provided by the master to
bus for translation of signal standards. Figure 1 initiate read/write operation. Since we are considering
represents a generic AMBA-based microcontroller. only single beat transactions in this project. Some of the
signals can neglected. The simplified master interface is
Bus Cycle in the AMBA AHB protocol description is shown in Figure 2. It consist of three states IDLE,
defined from rising edge to rising edge transitions. READ, WRITE Figure 3 shows the state diagram of
AHB master is able to initiate read and write master FSM.
operations by providing an address and control
information. Only one bus master is allowed to actively
use the bus at any one time. AHB slave responds to a
read or write operation within a given address-space

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 Figure 1. Typical AMBA based Micro-controller

Initially, the master fsm will be IDLE state. Depending

on type of transaction and control signals the master B. AMBA AHB slave
goes to either READ state or WRITE state. If it is a
read transaction (HTRANS = 1 and HWRITE =0) the AMBA AHB slave is also designed using Finite State
master fsm goes to READ state. if it is a write Machines (FSM). It is three states FSM. A slave
transaction (HTRANS =1 and HWRITE =1) the master responds to the transactions initiated by the master. The
fsm goes to WRITE state. In READ/WRIE state the slave uses the HSELx select signal from the decoder to
master specifies the address through HADDR and also control when it responds to a bus transfer. Since we are
forwards the control signal to the slave, so that the slave considering only single beat transactions in this project.
understands the type of transaction. In read transaction Some of the signals can neglected. The simplified slave
the master samples the read data from HRDATA signal interface is shown in Figure 4. It consist of three states
only when HREADY signal from slave is high. In write
IDLE, READ, WRITE Figure 6 shows the state
transaction the master extents the availability of the
diagram of master FSM.
address and control signal information until the slave
gives the HREADY signal. Once the HREADY signal
is made high by the slave the master goes back to the
IDLE state.

Figure 2. Master Interface Signals

Figure 4. Simplified Slave Interface

Initially, the slave will be inactive. The slave fsm will

get activated by the HSELx signal. The decoder
component in the bus is responsible for making the
HSELx signal high for the particular slave based on the
address (HADDR). The last two bits of the address
signal (HADDR) represents the slave that
Figure 3. Finite State Machine Diagram for Master

This FSM should be integrated with CPU’s and

processors to make them AHB compatible.

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 Figure 5. Single master AHB system diagram

has to participate in the transaction. The decoder will the address from the master so that the right slave is
decode the last two bits of the address and activates that selected and the multiplexor routes the corresponding
slave with HSELx signal. Once the slave is activated, slave output data back to the master. AHB also supports
based on the control signals (HTRANS and HWRITE) multi-master designs by the use of an interconnect
sent from the master the slave fsm goes to read/write component that provides arbitration and routing signals
state. If it is a read transaction (HTRANS = 1 and from different masters to the appropriate slaves. Figure
HWRITE = 0), the slave will decode the address and 5 shows only the main address and data buses and
sends the data in that address to the master through typical data routing. Not all signals are shown. In our
HRDATA signal and also makes the HREADY signal design we have designed one master four slave system.
high indicating that the data in HRDATA is valid. If it
is a write transaction(HTRANS = 1 and HWRITE = 1) III. VERFICATION
the slave will write the data present in the signal
HWDATA into the address location specified by the In this project Verification Environment is developed
HADDR signal and makes the HREADY signal high using System Verilog language. Verification using
indicating the end of transaction. environment is called as simulation based verification.
Different components of general verification
When master receives data HREADY from slave it environment, depicted in Figure 7 are as follows.
finishes the transaction and makes HRESP high. When
HRESP is made high the slave goes back to IDLE state Packet is an object which carries the values of inputs
from either READ or WRITE state. This FSM should and outputs at a given time. Packet class defines the
be integrated with memory modules like RAM to make type of input output it should carry.
them AHB compatible.
Generator generates the packet with input randomized
to values defined in the constraints and pushes it to the
driver.

Driver gets the packet from generator and drives it into

other environment components as required. Here it
drives into the DUT (Design Under Test) and
Scoreboard simultaneously.

Scoreboard collects the packets from driver and

calculates the expected output. This output is compared
with output of the Design that has to be verified.
Scoreboard decides the success/failure of a transaction
and stores the result in a log file.
Figure 6. Finite State Machine Diagram from Slave
Monitor gets the output signals from the design under
C. Single master with three slaves system verification and converts into packets to send it to the
scoreboard.
Figure 5 depicts an AHB system design with the one
AHB master and three AHB slaves. The bus
interconnects logic consists of one address decoder and
one slave-to-master multiplexor. The decoder monitors

312
 Figure 7. Generic verification environment

Architecture of Verification Environment (Env) with

system included in it is shown in the Figure 8. It has all IV. RESULTS
the components as mentioned earlier. The environment
interacts only with the master. It makes the master Figure 9 shows the simulation result of one master and
generate address and control signals and collects the four slave system. The result shows three consecutive
signals sent from the slave. Since these are only FSM’s read transactions with HADDR as 11. The logic in
which should be integrated with actual on-chip slave 1 gives the HRDATA as 12. Only when
components like CPU’s and memory here we are HREADY signal is high the value 12 is sampled and
integrating master with verification environment and into the master with rd_data signal. To carry out
slave with another logic which can generate data for multiple transactions more than 100 forcing the inputs
read transactions and store data from write transactions. no more helps. So, we develop verification
For example if the address of read transaction is 11 in environment.
decimal it adds one to this value and sends 12 in
decimal as HRDATA signal. This same logic is A. Scoreboard Results (Functional Coverage)
included in the scoreboard so that it can compare that
value with the value sent by the slave. If the values are If all the transactions are successful then functional
same then read transaction is successful. The priority of coverage is 100%. Figure 10 shows a snippet of
the slave requests are processed in first-come, first- scoreboard results saved in a log file.
served basis.
B. Code Coverage

Code coverage is calculated by the Verification Tool

QuestaSim. Figure 11 shows the code coverage of the
design. By improving the test plan and changing the
constraints code coverage values can be increased up to
100%. This is called constraint random based
verification.

Figure 8. Architecture of the verification environment

313
Figure 9. Simulation result of one master and four slave system

Figure 10. Functional coverage results of the design

Figure 11. Code coverage results of the design

314
 V. CONCLUSION [8] IEEE Draft Standard for System Verilog - Unified Hardware
Design,Specification and Verification Language, IEEE P1800/DS,
February2012 pp.1-1304
AMBA AHB protocol defines the communication [9] Soo Yun Hwang, Dong Soo Kang, Hyeong Jun Park, Kyoung Son
standards for high performance embedded systems. In Jhang, “Implementation of a Self-Motivated Arbitration Scheme for
this work we have design and verified the system the Multilayer AHB Busmatrix”, IEEE Transactions on Very Large
Scale Integration (VLSI) Systems ( Volume: 18 , Issue: 5 , May
depending upon the specifications, data transfer that are
2010 )
supported by AMBA bus architecture. Verification of
AHB Protocol for and Single Master - Four Slaves has
been verified by developing the Verification IP using
system Verilog using constraint random based
verification technique. The simulation and verification
result shows that the communication between master
and slave fsm’s using AHB protocol is as intended. All
of the address and data signals are successfully
transferred from master fsm to slave fsm following
AMBA-AHB protocol. There is no loss of address, data
and control signal information. The master fsm should
be integrated with modules in the system which tend to
initiate the transactions and slave fsm should be
integrated with memory modules in the system to make
the system AHB compatible. The Verification
environment developed using tool Questa and it is sure
that developed VIP is also compatible with other
verification tools from Cadence, Synopsys etc.

In the present work we have designed AHB system

which support only one master four slaves. Developing
the system which can support 16 masters and 16 slaves
with burst transactions compatible could be the future
work of this of this project in the design. In verifying
the system, developing VIP (Verification Intellectual
property) using standard methodologies like UVM
(Universal Verification Methodology) rather than using
a generic verification environment would be
appreciable. VIP’s developed in UVM could be
reusable for any design with minimal changes in the
architecture. The verification environment developed in
this work is not reusable for verifying other designs.

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