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DSD Lab 9 Handout

The document describes a lab experiment on implementing a universal shift register. It provides background on shift registers and universal shift registers. It includes Verilog code for a stimulus module and task instructions to instantiate a 4-bit universal shift register counter. It also provides homework to behaviorally model the same register.

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Muhammad Anas
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40 views5 pages

DSD Lab 9 Handout

The document describes a lab experiment on implementing a universal shift register. It provides background on shift registers and universal shift registers. It includes Verilog code for a stimulus module and task instructions to instantiate a 4-bit universal shift register counter. It also provides homework to behaviorally model the same register.

Uploaded by

Muhammad Anas
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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International Islamic University,

Islamabad
Digital System Design LAB

EXPERIMENT # 09: Universal Shift Register

Name of Student:

Roll No.:

Date of Experiment:

Report submitted on:

Marks obtained:

Remarks:

Instructor’s Signature:

Digital System Design Lab (EE-319L) Page 69


Universal Shift Register
1. Objective
This lab exercise is designed to understand the design and then implement Universal Shift
Register on Spartan 3E or Spartan 2 kit.

2. Resources Required
• A Computer
• Xilinx ISE
• Spartan 2 or Spartan 3 board

3. Introduction
A register capable of shifting the binary information held in each cell to its neighboring cell, in a
selected direction is called a shift register. The logical configuration of a shift register consists of
a chain of flip-flops in cascade with the output of one flip-flop connected to the input of the next
flip-flop. All flip-flops receive common clock pulses, which activate the shift of data from one
stage to the next. The simplest possible shift register is one that uses only flip-flops, as shown in
the following figure.

4-bit Shift Register

3.1 Universal Shift Register


If the flip‐flop outputs of a shift register are accessible, then information entered serially by
shifting can be taken out in parallel from the outputs of the flip‐flops. If a parallel load capability
is added to a shift register, then data entered in parallel can be taken out in serial fashion by shifting
the data stored in the register.
Some shift registers provide the necessary input and output terminals for parallel transfer. They
may also have both shift‐right and shift‐left capabilities. The most general shift register has the
following capabilities:

1. A clear control to clear the register to 0.


2. A clock input to synchronize the operations.
3. A shift‐right control to enable the shift‐right operation and the serial input and output
lines associated with the shift right.
4. A shift‐left control to enable the shift‐left operation and the serial input and output
lines associated with the shift left.
5. A parallel‐load control to enable a parallel transfer and the n input lines associated with
the parallel transfer.
6. n parallel output lines.

Digital System Design Lab (EE-319L) Page 70


7. A control state that leaves the information in the register unchanged in response to the
clock. Other shift registers may have only some of the preceding functions, with at least
one shift operation.

A register capable of shifting in one direction only is a unidirectional shift register. One that can
shift in both directions is a bidirectional shift register. If the register has both shifts and parallel‐
load capabilities, it is referred to as a universal shift register.

4-Bit Universal Shift Register

4. Verilog Codes (to be utilized in this lab)

Stimulus:

module Stimulus;
wire [3:0] A_out;
reg clk, clear, sleft, sright;
reg [1:0] mux_sel;
reg [3:0] I_in;

//Module Instantiation
universal_register u0(A_out, I_in, clk, clear, mux_sel, sleft, sright);
//Clock Generator (Must for Sequential circuits)
initial
begin
Clk=1'b0;
forever
#1 Clk = ~Clk;
end

Digital System Design Lab (EE-319L) Page 71


//Values checking part
initial
begin mux_sel=2'b00; I_in=4'b1111; clear=1; sleft=0; sright=1;
#5 mux_sel=2'b00; I_in=4'b1111; clear=0; sleft=1; sright=1;
#5 mux_sel=2'b10; I_in=4'b1111; clear=0; sleft=1; sright=1;
#5 mux_sel=2'b11; I_in=4'b1111; clear=0; sleft=1; sright=1;
#5 mux_sel=2'b01; I_in=4'b1111; clear=0; sleft=1; sright=1;
#5 mux_sel=2'b11; I_in=4'b1111; clear=0; sleft=1; sright=1;
#10 $stop;
#10 $finish;
end
endmodule

5. Lab Task
Implement a 4-bit Universal Shift Register Counter using instantiation (as given in the
figure) that implements the following table. Utilize the Stimulus given in code section.

6. Home Work
Implement a 4-bit Universal Shift Register Counter using Behavioral modeling as given in
the following figure. You can utilize the same Stimulus.

Digital System Design Lab (EE-319L) Page 72


International Islamic University, Islamabad
Digital System Design Lab

LAB WORKSHEET (Lab # 9)

Q.1 What is the purpose of Shift register? Explain briefly.


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Q.2 What is the difference between Universal and normal Shift registers?
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Q.3 What operator is used to implement shift in Behavioral Modeling?


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Q.4 What is the difference between arithmetic shift and binary shift?
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Digital System Design Lab (EE-319L)

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