DISCRETE SEMICONDUCTORS

DATA SHEET

BF1212; BF1212R; BF1212WR

N-channel dual-gate MOS-FETs
Product specification 2003 Nov 14
NXP Semiconductors Product specification

BF1212; BF1212R;
N-channel dual-gate MOS-FETs
BF1212WR

FEATURES PINNING
 Short channel transistor with high forward transfer PIN DESCRIPTION
admittance to input capacitance ratio
1 source
 Low noise gain controlled amplifier
2 drain
 Excellent low frequency noise performance
3 gate 2
 Partly internal self-biasing circuit to ensure good
4 gate 1
cross-modulation performance during AGC and good
DC stabilization.

APPLICATIONS 4
handbook, 2 columns 3

 Gain controlled low noise VHF and UHF amplifiers for

5 V digital and analog television tuner applications.

1 2
DESCRIPTION
Top view MSB014
Enhancement type N-channel field-effect transistor with
source and substrate interconnected. Integrated diodes
between gates and source protect against excessive input BF1212; marking code: LGp
voltage surges. The BF1212, BF1212R and BF1212WR
are encapsulated in the SOT143B, SOT143R and Fig.1 Simplified outline (SOT143B).
SOT343R plastic packages respectively.

3
handbook, 2 columns 4 handbook, halfpage 3 4

2 1
2 1

Top view MSB035 Top view MSB842

BF1212R; marking code: LKp BF1212WR; marking code: ML

Fig.2 Simplified outline (SOT143R). Fig.3 Simplified outline (SOT343R).

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

VDS drain-source voltage   6 V
ID drain current   30 mA
Ptot total power dissipation   180 mW
yfs forward transfer admittance 28 33 43 mS
Cig1-ss input capacitance at gate 1  1.7 2.2 pF
Crss reverse transfer capacitance f = 1 MHz  15 30 fF
F noise figure f = 800 MHz  1.1 1.8 dB
Xmod cross-modulation input level for k = 1 % at 100 104  dBV
40 dB AGC
Tj junction temperature   150 C

2003 Nov 14 2
NXP Semiconductors Product specification

N-channel dual-gate MOS-FETs BF1212; BF1212R; BF1212WR

CAUTION
This product is supplied in anti-static packing to prevent damage caused by electrostatic discharge during transport
and handling.

ORDERING INFORMATION

PACKAGE
TYPE NUMBER
NAME DESCRIPTION VERSION
BF1212  plastic surface mounted package; 4 leads SOT143B
BF1212R  plastic surface mounted package; reverse pinning; 4 leads SOT143R
BF1212WR  plastic surface mounted package; reverse pinning; 4 leads SOT343R

LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134).
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VDS drain-source voltage  6 V
ID drain current (DC)  30 mA
IG1 gate 1 current  10 mA
IG2 gate 2 current  10 mA
Ptot total power dissipation
BF1212; BF1212R Ts  116 C; note 1  180 mW
BF1212WR Ts  122 C; note 1  180 mW
Tstg storage temperature 65 +150 C
Tj junction temperature  150 C

Note
1. Ts is the temperature of the soldering point of the source lead.

THERMAL CHARACTERISTICS

SYMBOL PARAMETER VALUE UNIT

Rth j-s thermal resistance from junction to soldering point
BF1212; BF1212R 185 K/W
BF1212WR 155 K/W

2003 Nov 14 3
NXP Semiconductors Product specification

N-channel dual-gate MOS-FETs BF1212; BF1212R; BF1212WR

MDB828
250
handbook, halfpage
Ptot
(mW)
200

150 (2) (1)

100

50

0
0 50 100 150 200
Ts (°C)

(1) BF1212WR.
(2) BF1212; BF1212R.

Fig.4 Power derating curve.

STATIC CHARACTERISTICS
Tj = 25 C unless otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V(BR)DSS drain-source breakdown voltage VG1-S = VG2-S = 0 V; ID = 10 A 6  V
V(BR)G1-SS gate 1-source breakdown voltage VG2-S = VDS = 0 V; IG1-S = 10 mA 6 10 V
V(BR)G2-SS gate 2-source breakdown voltage VG1-S = VDS = 0 V; IG2-S = 10 mA 6 10 V
V(F)S-G1 forward source-gate 1 voltage VG2-S = VDS = 0 V; IS-G1 = 10 mA 0.5 1.5 V
V(F)S-G2 forward source-gate 2 voltage VG1-S = VDS = 0 V; IS-G2 = 10 mA 0.5 1.5 V
VG1-S(th) gate 1-source threshold voltage VG2-S = 4 V; VDS = 5 V; ID = 100 A 0.3 1.0 V
VG2-S(th) gate 2-source threshold voltage VG1-S = 5 V; VDS = 5 V; ID = 100 A 0.35 1.0 V
IDSX drain-source current VG2-S = 4 V; VDS = 5 V; RG1 = 150 k; 8 16 mA
note 1
IG1-S gate 1 cut-off current VG2-S = VDS = 0 V; VG1-S = 5 V  50 nA
IG2-S gate 2 cut-off current VG1-S = VDS = 0 V; VG2-S = 4 V  20 nA

Note
1. RG1 connects G1 to VGG = 5 V.

2003 Nov 14 4
NXP Semiconductors Product specification

N-channel dual-gate MOS-FETs BF1212; BF1212R; BF1212WR

DYNAMIC CHARACTERISTICS
Common source; Tamb = 25 C; VG2-S = 4 V; VDS = 5 V; ID = 12 mA; unless otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

yfs forward transfer admittance pulsed; Tj = 25 C 28 33 43 mS
Cig1-ss input capacitance at gate 1 f = 1 MHz  1.7 2.2 pF
Cig2-ss input capacitance at gate 2 f = 1 MHz  1.1  pF
Coss output capacitance f = 1 MHz  0.9  pF
Crss reverse transfer capacitance f = 1 MHz  15 30 fF
F noise figure f = 11 MHz; GS = 20 mS; BS = 0  4  dB
f = 400 MHz; YS = YS (opt)  0.9 1.6 dB
f = 800 MHz; YS = YS (opt)  1.1 1.8 dB
Gtr power gain f = 200 MHz; GS = 2 mS; BS = BS (opt);  35  dB
GL = 0.5 mS; BL = BL (opt)
f = 400 MHz; GS = 2 mS; BS = BS (opt);  30  dB
GL = 1 mS; BL = BL (opt)
f = 800 MHz; GS = 3.3 mS; BS = BS (opt);  25  dB
GL = 1 mS; BL = BL (opt)
Xmod cross-modulation input level for k = 1%; fw = 50 MHz;
funw = 60 MHz; note 1
at 0 dB AGC 90   dBV
at 10 dB AGC  89  dBV
at 40 dB AGC 100 104  dBV

Note
1. Measured in test circuit Fig.21.

2003 Nov 14 5
NXP Semiconductors Product specification

N-channel dual-gate MOS-FETs BF1212; BF1212R; BF1212WR

MLE233 MLE234
30 32
handbook, halfpage (1) handbook, halfpage (1)
(4) ID
ID (2)
(2)
(mA)
(mA) (3)
(5)
24 (3)
20
(4)

16 (5)
(6)
(6)
10
(7)
8
(8)
(7)
(9)

0 0
0 0.5 1 1.5 2 2.5 0 2 4 6
VDS (V)
VG1-S (V)

(1) VG2-S = 4 V. (5) VG2-S = 2 V. VDS = 5 V. (1) VG1-S = 1.6 V. (6) VG1-S = 1.1 V. VG2-S = 4 V.
(2) VG2-S = 3.5 V. (6) VG2-S = 1.5 V. Tj = 25 C. (2) VG1-S = 1.5 V. (7) VG1-S = 1.0 V. Tj = 25 C.
(3) VG2-S = 3 V. (7) VG2-S = 1 V. (3) VG1-S = 1.4 V. (8) VG1-S = 0.9 V.
(4) VG2-S = 2.5 V. (4) VG1-S = 1.3 V. (9) VG1-S = 0.8 V.
(5) VG1-S = 1.2 V.

Fig.5 Transfer characteristics; typical values. Fig.6 Output characteristics; typical values.

MLE235 MLE236
100 40
handbook, halfpage (1) (2) handbook, halfpage (3) (2) (1)
IG1
yfs
(μA) (3)
(mS) (4)
80
30
(4)
(5)

60

20
(5)
40
(6)

10
20 (6)
(7)

(7)
0 0
0 0.5 1 1.5 2 0 4 8 12 16 20
VG1-S (V) ID (mA)

(1) VG2-S = 4 V. (5) VG2-S = 2 V. VDS = 5 V. (1) VG2-S = 4 V. (5) VG2-S = 2 V. VDS = 5 V.
(2) VG2-S = 3.5 V. (6) VG2-S = 1.5 V. Tj = 25 C. (2) VG2-S = 3.5 V. (6) VG2-S = 1.5 V. Tj = 25 C.
(3) VG2-S = 3 V. (7) VG2-S = 1 V. (3) VG2-S = 3 V. (7) VG2-S = 1 V.
(4) VG2-S = 2.5 V. (4) VG2-S = 2.5 V.

Fig.7 Gate 1 current as a function of gate 1 Fig.8 Forward transfer admittance as a function
voltage; typical values. of drain current; typical values.

2003 Nov 14 6
NXP Semiconductors Product specification

N-channel dual-gate MOS-FETs BF1212; BF1212R; BF1212WR

MLE237 MLE238
24 16
handbook, halfpage handbook, halfpage
ID
ID
(mA)
(mA)
12
16

0 0
0 10 20 30 40 50 0 1 2 3 4 5
IG1 (μA) VGG (V)

VDS = 5 V; VG2-S = 4 V. VDS = 5 V; VG2-S = 4 V; Tj = 25 C.

Tj = 25 C. RG1 = 150 k (connected to VGG); see Fig.21.

Fig.9 Drain current as a function of gate 1 current; Fig.10 Drain current as a function of gate 1 supply
typical values. voltage; typical values.

MLE239 MLE240
20 (1) (2) 16
handbook, halfpage handbook, halfpage
ID
(3)
ID
(mA)
(mA) (1)
16
(4) (2)
12
(3)
(5)
(4)
12 (6) (5)
(7)
(8) 8
8

4
4

0 0
0 2 4 6 0 2 4 6
VGG = VDS (V) VG2-S (V)

(1) RG1 = 47 k. (5) RG1 = 120 k. VG2-S = 4 V; Tj = 25 C. (1) VGG = 5 V. (4) VGG = 3.5 V. VDS = 5 V; Tj = 25 C.
(2) RG1 = 56 k. (6) RG1 = 150 k. RG1 connected to VGG; (2) VGG = 4.5 V. (5) VGG = 3 V. RG1 = 150 k
(3) RG1 = 82 k. (7) RG1 = 180 k. see Fig.21. (3) VGG = 4 V. (connected to VGG);
see Fig.21.
(4) RG1 = 100 k. (8) RG1 = 220 k.

Fig.11 Drain current as a function of gate 1 and Fig.12 Drain current as a function of gate 2
drain supply voltage; typical values. voltage; typical values.

2003 Nov 14 7
NXP Semiconductors Product specification

N-channel dual-gate MOS-FETs BF1212; BF1212R; BF1212WR

MLE241 MLE242
30 0
handbook, halfpage handbook, halfpage

IG1 gain
reduction
(μA) (1)
(dB)
(2)
20 −20
(3)

(4)

(5)

10 −40

0 −60
0 2 4 6 0 1 2 3 4
VG2-S (V) VAGC (V)

(1) VGG = 5 V. (4) VGG = 3.5 V. VDS = 5 V; Tj = 25 C. VDS = 5 V; VGG = 5 V; RG1 = 150 k(connected to VGG);
(2) VGG = 4.5 V. (5) VGG = 3 V. RG1 = 150 k see Fig.21; f = 50 MHz; Tamb = 25 C.
(3) VGG = 4 V. (connected to VGG);
see Fig.21.

Fig.13 Gate 1 current as a function of gate 2 Fig.14 Typical gain reduction as a function of AGC
voltage; typical values. voltage.

MLE243 MLE244
120 16
handbook, halfpage handbook, halfpage
Vunw ID
(dBμV) (mA)
110 12

100 8

90 4

80 0
0 10 20 30 40 50 0 10 20 30 40 50
gain reduction (dB) gain reduction (dB)

VDS = 5 V; VGG = 5 V; RG1 = 150 k (connected to VGG); VDS = 5 V; VGG = 5 V; RG1 = 150 k (connected to VGG);
see Fig.21; f= 50 MHz; funw = 60 MHz; Tamb = 25 C. see Fig.21; f= 50 MHz; Tamb = 25 C.

Fig.15 Unwanted voltage for 1% cross-modulation

as a function of gain reduction; typical Fig.16 Drain current as a function of gain
values. reduction; typical values.

2003 Nov 14 8
NXP Semiconductors Product specification

N-channel dual-gate MOS-FETs BF1212; BF1212R; BF1212WR

MLE245 MLE246
102 103 −103
handbook, halfpage handbook, halfpage

yis yrs ϕrs

(mS) (μS) (deg)

ϕrs
10 102 −102

bis
yrs
gis
1 10 −10

10−1 1 −1
10 102 103 10 102 103
f (MHz) f (MHz)

VDS = 5 V; VG2 = 4 V. VDS = 5 V; VG2 = 4 V.

ID = 12 mA; Tamb = 25 C. ID = 12 mA; Tamb = 25 C.

Fig.17 Input admittance as a function of frequency; Fig.18 Reverse transfer admittance and phase as
typical values. functions of frequency; typical values.

MLE247 MLE248
102 −102 10
handbook, halfpage handbook, halfpage

yfs yfs ϕfs yos

(mS) (deg) (mS)

bos
10 −10 1

ϕfs

gos
1 −1 10−1
10 102 103 10 102 103
f (MHz) f (MHz)

VDS = 5 V; VG2 = 4 V. VDS = 5 V; VG2 = 4 V.

ID = 12 mA; Tamb = 25 C. ID = 12 mA; Tamb = 25 C.

Fig.19 Forward transfer admittance and phase as Fig.20 Output admittance as a function of
functions of frequency; typical values. frequency; typical values.

2003 Nov 14 9
NXP Semiconductors Product specification

N-channel dual-gate MOS-FETs BF1212; BF1212R; BF1212WR

handbook, full pagewidth VAGC

R1
10 kΩ
C1

4.7 nF C3

4.7 nF

L1 RL
C2
DUT ≈ 2.2 μH 50 Ω
RGEN 4.7 nF C4
R2
RG1
50 Ω 50 Ω
4.7 nF
VI VGG VDS
MGS315

Fig.21 Cross-modulation test set-up.

Table 1 Scattering parameters: VDS = 5 V; VG2-S = 4 V; ID = 12 mA; Tamb = 25 C

s11 s21 s12 s22

f
(MHz) MAGNITUDE ANGLE MAGNITUDE ANGLE MAGNITUDE ANGLE MAGNITUDE ANGLE
(ratio) (deg) (ratio) (deg) (ratio) (deg) (ratio) (deg)
50 0.990 3.39 3.288 176.5 0.0005 86.9 0.990 1.66
100 0.988 6.76 3.280 173.0 0.0011 85.6 0.990 3.30
200 0.983 13.40 3.261 166.1 0.0021 81.2 0.991 6.62
300 0.974 19.86 3.218 159.0 0.0030 77.5 0.991 9.92
400 0.969 26.46 3.205 152.6 0.0039 74.6 0.994 13.30
500 0.958 32.73 3.141 145.9 0.0045 72.4 0.994 16.56
600 0.947 38.83 3.086 139.5 0.0049 70.9 0.993 19.77
700 0.936 44.75 3.017 133.1 0.0051 69.5 0.991 22.78
800 0.924 50.51 2.949 126.9 0.0051 69.9 0.981 25.77
900 0.910 56.18 2.870 120.5 0.0049 69.8 0.984 28.72
1000 0.896 61.64 2.785 114.7 0.0045 72.7 0.980 31.77

Table 2 Noise data: VDS = 5 V; VG2-S = 4 V; ID = 12 mA; Tamb = 25 C

f Fmin opt Rn
(MHz) (dB) (ratio) (deg) ()

400 0.9 0.695 13.87 28.5

800 1.1 0.634 30.30 32.85

2003 Nov 14 10
NXP Semiconductors Product specification

N-channel dual-gate MOS-FETs BF1212; BF1212R; BF1212WR

PACKAGE OUTLINES
Plastic surface-mounted package; 4 leads SOT143B

D B E A X

y
v M A HE

e
bp w M B

4 3

A1

c
1 2
Lp
b1
e1 detail X

0 1 2 mm

scale

DIMENSIONS (mm are the original dimensions)

A1
UNIT A bp b1 c D E e e1 HE Lp Q v w y
max
1.1 0.1 0.48 0.88 0.15 3.0 1.4 2.5 0.45 0.55
mm 1.9 1.7 0.2 0.1 0.1
0.9 0.38 0.78 0.09 2.8 1.2 2.1 0.15 0.45

OUTLINE REFERENCES EUROPEAN

ISSUE DATE
VERSION IEC JEDEC JEITA PROJECTION

04-11-16
SOT143B
06-03-16

2003 Nov 14 11
NXP Semiconductors Product specification

N-channel dual-gate MOS-FETs BF1212; BF1212R; BF1212WR

Plastic surface-mounted package; reverse pinning; 4 leads SOT143R

D B E A X

y
v M A HE

e
bp w M B

3 4
Q

A1
c
2 1
Lp
b1
e1 detail X

0 1 2 mm

scale

DIMENSIONS (mm are the original dimensions)

A1
UNIT A bp b1 c D E e e1 HE Lp Q v w y
max
1.1 0.1 0.48 0.88 0.15 3.0 1.4 2.5 0.55 0.45
mm 1.9 1.7 0.2 0.1 0.1
0.9 0.38 0.78 0.09 2.8 1.2 2.1 0.25 0.25

OUTLINE REFERENCES EUROPEAN

ISSUE DATE
VERSION IEC JEDEC JEITA PROJECTION

04-11-16
SOT143R SC-61AA
06-03-16

2003 Nov 14 12
NXP Semiconductors Product specification

N-channel dual-gate MOS-FETs BF1212; BF1212R; BF1212WR

Plastic surface-mounted package; reverse pinning; 4 leads SOT343R

D B E A X

y HE v M A

3 4

A1

c
2 1

w M B bp b1 Lp

e1
detail X

0 1 2 mm

scale

DIMENSIONS (mm are the original dimensions)

A1
UNIT A bp b1 c D E e e1 HE Lp Q v w y
max
1.1 0.4 0.7 0.25 2.2 1.35 2.2 0.45 0.23
mm 0.1 1.3 1.15 0.2 0.2 0.1
0.8 0.3 0.5 0.10 1.8 1.15 2.0 0.15 0.13

OUTLINE REFERENCES EUROPEAN

ISSUE DATE
VERSION IEC JEDEC EIAJ PROJECTION

97-05-21
SOT343R
06-03-16

2003 Nov 14 13
NXP Semiconductors Product specification

N-channel dual-gate MOS-FETs BF1212; BF1212R; BF1212WR

DATA SHEET STATUS

DOCUMENT PRODUCT
DEFINITION
STATUS(1) STATUS(2)
Objective data sheet Development This document contains data from the objective specification for product
development.
Preliminary data sheet Qualification This document contains data from the preliminary specification.
Product data sheet Production This document contains the product specification.

Notes
1. Please consult the most recently issued document before initiating or completing a design.
2. The product status of device(s) described in this document may have changed since this document was published
and may differ in case of multiple devices. The latest product status information is available on the Internet at
URL http://www.nxp.com.

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2003 Nov 14 14
NXP Semiconductors Product specification

N-channel dual-gate MOS-FETs BF1212; BF1212R; BF1212WR

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2003 Nov 14 15
 NXP Semiconductors
provides High Performance Mixed Signal and Standard Product
solutions that leverage its leading RF, Analog, Power Management,
Interface, Security and Digital Processing expertise

Customer notification

This data sheet was changed to reflect the new company name NXP Semiconductors, including new legal
definitions and disclaimers. No changes were made to the technical content, except for package outline
drawings which were updated to the latest version.

Contact information

For additional information please visit: http://www.nxp.com

For sales offices addresses send e-mail to: [email protected]

© NXP B.V. 2010

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Printed in The Netherlands R77/02/pp16 Date of release: 2003 Nov 14