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7.4 EEPROM Data Memory: Section 27. "Memory Programming" On Page 241

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7.4 EEPROM Data Memory: Section 27. "Memory Programming" On Page 241

no2

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salar
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7.

4 EEPROM Data Memory


The Atmel® ATmega328P contains 1Kbyte of data EEPROM memory. It is organized as a separate data space, in which
single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access
between the EEPROM and the CPU is described in the following, specifying the EEPROM address registers, the EEPROM
data register, and the EEPROM control register.
Section 27. “Memory Programming” on page 241 contains a detailed description on EEPROM programming in SPI or
parallel programming mode.

7.4.1 EEPROM Read/Write Access


The EEPROM access registers are accessible in the I/O space.
The write access time for the EEPROM is given in Table 7-2 on page 22. A self-timing function, however, lets the user
software detect when the next byte can be written. If the user code contains instructions that write the EEPROM, some
precautions must be taken. In heavily filtered power supplies, VCC is likely to rise or fall slowly on power-up/down. This
causes the device for some period of time to run at a voltage lower than specified as minimum for the clock frequency used.
See Section 7.4.2 “Preventing EEPROM Corruption” on page 19 for details on how to avoid problems in these situations.
In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to the description of the
EEPROM control register for details on this.
When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is executed. When the
EEPROM is written, the CPU is halted for two clock cycles before the next instruction is executed.

7.4.2 Preventing EEPROM Corruption


During periods of low VCC, the EEPROM data can be corrupted because the supply voltage is too low for the CPU and the
EEPROM to operate properly. These issues are the same as for board level systems using EEPROM, and the same design
solutions should be applied.
An EEPROM data corruption can be caused by two situations when the voltage is too low. First, a regular write sequence to
the EEPROM requires a minimum voltage to operate correctly. Secondly, the CPU itself can execute instructions incorrectly,
if the supply voltage is too low.
EEPROM data corruption can easily be avoided by following this design recommendation:
Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can be done by enabling the
internal brown-out detector (BOD). If the detection level of the internal BOD does not match the needed detection level, an
external low VCC reset protection circuit can be used. If a reset occurs while a write operation is in progress, the write
operation will be completed provided that the power supply voltage is sufficient.

7.5 I/O Memory


The I/O space definition of the ATmega328P is shown in Section “” on page 275.
All ATmega328P I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD
and ST/STS/STD instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O
registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these
registers, the value of single bits can be checked by using the SBIS and SBIC instructions. Refer to the instruction set
section for more details. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used.
When addressing I/O registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The
ATmega328P is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved
in opcode for the IN and OUT instructions. For the extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and
LD/LDS/LDD instructions can be used.
For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses
should never be written.
Some of the status flags are cleared by writing a logical one to them. Note that, unlike most other AVR®, the CBI and SBI
instructions will only operate on the specified bit, and can therefore be used on registers containing such status flags. The
CBI and SBI instructions work with registers 0x00 to 0x1F only.
The I/O and peripherals control registers are explained in later sections.

ATmega328P [DATASHEET] 19
7810D–AVR–01/15

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