Arithmetic for Computers

CSE 212
KRISHNA K NAGAR

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 Introduction

 Computer words composed of bits

 Binary representation of integers

 What about real numbers?

 What happens when operation creates a bigger
number than can be represented?
 How multiplication and division are performed in
hardware?

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 Computer Arithmetic

 Operations on integers
 Addition and subtraction

 Multiplication and division

 Dealing with overflow

 Floating-point real numbers

 Representation and operations

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 Integer Addition and Subtraction

 Example: 7 + 6

 Example: 7 – 6 = 7 + (-6)

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 Overflow

 Overflow if result out of range

Operation Operand A Operand B Result

A+B Positive Positive Negative

A+B Negative Negative Positive

A-B Positive Negative Negative

A-B Negative Positive Positive

 Dealing with Overflow

 Some languages ignore: addu, addi, subu
 Some languages invoke exception handlers

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 Multiplication

 Maximum length of product is sum of lengths of operands

(m+n)
multiplicand
1000
multiplier
× 1001
-------
1000
0000
0000
1000
-------
product
1001000
 Shift and add

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Algorithm and Hardware

• 64 bit product register, 64 bit MD register

• 96 cycles required for 32 bit operands
• Seems expensive !!

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 Example

Step Multiplier Multiplicand Product itr

Initial Vals 0011 0000 0010 0000 0000 0
Prod=Prod+MD 0011 0000 0010 0000 0010 1
SLL MD 0011 0000 0100 0000 0010
SRL MR 0001 0000 0100 0000 0010
Prod=Prod+MD 0001 0000 0100 0000 0110 2
SLL MD 0001 0000 1000 0000 0110
SRL MR 0000 0000 1000 0000 0110
No Op 0000 0000 1000 0000 0110 3
SLL MD 0000 0001 0000 0000 0110
SLL MR 0000 0001 0000 0000 0110
No Op 0000 0001 0000 0000 0110 4
SLL MD 0000 0010 0000 0000 0110
SRL MD 0000 0010 0000 0000 0110

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Optimization

Catch????
Product register should actually be 65 bits.

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 Example

multiplicand register product register next action itr

(MR) (PR)
1001 0000 0101 LSB of PR is 1, so 1
PR[7:4]=PR[7:4]+MR

1001 1001 0101 shift PR 1

1001 0100 1010 LSB of PR is 0, so shift 2

1001 0010 0101 LSB of PR is 1, so 3

PR[7:4]=PR[7:4]+MR

1001 1011 0101 shift PR 3

1001 0101 1010 LSB of PR is 0, so shift 4

1001 0010 1101 PR is 45, done! X

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 Faster Multiplication

 Binary adder tree network

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 Division

 Dividend = Quotient x Divisor + Remainder

quotient
 Divide by 0 yeilds NAN
dividend
1001  Long division
1000 1001010
 If divisor ≤ dividend bits
-1000
divisor  1 bit in quotient, subtract
10
101  Otherwise
 0 bit in quotient, bring down next
1010
dividend bit
-1000
10  Signed division
remainder
 Divide using absolute values
 Adjust sign of quotient and remainder as
n-bit operands yield n-bit required
quotient and remainder

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Algorithm and Hardware

Initially divisor
in left half

Initially dividend

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 Step Quotient Divisor Remainder itr

Initial vals 0000 0010 0000 0000 0111 0

Rem = Rem –Div 0000 0010 0000 1110 0111 1
Rem < 0 : +Div, sll Q, Q0 = 0 0000 0010 0000 0000 0111
srl Div 0000 0001 0000 0000 0111
Rem = Rem –Div 0000 0001 0000 1111 0111 2
Rem < 0 : +Div, sll Q, Q0 = 0 0000 0001 0000 0000 0111
srl Div 0000 0000 1000 0000 0111
Rem = Rem –Div 0000 0000 1000 1111 1111 3
Rem < 0 : +Div, sll Q, Q0 = 0 0000 0000 1000 0000 0111
srl Div 0000 0000 0100 0000 0111
Rem = Rem –Div 0000 0000 0100 0000 0011 4
Rem >= 0 : sll Q, Q0 = 1 0001 0000 0100 0000 0011
srl Div 0001 0000 0010 0000 0011
Rem = Rem –Div 0001 0000 0010 0000 0001 5
Rem >= 0 : sll Q, Q0 = 1 0011 0000 0010 0000 0001
srl Div 0011 0000 0001 0000 0001
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Optimization

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 Example

divisor register (DR) remainder register (RR) next action Itr

0100 0000 1011 shift RR left 1 bit 0
0100 0001 0110 RR[7:4]=RR[7:4]-DR 1
0100 1101 0110 RR<0, so RR[7:4]=RR[7:4]+DR 1
0100 0001 0110 shift RR to left, shift in 0 1
0100 0010 1100 RR[7:4]=RR[7:4]-DR 2
0100 1110 1100 RR<0, so RR[7:4]=RR[7:4]+DR 2
0100 0010 1100 shift RR to left, shift in 0 2
0100 0101 1000 RR[7:4]=RR[7:4]-DR 3
0100 0001 1000 RR>=0, so shift RR to left, shift in 1 3
0100 0011 0001 RR[7:4]=RR[7:4]-DR 4
0100 1111 0001 RR<0, so RR[7:4]=RR[7:4]+DR 4
0100 0011 0001 shift RR to left, shift in 0 4
0100 0110 0010 shift RR[7:4] to right
0100 0011 0010 done, quotient=2, remainder=3

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 Multiplication and Division in MIPS

 MIPS registers 32 bits- need to handle more bits

 Special registers required: Lo and Hi
 mfhi $t0
 mflo $t1
 mult $t3, $t4
 multiply 32-bit quantities in $t3 and $t4, and store 64-bit
result in special registers Lo and Hi: (Hi,Lo) = $t3 * $t4
 div $t5,$t6
 Lo = $t5 / $t6 (integer quotient)

 Hi = $t5 mod $t6 (remainder)

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 To Do

 Prepare for exam.

 Project

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