C. L.

Chen
M. Y. Hsiao

Error-Correcting Codes for Semiconductor Memory

Applications: A State-of-the-Art Review

This paper presents a state-of-the-art review of error-correcting codes for computer semiconductor memory applications. The
construction of four classes of error-correcting codes appropriate for semiconductor memory designs is described, and for each class
of codes the number of check bits required for commonly used data lengths is provided. The implementation aspects of error
correction and error detection are also discussed, and certain algorithms useful in extending the error-correcting capability for the
correction of soft errors such as a-particle-induced errors are examined in some detail.

Introduction
In recent years error-correcting codes (ECCs) have been used have been widely implemented by IBM and the computer
increasingly to enhance the system reliabihty and the data industry worldwide [7-10]. Examples of systems which incor-
integrity of computer semiconductor memory subsystems. As porate these codes are the IBM 158, 168, 303X, 308X, and
the trend in semiconductor memory design continues toward 4300 series, Cray I, Tandem, etc. There are also various
higher chip density and larger storage capacity, ECCs are standard part numbers of these codes offered by many semi-
becoming a more cost-effective means of maintaining a high conductor manufacturers [11] (for example, the AM2960 and
level of system reliability [1-4]. AMZ8160 of Advanced Micro Devices, the MC68540 of
Motorola, the MB1412A of Fujitsu, and the SN54/74 LS630,
A memory system can be made fauh tolerant with the LS631 of Texas Instruments).
application of an error-correcting code; i.e., the mean time
between "failures" of a properly designed memory system can The number of errors generated in the failure of a memory
be significantly increased with ECC. In this context, a system chip is largely dependent on the chip failure type. For example,
"fails" only when the errors exceed the error-correcting capa- a cell failure may cause one error, while a line failure or a
bility of the code. Also, in order to optimize data integrity, total chip failure in general causes more than one error. For
the ECC should have the capability of detecting the most ECC applications, the memory array chips are usually orga-
likely of the errors that are uncorrectable. nized so that the errors generated in a chip failure can be
corrected by the ECC. In the case of SEC-DED codes, the
Error-correcting codes used in early computer memory one-bit-per-chip organization is the most effective design. In
systems were of the class oi single-error-correcting wad double- this organization, each bit of a codeword is stored in a different
error-detecting (SEC-DED) codes invented by R. W. Ham- chip; thus, any type of failure in a chip can corrupt, at most,
ming [5]. A SEC-DED code is capable of correcting one error one bit of the codeword. As long as the errors do not line up
and detecting two errors in a codeword. The double-error- in the same codeword, multiple errors in the memory are
detecting capability serves to guard against data loss. In 1970, correctable.
a new class of SEC-DED codes called odd-weight-column
codes was published by Hsiao [6]. With the same coding Memory array modules are generally packaged on printed-
efficiency, the odd-weight-column codes provide improve- circuit cards with current semiconductor memory technology,
ments over the Hamming codes in speed, cost and reliability and usually a group of bits from the same card form a portion
of the decoding logic. As a result, odd-weight-column codes of an ECC codeword, as illustrated in Figure 1. With this

® Copyright 1984 by International Business Machines Corporation. Copying in printed form for private use is permitted without payment of
royalty provided that (1) each reproduction is done without alteration and (2) the Journal reference and IBM copyright notice are included on the
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124 computer-based and other information-service systems. Permission to republish any other portion of this paper must be obtained from the Editor.

C. L. CHEN AND M, Y. HSIAO IBM J. RES. DEVELOP. • VOL. 28 • NO. 2 • MARCH 1984
multiple-bit-per-card type of organi2ation, a failure at the Card 1 • • • Card «

nnnn nnnn
card-support-circuit level would result in a byte error, where Chip

nnnn
the size of the byte is the number of bits feeding from the card
to a codeword. In this type of configuration, it is important
for data integrity that the ECC be able to detect byte errors
• nna
* •
[12], A SEC-DED code is in general not capable of detecting • •
all single-byte errors. However, a class of SEC-DED codes • • • • •
capable of detecting all single-byte errors can be constructed
[13, 14]. These are called single-error-correcting doubk-error- nnnn nnnn
detecting single-byte-error-delecting (SEC-DED-SBD) codes.
ECC codeword
There are certain design applications where the memory
array cannot be organized in one-bit-per-chip fashion because Figure 1 A 4-bit-per-card memory array.
of cost or other reasons such as system granularity or power
restrictions. As chip density increases, it becomes more diffi-
cult to design a one-bit-per-chip memory system. For a mul-
tiple-bit-per-chip type of memory organization, a single-byte- Binary linear block codes
error-correcting double-byte-error-detecting (SBC-DBD) code A binary (n.k) linear block code is a A-dimensional subspace
[15-20] would be more effective in error correction and error of a binary «-dimensional vector space [8,15, 16]. An n-bit
detection. codevvord of the code contains k data bits and r= n- k check
bits. An r X « parity check matrix H is used to describe the
System reliability generally tends to decrease as the capacity code. Let V = (t'l, x'2, • • • , i'«) be an «-bit vector. Then V is a
of a memory system increases. To maintain the same high codeword if and only if
level of reliability, a double-error-correcting triple-error-detect- H V' = 0, (1)
ing (DEC-TED) code may be used. However, this type of code
requires a larger number of check bits than a SEC-DED code where V denotes the transpose of V, and all additions are
and more complex hardware to implement the functions of performed modulo 2.
error correction and error detection [8, 15. 16]. The encoding process of a code consists of generating r
check bits for a set of A: data bits. To facilitate encoding, the
An error-correcting code can be used to correct "soft" errors H matrix is expressed as
as well as hard errors. Soft errors are temporary errors such as
«-particle-induced errors that disappear during the next mem- H = [P,I,], (2)
ory write operation. With a maintenance strategy that allows where P is an r x ^ binary matrix and h is the r X r identity
the accumulation of hard errors, a high soft error rate would matrix. Then the first k bits of a codeword can be designated
cause a high uncorrectable error (UE) rate. To reduce the UE as the data bits, and the last r bits can be designated as the
rate that involves soft errors, a SEC-DED code can be modified check bits. Furthermore, the ith check bit can be explicitly
to correct two hard errors or a combination of one hard and calculated from the ith equation of the set of r equations in
one soft error [21-25]. (1). A code specified by an H matrix of (2) is called a systematic
code.
In this paper we review the current status of error-correcting
codes for semiconductor memory applications and present Any binary r x n matrix H of rank r can always be
the state of the art by describing the construction of four transformed into the systematic form of (2). Since the rank of
classes of error-correcting codes suitable for this type of design H is r, there exists a set of r linearly independent columns.
application. These four classes are SEC-DED codes, SEC- The columns of the matrix can be reordered so that the
DED-SBD codes, SBC-DBD codes, and DEC-TED codes. For rightmost r columns are linearly independent. Applying ele-
each class of code we provide the number of check bits mentary row operations [ 16] on the resultant matrix, a matrix
required for commonly used data lengths, information that is of (2) is obtained. The systematic code obtained is equivalent
particularly useful to designers for system planning. We also to the code defined by the original H matrix. Figure 2(a) is an
discuss the implementation aspects of error correction and example of the parity check matrix of a (26,20) code in a
error detection for these classes of error control codes. In nonsystematic form. Note that the last six columns of the
addition, we describe a number of algorithms useful in ex- matrix are linearly independent. The submatrix of the six
tending the error-correcting capability of codes for the correc- columns can be inverted. The multiplication of the inverse of
tion of soft errors such as a-particle-induced errors and other the submatrix and the transpose of the parity check matrix
temporary errors. results in a matrix of systematic form shown in Figure 2(b). 125

IBM J. RES. DEVELOP. » VOL. 28 • NO. 2 » MARCH 1984 C. L, CHEN AND M. Y. HSIAO
 pairs of codewords. For a linear code, the minimum distance
of the code is equal to the minimum of the weights of all
nonzero codewords [8, 15, 16]. A code is capable of correcting
t errors and detecting t -¥ 1 errors if and only ii d>2t + 1.
(a)

In semiconductor memory applications, the encoding and

1 1
I 1
the decoding of a code are implemented in a parallel manner.
I 1 In encoding, the check bits are generated simultaneously by
• 1
1 1 processing the data bits in parallel. In decoding, the syndrome
1
(b)
•
is generated using the same hardware for the generation of the
check bits. The error vector is then generated by decoding the
Figure 2 (26,20) code: (a) nonsystematic form; (b) systematic form. syndrome bits in parallel. Finally, the errors are corrected by
subtracting the error vector from the fetched word. The sub-
traction is accomplished by the bit-by-bit exclusive-or (XOR)
of the components of the two vectors.
Table 1 Average number of uncorrectable errors (UEs) with three
memory systems employing different error control schemes: parity
check, SEC-DED code, and DEC-TED code. The reliability function of a memory system that employs
an error-correcting code can be handled either analytically or
Time Parity SEC-DED DEC-TED through Monte Carlo methods [1-4,26-28]. For a system
(X 10' hrs.) check
with a simple architecture, an analytical approach may be
0-10 49 3.2 0.56 possible. However, for a memory system consisting of hierar-
0-20 81 5.2 0.96 chical arrays, the memory reliability function is too intractable
0-30 111 6.9 1.3
0-50 9.3
to handle analytically. Monte Carlo methods are considered a
168 2.0
general approach to study the effectiveness of error-correcting
0-80 253 13 2,9
codes and other fault-tolerant schemes [27, 28].
Parity check: (9,8) code.
SEC-DED: (72,64) code,
DEC-TED: (80,64) code. To demonstrate the reliability improvement obtainable
with ECC, we consider three memory systems of four mega-
bytes. The first system consists of eight memory cards and is
designed with a parity check on each set of eight data bits.
A word read from the memory may not be the same as the The second system consists of 18 memory cards and is de-
original codeword written in the same location. Let U = (wi, signed with a (72,64) SEC-DED code. The last system consists
«2, • • • ,u„)bt the word read from the memory. The difference of 20 memory cards and is designed with an (80,64) DEC-
between U and the original codeword V is defined as the error TED code. The memory chips for the systems are 16K-bit
vector E = (ei, e2, • • • , e„); i.e., U = V + E. The /th position chips with 128 bit lines and 128 word lines in each chip. Each
of U is in error if and only if e, is nonzero. memory card contains an array of 32 X 9 chips for the first
system, and an array of 32 x 4 chips for the other two systems.
The decoding process consists of determining whether U The failure rates of the chips and the card-support circuits are
contains errors and determining the error vector. To deter- assumed to be the same as those described in [27]. When a
mine whether U is in error, an /--bit syndrome S is calculated UE occurs, the strategy is to replace the card that contains the
as follows: UE and that has the largest number of defective cells.

S = H-U' = H - ( V ' -I- E')

The modeling tool of [27] is used to simulate the reliability
= H E'. (3) of the three memory systems. The results of the simulation
are shown in Table 1. The improvement factor of ECC over
If S is an all-zeros vector, the word U is assumed to be error-
free. If S is a nonzero vector, it is used to determine the error the parity check scheme on the number of UEs is over 15 for
vector. SEC-DED code and over 84 for DEC-TED code.

The error-correcting capability of a code is closely related SEC-DED codes

to the minimum distance of the code. The weight of a code- The minimum distance of a single-error-correcting and dou-
word is the number of nonzero components in the codeword. ble-error-detecting (SEC-DED) code is greater than or equal
The distance between two codewords is the number of com- to four. Since an n-tuple of weight three or less is not a
ponents in which the two codewords differ. The minimum codeword, from Eq. (1) the sum of a set of three or fewer
126 distance d of the code is the minimum of the distances of all columns of the H matrix must be nonzero. In other words.

C, L, CHEN AND M, Y, HSIAO IBM J, RES, DEVELOP, • VOL, 28 • NO, 2 • MARCH 1984
 n i l 1 • • 1
11 1 •
• • • 1 • • I • 1
1• • 1 I M 1 I
• 1 • • 1 11 • •
• • 1 • • • • 1 1

(a)

I 1 •1
I • 1 •
I I
M i l
I I I 11 •
1 1 1
1 • 1
• 1 •

1 I 1 I 1 I 1 I I I 1 I I . . I . I . . . I . .
1 • • • 1 • • •
i n n n i l . . . 1 I I . . . 1 .
I . . . ] 1 I I 1 !1 n n I • 1 • • • I
• 1 • • • I • • 1 . . . I . . I . . .
I I • 1 1 • n I I • • • • ••
I I n I I n n I
I I I 1 n I II1I I. .
1 I 11 1 1 1 I I 1 I I 1

Mil n i l 1• • • n I• 1 1• I I
n i l I I I II I • 1 I n • • II • 1 I • I
1 1 1 1 1 I n • • I • I • 11 I I
1I n 1I • 1 n I 1
I • • • I I
. 1 . . 1 1
• • I • I . . I .
I I I I I I I I I I II I {
I • • • 1 • • I I I I 1 11 I 1 I
(d)

Figure 3 Parity check matrix of some SEC-DED codes: (a) (22,16) code (IBM Sysfem/3); (b) (40,32) code (IBM 8130); (c) (72,64) code (IBM
3033); (d) (72,64) code (IBM 3081).

any set of three columns of the H matrix are linearly inde- Table 2 Number of check bits required for SEC-DED codes.
pendent. Thus, the H matrix of a SEC-DED code must satisfy
the following conditions: Data bits Check bits

Al. The column vectors of the H matrix are nonzero and are 5
16 6
distinct. 32 7
A2. The sum of two columns of the H matrix is nonzero and 64 8
is not equal to a third column of the H matrix. 128 9
256 10
Note that the sum of two odd-weight r-tuples is an even-
weight r-tuple. A SEC-DED code with r check bits can be
constructed with its H matrix consisting of distinct nonzero
Muples of odd weights. This is an odd-weight-column code of than the maximum for a given number of check bits. There
Hsiao [6]. are various ways of shortening a maximum-length SEC-DED
code. Usually a code designer constructs a shonened code to
The maximum code length of an odd-weight-column code meet certain objectives for a particular application. These
with r check bits is 2""', for there are 2'^' possible distinct objectives may include the minimization of the number of
odd-weight r-tuples. This maximum code length is the same circuits, the amount of logic delay, the number of part num-
as that of a SEC-DED Hamming code. The maximum number bers, or the probability of miscorrecting triple errors [6].
of data bits A: of a SEC-DED code must satisfy k < 2'^' - r.
Table 2 lists the number of check bits required for a set of In a write operation, check bits are generated simultane-
data bits. Figure 3 shows examples of SEC-DED codes used ously by processing the data bits in a parallel manner accord-
in some IBM systems. ing to Eqs. (1) and (2). In a read operation, syndrome bits are
generated simultaneously from the word read according to
Most of the SEC-DED codes for semiconductor memory Eq. (.3). Typically the same XOR tree is used to generate both
applications are shortened codes in that the code length is less the check bit.s and the syndrome bits (see Figure 4). 127

IBM J, RES. DEVELOP. • VOL. 28 • NO. 2 . MARCH 1984 C- L. CHEN AND M. Y. HSIAO
 check bits
signal, and n two-way XOR gates for inverting tlie code bit in
data bits (read) error. Additionally, an «-bit data register and control logic for
timing are required.
XOR
iree A UE signal can also be generated based on the logical OR
of the minterms of all UE syndromes. A subset of all UE
syndromes is the set of even-weight syndromes caused by even
Bit-wise numbers of errors. This subset of syndromes can be recognized
XOR
by an r-way XOR gate.

check bits syndrome bits The failure of a common logic support in the memory may
(write) (read)
result in an all-ones or an all-zeros pattern in a codeword. In
Figure 4 Generation of check bits a n d syndrome bits.
this case, the error vector in general contains a multiple
number of errors that are not detectable by a SEC-DED code.
To prevent this kind of data loss, the code can be constructed
r-b ! syndrome or modiied so that an all-ones or an all-zeros «-tuple is not a
codeword. For example, if the check bits are inverted before
• Error
the codeword is written into the memory, then all the code-
OR
• detected words stored in the memory are nonzero. In general, the
2 • »• r
detection of all-ones and all-zeros errors can be achieved by
Syndrome decoder inverting a subset of the check bits [9].
(« r-way AND
gates)

SEC-DED-SBO codes
•• AND UE
1 2 ••• n •
NOR In some applications it is required that the memory array
chips be packaged in a l)-bits-per-chip organization. A chip
ECC
word
K
>
Error corrector
n t wo-wav XOR
failure or a word-line failure in this case would result in a
read gati
byte-oriented error that contains from 1 to b erroneous bits.
Byte errors can also be caused by the failures of the supporting
^ modules at the memory card level. The class of SEC-DED
Corrected word
codes that are capable of detecting all single-byte errors (SEC-
Figure 5 Error detection and correction block diagram. DED-SBD codes) may be used to maintain data integrity in
these applications.

An algorithm for correcting single errors and detecting The H matrix of a SEC-DED-SBD code can be divided into
multiple errors is described as follows: iV blocks of r X b submatrices, 81,82, • • • , B„, where 8,-
1. Test whether S is 0. If S is 0, the word is assumed to be represents the parity checks for byte position /. From (3), the
error-free. syndrome of a byte error at position / is a sum of the columns
2. If S # 0, try to find a perfect match between S and a of B, that correspond to the bit error positions within the byte.
column of the H matrix. The match can be implemented The syndromes of all possible byte errors at position i are the
in n r-way AND gates. sum of all possible combinations of the columns of B,. Let
3. If S is the same as the ith column of H, the /th bit of the <B,) denote the sums of all possible nonzero linear combina-
word is in error. tions of the columns of B,. Each member of <B/) should be
4. If S is not equal to any column of H, the errors are detected nonzero and should not be equal to a column of B,, for/ # /.
Otherwise, the byte error at position / will be mistaken as no
as uncorrectable (UE).
error or as a correctable single error at position/ Thus, the H
This algorithm applied to a SEC-DED code corrects all single matrix of a SEC-DED-SBD code must satisfy the conditions
errors and detects all double errors. Multiple-bit errors may A1 and A2 given previously, as well as the following condition:
be detected or falsely corrected. The extent of multiple errors
detected depends on the structure of the code. A3. Each vector of (B,) is nonzero and is not equal to a
column vector ofBj, forj T* /.
As shown in Figure 5, hardware implementation of the
error correction and detection mainly consists of an r-way OR For i? < 4, most of the SEC-DED codes for practical
gate for testing nonzero syndrome, n r-way AND gates for applications can be reconfigured to detect single-byte errors.
128 decoding syndromes, an «-way NOR gate for generating UE The reconfiguration involves the regrouping or rewiring of the

C L, CHEN AND M. Y. HSIAO IBM 1- RES. DEVELOP. » VOL. 28 » N a 2 % MARCH 1984

 1 I 1
I 1 I I I I I
I1 I I 1 I
I I 1
1• •
• ! •
• I • I •• • •1
. . I ; . . I I

11 I I •
1 I I I 1
1 I • 1 1
1 ! 1 1 1 - 1
I I11 I
1 I 1 1 i ! • • • •

• I 1 I • 1 • •
• I •

I 1

I I
I i I M I
I I 1 n
1I

Figure 6 Examples of SEC-DED-SBD codes: (a) (40,32) code, b = 4; (b) (72,64) code, h = 4; (c) (72.64) code, i = 3 and A = 4.

bit positions of the original code. Since the same encoding Table 3 Code length in bytes for some SEC-DED-SBD codes.
and decoding hardware can be used, no additional hardware
is required if a SEC-DED code can be reconfigured for single-
byte error detection. Figure 6 illustrates some examples of
SEC-DED-SBD codes. The codes in Figs. 6(a) and (b) are b+ 1 2 2 3 3 3 3 3
obtained from those in Figs. 3(b) and (d) by reconfiguration, h+2 5 6 7 8 9 10 11
6+3 10 12 15 16 18 20 22
and the code in Fig. 6(c) is the same as that in Fig. 3(c). The h+4 21 26 31 36 41 46 51
(72,64) codes of Fig. 6 are those used in IBM systems 3081 h+5 42 52 63 72 82 92 102
and 3033. b+6 85 106 127 148 169 190 21)

Techniques for the construction of SEC-DED-SBD codes

have been presented in [13,14]. Let iV(nft) be the code length
Table 4 All binary 3-tuples expressed as elements of GF(S).
in 6-bit bytes. For d = 3, it is shown in [14] that optimal codes
with AX''.3)= L2'~73 J, where [ x J denotes the integer part 0= 0 0 0
of X, can be constructed. For other values ofb, the construction x» = 1 0 0
of the longest code for a given r is an open question. A list of x' = 0 I 0
jc" = 0 0 1
the code lengths of some known SEC-DED-SBD codes is x^=] 10
given in Table 3. x'^O 1 1
x'= I 1 I
.x:' = 1 0 1
SBC-DBD codes
For a memory system packaged in a A-bits-per-chip organi-
zation, the reliability provided by a SEC-DED code may not
be acceptable. T o increase the reliability, a byte-oriented error- tuples can be assigned as the elements of GF(8), as shown in
correcting code may be used [15-20, 29]. In this section, we Table 4. In the finite-field representation of 6-tuples, the sum
discuss the construction and implementation of single-byle- of two elements is the bit-by-bit XOR of the two associated
error-correcting and double-byte-error-detecting (SBC-DBD) /b-tuples. The product of two elements X' and X' is X* with
codes. A:=/-l-7mod(2'')-l.Forexample,X' + X'' = (l 1 0)-f-
(1 0 1) = (0 1 1) = X^ and A''.X'' = X-from Table 4.
A codeword of a SBC-DBD code consists of A ' ^ b i t bytes.
A binary b-tuple is considered an element of the finite field With the finite-field representation, an SBC-DBD code is a
GF(2*) of 2* elements [8,15, 16]. For example, all binar>' 3- linear code over GF(2*) with a minimum distance ds: 4. The 129

IBM J. RES. DEVELOP. « VOL, 28 % NO. 2 « MARCH \9U C. L. CHEN AND M. Y. HSIAO
 • • 1 1 • • 1 1 • • 1 1 • • 1 1 • • 11 •
• 1 1 • 1• 1• 1• 1• 1• 1• 1• 1• 1• 1 1 • 1
11 • • 1 • • • 1 • • •
• I • • • 1 • • •
ro 0 n
1 1 • l i - • u - • 1 1 - • 1 1 - • 1 1 - • 1 •• 1 1- • • !• • • T = 1 0 1
• 1 • 1 1 • 1 • 1 I • 1 1 • 1 1 1 1 1 1 1 1 1 1 •. . 1 1 , . 1 . . . 0 1 0
• 1 • 1 1 • 1 1 1 1 1 1 1 1 1 • 1 1 • • 1 • • 1 •• • 1 • 1 • 1 • • •
1 .1 - J 1• U • 1 l i i 1 1 1 1 1 - 1 1 •_ 1 • • • 1 • • 1 i • • • and the H matrix for a (10,7) SBC-DBD code with ft = 3 is
I • i • 111 11 • 1 • • 1 11 • 1 1 1 1
II i 11 • 1 • • 1j 1 • 1 11 1 1 1 1 •
; •• •• ! 1• • • •• • 11 •• 1• 1• shown in Figure 7.
• 11 111 1 1• • ! • 1 • 1• 11 1 1 1

Figure 7 (10,7) SBC-DBD code with b=i. Using the H matrix of Eq. (4), the last three column
positions of H can be designated as the positions of check
bytes and the other column positions of H can be designated
as data byte positions. The check bytes can be generated with
Table 5 Number of check bits required for SBC-DBD codes. an XOR tree just as in the case of SEC-DED codes. The
syndrome can also be generated with the same XOR tree. For
Bits per byte Data bits per ECC word decoding, the syndrome S is divided into three parts, S|, S2,
S3. Each S, consists of b bits and represents the parity check
16 32 64 128 equations for the /th row of (4). From (3), if E is a single-byte
2 8 10 10 12 error pattern at data byte position /, then E is a unique solution
3 9 12 12 12 to the following three equations:
4 12 12 14 16
b>5 ib 3b 36 36 S, = E',
52 = T'-E',
53 = T^'-E'.
On the other hand, if E is a byte error pattern at check byte
code can also be defined by the parity check matrix H of (1)
position /, where / = 1, 2, or 3, then E = S,'and the other two
and (2), with the components of the matrices and vectors
subsyndromes are zeros. The following steps can be taken to
considered elements of GF(2''). Let h„ 1 < / < A^, be the
find the correctable single-byte error patterns and to detect
column vectors of the H matrix. The SBC-DBD code must
multiple uncorrectable byte errors.
satisfy the following conditions:
1. If S is a zero vector, assume that there is no error. If S is
BI. /!, ^ X-hj for / # ;, X e GF(2*).
nonzero, go to step 2.
B2. h, + Xx-hj ¥= X2-/I/, for distinct/,;,/and Ji'i,X2(; GF(2'').
2. If one of the subsyndromes S, =^ 0, and the other two
subsyndromes are zero, i = 1, 2, 3, the check byte position
Let r be the number of check bytes of an SBC-DBD code
/ with error pattern S is assumed. Otherwise, go to step 3.
over GF(2*). For r = 3, a code of length TV = 2 -I- 2* bytes can
3. Assume that E = SI Find /' that satisfies 0 < ; < Af - 4, T' •
be constructed by extending a Reed-Solomon code of length
E' = S2, and T^' • E' = S3. If / has a solution, the byte error
(2*) - 1 [15-19]. The parity check matrix of the code can be
with pattern E at data byte position / is assumed. If / has
expressed as
no solution, then an uncorrectable error is detected.
I I I I I O O
A block diagram for the generation of the error pointers for
H I T T^ T^'^ O I O (4) the code of Fig. 7 is shown in Figure 8.
I T^ T* T^(2'^* O O I
The extended Reed-Solomon codes defined in Eq. (4) are
where I is the 6 x i identity matrix, O is a A x 6 all-zero optimal in that no other SBC-DBD codes with three check
matrix, T is the b x b companion matrix of X, and X is a bytes contain more data bytes. However, there exists only one
primitive element of GF(2*) [15, 16], If X is a root of the code for a given byte size b. When b is small, the code may
primitive polynomial P(X) = Oo + a\X + a2X^ + •••,-(- be too short for memory applications. For example, the code
flA-iX*"', the companion matrix of A' is for ft = 2 can only accommodate six data bits. This code
certainly is not practical for most applications. In order to
0 0 •• 0 oo increase the code length for a given ft, additional check bits
1 0 •• 0 a, are required.
ry _ 0 1
U •••• • 0 02

Techniques for the construction of SBC-DBD codes for r >

_0 0 •• 1 a*-i 3 can be found in [15, 16, 30, 31]. Table 5 lists the minimum
number of check bits required for some known SBC-DBD
130 For example, the companion matrix of X in Table 4 is codes.

C. L. CHEN AND M. Y. HSIAO IBM J. RES. DEVELOP. • VOL. 28 • NO. 2 • MARCH 1984
DEC-TED codes
A memory system with a large capacity or with high chip
failure rates may use a double-error-correcting and triple-
error-detecting (DEC-TED) code to meet its reliability require-
ments. A DEC-TED code is also attractive for a memory with
AND AND AND
a high soft error rate. Although there are schemes [21-25], to
be discussed in a subsequent section, for a SEC-DED code to
correct hard-hard and hard-soft types of double errors, these
schemes cannot correct double soft errors and they require J i , J I , * J_L J_L JJ_, J±,
the interruption of a normal memory read operation. With a [AND] |AND| I AND I I AND I | AND | | AND |
DEC-TED code, any combination of hard and soft double £,
errors, including double soft errors, can be corrected auto-
matically without system interruption. Figure 8 Generation of error vectors for a (10,7) SBC-DBD code
with 6 = 3.

A minimum distance of a DEC-TED code is at least equal

to six. The parity check matrix H of a DEC-TED code must
have the property that any linear combination of five or fewer
columns of H is not an all-zeros vector.

A class of DEC-TED binary linear block codes can be

constructed according to the theory of BCH codes
[8, 15, 16,32,33]. Let X be a root of a primitive binary
polynomial P{X) of degree m. The powers of X can be
considered elements of GF{N), N = T", and can be expressed (a)
as binary w-tuples. A binary code defined by (1) with the
following parity check matrix is a DEC-TED code:

1 1 1 1
H = 1 X x^ • x^-^ (5)
1 x^ X ' • . J^3(JV-2)

The powers of X in H are expressed in w-tuples. Since there

are Im -(- 1 hnearly inder>endent row vectors in H, the number (b)
of check bits of the code is 2w + 1. The code length is equal
to JV - 1. The code can be extended to length A' by adding a Figure 9 Parity check matrix of a (31,20) code: (a) nonsystematic
column of 1 followed by Im zeros. Figure 9(a) shows the form H; (b) systematic form HI.
parity check matrix of a (31,20) code constructed from Eq.
(5).
Table 6 Number of check bits required for DEC-TED BCH codes.
A full-length BCH code can be shortened by deleting a
number of columns from its H matrix. The shortened code Data bits Check bits
has a minimum distance at least as large as the original code.
The number of check bits of the shortened code may be less 9
16 11
than the original code when proper bit positions are deleted 32 13
[34-35]. In particular, let Y be a row vector in the space 64 15
generated by the row vectors of H. Deleting the column 2m + 3
positions of H where the corresponding positions of Y are
ones, then the shortened H matrix has one fewer linearly
independent row vector and the shortened code has one fewer
check bit than the original code. Table 6 presents a list of the Fig. 9 for example). Let HI be the parity check matrix in
number of check bits required for some DEC-TED BCH systematic form, and T be an r x r transformation matrix that
codes. satisfies

H = TH1. (6)
The H matrix defined by (5) can be transformed into the
systematic form of (2) for the generation of check bits (see The generation of check bits from matrix HI can be imple- 131

IBM J. RES. DEVELOP. • VOL. 28 • NO. 2 • MARCH 1984 C. L. CHEN AND M. Y. HSIAO
 Table 7 Example of locating erasures. Extended error correction
Errors in semiconductor memory can be broadly divided into
Direction of 10 hard errors and soft errors [24, 25]. Hard errors are caused by
stuck faults
stuck faults or by permanent physical damage to the memory
r, (WRITE) 1 10 0 1 10 0 devices. Soft errors are temporary errors or a-particle-induced
r, (READ) 10 0 0 1 1 0 1 errors that will be erased during the next data storage opera-
T2 (WRITE) 0 0 1 1 0 0 11
T2 (READ) 10 1 1 0 0 11 tion. For this discussion, the errors that will stay in their
r, (READ) + 0 0 111110 locations during the next few write cycles are considered hard
T2 (READ) errors.
ERASURE ERROR 1 10 0 0 0 0 1
Error-correcting codes can be used to correct hard as well
as soft errors. However, the maintenance strategy for a system
mented with an XOR tree. For decoding, it is convenient to may allow the hard errors to accumulate. The presence of
define the syndrome S from (3) with the H matrix instead of errors in the memory increases the probability of uncorrecta-
the HI matrix. The syndrome can be generated using an XOR ble errors (UE) due to the lineup of multiple errors in a
tree associated with the H matrix. Thus, two separate XOR codeword. The UE rate can be reduced by repair service
trees are used to generate check bits and syndrome bits. The scheduled periodically. It can also be reduced by extending
syndrome can also be generated by first generating SI from the conventional error correction to some of the otherwise
Eq. (3) with the HI matrix, then multiplying matrix T by SI. uncorrectable errors. The latter approach is especially attrac-
Using this approach, the same XOR tree can be used to tive when the soft error rates are high, because it does not
generate check bits and SI. The validity of this procedure require the replacement of memory components. The ex-
follows directly from Eq. (6). tended error-correction schemes are discussed in this section.

The syndrome S can be divided into three parts. So, Si, and The errors for which locations but not values are known
S2, where So consists of one bit, and Si and S2 consist of m are called erasures [15, 16]. Erasures are easier to correct than
bits. Let the bit positions of the code be assigned as the powers random errors. Let / and e be the number of random errors
of X Assume that Ei and E2 are the positions of two erroneous and erasures, respectively, that a code is capable of correcting;
bits. Then So = 0 and Si = Ei + E2, S2 = E] -1- E i Since then the minimum distance d of the code must satisfy [ 15,
S] -t- S2 = E]E2 + EiEi = E1E2S1, the error positions Ei and 16],
E2 are roots of the quadratic equation
2t + e<d. (8)
S i / + S?y -f- {S? + S2) = 0. (7)
For example, a SEC-DED code is capable of correcting one
On the other hand, if there is only one error, then So = 1 and random error and one erasure.
the error position is the root of the linear equation 3^ -I- Si =
0. In memory applications, the hard errors can be considered
erasures if their locations can be identified. To locate the
The major part of the error correction is to find the error erasures of a particular word in the memory, we may apply
positions from the syndrome. Once the error positions are some test patterns to the memory. Assume that any binary
known, the errors are corrected by inverting the data bits at pattern can be written into the memory. An example is shown
the error positions. The error positions are determined by in Table 7 for finding the locations of erasures with two test
solving Eq. (7). If So = 0, and Eq. (7) has two solutions, then patterns, Ti and T2, of length 8, where T2 is the complement
the solutions are the positions of two errors. If So = 1, and of Ti. Before the test patterns are written into and read out of
Eq. (7) degenerates to a linear equation, then the solution is the memory, the word originally stored in the memory is read
the position of a single error. Uncorrectable errors are detected out and stored in a temporary storage. The erasure vector is
if Eq. (7) has no solution when So = 0, or Eq. (7) does not obtained by the complement of T,(READ) + T J I R E A D ) . The
degenerate into a linear equation when So = 1. locations of the erasures are indicated by the ones in the
erasure vector. Since Ti can be arbitrarily chosen, we may
also use the word that originally stored in the memory as Tu
There are various schemes for solving Eq. (7) [36-38]. The
This approach for locating the erasures, known as the double
equation can be solved algebraically using hardware that im-
complement algorithm, saves one write and one read opera-
plements finite-field operations as in [36]. It can also be solved
tion. An example of the algorithm is shown in Table 8.
by substituting all possible solutions into the equation, as in
[38]. Another approach is to store the error positions of
correctable errors in a table. The syndrome is used as the Some system designs permit only the codewords to be
132 address to the table of error positions [37]. written into the memory [21, 22, 25]. If the complement of a

C. L. CHEN AND M. Y. HSIAO IBM J. RES. DEVELOP. • VOL. 28 • NO. 2 • MARCH 1984
codeword is not a codeword, then the approaches just de- Table 8 Example of double complement algorithm.
scribed for the identification of erasures are not applicable. In
this case, one solution is to design codes with some special Original word = T, (WRITE) I 10 0 1 10 0
Hard and soft errors H S -
properties [21, 22]. Another solution is to employ three test r , (READ) 0 10 0 1 1 1 0
patterns in locating the erasures [25]. The test patterns are Ti (WRITE) = r , (READ) 10 1 1 0 0 0 1
chosen in such a way that they contain at least one 1 and one Ti (READ) 0 0 1 10 0 0 I
r, (READ) + Ti (READ) 0 1 1 1 1 1 1 1
0 in every bit position. It can be shown that three test patterns
Erasure error 10 0 0 0 0 0 0
are sufficient to satisfy this condition for any linear code. Ty = Tt (READ) 1 10 0 1 1 I 0
Soft error = Tj + T, (WRITE) 0 0 0 0 0 0 10
Once the locations of the erasures are identified, algorithms
can be designed to correct the hard and soft errors, provided
that the number of errors satisfies Eq. (8). Assume that the
with additional check bits, which are used to mask the erasures
double complement algorithm is applicable for locating the
in decoding. For example, a (76,64) code can be designed to
erasures. The following procedure can be used to correct up
correct double erasures and single random errors, and to detect
to two hard errors or a combination of one hard and one soft
double random errors [40].
error for a SEC-DED code:

1. Read word Ti from a memory location. Conclusions

2. If a single error in Ti is detected by the ECC logic, the Advances in semiconductor technology have brought about
error in the word is corrected, and the corrected codeword very high levels of integration, especially in the memory area
is sent out to its destination. where circuit densities are up to 256K bits per chip. In VLSI
3. If uncorrectable errors in Ti are detected by the ECC logic, memory, higher density usually means a reduced signal-to-
the complement of Tt is written into the same memory noise margin. It also increases the likelihood of soft errors due
location. Then the word from the same memory location to radiation and other sources. Error-correcting codes have
is read and complemented. Let the resultant word be Fj provided a very effective solution to these problems. They
(see Table 8). have become an essential part of modem memory design. In
4. If a single error in Tj is detected by the ECC logic, the the future, the ECC could even be an integral part of the
error is corrected. The corrected word is sent out to its memory chips that manufacturers would offer.
destination and is also written into the same memory
location. In this paper, we have described the essentials of the prin-
5. If no error is detected by the ECC logic, T^ is assumed cipal error-correcting codes used in semiconductor memory
error free. T:^ is sent out to its destination and is also written design applications. The class of SEC-DED codes is currently
into the same memory location. most widely used throughout the industry. However, more
6. If uncorrectable errors are detected by the ECC logic, the powerful codes such as SBC-DBD and DEC-TED codes are
original word is declared uncorrectable. quite likely to be used in future commercial systems.

Note that double soft errors are not correctable by this pro-
Acknowledgment
cedure. All single errors are corrected at the normal speed.
Contributions made by D. C. Bossen are gratefully acknowl-
The correction of hard-hard and hard-soft types of double
edged.
errors takes more time because additional write and read
operations are involved. The procedure can be modified or
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this issue). Diagnostic Engineering Department. In 1969, he was promoted to
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for Computer Applications," IEEE Trans. Computers C-21, ment. He assumed his present position in 1979. Dr. Hsiao received
1322-1331 (December 1972). his B.S. in electrical engineering in 1956 from Taiwan University,
30. T. T. Dao, "Design and Implementation of a Non-Binary Code Taipei, his M.S. in mathematics in 1960 from the University of UUnois,
for Byte-Organized Memory with Binary and Quaternary Log- and his Ph.D. in electrical engineering in 1967 from the University of
ics," Proceedings of the 8th IEEE International Symposium on Florida. He has seven IBM Invention Achievement Awards, two IBM
Multi-Valued Logic, Rosemont, IL, May 1973, pp. 24-26. Outstanding Innovation Awards, and a Corporate Award in the areas
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134

C. L. CHEN AND M. Y. HSIAO IBM J. RES. DEVELOP. . VOL. 28 « NO. 2 • MARCH 1984