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SN54LV245A, SN74LV245A
SCLS382O – SEPTEMBER 1997 – REVISED SEPTEMBER 2014

SNx4LV245A Octal Bus Transceivers With 3-State Outputs

1 Features 2 Applications
•
1 2-V to 5.5-V VCC Operation • Servers
• Max tpd of 6.5 ns at 5 V • LED Displays
• Typical VOLP (Output Ground Bounce) • Network Switches
<0.8 V at VCC = 3.3 V, TA = 25°C • Telecom Infrastructure
• Typical VOHV (Output VOH Undershoot) • Motor Drivers
>2.3 V at VCC = 3.3 V, TA = 25°C • I/O Expanders
• Support Mixed-Mode Voltage Operation on All
Ports 3 Description
• Ioff Supports Partial-Power-Down Mode Operation These octal bus transceivers are designed for 2-V to
• Latch-Up Performance Exceeds 250 mA Per 5.5-V VCC operation.
JESD 17
Device Information
• ESD Protection Exceeds JESD 22
PART NUMBER PACKAGE BODY SIZE (NOM)
– 2000-V Human-Body Model (A114-A) SSOP (20) 7.20 mm × 5.30 mm
– 200-V Machine Model (A115-A) TVSOP (20) 5.00 mm × 4.40 mm
– 1000-V Charged-Device Model (C101) SNx4LV245A TSSOP (20) 6.50 mm × 4.40 mm
VQFN (20) 4.50 mm × 3.50 mm
SOIC (20) 12.80 mm × 7.50 mm

4 Simplified Schematic

DIR

OE

A1

B1

To Seven Other Channels

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA.
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Table of Contents
1 Features .................................................................. 1 9 Detailed Description ............................................ 11
2 Applications ........................................................... 1 9.1 Overview ................................................................. 11
3 Description ............................................................. 1 9.2 Functional Block Diagram ....................................... 11
4 Simplified Schematic............................................. 1 9.3 Feature Description................................................. 11
9.4 Device Functional Modes........................................ 11
5 Revision History..................................................... 2
6 Pin Configuration and Functions ......................... 3 10 Application and Implementation........................ 12
10.1 Application Information.......................................... 12
7 Specifications......................................................... 5
10.2 Typical Application ............................................... 12
7.1 Absolute Maximum Ratings ...................................... 5
7.2 Handling Ratings....................................................... 5 11 Power Supply Recommendations ..................... 13
7.3 Recommended Operating Conditions....................... 6 12 Layout................................................................... 13
7.4 Thermal Information .................................................. 6 12.1 Layout Guidelines ................................................. 13
7.5 Electrical Characteristics........................................... 7 12.2 Layout Example .................................................... 13
7.6 Switching Characteristics, VCC = 2.5 V ± 0.2 V ........ 7 13 Device and Documentation Support ................. 14
7.7 Switching Characteristics, VCC = 3.3 V ± 0.3 V ........ 8 13.1 Related Links ........................................................ 14
7.8 Switching Characteristics, VCC = 5 V ± 0.5 V ........... 8 13.2 Trademarks ........................................................... 14
7.9 Noise Characteristics ................................................ 8 13.3 Electrostatic Discharge Caution ............................ 14
7.10 Operating Characteristics........................................ 8 13.4 Glossary ................................................................ 14
7.11 Typical Characteristics ............................................ 9 14 Mechanical, Packaging, and Orderable
8 Parameter Measurement Information ................ 10 Information ........................................................... 14

5 Revision History
Changes from Revision N (August 2012) to Revision O Page

• Updated document to new TI data sheet format. ................................................................................................................... 1

• Deleted Ordering Information table. ....................................................................................................................................... 1
• Added Applications. ................................................................................................................................................................ 1
• Added Device Information table. ............................................................................................................................................ 1
• Added Pin Functions table...................................................................................................................................................... 3
• Added Handling Ratings table. ............................................................................................................................................... 5
• Changed MAX operating temperature to 125°C in Recommended Operating Conditions table. ......................................... 6
• Added –40°C to 125°C for SN74LV245A in Electrical Characteristics table.......................................................................... 7
• Added –40°C to 125°C for SN74LV245A in all three Switching Characteristics tables. ........................................................ 7
• Added Typical Characteristics. ............................................................................................................................................... 9
• Added Detailed Description section...................................................................................................................................... 11
• Added Application and Implementation section.................................................................................................................... 12
• Added Power Supply Recommendations and Layout sections............................................................................................ 13

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6 Pin Configuration and Functions

SN54LV245A . . . J OR W PACKAGE SN74LV245A . . . RGY PACKAGE SN54LV245A . . . FK PACKAGE
SN74LV245A . . . DB, DGV, DW, NS, (TOP VIEW) (TOP VIEW)
OR PW PACKAGE

VCC
DIR
VCC
DIR

OE
A2
A1
(TOP VIEW)

DIR 1 20 VCC 1 20 3 2 1 20 19
A1 2 19 OE A3 4 18 B1
A1 2 19 OE
A2 3 18 B1 A4 5 17 B2
A2 3 18 B1
A3 4 17 B2 A5 6 16 B3
A3 4 17 B2
A4 5 16 B3 A6 7 15 B4
A4 5 16 B3
A5 6 15 B4 A7 8 14 B5
A5 6 15 B4 9 10 11 12 13
A6 7 14 B5
A6 7 14 B5

A8
GND
B8
B7
B6
8 13 A7 8 13 B6
A7 B6
9 12 A8 9 12 B7
A8 B7
GND 10 11 B8 10 11

GND

B8
Pin Functions
PIN
I/O DESCRIPTION
NO. NAME
1 DIR I Direction Pin
2 A1 I/O A1 I/O
3 A2 I/O A2 I/O
4 A3 I/O A3 I/O
5 A4 I/O A4 I/O
6 A5 I/O A5 I/O
7 A6 I/O A6 I/O
8 A7 I/O A7 I/O
9 A8 I/O A8 I/O
10 GND — Ground Pin
11 B8 I/O B8 I/O
12 B7 I/O B7 I/O
13 B6 I/O B6 I/O
14 B5 I/O B5 I/O
15 B4 I/O B4 I/O
16 B3 I/O B3 I/O
17 B2 I/O B2 I/O
18 B1 I/O B1 I/O
19 OE I Output Enable
20 VCC — Power Pin

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GQN PACKAGE
(TOP VIEW)
Pin Assignments
1 2 3 4
1 2 3 4
A A A1 DIR VCC OE
B B A3 B2 A2 B1
C C A5 A4 B4 B3

D D A7 B6 A6 B5

E E GND A8 B8 B7

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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
VCC Supply voltage range –0.5 7 V
(2)
Except I/O ports –0.5 7
VI Input voltage range V
I/O ports (2) (3) –0.5 7
VO Voltage range applied to any output in the high-impedance or power-off state (2) –0.5 7 V
(2) (3)
VO Output voltage range applied in the high or low state –0.5 VCC + 0.5 V
IIK Input clamp current VI < 0 –20 mA
IOK Output clamp current VO < 0 –50 mA
IO Continuous output current VO = 0 to VCC ±35 mA
Continuous current through VCC or GND ±70 mA

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
(3) This value is limited to 5.5-V maximum.

7.2 Handling Ratings

MIN MAX UNIT
Tstg Storage temperature range –65 150 °C
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
0 2000
pins (1)
V(ESD) Electrostatic discharge V
Charged device model (CDM), per JEDEC specification
0 1000
JESD22-C101, all pins (2)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

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7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) (1)
SN54LV245A (2) SN74LV245A
UNIT
MIN MAX MIN MAX
VCC Supply voltage 2 5.5 2 5.5 V
VCC = 2 V 1.5 1.5
VCC = 2.3 V to 2.7 V VCC × 0.7 VCC × 0.7
VIH High-level input voltage V
VCC = 3 V to 3.6 V VCC × 0.7 VCC × 0.7
VCC = 4.5 V to 5.5 V VCC × 0.7 VCC × 0.7
VCC = 2 V 0.5 0.5
VCC = 2.3 V to 2.7 V VCC × 0.3 VCC × 0.3
VIL Low-level input voltage V
VCC = 3 V to 3.6 V VCC × 0.3 VCC × 0.3
VCC = 4.5 V to 5.5 V VCC × 0.3 VCC × 0.3
VI Input voltage 0 5.5 0 5.5 V
High or low state 0 VCC 0 VCC
VO Output voltage V
3-state 0 5.5 0 5.5
VCC = 2 V –50 –50 µA
VCC = 2.3 V to 2.7 V –2 –2
IOH High-level output current
VCC = 3 V to 3.6 V –8 –8 mA
VCC = 4.5 V to 5.5 V –16 –16
VCC = 2 V 50 50 µA
VCC = 2.3 V to 2.7 V 2 2
IOL Low-level output current
VCC = 3 V to 3.6 V 8 8 mA
VCC = 4.5 V to 5.5 V 16 16
VCC = 2.3 V to 2.7 V 200 200
Δt/Δv Input transition rise or fall rate VCC = 3 V to 3.6 V 100 100 ns/V
VCC = 4.5 V to 5.5 V 20 20
TA Operating free-air temperature –55 125 –40 125 °C

(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs (SCBA004).
(2) Product Preview

7.4 Thermal Information

SN74LV245A
(1)
THERMAL METRIC DB DGV DW NS PW RGY UNIT
20 PINS
RθJA Junction-to-ambient thermal resistance 94.6 114.8 77.5 76.6 101.5 34.1
RθJC(top) Junction-to-case (top) thermal resistance 56.3 30.1 43.7 43.0 35.6 38.4
RθJB Junction-to-board thermal resistance 49.8 56.3 45.1 44.1 52.5 12.0
ψJT Junction-to-top characterization parameter 18.3 0.9 16.9 16.7 2.2 0.8 °C/W
ψJB Junction-to-board characterization
49.4 55.6 44.7 43.7 52.0 12.0
parameter
RθJC(bot) Junction-to-case (bottom) thermal
— — — — — 7.1
resistance

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report (SPRA953).

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7.5 Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)
–40°C to 85°C –40°C to 125°C
SN54LV245A (1)
PARAMETER TEST CONDITIONS VCC SN74LV245A SN74LV245A UNIT
MIN TYP MAX MIN TYP MAX MIN TYP MAX
2 V to
IOH = –50 µA VCC – 0.1 VCC – 0.1 VCC – 0.1
5.5 V

VOH IOH = –2 mA 2.3 V 2 2 2 V

IOH = –8 mA 3V 2.48 2.48 2.48
IOH = –16 mA 4.5 V 3.8 3.8 3.8
2 V to
IOL = 50 µA 0.1 0.1 0.1
5.5 V

VOL IOL = 2 mA 2.3 V 0.4 0.4 0.4 V

IOL = 8 mA 3V 0.44 0.44 0.44
IOL = 16 mA 4.5 V 0.55 0.55 0.55
0 to
II Control inputs VI = 5.5 V or GND ±1 ±1 ±1 µA
5.5 V
IOZ A or B port VO = VCC or GND 5.5 V ±5 ±5 ±5 µA
ICC VI = VCC or GND, IO = 0 5.5 V 20 20 20 µA
Ioff VI or VO = 0 to 5.5 V 0 5 5 5 µA
3.3 V 3 3
Ci Control inputs VI = VCC or GND pF
5V 3 3
3.3 V 5.5 5.5
Cio A or B port VO = VCC or GND pF
5V 5.5 5.5

(1) Product Preview

7.6 Switching Characteristics, VCC = 2.5 V ± 0.2 V

over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
–40°C to 125°C
FROM TO LOAD TA = 25°C SN54LV245A (1) SN74LV245A
PARAMETER SN74LV245A UNIT
(INPUT) (OUTPUT) CAPACITANCE
MIN TYP MAX MIN MAX MIN MAX MIN MAX
tpd A or B B or A 8.3 (2) 13 (2) 1 (2) 15 (2) 1 15 1 17
(2) (2) (2) (2)
ten OE A or B CL = 15 pF 11.8 19.9 1 22 1 22 1 24 ns
tdis OE A or B 11.8 (2) 18.1 (2) 1 (2) 20 (2) 1 20 1 22
tpd A or B B or A 11.2 15.9 1 18 1 18 1 21
ten OE A or B 14.1 22.7 1 26 1 26 1 28
CL = 50 pF ns
tdis OE A or B 17.6 23.1 1 25 1 25 1 27
tsk(o) 2 2

(1) Product Preview

(2) On products compliant to MIL-PRF-38535, this parameter is not production tested.

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7.7 Switching Characteristics, VCC = 3.3 V ± 0.3 V

over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
–40°C to 125°C
FROM TO LOAD TA = 25°C SN54LV245A (1) SN74LV245A
PARAMETER SN74LV245A UNIT
(INPUT) (OUTPUT) CAPACITANCE
MIN TYP MAX MIN MAX MIN MAX MIN MAX
tpd A or B B or A 5.9 (2) 8.4 (2) 1 (2) 10 (2) 1 10 1 11
(2) (2) (2)
ten OE A or B CL = 15 pF 8.2 13.2 1 15.5 (2) 1 15.5 1 16.5 ns
tdis OE A or B 9.6 (2) 16.5 (2) 1 (2) 19.5 (2) 1 19.5 1 20.5
tpd A or B B or A 7.9 11.9 1 13.5 1 13.5 1 14.5
ten OE A or B 9.9 16.7 1 19 1 19 1 20
CL = 50 pF ns
tdis OE A or B 13.9 19.8 1 22 1 22 1 23
tsk(o) 1.5 1.5

(1) Product Preview

(2) On products compliant to MIL-PRF-38535, this parameter is not production tested.

7.8 Switching Characteristics, VCC = 5 V ± 0.5 V

over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
–40°C to 125°C
FROM TO LOAD TA = 25°C SN54LV245A (1) SN74LV245A
PARAMETER SN74LV245A UNIT
(INPUT) (OUTPUT) CAPACITANCE
MIN TYP MAX MIN MAX MIN MAX MIN MAX
tpd A or B B or A 4.3 (2) 5.5 (2) 1 (2) 6.5 (2) 1 6.5 1 7
(2) (2) (2)
ten OE A or B CL = 15 pF 5.7 8.5 1 10.6 (2) 1 10 1 10.5 ns
tdis OE A or B 7.8 (2) 12.8 (2) 1 (2) 14.7 (2) 1 14.2 1 14.7
tpd A or B B or A 5.6 7.5 1 8.5 1 8.5 1 9
ten OE A or B 7 10.6 1 12 1 12 1 12.5
CL = 50 pF ns
tdis OE A or B 10.9 14.7 1 16 1 16 1 16.5
tsk(o) 1 1

(1) Product Preview

(2) On products compliant to MIL-PRF-38535, this parameter is not production tested.

7.9 Noise Characteristics (1)

VCC = 3.3 V, CL = 50 pF, TA = 25°C
SN74LV245A
PARAMETER UNIT
MIN TYP MAX
VOL(P) Quiet output, maximum dynamic VOL 0.5 0.8 V
VOL(V) Quiet output, minimum dynamic VOL –0.4 –0.8 V
VOH(V) Quiet output, minimum dynamic VOH 2.9 V
VIH(D) High-level dynamic input voltage 2.31 V
VIL(D) Low-level dynamic input voltage 0.99 V

(1) Characteristics are for surface-mount packages only.

7.10 Operating Characteristics

TA = 25°C
PARAMETER TEST CONDITIONS VCC TYP UNIT
3.3 V 20
Cpd Power dissipation capacitance Outputs enabled CL = 50 pF, f = 10 MHz pF
5V 25

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7.11 Typical Characteristics

10 14
TPD in ns TPD in ns
12
8
10

6
TPD (ns)

TPD (ns)
8

6
4

4
2
2

0 0
-100 -50 0 50 100 150 0 1 2 3 4 5 6
Temperature qC) D001
VCC D001
Figure 1. TPD vs Temperature at 3.3V Figure 2. TPD vs VCC

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8 Parameter Measurement Information

VCC
RL = 1 kΩ S1 Open
From Output Test From Output TEST S1
Under Test Point Under Test GND tPLH/tPHL Open
CL CL tPLZ/tPZL VCC
(see Note A) (see Note A) tPHZ/tPZH GND
Open Drain VCC

LOAD CIRCUIT FOR LOAD CIRCUIT FOR

TOTEM-POLE OUTPUTS 3-STATE AND OPEN-DRAIN OUTPUTS

VCC
Timing Input 50% VCC
tw 0V
th
VCC tsu
VCC
Input 50% VCC 50% VCC
Data Input 50% VCC 50% VCC
0V 0V
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PULSE DURATION SETUP AND HOLD TIMES

VCC VCC
Output
Input 50% VCC 50% VCC 50% VCC 50% VCC
Control
0V 0V

tPLH tPHL tPZL tPLZ

Output
VOH Waveform 1 ≈VCC
In-Phase 50% VCC 50% VCC
50% VCC S1 at VCC
Output VOL + 0.3 V
VOL (see Note B) VOL
tPHL tPLH tPZH tPHZ
Output
VOH VOH
Out-of-Phase Waveform 2 VOH – 0.3 V
50% VCC 50% VCC 50% VCC
Output S1 at GND
VOL ≈0 V
(see Note B)
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES
INVERTING AND NONINVERTING OUTPUTS LOW- AND HIGH-LEVEL ENABLING

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns.
D. The outputs are measured one at a time, with one input transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. t PZL and tPZH are the same as ten.
G. tPHL and tPLH are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.

Figure 3. Load Circuit and Voltage Waveforms

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9 Detailed Description

9.1 Overview
The SNx4LV245A devices are designed for asynchronous communication between data buses. The device
transmits data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the
direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so the buses are
effectively isolated.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow through the devices when they are powered down.

9.2 Functional Block Diagram

DIR

OE

A1

B1

To Seven Other Channels

Figure 4. Logic Diagram (Positive Logic)

9.3 Feature Description

• Allows down voltage translation from 5 V to 3.3 V
– Inputs accept voltage levels up to 5.5 V
• Slow edge rates minimize output ringing

9.4 Device Functional Modes

Table 1. Function Table

INPUTS
OPERATION
OE DIR
L L B data to A bus
L H A data to B bus
H X Isolation

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10 Application and Implementation

10.1 Application Information
The SNx4LV245A is a low-drive CMOS device that can be used for a multitude of bus-interface type applications
where output ringing is a concern. The low drive and slow edge rates will minimize overshoot and undershoot on
the outputs. The inputs can accept voltages to 5.5 V at any valid VCC making the device ideal for down
translation.

10.2 Typical Application

Regulated 5 V
Regulated 5 V

OE VCC VCC
OE
DIR DIR

A1 B1 A1 B1
µC
5-V LEDs, relays, 5-V LEDs, relays
or other µC
3.3-V µC or other 5-V LEDs, relays
system boards A8 B8 system boards A8 B8
or other or other
system boards system boards
GND GND

Figure 5. Typical Application Schematic

10.2.1 Design Requirements

This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus
contention, because it can drive currents that would exceed maximum limits. Outputs can be combined to
produce higher drive, but the high drive will also create faster edges into light loads; therefore, routing and load
conditions should be considered to prevent ringing.

10.2.2 Detailed Design Procedure

1. Recommended Input Conditions:
– Rise time and fall time specifications, see (Δt/ΔV) in Recommended Operating Conditions table.
– Specified high and low levels, see (VIH and VIL) in Recommended Operating Conditions table.
– Inputs are overvoltage tolerant, allowing them to go as high as 5.5 V at any valid VCC.
2. Recommend Output Conditions:
– Load currents should not exceed 35 mA per output and 70 mA total for the part.
– Outputs should not be pulled above VCC.

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Typical Application (continued)

10.2.3 Application Curves

AC245

HC245

LV245

LV

Figure 6. Switching Characteristics Comparison

11 Power Supply Recommendations

The power supply can be any voltage between the Min and Max supply voltage rating located in the
Recommended Operating Conditions table.
Each VCC terminal should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, 0.1 μF is recommended and if there are multiple VCC terminals then 0.01 μF or 0.022 μF is recommended
for each power terminal. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise.
A 0.1 μF and 1 μF are commonly used in parallel. The bypass capacitor should be installed as close to the
power terminal as possible for best results.

12 Layout

12.1 Layout Guidelines

When using multiple bit logic devices inputs should not ever float.
In many cases, functions or parts of functions of digital logic devices are unused, for example, when only two
inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such input pins should not be
left unconnected because the undefined voltages at the outside connections result in undefined operational
states. Specified in Figure 7 are the rules that must be observed under all circumstances. All unused inputs of
digital logic devices must be connected to a high or low bias to prevent them from floating. The logic level that
should be applied to any particular unused input depends on the function of the device. Generally they will be
tied to GND or VCC, whichever makes more sense or is more convenient. It is generally acceptable to float
outputs unless the part is a transceiver. If the transceiver has an output enable pin, it will disable the outputs
section of the part when asserted. This will not disable the input section of the I/Os so they cannot float when
disabled.

12.2 Layout Example

Vcc
Input

Unused Input Output Output

Unused Input

Input

Figure 7. Layout Diagram

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13 Device and Documentation Support

13.1 Related Links

The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.

Table 2. Related Links

TECHNICAL TOOLS & SUPPORT &
PARTS PRODUCT FOLDER SAMPLE & BUY
DOCUMENTS SOFTWARE COMMUNITY
SN54LV245A Click here Click here Click here Click here Click here
SN74LV245A Click here Click here Click here Click here Click here

13.2 Trademarks
All trademarks are the property of their respective owners.
13.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

13.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

14 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

14 Submit Documentation Feedback Copyright © 1997–2014, Texas Instruments Incorporated

Product Folder Links: SN54LV245A SN74LV245A

 PACKAGE OPTION ADDENDUM

www.ti.com 6-Feb-2020

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

SN74LV245ADBR ACTIVE SSOP DB 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LV245A
& no Sb/Br)
SN74LV245ADGVR ACTIVE TVSOP DGV 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LV245A
& no Sb/Br)
SN74LV245ADW ACTIVE SOIC DW 20 25 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LV245A
& no Sb/Br)
SN74LV245ADWE4 ACTIVE SOIC DW 20 25 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LV245A
& no Sb/Br)
SN74LV245ADWR ACTIVE SOIC DW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LV245A
& no Sb/Br)
SN74LV245ANSR ACTIVE SO NS 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 74LV245A
& no Sb/Br)
SN74LV245ANSRG4 ACTIVE SO NS 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 74LV245A
& no Sb/Br)
SN74LV245APW ACTIVE TSSOP PW 20 70 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LV245A
& no Sb/Br)
SN74LV245APWG4 ACTIVE TSSOP PW 20 70 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LV245A
& no Sb/Br)
SN74LV245APWR ACTIVE TSSOP PW 20 2000 Green (RoHS NIPDAU | SN Level-1-260C-UNLIM -40 to 125 LV245A
& no Sb/Br)
SN74LV245APWRE4 ACTIVE TSSOP PW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LV245A
& no Sb/Br)
SN74LV245APWRG3 ACTIVE TSSOP PW 20 2000 Green (RoHS SN Level-1-260C-UNLIM -40 to 125 LV245A
& no Sb/Br)
SN74LV245APWRG4 ACTIVE TSSOP PW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LV245A
& no Sb/Br)
SN74LV245ARGYR ACTIVE VQFN RGY 20 3000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 LV245A
& no Sb/Br)
SN74LV245AZQNR LIFEBUY BGA ZQN 20 1000 Green (RoHS SNAGCU Level-1-260C-UNLIM -40 to 85 LV245A
MICROSTAR & no Sb/Br)
JUNIOR

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 6-Feb-2020

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 21-May-2020

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74LV245ADBR SSOP DB 20 2000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1
SN74LV245ADGVR TVSOP DGV 20 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74LV245ADWR SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.0 Q1
SN74LV245ANSR SO NS 20 2000 330.0 24.4 8.4 13.0 2.5 12.0 24.0 Q1
SN74LV245APWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1
SN74LV245APWR TSSOP PW 20 2000 330.0 16.4 6.95 7.0 1.4 8.0 16.0 Q1
SN74LV245APWRG3 TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1
SN74LV245APWRG4 TSSOP PW 20 2000 330.0 16.4 6.95 7.0 1.4 8.0 16.0 Q1
SN74LV245ARGYR VQFN RGY 20 3000 330.0 12.4 3.8 4.8 1.6 8.0 12.0 Q1
SN74LV245AZQNR BGA MI ZQN 20 1000 330.0 12.4 3.3 4.3 1.6 8.0 12.0 Q1
CROSTA
R JUNI
OR

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 21-May-2020

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74LV245ADBR SSOP DB 20 2000 367.0 367.0 38.0
SN74LV245ADGVR TVSOP DGV 20 2000 367.0 367.0 35.0
SN74LV245ADWR SOIC DW 20 2000 367.0 367.0 45.0
SN74LV245ANSR SO NS 20 2000 367.0 367.0 45.0
SN74LV245APWR TSSOP PW 20 2000 364.0 364.0 27.0
SN74LV245APWR TSSOP PW 20 2000 367.0 367.0 38.0
SN74LV245APWRG3 TSSOP PW 20 2000 364.0 364.0 27.0
SN74LV245APWRG4 TSSOP PW 20 2000 367.0 367.0 38.0
SN74LV245ARGYR VQFN RGY 20 3000 367.0 367.0 35.0
SN74LV245AZQNR BGA MICROSTAR ZQN 20 1000 350.0 350.0 43.0
JUNIOR

Pack Materials-Page 2
 PACKAGE OUTLINE
DB0020A SCALE 2.000
SSOP - 2 mm max height
SMALL OUTLINE PACKAGE

C
8.2
TYP
A 7.4
0.1 C
PIN 1 INDEX AREA SEATING
18X 0.65 PLANE
20
1

2X
7.5
5.85
6.9
NOTE 3

10
11 0.38
20X
0.22
5.6 0.1 C A B
B
5.0
NOTE 4

2 MAX
(0.15) TYP 0.25
SEE DETAIL A GAGE PLANE

0.95 0.05 MIN

0 -8 0.55

DETAIL A
A 15

TYPICAL

4214851/B 08/2019

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-150.

www.ti.com
 EXAMPLE BOARD LAYOUT
DB0020A SSOP - 2 mm max height
SMALL OUTLINE PACKAGE

20X (1.85) SYMM

1 (R0.05) TYP

20X (0.45) 20

SYMM
18X (0.65)

10 11

(7)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 10X

SOLDER MASK METAL UNDER SOLDER MASK

METAL
OPENING SOLDER MASK OPENING

EXPOSED METAL EXPOSED METAL

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

NON-SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)
SOLDER MASK DETAILS
15.000

4214851/B 08/2019
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DB0020A SSOP - 2 mm max height
SMALL OUTLINE PACKAGE

20X (1.85) SYMM

(R0.05) TYP
1
20X (0.45) 20

SYMM
18X (0.65)

10 11

(7)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE: 10X

4214851/B 08/2019
NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
 MECHANICAL DATA

MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000

DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE

24 PINS SHOWN

0,23
0,40 0,07 M
0,13
24 13

0,16 NOM
4,50 6,60
4,30 6,20

Gage Plane

0,25

0°–
8°
0,75
1 12
0,50
A

Seating Plane

0,15
1,20 MAX 0,08
0,05

PINS **
14 16 20 24 38 48 56
DIM

A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40

A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20

4073251/E 08/00

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 GENERIC PACKAGE VIEW
RGY 20 VQFN - 1 mm max height
3.5 x 4.5, 0.5 mm pitch PLASTIC QUAD FGLATPACK - NO LEAD

This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4225264/A

www.ti.com
 PACKAGE OUTLINE
RGY0020A SCALE 3.000
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

3.65 B
A
3.35

PIN 1 INDEX AREA

4.65
4.35

1.0
0.8

SEATING PLANE
0.05
0.00 0.08 C
2.05 0.1

2X 1.5
(0.2) TYP
10 11 EXPOSED
THERMAL PAD
9
12
14X 0.5

2X SYMM 21
3.05 0.1
3.5

2
19
0.30
1 20 20X
PIN 1 ID 0.18
SYMM
0.1 C A B
0.5 0.05
20X
0.3
4225320/A 09/2019

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com
 EXAMPLE BOARD LAYOUT
RGY0020A VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

(2.05)
SYMM
1 20
20X (0.6)

2
19

20X (0.24)

(1.275)

(4.3)
SYMM 21
(3.05)

14X (0.5)

(0.775) 12
9

(R0.05) TYP

( 0.2) TYP
VIA 10 11
(0.75) TYP

(3.3)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:18X

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

SOLDER MASK
METAL OPENING

EXPOSED EXPOSED
METAL SOLDER MASK METAL UNDER
OPENING METAL SOLDER MASK

NON SOLDER MASK

SOLDER MASK
DEFINED
DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4225320/A 09/2019

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com
 EXAMPLE STENCIL DESIGN
RGY0020A VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

SYMM

4X (0.92)

1 20 (R0.05) TYP

20X (0.6)

2
19

20X (0.24)

4X
(1.33)

21
SYMM

(4.3)
(0.77)

14X (0.5)

(0.56)
9 12

METAL
TYP
10 11
(0.75)
TYP
(3.3)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 21
78% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X

4225320/A 09/2019

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.

www.ti.com
 PACKAGE OUTLINE
DW0020A SCALE 1.200
SOIC - 2.65 mm max height
SOIC

10.63 SEATING PLANE

TYP
9.97
PIN 1 ID 0.1 C
A
AREA
18X 1.27
20
1

13.0 2X
12.6 11.43
NOTE 3

10
11
0.51
20X
7.6 0.31 2.65 MAX
B 0.25 C A B
7.4
NOTE 4

0.33
TYP
0.10

0.25
SEE DETAIL A GAGE PLANE

1.27 0.3
0 -8 0.40 0.1

DETAIL A
TYPICAL

4220724/A 05/2016

NOTES:

1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side.
5. Reference JEDEC registration MS-013.

www.ti.com
 EXAMPLE BOARD LAYOUT
DW0020A SOIC - 2.65 mm max height
SOIC

20X (2) SYMM

1
20

20X (0.6)

18X (1.27)

SYMM

(R0.05)
TYP

10 11

(9.3)

LAND PATTERN EXAMPLE

SCALE:6X

SOLDER MASK METAL UNDER SOLDER MASK

METAL OPENING
OPENING SOLDER MASK

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4220724/A 05/2016
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DW0020A SOIC - 2.65 mm max height
SOIC

20X (2)
SYMM
1
20

20X (0.6)

18X (1.27)

SYMM

10 11

(9.3)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:6X

4220724/A 05/2016
NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
 IMPORTANT NOTICE AND DISCLAIMER

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