Schematic Vinafix - VN - LA-D301P - R10 - 1218a - HW - PWR
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Ryzal FirmansaSchematic Vinafix - VN - LA-D301P - R10 - 1218a - HW - PWR
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Ryzal FirmansaA B C D E
Compal Confidential
Model Name : B4DBU(WIFI) / B4DBG(LTE)
File Name : LA-D301P
1 1
BOM P/N:43
ZZZ UC1
LA-D301P S IC FJ8066201931104 SR2EU D1 2.3G ABO!
DAA000BG000 CPU_2NB0@
Compal Confidential
DA2@ SA000092NB0
ZZZ UC1
LS-D303P FUN/B S IC FJ8066201930409 SR2EY D1 2.3G ABO!
DA400299000 CPU_2OB0@
DA2@ SA000092OB0
ZZZ
UC1
2 LS-D302P USB/B
DA6001HX000
DA2@ B4DBU(WIFI) / B4DBG(LTE) S IC FJ8066201930408 SR2EZ D1 2.5G ABO!
CPU_2P90@
SA000092P90
2
M/B Schematics Document
ZZZ
UC1
LS-A133P
DA600101010
DA2@ S IC FJ8066201924931 QJKM D1 2.4G ABO!
CPU_2T50@
ZZZ
Skylake U Processor + DDR4 + Nvidia N16X SA000092T50
UC1
LS-D301P LID/B
DA400272000
DA2@ S IC FJ8066201924931 SR2F0 D1 2.4G ABO!
CPU_2T80@
ZZZ SA000092T80
UC1
3
LS-B734P
DA6001B8010
DA2@
ZZZ
2015-12-09 S IC FJ8066201924950 QJKH D1 2.6G ABO!
CPU_2U70@
3
SA000092U70
HDMI LOGO
Rev:1.0 UC1
RO0000003HM
HDMI@
ZZZ S IC FJ8066201924950 SR2F1 D1 2.6G ABO!
CPU_2U80@
SA000092U80
LS-B732P
DA4001YF010
DA2@
ZZZ
DAZ PCB
DAZ1IB00100
DAZ@
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2014/02/14 Deciphered Date 2015/02/14 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
LA-D301P 0.1
Date: Thursday, December 17, 2015 Sheet 1 of 63
A B C D E
A B C D E
Compal Confidential 260pin DDR4-SO-DIMM X1
page 18
GPU Memory BUS(DDR4)
Nvidia N16x Dual Channel
PEG(DIS) PEG 2.0x4 5GT/s PER LANE
with DDR3 x4 CLK=100MHz
Intel Skylake U 1.2V DDR4 1866/2133 DDR4-ON BOARD 4G 8Gbx16
1
page21~27 eDP Conn. eDP
1
page28
Skylake U page 19 ,20
CRT SW. DP to VGA DDI1 Skylake PCH-LP(MCP)
CRT Conn.
DOCK CONN.
page 30
PI3V713
page 30
RTD2168 page 29 (SKL-U_2+2) USB 3.0 WLAN Module CMOS
DOCK CONN.
DP SW conn x3 for BT Camera
page 44
HDMI/DP DDI2 USB port 3 USB port 1,2,4 USB port 5 USB port 7
PS 8338 Processor
page 31 page 44 page 39 page 38 page 28
HDMI CONN
page 32
Thunderbolt USBx8
PCIE Dual Core + GT2 3.3V 48MHz
AR4C page 40~41
MIDI MIDI RJ45 Conn. TYPE-C CONN port 9,10
HD Audio 3.3V 24MHz
LTE Finger
CHC CHB page 36 page 42 Power delivery Card Print
SPI USB port 9
page 42
2
15W USB port 8
2
page 38 page 45
LAN SW. PCI-Express x 8 (PCIE2.0 5GT/s) CLK=100MHz
1356pin BGA
page 35 SATA x 6 (GEN2 3.0GT/S ,GEN3 6GT/S) page 6~17
MIDI CLK=100MHz
SPI ROM x2 HDA Codec
port 5 port 6,8 port 11
ALC3225 Combo Jack
(8M+8M) HP (CTIA)
LAN(GbE) NGFF Card Card reader LPC BUS MIC
page 8 page 37
Intel I219 WLAN+BT+Wigig RTS5229 CLK=33MHz
LINE IN page 37
(Combo) Conn. GEN3 GEN3 SM BUS
page 35 page 38 page 45 port 2 port 0
mSATA SATA
HDD TPM NFC Int.
NGFF Card NPCT650 Module Speaker
Conn.
page 34 page 33
page 45 page 34 page 37
DOCK CONN.
3 3
G-Sensor
LS-A131P Fan ENE KB9022 LIS3DHTR page 44
FUN/B page 45 page 33
page 46 page 43
LS-D302
USB/B page 39
LS-A133P LS-B732P Touch Pad Int.KBD
CardReader/B TP/B
page 45 page 45 RTC CKT. page 45 page 45
page 14
LS-D301P LS-A136P
LID/B page 45 DC/DC Interface CKT.
4
Docking1/B page 44 4
page 47
LS-B734P LS-A137P
FP/B Docking2/B Power Circuit DC/DC
page 45 Security Classification Compal Secret Data Compal Electronics, Inc.
page 48~60
Issued Date 2014/02/14 Deciphered Date 2015/02/14 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagrams
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D301P
Date: Thursday, December 17, 2015 Sheet 2 of 63
A B C D E
A B C D E
Board ID Table for AD channel
Vcc 3.3V +/- 5% BOARD ID Table
Ra 100K +/- 5% Power State
SIGNAL
Board ID PCB Revision
Board ID Rb V BID min V BID typ V BID max EC AD3 STATE SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock 0 0.1
0 0 0 V 0 V 0.300 V 0x00 - 0x0B 1
S0 (Full ON) HIGH HIGH HIGH ON ON ON ON
0.2
1 12K +/- 1% 0.347 V 0.345 V 0.360 V 0x0C - 0x1C 2 0.3
2 15K +/- 1% 0.423 V 0.430 V 0.438 V 0x1D - 0x26 S3 (Suspend to RAM) LOW HIGH HIGH ON ON OFF OFF 3 1.0
3 20K +/- 1% 0.541 V 0.550 V 0.559 V 0x27 - 0x30
1
S4 (Suspend to Disk) LOW LOW HIGH ON OFF OFF OFF
4 1
4 27K +/- 1% 0.691 V 0.702 V 0.713 V 0x31 - 0x3B
5
5 33K +/- 1% 0.807 V 0.819 V 0.831 V 0x3C - 0x46 S5 (Soft OFF) LOW LOW LOW ON OFF OFF OFF 6
6 43K +/- 1% 0.978 V 0.992 V 1.006 V 0x47 - 0x54 7
7 56K +/- 1% 1.169 V 1.185 V 1.200 V 0x55 - 0x64
BOM Structure Table
BOM Option Table BOM Option Table Voltage Rails
Power Plane Description S0 S3 S4/S5
Item BOM Structure Item BOM Structure Adapter power supply N/A N/A N/A
+19V_VIN
Unpop @ dGPU VGA@ +17.4V_BATT Battery power supply N/A N/A N/A
Connector CONN@ SAMSUNG DDR4 X76SAM@ +19VB AC or battery power rail for power circuit. N/A N/A N/A
EMC requirement EMC@ N16S-GT SGT@ +VCC_CORE Processor IA Cores Power Rail ON OFF OFF
EMC requirement depop @EMC@ Without WiGi Funct i on NOWG@ +VCC_GT Processor Graphics Power Rails ON OFF OFF
EMI requirement @EMC@/EMI@ HDD Redriver X76TI@/X76PAR@ +VCC_SA System Agent power rail ON OFF OFF
Thunderbolt Funct i on TBT@ GPU CG6 funct i on VGM@ +0.6VS_VTT DDR +0.6VS power rail for DDR terminator . ON OFF OFF
RF requirement @RF@/RF@ VRAM BOM Select X76@ +1.0VALW_PRIM +1.0V Always power rail ON ON ON*1
LTE Funct i on 3G@ +1.0V_VCCSTU Sustain voltage for processor in Standby modes ON ON OFF
2 SR@/DR@ 2
UMA only UMA@ Single/Dual Rank (DR@ is not been used +VCCIO CPU IO power rail ON OFF OFF
VPRO Funct i on VPRO@/NOVPRO@ in this project) +1.0VS_VCCSTG +1.0VALW_PRIM Gated version of VCCST ON OFF OFF
VGA EMI Requirement @VGA_EMI@/VGA_EMI@ PD Funct i on PD@ +1.2V_VDDQ DDR4 +1.2V Power Rail ON ON OFF
VGA UNPOP @VGA@ CPU Code QH7Y@ +1.8VALW_PRIM +1.8V Always power rail ON ON ON*1
VGA RF Requirement @RF@_VGA@ CPU Code QH7Y@ +1.8VS System +1.8V power rail ON OFF OFF
VGA Power 22@/23E@ +3VLP +19VB to +3VLP power rail for suspend power ON ON ON
GC6 Funct i on GC6@/NOGC6@/NGC6
+3VALW System +3VALW always on power rail ON ON ON*1
INTEL CMC CMC@ +3VS System +3V power rail ON OFF OFF
ESPI ESPI @ +5VALW +5V Always power rail ON ON ON
+5VS System +5V power rail ON OFF OFF
I2C Address Table +RTCVCC RTC Battery Power ON ON ON
+1.05VSDGPU +1.05VS power rail for GPU ON OFF OFF
Address(8bit)
BUS Device Address(7 bit) +1.5VSDGPU +1.5VS power rail for GPU ON OFF OFF
Write Read
+3VSDGPU_AON +3VS power rail for GPU(AON rails) ON OFF OFF
I2C_0 (+3VS) Reserved (Touch Panel) +3VSDGPU_MAIN +3VS power rail for GPU GC62.0 ON OFF OFF
I2C_1 (+3VS) TM-P2969-001 (TP) 0x2C +VGA_CORE Core power for descrete GPU ON OFF OFF
SB8787-1200 (TP-ELAN) 0x16 +2.5V DDR4 +2.5V Power Rail ON ON OFF
3
DIMM1 0xA0 3
SOC_SMBCLK +3VS DIMM2 0xA4
LIS3DHTR(G-Sensor) 0x30
SOC_SML1CLK +3VS N16S-GT (VGA) 0x9E
PCH-LP (SOC) 0x90 Note : ON*1 means power plane is ON only when WOL enable and RTC wake at BIOS setting, otherwise it is OFF.
BQ24780 (Charger IC) 0x12
EC_SMB_CK1 +3VLP
BATTERY PACK 0x16
LAN 0xC8
SOC_SML0CLK +3VS
NFC 0x28
43 level BOM table
43 Level Description BOM Structure
431A0NBOL01 SMT MB AD301 B4DBG QJFC 2.3G UMA HDMI 3G@/CMC@/DA2@/SR@/EMC@/EMI@/ESD@/HDMI@/NOVPRO@/PD@/TBT@/UMA@/X76PAR@/X76SAM@/RF@
431A0NBOL02 SMT MB AD301 B4DBG QJ8M 2.4G UMA HDMI 3G@/CMC@/DA2@/SR@/EMC@/EMI@/ESD@/HDMI@/NOVPRO@/PD@/TBT@/UMA@/X76PAR@/X76SAM@/RF@
431A0NBOL03 SMT MB AD301 B4DBG QJKP 2.3G DIS HDMI 3G@/CMC@/DA2@/SR@/EMC@/EMI@/ESD@/GC6@/HDMI@/PD@/SGT@/TBT@/VGA@/VGA_EMI@/VPRO@/X76PAR@/X76SAM@/RF@
431A0NBOL04 SMT MB AD301 B4DBG QJKK 2.5G DIS HDMI 3G@/CMC@/DA2@/SR@/EMC@/EMI@/ESD@/GC6@/HDMI@/PD@/SGT@/TBT@/VGA@/VGA_EMI@/VPRO@/X76PAR@/X76SAM@/RF@
4 4
Security Classification
2014/11/10
Compal Secret Data
2016/11/10 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
LA-D301P 0.2
Date: Thursday, December 17, 2015 Sheet 3 of 63
A B C D E
5 4 3 2 1
D D
C C
B B
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2014/11/10 Deciphered Date 2016/11/10 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power Map
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D301P
Date: Thursday, December 17, 2015 Sheet 4 of 63
5 4 3 2 1
A B C D E
PWR Sequence_SKL-U2+2_DDR4_Value_NON CS
+RTCVCC
tPCH01_Min : 9 ms
SOC_RTCRST#
+19VB
248us
+3VLP
240us
1 1
EC_ON
2.24ms
+5VALW
tPCH04_Min : 9 ms
+3VALW(+3VALW_DSW...)
tPCH34_Max : 20 ms
SPOK 1.23ms tPCH06_Min : 200 us (+3VALW stable (@95% of full value) to +1.0VALW_PRIM starting to ramp)
1.98ms
+1.8VALW_PRIM 396us
+1.8VALW_PG 1.032ms
+VCCPRIM_CORE(+1.0VALW_PRIM) tPCH03_Min : 10 ms
191.2ms
EC_RSMRST#
ON/OFF
tPCH43_Min : 95 ms
PBTN_OUT# 132ms Minimum duration of PWRBTN# assertion = 16mS. PWRBTN# can assert before or after RSMRST#
20.2ms
PM_SLP_S5# 147.6ms
2
tPCH18_Min : 90 us 2
ESPI_RST# 312.8ms
PM_SLP_S4# 39.2us
PM_SLP_S3# 73us
SYSON 3.67ms
SUSP# 14.16ms
+1.2V_VDDQ 4.6ms tCPU03 Max : 25 ms
164us
+1.0V_VCCSTU
tCPU04 Min : 100 ns
tCPU03 Max : 25 ms
+1.0VS_VCCSTG 9.32ms
+1.8VS: 10.14ms ; +3VS: 10.74ms
+5VS/+3VS/+1.8VS +5VS: 11.16ms
+1.5VS +1.5VS: 15.66ms tCPU00 Min : 1 ms
20.1ms
tCPU01 Min : 1 ms
3
EC_VCCST_PG 29.1ms 3
VR_ON 6.6us
tCPU19 Max : 100 ns
SM_PG_CTRL 80ns
tCPU18 Max : 35 us
+0.6VS_VTT 9.9us tCPU09 Min : 1 ms
127.6ms
+VCC_SA 2.2ms
VR_PWRGD 2.16ms
tCPU16 Min : 0 ns
PCH_PWROK (SYS_PWROK) tPLT05 Min : Platform dependent 9.96ms tCPU10 Min : 1 ms
30.1ms
+VCCIO
H_CPUPWRGD
PLT_RST# 151.6ms
+VCC_CORE / +VCC_GT 21.2ms
4 4
Security Classification
2014/11/10
Compal Secret Data
2016/11/10 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power Sequence
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
LA-D301P 0.2
Date: Thursday, December 17, 2015 Sheet 5 of 63
A B C D E
A B C D E
UC1A
Functional Strap Definitions
SKL-U
Rev_0.53
E55 C47
<29> SOC_DP1_N0 DDI1_TXN[0] EDP_TXN[0] EDP_TXN0 <28>
<DP to VGA> F55 C46
<29> SOC_DP1_P0 DDI1_TXP[0] EDP_TXP[0] EDP_TXP0 <28>
#543016 PDG0.9 P.775 E58 D46
<29> SOC_DP1_N1 DDI1_TXN[1] EDP_TXN[1] EDP_TXN1 <28>
F58 C45
<29> SOC_DP1_P1 DDI1_TXP[1] EDP_TXP[1] EDP_TXP1 <28>
DDPB_CTRLDATA/ GPP_E19 (Internal Pull Down): F53 A45 <eDP>
DDI1_TXN[2] EDP_TXN[2] EDP_TXN2 <28>
G53 B45
DDPC_CTRLDATA/ GPP_E21 (Internal Pull Down): F56 DDI1_TXP[2] EDP_TXP[2] A47
EDP_TXP2 <28>
DDI1_TXN[3] EDP_TXN[3] EDP_TXN3 <28>
DDPD_CTRLDATA/ GPP_E23 (Internal Pull Down): G56
DDI1_TXP[3] EDP_TXP[3]
B47
EDP_TXP3 <28>
(Sampled:Rising edge of PCH_PWROK) C50 E45 EDP_AUXN <28>
Display Port B/C/D Detected <31> CPU_DP2_N0
D50 DDI2_TXN[0] DDI EDP EDP_AUXN F45 EDP_AUXP <28>
<31> CPU_DP2_P0 DDI2_TXP[0] EDP_AUXP
0 =Port is not detected. < PS8338 > <31> CPU_DP2_N1
C52
DDI2_TXN[1]
D52 B52
1
1 =Port is detected. Docking HDMI+TBT <31> CPU_DP2_P1
A50 DDI2_TXP[1] EDP_DISP_UTIL
1
<31> CPU_DP2_N2 DDI2_TXN[2] SOC_DP1_AUXN
B50 G50
<31> CPU_DP2_P2 DDI2_TXP[2] DDI1_AUXN SOC_DP1_AUXP SOC_DP1_AUXN <29>
D51 F50 DP Aux (Port B for VGA)
<31> CPU_DP2_N3 DDI2_TXN[3] DDI1_AUXP SOC_DP2_AUXN SOC_DP1_AUXP <29>
C51 E48
<31> CPU_DP2_P3 DDI2_TXP[3] DDI2_AUXN SOC_DP2_AUXP DDI2_AUX_DN <31> +3VS
F48 PS8338
+3VS DDI2_AUXP DDI2_AUX_DP <31>
COMPENSATION PU FOR eDP G46 RC212
DISPLAY SIDEBANDS DDI3_AUXN F46 10K_0402_5%
+VCCIO L13 DDI3_AUXP EC_SCI# 1 @ 2
R4955 2 1 2.2K_0402_5% SOC_DP1_CTRL_DATA L12 GPP_E18/DDPB_CTRLCLK L9 SOC_DP1_HPD
GPP_E19/DDPB_CTRLDATA GPP_E13/DDPB_HPD0 CPU_HDMI_HPD SOC_DP1_HPD <29> From VGA Trans.
L7 CPU_HDMI_HPD <31> EC_SCI# SOC internal PU
EDP_COMP DDI2_CTRL_CK GPP_E14/DDPC_HPD1 From DP MUX
RC1 1 2 <31> DDI2_CTRL_CK N7 L6
24.9_0402_1% PS8338 HDMI DDC DDI2_CTRL_DATA N8 GPP_E20/DDPC_CTRLCLK GPP_E15/DDPD_HPD2 N9 EC_SCI#
<31> DDI2_CTRL_DATA GPP_E21/DDPC_CTRLDATA GPP_E16/DDPE_HPD3 CPU_EDP_HPD EC_SCI# <43>
L10 CPU_EDP_HPD <28>
TBT_DP1_CTRL_CLK0_0402_5% 2 GPP_E17/EDP_HPD From eDP
#54 016 PDG0.9 P.186 <40> TBT_DP1_CTRL_CLK @ 1RC238 N11
TBT_DP1_CTRL_DATA
0_0402_5% 2 @ 1RC245 N12 GPP_E22/DDPD_CTRLCLK R12 ENBKL
Trace width= 0 mils,Spacing= 5mil,Max length=100mils AR HDMI DDC
<40> TBT_DP1_CTRL_DATA GPP_E23/DDPD_CTRLDATA EDP_BKLTEN ENBKL <43>
R11 SOC_BKL_PWM
EDP_COMP EDP_BKLTCTL SOC_ENVDD SOC_BKL_PWM <28>
#54 016 PDG0.9 P.75 E52 1 OF 20 U13
+1.0V_VCCST EDP_RCOMP EDP_VDDEN SOC_ENVDD <28>
PH 1K to VCCST
CPU over 1 0 degree will output low force S0->S5 SKL-U_BGA1356
+1.0VS_VCCSTG @ #545659 PCH EDS 0.7 P.108
SCI capability is available on all GPIOs,
1 2 H_THERMTRIP# while NMI and SMI capability is available on selected GPIOs only.
Below are the PCH GPIOs that can be routed to generate SMI# or NMI:
1
RC2 1K_0402_5%
‧ GPP B14, GPP B 0, GPP B
RC3 UC1D SKL-U
‧ GPP C :
1K_0402_5% follow INTEL check list to reserve D63 test point Rev_0.53 ‧ GPP D 4: 0
@ T167 CATERR# D63 ‧ GPP E 8: 0 , GPP E 16: 1
H_PECI A54 CATERR#
<43> H_PECI H_PROCHOT#_R C65 PECI
2
<43,50> H_PROCHOT# 1 2 JTAG
RC4 499_0402_1% H_THERMTRIP# C63 PROCHOT#
A65 THERMTRIP# B61 CPU_XDP_TCK0
SKTOCC# PROC_TCK D60 SOC_XDP_TDI
CPU MISC PROC_TDI
XDP_BPM#0 C55 A61 SOC_XDP_TDO
@ T160 XDP_BPM#1 BPM#[0] PROC_TDO SOC_XDP_TMS
@ T161 D55 C60
B54 BPM#[1] PROC_TMS B59 SOC_XDP_TRST#
2
C56 BPM#[2] PROC_TRST# 2
BPM#[3] B56 PCH_JTAG_TCK1
I2C_TS_INT# A6 PCH_JTAG_TCK D59 SOC_XDP_TDI
@ T170 GPP_E3/CPU_GP0 PCH_JTAG_TDI SOC_XDP_TDO
A7 A56
CC52 @EMC@ BA5 GPP_E7/CPU_GP1 PCH_JTAG_TDO C59 SOC_XDP_TMS
@ T169 GPP_B3/CPU_GP2 PCH_JTAG_TMS SOC_XDP_TRST#
.1U_0402_16V7K <35,44> DET_SIG#_R AY5 C61
2 1 H_PECI GPP_B4/CPU_GP3 PCH_TRST# A59 CPU_XDP_TCK0
RC5 2 1 49.9_0402_1% CPU_POPIRCOMP AT16 JTAGX
PDG0.9 P.771 PROC_POPIRCOMP
CC53 @EMC@ PROC_POPIRCOMP/PCH_OPIRCOMP RC6 2 1 49.9_0402_1% PCH_OPIRCOMP AU16
.1U_0402_16V7K RC7 2 1 49.9_0402_1% EDRAM_OPIO_RCOMP H66 PCH_OPIRCOMP
H_PROCHOT#_R
PD 50ohm OPCE_RCOMP
2 1 RC8 2 1 49.9_0402_1% EOPIO_RCOMP H65
OPC_RCOMP
#544669 CRB RVP7 1.0
Reserved for ESD 2014/9/17 EDRAM_OPIO_RCOMP/EOPIO_RCOMP 4 OF 20
PD50ohm SKL-U_BGA1356
@
+1.0VS_VCCSTG
RC11 2 CMC@ 1 51_0402_5% SOC_XDP_TMS CMC@
RPC2
Place to CPU side
RC13 2 CMC@ 1 51_0402_5% SOC_XDP_TDI SOC_XDP_TMS
SOC_XDP_TDI
1
2
8
7
XDP_TMS
XDP_TDI XDP CONN
RC15 2 CMC@ 1 51_0402_5% SOC_XDP_TDO SOC_XDP_TRST# 3 6 XDP_TRST# +1.0VALW_PRIM +1.0V_XDP
SOC_XDP_TDO 4 5 XDP_TDO
RC12 @ 0_0603_5%
3 0_0804_8P4R_5% 1 2 3
APS CONN <17> XDP_ITP_PMODE
CFG3
XDP_ITP_PMODE
RC55 1
RC56 1
@
@
2 0_0402_5% XDP_PRSENT_CPU
2 0_0402_5% XDP_HOOK6 JPCMC1 CMC_DEBUG_36P
+1.0V_XDP +1.0V_XDP
+3VALW +3VALW_PRIM OBS DATA JTAG/RC/HOOKS
JAPS1 RC31 1 CMC@ 2 1K_0402_5% XDP_ITP_PMODE CFG0 1 22
<17> CFG0 DATA_0 VCCOBS_AB
1 CFG1 3
1 <17> CFG1 DATA_1
<10,43,47> PM_SLP_S3# 2 CMC@ CFG2 5
2 XDP_PRSENT_CPU <17> CFG2 DATA_2
3 RC43 2 @ 1 0_0402_5% RPC15 CFG3 7
3 XDP_SPI_SI XDP_HOOK3 <17> CFG3 DATA_3 XDP_TRST#
<10> PM_SLP_S5# 4 <8> XDP_SPI_SI 1 8 CFG4 9 28
4 XDP_PRSENT_PCH PCH_JTAG_TCK1 XDP_TCK1 <17> CFG4 DATA_4 XDP_TRST* XDP_TDI
<10,43,47> PM_SLP_S4# 5 RC46 2 @ 1 0_0402_5% 2 7 CFG5 11 29
5 CPU_XDP_TCK0 XDP_TCK0 <17> CFG5 DATA_5 XDP_TDI XDP_TMS
<10,43> PM_SLP_A# 6 3 6 CFG6 13 30
6 XDP_SPI_IO2 XDP_PRSENT_PCH <17> CFG6 DATA_6 XDP_TMS XDP_TCK0
7 <8> XDP_SPI_IO2 4 5 CFG7 15 32
7 CPU_XDP_TCK0 <17> CFG7 DATA_7 XDP_TCK0 XDP_TCK1
8 RC35 2 CMC@ 1 51_0402_1% 31
9 8 0_0804_8P4R_5% CFG17 17 XDP_TCK1 35 XDP_TDO
<10> SOC_RTCRST# 9
Place to CPU side PCH_JTAG_TCK1 <17> CFG17 DATA_CLK_1P XDP_TDO
10 RC37 2 @ 1 51_0402_5% CFG16 21
PBTN_OUT#_R2 10 <17> CFG16 DATA_CLK_1N XDP_PREQ#
11 33 XDP_PREQ# <12>
12 11 CFG8 2 XDP_PREQ* 34 XDP_PRDY#
12 EC_RSMRST# <17> CFG8 DATA_8 XDP_PRDY* XDP_PRDY# <12>
<10> SYS_RESET# 13 RC151 2 @ 1 1K_0402_5% CFG0 <10,43> EC_RSMRST# RC23 1 CMC@ 2 1K_0402_5% XDP_HOOK0 CFG9 4
13 <17> CFG9 DATA_9 XDP_HOOK0
14 CFG10 6 27
14 <17> CFG10 DATA_10 HOOK_0 XDP_HOOK3
<10,43> PM_SLP_S0# 15 CFG11 8 25
15 <17> CFG11 DATA_11 HOOK_3 XDP_HOOK6
16 CFG12 10 26
16 <17> CFG12 DATA_12 HOOK_6
17 Follow 544924_Skylake_EDS_Vol_1_Rev_0.93 CFG13 12
17 <17> CFG13 DATA_13 XDP_PRSENT_PCH
18 CFG14 14 24
18 <17> CFG14 DATA_14 XDP_PRSNT_PCH* XDP_PRSENT_CPU
19 CFG15 16 23
GND <17> CFG15 DATA_15 XDP_PRSNT_CPU*
20
GND +3VALW_PRIM CFG19 18 19
<17> CFG19 DATA_CLK_2P GND
ACES_50506-01841-P01 CFG18 20 36
<17> CFG18 DATA_CLK_2N <MT> GND
CONN@
RC9 1 CMC@ 2 1K_0402_5% XDP_SPI_SI
4 4
INTEL_CMC_PRIMARY
CONN@
<10,43> PBTN_OUT#
RC53 2 @ 1 0_0402_5% PBTN_OUT#_R2 Security Classification
2014/11/10
Compal Secret Data
2016/11/10
Compal Electronics, Inc.
www.vinafix.vn
Issued Date Title
RC54 2 @ 1 0_0402_5% Deciphered Date
<43,45> ON/OFF#
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SKL-U(1/12)DDI,MSIC,XDP,EDP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D301P
Date: Thursday, December 17, 2015 Sheet 6 of 63
A B C D E
A B C D E
Interleaved Memory
1 1
SKL-U
UC1B SKL-U UC1C
Rev_0.53 Rev_0.53
AU53 DDR_A_CLK#0
19> DDR_A_D[0..15] DDR_A_D0 DDR0_CKN[0] DDR_A_CLK0 DDR_A_CLK#0 <19> <18> DDR_B_D[0..15] DDR_B_D0 DDR_B_CLK#0
AL71 AT53 DDR_A_CLK0 <19> AF65 AN45 DDR_B_CLK#0 <18>
DDR_A_D1 AL68 DDR0_DQ[0] DDR0_CKP[0] AU55 DDR_A_CLK#1 DDR_B_D1 AF64 DDR1_DQ[0]/DDR0_DQ[16] DDR1_CKN[0] AN46 DDR_B_CLK#1
DDR_A_D2 DDR0_DQ[1] DDR0_CKN[1] DDR_A_CLK1 @ T20 DDR_B_D2 DDR1_DQ[1]/DDR0_DQ[17] DDR1_CKN[1] DDR_B_CLK0 DDR_B_CLK#1 <18>
AN68 AT55 @ T19 AK65 AP45 DDR_B_CLK0 <18>
DDR_A_D3 AN69 DDR0_DQ[2] DDR0_CKP[1] DDR_B_D3 AK64 DDR1_DQ[2]/DDR0_DQ[18] DDR1_CKP[0] AP46 DDR_B_CLK1
DDR_A_D4 DDR0_DQ[3] DDR_A_CKE0 DDR_B_D4 DDR1_DQ[3]/DDR0_DQ[19] DDR1_CKP[1] DDR_B_CLK1 <18>
AL70 BA56 DDR_A_CKE0 <19,20> AF66
DDR_A_D5 AL69 DDR0_DQ[4] DDR0_CKE[0] BB56 DDR_A_CKE1 DDR_B_D5 AF67 DDR1_DQ[4]/DDR0_DQ[20] AN56 DDR_B_CKE0
DDR_A_D6 DDR0_DQ[5] DDR0_CKE[1] @ T21 DDR_B_D6 DDR1_DQ[5]/DDR0_DQ[21] DDR1_CKE[0] DDR_B_CKE1 DDR_B_CKE0 <18>
AN70 AW56 AK67 AP55 DDR_B_CKE1 <18>
DDR_A_D7 AN71 DDR0_DQ[6] DDR0_CKE[2] AY56 DDR_B_D7 AK66 DDR1_DQ[6]/DDR0_DQ[22] DDR1_CKE[1] AN55
DDR_A_D8 AR70 DDR0_DQ[7] DDR0_CKE[3] DDR_B_D8 AF70 DDR1_DQ[7]/DDR0_DQ[23] DDR1_CKE[2] AP53
DDR_A_D9 AR68 DDR0_DQ[8] AU45 DDR_A_CS#0 DDR_B_D9 AF68 DDR1_DQ[8]/DDR0_DQ[24] DDR1_CKE[3]
DDR_A_D10 DDR0_DQ[9] DDR0_CS#[0] DDR_A_CS#1 DDR_A_CS#0 <19,20> DDR_B_D10 DDR1_DQ[9]/DDR0_DQ[25] DDR_B_CS#0
AU71 AU43 @ T23 AH71 BB42 DDR_B_CS#0 <18>
DDR_A_D11 AU68 DDR0_DQ[10] DDR0_CS#[1] AT45 DDR_A_ODT0 DDR_B_D11 AH68 DDR1_DQ[10]/DDR0_DQ[26] DDR1_CS#[0] AY42 DDR_B_CS#1
DDR_A_D12 DDR0_DQ[11] DDR0_ODT[0] DDR_A_ODT1 DDR_A_ODT0 <19,20> DDR_B_D12 DDR1_DQ[11]/DDR0_DQ[27] DDR1_CS#[1] DDR_B_ODT0 DDR_B_CS#1 <18>
AR71 AT43 @ T22 AF71 BA42 DDR_B_ODT0 <18>
DDR_A_D13 AR69 DDR0_DQ[12] DDR0_ODT[1] DDR_B_D13 AF69 DDR1_DQ[12]/DDR0_DQ[28] DDR1_ODT[0] AW42 DDR_B_ODT1
DDR_A_D14 DDR0_DQ[13] DDR_A_MA5 DDR_B_D14 DDR1_DQ[13]/DDR0_DQ[29] DDR1_ODT[1] DDR_B_ODT1 <18>
AU70 BA51 DDR_A_MA5 <19,20> AH70
DDR_A_D15 AU69 DDR0_DQ[14] DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5] BB54 DDR_A_MA9 DDR_B_D15 AH69 DDR1_DQ[14]/DDR0_DQ[30] AY48 DDR_B_MA5
19> DDR_A_D[16..31] DDR_A_D16 DDR0_DQ[15] DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9] DDR_A_MA6 DDR_A_MA9 <19,20> <18> DDR_B_D[16..31] DDR_B_D16 DDR1_DQ[15]/DDR0_DQ[31] DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5] DDR_B_MA9 DDR_B_MA5 <18>
BB65 BA52 DDR_A_MA6 <19,20> AT66 AP50 DDR_B_MA9 <18>
DDR_A_D17 AW65 DDR0_DQ[16]/DDR0_DQ[32] DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6] AY52 DDR_A_MA8 DDR_B_D17 AU66 DDR1_DQ[16]/DDR0_DQ[48] DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9] BA48 DDR_B_MA6
DDR_A_D18 DDR0_DQ[17]/DDR0_DQ[33] DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8] DDR_A_MA7 DDR_A_MA8 <19,20> DDR_B_D18 DDR1_DQ[17]/DDR0_DQ[49] DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6] DDR_B_MA8 DDR_B_MA6 <18>
AW63 AW52 DDR_A_MA7 <19,20> AP65 BB48 DDR_B_MA8 <18>
DDR_A_D19 AY63 DDR0_DQ[18]/DDR0_DQ[34] DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7] AY55 DDR_A_BG0 DDR_B_D19 AN65 DDR1_DQ[18]/DDR0_DQ[50] DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8] AP48 DDR_B_MA7
DDR_A_D20 DDR0_DQ[19]/DDR0_DQ[35] DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0] DDR_A_MA12 DDR_A_BG0 <19,20> DDR_B_D20 DDR1_DQ[19]/DDR0_DQ[51] DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7] DDR_B_BS2 DDR_B_MA7 <18>
BA65 AW54 DDR_A_MA12 <19,20> AN66 AP52 DDR_B_BG0 <18>
DDR_A_D21 AY65 DDR0_DQ[20]/DDR0_DQ[36] DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] BA54 DDR_A_MA11 DDR_B_D21 AP66 DDR1_DQ[20]/DDR0_DQ[52] DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0] AN50 DDR_B_MA12
DDR_A_D22 DDR0_DQ[21]/DDR0_DQ[37] DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11] M_A_ACT# DDR_A_MA11 <19,20> DDR_B_D22 DDR1_DQ[21]/DDR0_DQ[53] DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12] DDR_B_MA11 DDR_B_MA12 <18>
BA63 BA55 M_A_ACT# <19,20> AT65 AN48 DDR_B_MA11 <18>
DDR_A_D23 BB63 DDR0_DQ[22]/DDR0_DQ[38] DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT# AY54 DDR_B_D23 AU65 DDR1_DQ[22]/DDR0_DQ[54] DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11] AN53 M_B_ACT#
DDR_A_D24 DDR0_DQ[23]/DDR0_DQ[39] DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1] @ T16 DDR_B_D24 DDR1_DQ[23]/DDR0_DQ[55] DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT# DDR_B_BG1 M_B_ACT# <18>
BA61 AT61 AN52 DDR_B_BG1 <18>
2 DDR_A_D25 AW61 DDR0_DQ[24]/DDR0_DQ[40] AU46 DDR_A_MA13 DDR_B_D25 AU61 DDR1_DQ[24]/DDR0_DQ[56] DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1] 2
DDR_A_D26 DDR0_DQ[25]/DDR0_DQ[41] DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13] DDR_A_MA15 DDR_A_MA13 <19,20> DDR_B_D26 DDR1_DQ[25]/DDR0_DQ[57] DDR_B_MA13
BB59 AU48 DDR_A_MA15 <19,20> AP60 BA43 DDR_B_MA13 <18>
DDR_A_D27 AW59 DDR0_DQ[26]/DDR0_DQ[42] DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15] AT46 DDR_A_MA14 DDR_B_D27 AN60 DDR1_DQ[26]/DDR0_DQ[58] DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13] AY43 DDR_B_MA15
DDR_A_D28 DDR0_DQ[27]/DDR0_DQ[43] DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14] DDR_A_MA16 DDR_A_MA14 <19,20> DDR_B_D28 DDR1_DQ[27]/DDR0_DQ[59] DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15] DDR_B_MA14 DDR_B_MA15 <18>
BB61 AU50 DDR_A_MA16 <19,20> AN61 AY44 DDR_B_MA14 <18>
DDR_A_D29 AY61 DDR0_DQ[28]/DDR0_DQ[44] DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16] AU52 DDR_A_BA0 DDR_B_D29 AP61 DDR1_DQ[28]/DDR0_DQ[60] DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14] AW44 DDR_B_MA16
DDR_A_D30 DDR0_DQ[29]/DDR0_DQ[45] DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0] DDR_A_MA2 DDR_A_BA0 <19,20> DDR_B_D30 DDR1_DQ[29]/DDR0_DQ[61] DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16] DDR_B_BA0 DDR_B_MA16 <18>
BA59 AY51 DDR_A_MA2 <19,20> AT60 BB44 DDR_B_BA0 <18>
DDR_A_D31 AY59 DDR0_DQ[30]/DDR0_DQ[46] DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2] AT48 DDR_A_BA1 DDR_B_D31 AU60 DDR1_DQ[30]/DDR0_DQ[62] DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0] AY47 DDR_B_MA2
19> DDR_A_D[32..47] DDR_A_D32 DDR0_DQ[31]/DDR0_DQ[47] DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1] DDR_A_MA10 DDR_A_BA1 <19,20> <18> DDR_B_D[32..47] DDR_B_D32 DDR1_DQ[31]/DDR0_DQ[63] DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2] DDR_B_BA1 DDR_B_MA2 <18>
AY39 AT50 DDR_A_MA10 <19,20> AU40 BA44 DDR_B_BA1 <18>
DDR_A_D33 AW39 DDR0_DQ[32]/DDR1_DQ[0] DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10] BB50 DDR_A_MA1 DDR_B_D33 AT40 DDR1_DQ[32]/DDR1_DQ[16] DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1] AW46 DDR_B_MA10
DDR_A_D34 DDR0_DQ[33]/DDR1_DQ[1] DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1] DDR_A_MA0 DDR_A_MA1 <19,20> DDR_B_D34 DDR1_DQ[33]/DDR1_DQ[17] DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10] DDR_B_MA1 DDR_B_MA10 <18>
AY37 AY50 DDR_A_MA0 <19,20> AT37 AY46 DDR_B_MA1 <18>
DDR_A_D35 AW37 DDR0_DQ[34]/DDR1_DQ[2] DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0] BA50 DDR_A_MA3 DDR_B_D35 AU37 DDR1_DQ[34]/DDR1_DQ[18] DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1] BA46 DDR_B_MA0
DDR_A_D36 DDR0_DQ[35]/DDR1_DQ[3] DDR0_MA[3] DDR_A_MA4 DDR_A_MA3 <19,20> DDR_B_D36 DDR1_DQ[35]/DDR1_DQ[19] DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0] DDR_B_MA3 DDR_B_MA0 <18>
BB39 BB52 DDR_A_MA4 <19,20> AR40 BB46 DDR_B_MA3 <18>
DDR_A_D37 BA39 DDR0_DQ[36]/DDR1_DQ[4] DDR0_MA[4] DDR_B_D37 AP40 DDR1_DQ[36]/DDR1_DQ[20] DDR1_MA[3] BA47 DDR_B_MA4
DDR_A_D38 DDR0_DQ[37]/DDR1_DQ[5] DDR_A_DQS#0 DDR_B_D38 DDR1_DQ[37]/DDR1_DQ[21] DDR1_MA[4] DDR_B_MA4 <18>
BA37 AM70 DDR_A_DQS#0 <19> AP37
DDR_A_D39 BB37 DDR0_DQ[38]/DDR1_DQ[6] DDR0_DQSN[0] AM69 DDR_A_DQS0 DDR_B_D39 AR37 DDR1_DQ[38]/DDR1_DQ[22] AH66 DDR_B_DQS#0
DDR_A_D40 DDR0_DQ[39]/DDR1_DQ[7] DDR0_DQSP[0] DDR_A_DQS#1 DDR_A_DQS0 <19> DDR_B_D40 DDR1_DQ[39]/DDR1_DQ[23] DDR1_DQSN[0]/DDR0_DQSN[2] DDR_B_DQS0 DDR_B_DQS#0 <18>
AY35 AT69 DDR_A_DQS#1 <19> AT33 AH65 DDR_B_DQS0 <18>
DDR_A_D41 AW35 DDR0_DQ[40]/DDR1_DQ[8] DDR0_DQSN[1] AT70 DDR_A_DQS1 DDR_B_D41 AU33 DDR1_DQ[40]/DDR1_DQ[24] DDR1_DQSP[0]/DDR0_DQSP[2] AG69 DDR_B_DQS#1
DDR_A_D42 DDR0_DQ[41]/DDR1_DQ[9] DDR0_DQSP[1] DDR_A_DQS#2 DDR_A_DQS1 <19> DDR_B_D42 DDR1_DQ[41]/DDR1_DQ[25] DDR1_DQSN[1]/DDR0_DQSN[3] DDR_B_DQS1 DDR_B_DQS#1 <18>
AY33 BA64 DDR_A_DQS#2 <19> AU30 AG70 DDR_B_DQS1 <18>
DDR_A_D43 AW33 DDR0_DQ[42]/DDR1_DQ[10] DDR0_DQSN[2]/DDR0_DQSN[4] AY64 DDR_A_DQS2 DDR_B_D43 AT30 DDR1_DQ[42]/DDR1_DQ[26] DDR1_DQSP[1]/DDR0_DQSP[3] AR66 DDR_B_DQS#2
DDR_A_D44 DDR0_DQ[43]/DDR1_DQ[11] DDR0_DQSP[2]/DDR0_DQSP[4] DDR_A_DQS#3 DDR_A_DQS2 <19> DDR_B_D44 DDR1_DQ[43]/DDR1_DQ[27] DDR1_DQSN[2]/DDR0_DQSN[6] DDR_B_DQS2 DDR_B_DQS#2 <18>
BB35 AY60 DDR_A_DQS#3 <19> AR33 AR65 DDR_B_DQS2 <18>
DDR_A_D45 BA35 DDR0_DQ[44]/DDR1_DQ[12] DDR0_DQSN[3]/DDR0_DQSN[5] BA60 DDR_A_DQS3 DDR_B_D45 AP33 DDR1_DQ[44]/DDR1_DQ[28] DDR1_DQSP[2]/DDR0_DQSP[6] AR61 DDR_B_DQS#3
DDR_A_D46 DDR0_DQ[45]/DDR1_DQ[13] DDR0_DQSP[3]/DDR0_DQSP[5] DDR_A_DQS#4 DDR_A_DQS3 <19> DDR_B_D46 DDR1_DQ[45]/DDR1_DQ[29] DDR1_DQSN[3]/DDR0_DQSN[7] DDR_B_DQS3 DDR_B_DQS#3 <18>
BA33 BA38 DDR_A_DQS#4 <19> AR30 AR60 DDR_B_DQS3 <18>
DDR_A_D47 BB33 DDR0_DQ[46]/DDR1_DQ[14] DDR0_DQSN[4]/DDR1_DQSN[0] AY38 DDR_A_DQS4 DDR_B_D47 AP30 DDR1_DQ[46]/DDR1_DQ[30] DDR1_DQSP[3]/DDR0_DQSP[7] AT38 DDR_B_DQS#4
19> DDR_A_D[48..63] DDR_A_D48 DDR0_DQ[47]/DDR1_DQ[15] DDR0_DQSP[4]/DDR1_DQSP[0] DDR_A_DQS#5 DDR_A_DQS4 <19> <18> DDR_B_D[48..63] DDR_B_D48 DDR1_DQ[47]/DDR1_DQ[31] DDR1_DQSN[4]/DDR1_DQSN[2] DDR_B_DQS4 DDR_B_DQS#4 <18>
AY31 AY34 DDR_A_DQS#5 <19> AU27 AR38 DDR_B_DQS4 <18>
DDR_A_D49 AW31 DDR0_DQ[48]/DDR1_DQ[32] DDR0_DQSN[5]/DDR1_DQSN[1] BA34 DDR_A_DQS5 DDR_B_D49 AT27 DDR1_DQ[48] DDR1_DQSP[4]/DDR1_DQSP[2] AT32 DDR_B_DQS#5
DDR_A_D50 DDR0_DQ[49]/DDR1_DQ[33] DDR0_DQSP[5]/DDR1_DQSP[1] DDR_A_DQS#6 DDR_A_DQS5 <19> DDR_B_D50 DDR1_DQ[49] DDR1_DQSN[5]/DDR1_DQSN[3] DDR_B_DQS5 DDR_B_DQS#5 <18>
AY29 BA30 DDR_A_DQS#6 <19> AT25 AR32 DDR_B_DQS5 <18>
DDR_A_D51 AW29 DDR0_DQ[50]/DDR1_DQ[34] DDR0_DQSN[6]/DDR1_DQSN[4] AY30 DDR_A_DQS6 DDR_B_D51 AU25 DDR1_DQ[50] DDR1_DQSP[5]/DDR1_DQSP[3] AR25 DDR_B_DQS#6
DDR_A_D52 DDR0_DQ[51]/DDR1_DQ[35] DDR0_DQSP[6]/DDR1_DQSP[4] DDR_A_DQS#7 DDR_A_DQS6 <19> DDR_B_D52 DDR1_DQ[51] DDR1_DQSN[6] DDR_B_DQS6 DDR_B_DQS#6 <18>
BB31 AY26 DDR_A_DQS#7 <19> AP27 AR27 DDR_B_DQS6 <18>
DDR_A_D53 BA31 DDR0_DQ[52]/DDR1_DQ[36] DDR0_DQSN[7]/DDR1_DQSN[5] BA26 DDR_A_DQS7 DDR_B_D53 AN27 DDR1_DQ[52] DDR1_DQSP[6] AR22 DDR_B_DQS#7
DDR_A_D54 DDR0_DQ[53]/DDR1_DQ[37] DDR0_DQSP[7]/DDR1_DQSP[5] DDR_A_DQS7 <19> DDR_B_D54 DDR1_DQ[53] DDR1_DQSN[7] DDR_B_DQS7 DDR_B_DQS#7 <18>
BA29 AN25 AR21 DDR_B_DQS7 <18>
DDR_A_D55 BB29 DDR0_DQ[54]/DDR1_DQ[38] AW50 DDR_B_D55 AP25 DDR1_DQ[54] DDR1_DQSP[7]
DDR_A_D56 DDR0_DQ[55]/DDR1_DQ[39] DDR0_ALERT# DDR_A_ALERT# <19> DDR_B_D56 DDR1_DQ[55] DDR_B_ALERT#
AY27 AT52 DDR_A_PARITY <19,20> AT22 AN43 DDR_B_ALERT# <18>
DDR_A_D57 AW27 DDR0_DQ[56]/DDR1_DQ[40] DDR0_PAR DDR_B_D57 AU22 DDR1_DQ[56] DDR1_ALERT# AP43 DDR_B_PARITY
DDR_A_D58 DDR0_DQ[57]/DDR1_DQ[41] +0.6V_VREFCA DDR_B_D58 DDR1_DQ[57] DDR1_PAR DDR_DRAMRST# DDR_B_PARITY <18>
AY25 AY67 +0.6V_VREFCA
Trace width/Spacing >= 20mils
<19> componment near SODIMM AU21 AT13 DDR_DRAMRST# <18,19>
DDR_A_D59 AW25 DDR0_DQ[58]/DDR1_DQ[42] DDR_VREF_CA AY68 Place DDR_B_D59 AT21 DDR1_DQ[58] DRAM_RESET# AR18
3 @ T25 3
DDR_A_D60 BB27 DDR0_DQ[59]/DDR1_DQ[43] DDR CH - A
DDR0_VREF_DQ BA67 +0.6V_B_VREFDQ DDR_B_D60 AN22 DDR1_DQ[59] DDR_RCOMP[0] AT18 follow INTEL review feedback change to 200ohm
DDR_A_D61 DDR0_DQ[60]/DDR1_DQ[44] DDR1_VREF_DQ +0.6V_B_VREFDQ <18> DDR_B_D61 DDR1_DQ[60] DDR_RCOMP[1] SM_RCOMP0
BA27 #543016 PDG0.9 P.163 RC place near SODIMM AP22 DDR CH - B AU18 RC38 1 2 200_0402_1%
DDR_A_D62 BA25 DDR0_DQ[61]/DDR1_DQ[45] AW67 DDR_PG_CTRL DDR_B_D62 AP21 DDR1_DQ[61] DDR_RCOMP[2] SM_RCOMP1 RC39 1 2 80.6_0402_1%
DDR_A_D63 BB25 DDR0_DQ[62]/DDR1_DQ[46] DDR_VTT_CNTL DDR_B_D63 AN21 DDR1_DQ[62] SM_RCOMP2 RC40 1 2 100_0402_1%
DDR0_DQ[63]/DDR1_DQ[47] 2 OF 20 DDR1_DQ[63] 3 OF 20
#543016 PDG0.9 P.117
SKL-U_BGA1356 SKL-U_BGA1356 W=12-15 Space= 20/25 L=500mil
@ @
DDR_VTT_CNTL to DDR
VTT supplied ramped +1.2V_VDDQ
<35uS
+3VS
(tCPU18)
.1U_0402_16V7K 2 1 CC57
1
UC7
1 5 RC10
NC VCC 220K_0402_5%
DDR_PG_CTRL 2
A
2
4
Y SM_PG_CTRL <52>
3
GND
2
74AUP1G07GW_TSSOP5
ES Sample RC16
@ 2M_0402_5%
UC1 UC1
+1.2V_VDDQ
1
2
G
4 4
CPU_QHMF_C0_2.3G CPU_QHMG_C0_1.6G 3 1
QHMF@ QHMG@
S
SA00008M420 SA00008M320 Reserve for cost test. @ Q2009
MESS138W-G_SOT323-3
Security Classification
2014/11/10
Compal Secret Data
2016/11/10 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SKL-U(2/12)DDR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
LA-D301P 0.2
Date: Thursday, December 17, 2015 Sheet 7 of 63
A B C D E
A B C D E
RC44 1 CMC@ 2 1K_0402_1% SOC_SPI_SI
<6> XDP_SPI_SI
SOC_SPI_IO2 SKL-U
<6> XDP_SPI_IO2 RC21 1 CMC@ 2 1K_0402_1% UC1E
Rev_0.53
SPI - FLASH
RC21/44 place to within 1100 mil of SPIO_MOSI/SPI0_IO2 pin for XDP SMBUS, SMLINK
SOC_SPI_CLK AV2
SOC_SPI_SO AW3 SPI0_CLK R7 SOC_SMBCLK_1 +3VALW_PRIM SMB
SOC_SPI_SI AV3 SPI0_MISO GPP_C0/SMBCLK R8 SOC_SMBDATA_1 RC250 2.2K_0402_5% (Link to DDR, G-sensor)
SOC_SPI_IO2 AW2 SPI0_MOSI GPP_C1/SMBDATA R10 SOC_SMBALERT# 2 1
SPI ROM SOC_SPI_IO3 AU4 SPI0_IO2 GPP_C2/SMBALERT#
SOC_SPI_CS#0 AU3 SPI0_IO3 R9 SOC_SML0CLK +3VALW_PRIM SML0
SOC_SPI_CS#1 SPI0_CS0# GPP_C3/SML0CLK SOC_SML0DATA SOC_SML0CLK <34,35>
AU2 W2 (Link to NFC, LAN)
1 AU1 SPI0_CS1#
SPI0_CS2#
GPP_C4/SML0DATA
GPP_C5/SML0ALERT#
W1 SOC_SML0ALERT# SOC_SML0DATA <34,35>
4.7K_0402_5% 2 ESPI@ 1 RC202 Strap Pin 1
W3 SOC_SML1CLK_1
SPI - TOUCH GPP_C6/SML1CLK V3 SOC_SML1DATA_1 SML1
M2 GPP_C7/SML1DATA AM7 SOC_SML1ALERT# (Link to EC, DGPU, DDR thermal, RTD2168)
GPP_D1/SPI1_CLK GPP_B23/SML1ALERT#/PCHHOT# @ T234
M3
<40> RTD3_USB_PWR_EN GPP_D2/SPI1_MISO
J4
<40> RTD3_CIO_PWR_EN GPP_D3/SPI1_MOSI
AR GPIO V1
<40> TBT_BATLOW# TBT_FORCE_PWR GPP_D21/SPI1_IO2
V2 ESPI / LPC Bus
<40> TBT_FORCE_PWR TBT_CIO_PLUG_EVENT# M1 GPP_D22/SPI1_IO3
<40> TBT_CIO_PLUG_EVENT# LPC
GPP_D0/SPI1_CS# AY13 LPC_AD0 1 2
GPP_A1/LAD0/ESPI_IO0
RC144 @ 0_0402_5%
LPC_AD0_R <43,45> ESPI : +1.8V
BA13 LPC_AD1 RC145 1 @ 2 0_0402_5%
C LINK GPP_A2/LAD1/ESPI_IO1 LPC_AD2 LPC_AD1_R <43,45> LPC : +3.3V
BB13 RC146 1 @ 2 0_0402_5%
GPP_A3/LAD2/ESPI_IO2 LPC_AD3 LPC_AD2_R <43,45>
<38> CL_CLK G3 AY12 RC147 1 @ 2 0_0402_5%
CL_CLK GPP_A4/LAD3/ESPI_IO3 LPC_FRAME# LPC_AD3_R <43,45>
WLAN <38> CL_DATA G2 BA12
CL_DATA GPP_A5/LFRAME#/ESPI_CS# ESPI_RST# LPC_FRAME# <43,45>
<38> CL_RST# G1 BA11 @ T235 RC45
CL_RST# GPP_A14/SUS_STAT#/ESPI_RESET#
To EC
EC_KBRST#_R AW13 AW9 ESPI_CLK RC45 2 1 22_0402_5%
<43> EC_KBRST#_R GPP_A0/RCIN# GPP_A9/CLKOUT_LPC0/ESPI_CLK AY9 CK_LPC_TPM_R ESPI_CLK_R <43>
R395 2 1 22_0402_5%
TPM_SERIRQ GPP_A10/CLKOUT_LPC1 AW11 PM_CLKRUN# CK_LPC_TPM <45>
To TPM <43,45> TPM_SERIRQ AY11 1
GPP_A6/SERIRQ GPP_A8/CLKRUN# PM_CLKRUN# <45>
5 OF 20 For TPM @RF@ 15_0402_5%
LPC Mode C5241 ESPI@
SKL-U_BGA1356 22P_0402_50V8J
@ 2
+1.8VS_3VS_PGPPA +3VALW_PRIM
SOC_SML0CLK RC49 1 2 499_0402_1%
SOC_SML0DATA RC50 1 2 499_0402_1%
PM_CLKRUN# 1 2
2 2
RC107 10K_0402_5% +3VS
RPC7
TPM_SERIRQ 1 2 SOC_SMBCLK_1 1 8 SOC_SMBCLK RC222 1 2 2.2K_0402_5%
RC112 10K_0402_5% SOC_SMBDATA_1 2 7 SOC_SMBDATA RC223 1 2 2.2K_0402_5%
SOC_SML1CLK_1 3 6
SOC_SML1DATA_1 4 5 SOC_SML1CLK RC246 1 2 2.2K_0402_5%
SOC_SML1DATA RC247 1 2 2.2K_0402_5%
2.2K_0804_8P4R_5%
+3VS
5
2015MOW06 no need PU1K on SPI_IO2/IO3 Q2017B
DMN66D0LDW-7_SOT363-6
+3VALW_SPI SOC_SMBCLK_1 3 4 SOC_SMBCLK
SOC_SMBCLK <18,33>
RC220 2 @ 1 0_0402_5%
SOC_SPI_IO2 RC47 1 @ 2 1K_0402_1% RC221 2 @ 1 0_0402_5%
SOC_SMBDATA_1 6 1 SOC_SMBDATA
Single SPI ROM_CS0# SOC_SMBDATA <18,33>
RPC5 and RC52 are close UC2
Q2017A
RPC5 SOC_SPI_IO3 RC48 1 @ 2 1K_0402_1% DMN66D0LDW-7_SOT363-6
2
SOC_SPI_IO3_0_R 1 8 SOC_SPI_IO3
SOC_SPI_SI_0_R SOC_SPI_SI +3VS
2 7
To SPI ROM SOC_SPI_CLK_0_R 3 6 SOC_SPI_CLK
SOC_SPI_SO_0_R 4 5 SOC_SPI_SO
+3VS
5
3 33_0804_8P4R_5% Q2018B 3
RC52 DMN66D0LDW-7_SOT363-6
SOC_SPI_IO2_0_R 2 1 SOC_SPI_IO2 SOC_SML1CLK_1 3 4 SOC_SML1CLK
SOC_SML1CLK <19,21,29,43>
33_0402_5% RPC23 and RC59 are close UC9
Dual SPI ROM_CS1# RC225 2 @ 1 0_0402_5%
RPC23 RC224 2 @ 1 0_0402_5%
UC2 UC2 UC9 SOC_SPI_IO3_1_R 1 8 SOC_SPI_IO3
SOC_SPI_CLK_1_R 2 7 SOC_SPI_CLK SOC_SML1DATA_1 6 1 SOC_SML1DATA
SOC_SPI_SI_1_R SOC_SPI_SI SOC_SML1DATA <19,21,29,43>
3 6
SOC_SPI_SO_1_R 4 5 SOC_SPI_SO Q2018A
To SPI ROM DMN66D0LDW-7_SOT363-6
2
33_0804_8P4R_5% +3VS
W25Q128FVSIQ_SO8 W25Q64FVSSIQ_SO8 W25Q64FVSSIQ_SO8
ROM16M@ ROM8M@ ROM8M@
SOC_SPI_IO2_1_R 2 1 SOC_SPI_IO2
RC59 33_0402_5%
+3VALW_SPI CC8
SPI ROM ( 8MByte ) .1U_0402_16V7K
UC2 1 2
SOC_SPI_CS#0 1 8
SPI ROM ( 2/4/8/16MByte ) +3VALW_SPI CC101
SOC_SPI_SO_0_R 2 /CS VCC 7 SOC_SPI_IO3_0_R .1U_0402_16V7K
SOC_SPI_IO2_0_R 3 DO(IO1) /HOLD(IO3) 6 SOC_SPI_CLK_0_R UC9 1 2
4 /WP(IO2) CLK 5 SOC_SPI_SI_0_R SOC_SPI_CS#1 1 8
GND DI(IO0) SOC_SPI_SO_1_R 2 /CS VCC 7 SOC_SPI_IO3_1_R
W25Q64FVSSIQ_SO8 SOC_SPI_IO2_1_R 3 DO(IO1) /HOLD(IO3) 6 SOC_SPI_CLK_1_R
4 /WP(IO2) CLK 5 SOC_SPI_SI_1_R
@ GND DI(IO0)
+3VALW_SPI W25Q64FVSSIQ_SO8
ROM Socket
4 @ 4
JC1 RC26
SOC_SPI_CS#0 1 8 SOC_SPI_CLK_1_R 1 @EMC@2 0_0402_5% 1 2
SOC_SPI_IO2_0_R 3 CS# VCC 6 SOC_SPI_CLK_0_R CC70 @EMC@
SOC_SPI_IO3_0_R 7 WP# SCLK 5 SOC_SPI_SI_0_R 10P_0402_50V8J
4 HOLD# SI/SIO0 2 SOC_SPI_SO_0_R
GND SO/SIO1
ACES_91960-0084N_MX25L3206EM2I
CONN@ RC24
Security Classification
2014/11/10
Compal Secret Data
2016/11/10 Title
Compal Electronics, Inc.
SOC_SPI_CLK_0_R 1 @EMC@2 0_0402_5% 1 2
Issued Date Deciphered Date
CC9
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SKL-U(3/12)SPI,ESPI,SMB,LPC
10P_0402_50V8J AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
@EMC@ DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
LA-D301P 0.2
Date: Thursday, December 17, 2015 Sheet 8 of 63
A B C D E
A B C D E
#545659 SKL_PCH_EDS_R0.7 P.84
UC1G SKL-U
Rev_0.53
AUDIO
HDA_SYNC
#54 016 PDG0.9 P. 1
BA22 Terminat i ng Unus ed S DI O/S DXC Si gnal s
HDA_BIT_CLK AY22 HDA_SYNC/I2S0_SFRM
HDA_SDOUT HDA_BLK/I2S0_SCLK SDIO signals are mult i pl exed w i t h GPI Os and
BB22 SDIO/SDXC
HDA_SDIN0 BA21 HDA_SDO/I2S0_TXD default to GPIO funct i onali t y ( as i nput). If
AY21 HDA_SDI0/I2S0_RXD AB11 SDIO interface is not used, the signals
HDA_RST# AW22 HDA_SDI1/I2S1_RXD GPP_G0/SD_CMD AB13 can be used as GPIOs instead. If the GPIO
1 HDA_RST#/I2S1_SCLK GPP_G1/SD_DATA0 AB12 funct i onali t y i s al s o not us ed, t he si gnal s can be l e ft as no- c onnect. 1
J5
AY20 GPP_D23/I2S_MCLK GPP_G2/SD_DATA1 W12
AW20 I2S1_SFRM GPP_G3/SD_DATA2 W11
Functional Strap Definitions I2S1_TXD GPP_G4/SD_DATA3
GPP_G5/SD_CD#
W10
AK7 W8
AK6 GPP_F1/I2S2_SFRM GPP_G6/SD_CLK W7
AK9 GPP_F0/I2S2_SCLK GPP_G7/SD_WP
AK10 GPP_F2/I2S2_TXD BA9
SPKR / GPP_B14 (Internal Pull Down): GPP_F3/I2S2_RXD GPP_A17/SD_PWR_EN#/ISH_GP7 BB9
(Sampled:Rising edge of PCH_PWROK) GPP_A16/SD_1P8_SEL
PCH_DMIC_CLK H5 AB7 SD_RCOMP RC76 2 1 200_0402_1%
<37> PCH_DMIC_CLK PCH_DMIC_DATA GPP_D19/DMIC_CLK0 SD_RCOMP
TOP Swap Override <37> PCH_DMIC_DATA D7
GPP_D20/DMIC_DATA0
0 = Disable TOP Swap mode.---> AAX05 Use D8 AF13
GPP_D17/DMIC_CLK1 GPP_F23
1 = Enable TOP Swap Mode. C8
GPP_D18/DMIC_DATA1
<37> BEEP# BEEP# AW5
GPP_B14/SPKR
7 OF 20
SKL-U_BGA1356
@
HDA for AUDIO
RPC9
HDA_BIT_CLK_R 1 8 HDA_SYNC
<37> HDA_SYNC_R HDA_SDOUT
<37> HDA_SDOUT_R 2 7
HDA_BIT_CLK
1
2 RF@ <37> HDA_BIT_CLK_R 3 6 2
4 5 HDA_RST#
0_0402_5% <37> HDA_RST#_R
R5253 33_0804_8P4R_5%
2
1 @ 2 HDA_SDOUT
2 <43> ME_EN
RF@ RC77 0_0402_5%
C5228 HDA_SDIN0
<37> HDA_SDIN0
22P_0402_50V8J
1
SKL_ULT
UC1I
Rev_0.53
CSI-2
A36 C37 +3VALW_1.8VALW_PGPPD
B36 CSI2_DN0 CSI2_CLKN0 D37
C38 CSI2_DP0 CSI2_CLKP0 C32
CSI2_DN1 CSI2_CLKN1
1
D38 D32
C36 CSI2_DP1 CSI2_CLKP1 C29 RC133
D36 CSI2_DN2 CSI2_CLKN2 D29 UMA@
CSI2_DP2 CSI2_CLKP2 10K_0402_5%
A38 B26
B38 CSI2_DN3 CSI2_CLKN3 A26
CSI2_DP3 CSI2_CLKP3
2
3 C31 E13 CSI2_COMP RC80 2 1 100_0402_1% DGPU_PRSNT#
3
D31 CSI2_DN4 CSI2_COMP B7 DGPU_PRSNT#
C33 CSI2_DP4 GPP_D4/FLASHTRIG
D33 CSI2_DN5
CSI2_DP5
1
EMMC
A31
B31 CSI2_DN6 AP2 RC134
A33 CSI2_DP6 GPP_F13/EMMC_DATA0 AP1 VGA@
CSI2_DN7 GPP_F14/EMMC_DATA1 10K_0402_5%
B33 AP3
CSI2_DP7 GPP_F15/EMMC_DATA2 AN3
GPP_F16/EMMC_DATA3
2
A29 AN1
B29 CSI2_DN8 GPP_F17/EMMC_DATA4 AN2
C28 CSI2_DP8 GPP_F18/EMMC_DATA5 AM4
D28 CSI2_DN9 GPP_F19/EMMC_DATA6 AM1
A27 CSI2_DP9 GPP_F20/EMMC_DATA7 GPIO67
B27 CSI2_DN10 AM2
CSI2_DP10 GPP_F21/EMMC_RCLK
DGPU_PRSNT#
C27 AM3
D27 CSI2_DN11 GPP_F22/EMMC_CLK AP4
CSI2_DP11 GPP_F12/EMMC_CMD DIS,Optimus 0
AT1 EMMC_RCOMP 2 1
9 OF 20
EMMC_RCOMP RC89 200_0402_1%
UMA 1
SKL-U_BGA1356
@
4 4
Security Classification
2014/11/10
Compal Secret Data
2016/11/10 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SKL-U(4/12)HDA,EMMC,SDIO,CSI2
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
LA-D301P 0.2
Date: Thursday, December 17, 2015 Sheet 9 of 63
A B C D E
A B C D E
UC1J SKL_ULT
+RTCVCC Rev_0.53
CLOCK SIGNALS
RC91 1 2 20K_0402_5% SOC_SRTCRST# CLK_PCIE_N0 D42
<21> CLK_PCIE_N0 CLK_PCIE_P0 CLKOUT_PCIE_N0
DGPU C42
<21> CLK_PCIE_P0 CLKREQ_PCIE#0 AR10 CLKOUT_PCIE_P0
CC10 1 2 1U_0402_6.3V6K
GPP_B5/SRCCLKREQ0#
PH at DGPU side
CLK_PCIE_N1 B42
Remove CLR ME <35> CLK_PCIE_N1 CLK_PCIE_P1 CLKOUT_PCIE_N1 CLK_CPU_ITP#
GLAN A42 F43 T164 @
<35> CLK_PCIE_P1 CLKREQ_PCIE#1 CLKOUT_PCIE_P1 CLKOUT_ITPXDP_N CLK_CPU_ITP
<35> CLKREQ_PCIE#1 AT7 E43 T165 @ Follow 2014MOW48
RC93 1 2 20K_0402_5% SOC_RTCRST# GPP_B6/SRCCLKREQ1# CLKOUT_ITPXDP_P
Skylake U PU 2.7k ohm to 1V
CLK_PCIE_N2 D41 BA17 SUSCLK
1 <38> CLK_PCIE_N2 CLK_PCIE_P2 CLKOUT_PCIE_N2 GPD8/SUSCLK SUSCLK Cannonlake
<34,38> U PD 60.4 ohm 1
CC11 1 2 1U_0402_6.3V6K NGFF WL+BT(KEY E) C41
<38> CLK_PCIE_P2 CLKREQ_PCIE#2 CLKOUT_PCIE_P2 SOC_XTAL24_IN
<38> CLKREQ_PCIE#2 AT8 E37 XCLK_BIASREF
JCMOS1 1 2 0_0603_5% GPP_B7/SRCCLKREQ2# XTAL24_IN E35 SOC_XTAL24_OUT
@ CLR CMOS XTAL24_OUT T:50ohm S:12/15 L:1000 Via:2
CLK_PCIE_N3 D40
<40> CLK_PCIE_N3 CLK_PCIE_P3 CLKOUT_PCIE_N3 XCLK_BIASREF
Place at RAM DOOR AR C40 E42 RC96 1 2 2.7K_0402_1% +1.0VALW_CLK5_F24NS
<40> CLK_PCIE_P3 CLKREQ_PCIE#3 CLKOUT_PCIE_P3 XCLK_BIASREF
<40> CLKREQ_PCIE#3 AT10 1 @ 2
GPP_B8/SRCCLKREQ3# AM18 SOC_RTCX1 RC136 60.4_0402_1%
CLK_PCIE_CARD B40 RTCX1 AM20 SOC_RTCX2
SM_INTRUDER# <45> CLK_PCIE_CARD CLK_PCIE_CARD# CLKOUT_PCIE_N4 RTCX2
RC94 1 2 1M_0402_5% CR A40
<45> CLK_PCIE_CARD# CLKREQ_PCIE#4 CLKOUT_PCIE_P4 SOC_SRTCRST#
<45> CLKREQ_PCIE#4 AU8 AN18
GPP_B9/SRCCLKREQ4# SRTCRST# AM16 SOC_RTCRST#
+3VS CLK_PCIE_N5 RTCRST# SOC_RTCRST# <6>
WIGIG E40
<38> CLK_PCIE_N5 CLK_PCIE_P5 CLKOUT_PCIE_N5
E38
<38> CLK_PCIE_P5 CLKREQ_PCIE#5 CLKOUT_PCIE_P5
AU7
CLKREQ_PCIE#4 <38> CLKREQ_PCIE#5 GPP_B10/SRCCLKREQ5#
1 2
RC165 10K_0402_5%
1 2 CLKREQ_PCIE#5 10 OF 20
RC105 10K_0402_5% 2014MOW48:
SKL-U_BGA1356 Skylake U use 24M 50 ohm ESR
@ Cannonlake U use 38.4M 30 ohm ESR
1 2 CLKREQ_PCIE#1
RC121 10K_0402_5% +3VS
1 2 CLKREQ_PCIE#2 +3VS +3VM SOC_XTAL24_IN
RC123 10K_0402_5%
<21,47,59,60> DGPU_PWROK PCH PLTRST Buffer RC248 0_0402_5%
CLKREQ_PCIE#3
1
1 2 2 @ 1
RC124 10K_0402_5% R115 2 1
VGA@ 10K_0402_5% SOC_XTAL24_OUT 1 2
2
G
L2N7002LT1G_SOT23-3 Q2 RC249 0_0402_5% RC92 1M_0402_5%
5
2 Pull high @ VGA side 2
2
3 1 CLKREQ_PCIE#0 PLT_RST# 2
P
+3VALW_PRIM <21> PEG_CLKREQ# B PLT_RST_BUF#
4 YC1
D
Y PLT_RST_BUF# <34,35,38>
1
1 24MHZ_12PF_7V24000020
RPC11 A
1
+3VALW_DSW R107 R112
8 1 PCH_PWROK 2.2K_0402_5% 2.2K_0402_5% UC3 R157 3 1
3 1
3
7 2 EC_RSMRST# @ @ MC74VHC1G08DFT2G_SC70-5 100K_0402_5%
SYS_RESET# GND GND
1
6 3
15P_0402_50V8J
CC12
15P_0402_50V8J
CC13
2
2
5 4 LAN_PME#
2
2 @ 1 4 2
2
10K_0804_8P4R_5% RC125 0_0402_5%
Follow 543016_SKL_U_Y_PDG_0_9 Note for PCH_PWROK
PDG1.0 Figure43-4 note20: PCH_PWROK UC1K SKL-U
Rev_0.53
@ T84
does not glitch when RSMRST# is @ T85
+3VALW_DSW SYSTEM POWER MANAGEMENT
de-asserted PM_SLP_S0#
AT11
GPP_B12/SLP_S0# PM_SLP_S3# PM_SLP_S0# <6,43>
AP15
PM_BATLOW# PLT_RST# GPD4/SLP_S3# PM_SLP_S4# PM_SLP_S3# <6,43,47>
1 2 AN10 BA16
<21,34,40,43,45> PLT_RST# SYS_RESET# GPP_B13/PLTRST# GPD5/SLP_S4# PM_SLP_S5# PM_SLP_S4# <6,43,47>
RC103 10K_0402_5% <6> SYS_RESET# B5 AY16
PCH_PCIE_WAKE# EC_RSMRST# SYS_RESET# GPD10/SLP_S5# PM_SLP_S5# <6>
1 2 <6,43> EC_RSMRST# AY17 @ T86
RC104 1K_0402_5% RSMRST# AN15 SLP_SUS#
AC_PRESENT H_CPUPWRGD SLP_SUS# SLP_LAN# @ T90
1 @ 2 #543016 PDG0.9 P.526
T95 @ A68 AW15
PROCPWRGD is used only for power sequence EC_VCCST_PG PROCPWRGD SLP_LAN# SLP_WLAN# SLP_LAN# <43>
RC106 10K_0402_5% B65 BB17
debug and is not required to be connected to VCCST_PWRGD GPD9/SLP_WLAN# PM_SLP_A# SLP_WLAN# <43>
anything on the platform. T89 @ AN16 PM_SLP_A# <6,43>
SYS_PWROK B6 GPD6/SLP_A#
+3VALW_PRIM <43> SYS_PWROK PCH_PWROK SYS_PWROK PBTN_OUT#_R
<43> PCH_PWROK BA20 BA15
PCH_DPWROK BB20 PCH_PWROK GPD3/PWRBTN# AY15 AC_PRESENT
DSW_PWROK GPD1/ACPRESENT PM_BATLOW# AC_PRESENT <43>
3 AU13 3
SUSPWRDNACK AR13 GPD0/BATLOW#
<43> SUSPWRDNACK GPP_A13/SUSWARN#/SUSPWRDNACK
RC115 1 @ 2 10K_0402_5% SOC_VRALERT# WAKE# (DSX wake event) @ SUSACK# AP11
T92 GPP_A15/SUSACK# AU11
10 KΩ pull- up t o Vcc DS W . PCH_PCIE_WAKE# BB15 GPP_A11/PME# SM_INTRUDER# @ T91
The pull-up is required even if PCIe* interface PCH_PCIE_WAKE#
<35,40> is not AP16
LAN_PME# AM15 WAKE# INTRUDER#
+3VALW_DSW used on the plat f or m
. <35> LAN_PME# LAN_DISABLE_N AW17 GPD2/LAN_WAKE# EXT_PWR_GATE#
<35> LAN_DISABLE_N AM10 @ T93
AT15 GPD11/LANPHYPC GPP_B11/EXT_PWR_GATE# AM11 SOC_VRALERT#
GPD7/RSVD GPP_B2/VRALERT#
LAN WAKE: LAN Wake Indicator from the GbE PHY. 11 OF 20
SOC_RTCX2
SKL-U_BGA1356
RC111 2 @ 1 100K_0402_5% PBTN_OUT#_R @
SOC_RTCX1
Note for VCCST_PWRGD 1 2
+1.0V_VCCST 1. 1.0V tolerance RC98 10M_0402_5%
2 @ 1 PBTN_OUT#_R
2. PDG1.0 Figure43-4 note17: when failure events, <6,43> PBTN_OUT#
VCCST_PWRGD and PCH_PWROK de-assert at the same time RC109 0_0402_5%
1
RC113 EC_RSMRST# 2 @ 1 PCH_DPWROK YC2
From EC(open-drain) 1K_0402_5% RC114 0_0402_5% 1 2
32.768KHZ_9PF_CM7V-T1A9.0PF20PPM
2
RC116 1 2 60.4_0402_1% EC_VCCST_PG Change PN to SJ10000L000
<43,47> EC_VCCST_PG_R
1 1
SYS_PWROK 2 @ 1 PCH_PWROK CC15 CC16
RC122 0_0402_5% 8.2P_0402_50V8D 8.2P_0402_50V8D
CC51 @EMC@ 2 2
4 4
.1U_0402_16V7K
2 1 SYS_RESET# SYS_PWROK RC110 1 2 10K_0402_5%
CC50 @EMC@
.1U_0402_16V7K
2 1 H_CPUPWRGD
Security Classification
2014/11/10
Compal Secret Data
2016/11/10 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SKL-U(5/12)CLK,GPIO
Reserved for ESD 2014/9/17 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
LA-D301P 0.2
Date: Thursday, December 17, 2015 Sheet 10 of 63
A B C D E
A B C D E
# 543016 SKY PDG 0.9 P.401
+3VS
DGPU_PWR_EN RC214 1 VGA@ 2 10K_0402_5%
UC1F SKL-U
Rev_0.53
LPSS ISH
DGPU_HOLD_RST# RC219 1 VGA@ 2 10K_0402_5%
NFC_DFU follow PDG 1.3<34> NFC_DFU AN8 +3VS
NFC_DFU AP7 GPP_B15/GSPI0_CS# P2 VGA_ID
GC6_FB_EN_R AP8 GPP_B16/GSPI0_CLK GPP_D9 P3 RANK_ID +1.8VS_3VS_PGPPA +1.8VS
GSPI0_MOSI AR7 GPP_B17/GSPI0_MISO GPP_D10 P4 PROJECT_ID0
@ T111 GPP_B18/GSPI0_MOSI GPP_D11 PROJECT_ID1
P1 RC177
1
AM5 GPP_D12 0_0402_5% 2 ESPI@ 1 1
AN7 GPP_B19/GSPI1_CS# M4 ISH_I2C0_SDA
EC_LID_OUT# AP5 GPP_B20/GSPI1_CLK GPP_D5/ISH_I2C0_SDA N3 ISH_I2C0_SCL
@ T114 GSPI1_MOSI AN5 GPP_B21/GSPI1_MISO GPP_D6/ISH_I2C0_SCL ISH sensor HUB MINI_DET# 1
RPC12
8
RC178
@ T112 0_0402_5% 2 @ 1
GPP_B22/GSPI1_MOSI N1 ISH_I2C1_SDA (Reserve for Verify) NFC_DET# 2 7
RC189 2 @ 1 SOC_AC_DET AB1 GPP_D7/ISH_I2C1_SDA N2 ISH_I2C1_SCL 3 6
<21,43> DGPU_AC_DETECT AB2 GPP_C8/UART0_RXD GPP_D8/ISH_I2C1_SCL SSD_DET# 4 5
0_0402_5%
GPU_EVENT_R# W4 GPP_C9/UART0_TXD AD11 I2C_5_SDA
GPP_C10/UART0_RTS# GPP_F10/I2C5_SDA/ISH_I2C2_SDA I2C_5_SCL T105 @
AB3 AD12 T106 @ no use 10K_0804_8P4R_5%
GPP_C11/UART0_CTS# GPP_F11/I2C5_SCL/ISH_I2C2_SCL
UART_2_CRXD_DTXD AD1
<38> UART_2_CRXD_DTXD UART_2_CTXD_DRXD AD2 GPP_C20/UART2_RXD U1 SOC_GPIOD13
<38> UART_2_CTXD_DRXD UART_2_CRTS_DCTS GPP_C21/UART2_TXD GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA SOC_GPIOD14 T107 @
AD3 U2 T108 @ no use
UART_2_CCTS_DRTS AD4 GPP_C22/UART2_RTS# GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL U3 SOC_GPIOD15
GPP_C23/UART2_CTS# GPP_D15/ISH_UART0_RTS# SOC_GPIOD16 T113 @
U4 +3VS
GPP_D16/ISH_UART0_CTS#/SML0BALERT# T110 @
I2C_0_SDA U7 AC1 DGPU_PWR_EN
T141 @ I2C_0_SCL GPP_C16/I2C0_SDA GPP_C12/UART1_RXD/ISH_UART1_RXD DGPU_HOLD_RST# DGPU_PWR_EN <47>
U6 AC2
T142 @ GPP_C17/I2C0_SCL GPP_C13/UART1_TXD/ISH_UART1_TXD GPU_OVERT DGPU_HOLD_RST# <21> GPU_OVERT
AC3 RC232 1 VGA@ 2 10K_0402_5%
I2C_1_SDA GPP_C14/UART1_RTS#/ISH_UART1_RTS# GPU_ALERT GPU_OVERT <21>
U8 AB4
T140 @ I2C_1_SCL GPP_C18/I2C1_SDA GPP_C15/UART1_CTS#/ISH_UART1_CTS# GPU_ALERT <21>
U9
T143 @ GPP_C19/I2C1_SCL RAM_FLAG0 GPU_ALERT
AY8 RC233 1 VGA@ 2 10K_0402_5%
I2C_2_SDA GPP_A18/ISH_GP0 RAM_FLAG1 RAM_FLAG0 <19>
no use AH9 BA8
T135 @ I2C_2_SCL GPP_F4/I2C2_SDA GPP_A19/ISH_GP1 G_INT RAM_FLAG1 <19>
AH10 BB7
T134 @ GPP_F5/I2C2_SCL GPP_A20/ISH_GP2 SSD_DET# G_INT <33>
BA7
I2C_3_SDA GPP_A21/ISH_GP3 ALS_INT# SSD_DET# <34>
no use AH11 AY7 T115 @
T131 @ I2C_3_SCL GPP_F6/I2C3_SDA GPP_A22/ISH_GP4 NFC_DET#
AH12 AW7
T130 @ GPP_F7/I2C3_SCL GPP_A23/ISH_GP5 MINI_DET# NFC_DET# <34>
AP13
I2C_4_SDA GPP_A12/BM_BUSY#/ISH_GP6 MINI_DET# <38>
no use AF11
T128 @ I2C_4_SCL GPP_F8/I2C4_SDA
AF12
T129 @ GPP_F9/I2C4_SCL +3VALW_1.8VALW_PGPPD
6 OF 20
2 RPC19 2
SKL-U_BGA1356 ISH_I2C1_SCL 1 8
@ ISH_I2C1_SDA 2 7
Functional Strap Definitions ISH_I2C0_SCL
ISH_I2C0_SDA
3 6
4 5
@
GPU_EVENT_R# 1 GC6@ 2 GPU_EVENT# 1K_0804_8P4R_5% +3VS
GPU_EVENT# <21>
SPKR / GPP_B14 (Internal Pull Down): RC204 0_0402_5%
(Sampled:Rising edge of PCH_PWROK) GC6_FB_EN_R 1 GC6@ 2 GC6_FB_EN TO DGPU UART_2_CRXD_DTXD 1 2
GC6_FB_EN <21>
RC195 0_0402_5% RC62 49.9K_0402_1%
UART_2_CTXD_DRXD 1 2
TOP Swap Override
RC63 49.9K_0402_1%
0 = Disable TOP Swap mode.---> AAX05 Use UART_2_CRTS_DCTS 1 2
* @
1 = Enable TOP Swap Mode. RC64 49.9K_0402_1%
UART_2_CCTS_DRTS 1 @ 2
RC65 49.9K_0402_1%
+3VALW_1.8VALW_PGPPD +3VALW_1.8VALW_PGPPD
GSPI0_MOSI /GPP_B18 (Internal Pull Down): VGA_ID 1 2 10K_0402_5% PROJECT_ID0
NOVPRO@
2 1 10K_0402_5%
RC215 @ RC207
(Rising edge of PCH_PWROK) RC216 1 2 10K_0402_5% RC210 1 2 10K_0402_5%
No Reboot VPRO@
RANK_ID RC217 1 SR@ 2 10K_0402_5% PROJECT_ID1 RC211 2 @ 1 10K_0402_5%
0 = Disable No Reboot mode. --> AAX05 Use 1 DR@ 2 10K_0402_5% 1 2 10K_0402_5%
* 1 = Enable No Reboot Mode. (PCH will disable the TCO RC218 RC213 I2C/ISH Port(From PDG 0.9)
Timer system reboot feature). This function is useful
when running ITP/XDP.
3 3
GSPI1_MOSI / GPP_B22 (Internal Pull Down):
VGA_ID GPP_D9 Project_ID1 Project_ID0
Project ID
(Rising edge of PCH_PWROK) GL 0 GPP_D12 GPP_D11
GM 1 *B4DBU+VPRO 0 0
Boot BIOS Strap Bit
0 = SPI Mode --> AAX05 Use
* 1 = LPC Mode
B4DBU+NVPRO 0 1
RANK_ID GPP_D10 Reserved 1 0
DR 0 Reserved 1 1
SML0ALERT# / GPP_C5 (Internal Pull Down):
SR 1
(Sampled: Rising edge of RSMRST# )
eSPI or LPC
0 = LPC is selected for EC --> For KB9022/9032 Use
* 1 = eSPI is selected for EC --> For KB9032 Only.
SMBALERT# / GPP_C2 (Internal Pull Down): HDA_SDO/I2S_TXD0 (Internal Pull Down):
(Sampled: Rising edge of RSMRST# ) (Sampled: Rising edge of PCH_PWROK ) DDPB_CTRLDATA/ GPP_E19 (Internal Pull Down):
Flash Descriptor Security Override DDPC_CTRLDATA/ GPP_E21 (Internal Pull Down):
TLS Confidentiality 0 = Enable security measures defined in the Flash DDPD_CTRLDATA/ GPP_E23 (Internal Pull Down):
0 = Disable Intel ME Crypto Transport Layer Security Descriptor. (Sampled:Rising edge of PCH_PWROK)
4 * Display Port B/C/D Detected 4
(TLS) cipher suite (no confidentiality). 1 = Disable Flash Descriptor Security (override). This
1 = Enable Intel ME Crypto (TLS) (with confidentiality). strap should only be asserted high using external 0 =Port D is not detected.
Must be pulled up to support Intel AMT with TLS and Intelpull-up in manufacturing/debug environments ONLY. 1 =Port D is detected.
SBA (Small Business Advantage) with TLS.
Security Classification
2014/11/10
Compal Secret Data
2016/11/10 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SKL-U(6/12)GPIO
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
LA-D301P 0.2
Date: Thursday, December 17, 2015 Sheet 11 of 63
A B C D E
A B C D E
UC1H SKL-U
Rev_0.53
SSIC / USB3
PCIE/USB3/SATA
H8 PCH_USB3_RX1_N <39>
USB3_1_RXN G8
PCIE_CRX_GTX_N1 H13 USB3_1_RXP C13
PCH_USB3_RX1_P <39> IO/B
<21> PCIE_CRX_GTX_N1 PCIE_CRX_GTX_P1 PCIE1_RXN/USB3_5_RXN USB3_1_TXN PCH_USB3_TX1_N <39>
<21> PCIE_CRX_GTX_P1 G13 D13
PCIE_CTX_GRX_N1 PCIE1_RXP/USB3_5_RXP USB3_1_TXP PCH_USB3_TX1_P <39>
<21> PCIE_CTX_C_GRX_N1 CC17 VGA@ 1 2 0.22U_0402_16V7K B17
CC21 VGA@ 1 2 0.22U_0402_16V7K PCIE_CTX_GRX_P1 A17 PCIE1_TXN/USB3_5_TXN J6
<21> PCIE_CTX_C_GRX_P1 PCIE1_TXP/USB3_5_TXP USB3_2_RXN/SSIC_1_RXN PCH_USB3_RX2_N <39>
H6 PCH_USB3_RX2_P <39>
PCIE_CRX_GTX_N2 G11 USB3_2_RXP/SSIC_1_RXP B13
<21> PCIE_CRX_GTX_N2 PCIE_CRX_GTX_P2 F11 PCIE2_RXN/USB3_6_RXN USB3_2_TXN/SSIC_1_TXN A13
PCH_USB3_TX2_N <39> USB3 MB
1 <21> PCIE_CRX_GTX_P2 PCIE_CTX_GRX_N2 PCIE2_RXP/USB3_6_RXP USB3_2_TXP/SSIC_1_TXP PCH_USB3_TX2_P <39> 1
<21> PCIE_CTX_C_GRX_N2 CC18 VGA@ 1 2 0.22U_0402_16V7K D16
CC19 VGA@ 1 2 0.22U_0402_16V7K PCIE_CTX_GRX_P2 C16 PCIE2_TXN/USB3_6_TXN J10
<21> PCIE_CTX_C_GRX_P2 PCIE2_TXP/USB3_6_TXP USB3_3_RXN/SSIC_2_RXN PCH_USB3_RX3_N <44>
DGPU H10 PCH_USB3_RX3_P <44>
PCIE_CRX_GTX_N3 H16 USB3_3_RXP/SSIC_2_RXP B15
<21> PCIE_CRX_GTX_N3 PCIE_CRX_GTX_P3 G16 PCIE3_RXN USB3_3_TXN/SSIC_2_TXN A15
PCH_USB3_TX3_N <44> DOCKING
<21> PCIE_CRX_GTX_P3 PCIE_CTX_GRX_N3 PCIE3_RXP USB3_3_TXP/SSIC_2_TXP PCH_USB3_TX3_P <44>
CC20 VGA@ 1 2 0.22U_0402_16V7K D17
<21> PCIE_CTX_C_GRX_N3 PCIE_CTX_GRX_P3 PCIE3_TXN
CC22 VGA@ 1 2 0.22U_0402_16V7K C17 E10 PCH_USB3_RX4_N <39>
<21> PCIE_CTX_C_GRX_P3 PCIE3_TXP USB3_4_RXN F10 PCH_USB3_RX4_P <39>
PCIE_CRX_GTX_N4 G15 USB3_4_RXP C15
<21> PCIE_CRX_GTX_N4 PCIE_CRX_GTX_P4 F15 PCIE4_RXN USB3_4_TXN D15
PCH_USB3_TX4_N <39> IO/B
<21> PCIE_CRX_GTX_P4 PCIE_CTX_GRX_N4 PCIE4_RXP USB3_4_TXP PCH_USB3_TX4_P <39>
CC23 VGA@ 1 2 0.22U_0402_16V7K B19
<21> PCIE_CTX_C_GRX_N4 PCIE_CTX_GRX_P4 PCIE4_TXN USB20_N1
CC24 VGA@ 1 2 0.22U_0402_16V7K A19 AB9
<21> PCIE_CTX_C_GRX_P4 PCIE4_TXP USB2N_1 USB20_P1 USB20_N1 <39>
AB10 IO/B
PCIE_CRX_DTX_N5 USB2P_1 USB20_P1 <39>
F16
<35> PCIE_CRX_DTX_N5 PCIE_CRX_DTX_P5 PCIE5_RXN USB20_N2
E16 AD6
<35> PCIE_CRX_DTX_P5 PCIE_CTX_DRX_N5 PCIE5_RXP USB2N_2 USB20_P2 USB20_N2 <39>
GLAN CC25 2 1 .1U_0402_16V7K C19 AD7 USB3 MB
<35> PCIE_CTX_C_DRX_N5 PCIE_CTX_DRX_P5 PCIE5_TXN USB2P_2 USB20_P2 <39>
CC26 2 1 .1U_0402_16V7K D19
<35> PCIE_CTX_C_DRX_P5 PCIE5_TXP AH3 USB20_N3
PCIE_CRX_DTX_N6 USB2N_3 USB20_P3 USB20_N3 <44>
G18 AJ3 DOCKING
<38> PCIE_CRX_DTX_N6 PCIE_CRX_DTX_P6 PCIE6_RXN USB2P_3 USB20_P3 <44>
F18
<38> PCIE_CRX_DTX_P6 1 2 .1U_0402_16V7K PCIE_CTX_DRX_N6 D20 PCIE6_RXP AD9 USB20_N4
NGFF WLAN+BT(Key E)<38> PCIE_CTX_C_DRX_N6
C3803
PCIE_CTX_DRX_P6 PCIE6_TXN USB2N_4 USB20_P4 USB20_N4 <39>
C3804 1 2 .1U_0402_16V7K C20 AD10 IO/B
<38> PCIE_CTX_C_DRX_P6 PCIE6_TXP USB2P_4 USB20_P4 <39>
F20 AJ1 USB20_N5
<33> SATA_CRX_DTX_N0 PCIE7_RXN/SATA0_RXN USB2N_5 USB20_P5 USB20_N5 <38>
E20 AJ2 BT
<33> SATA_CRX_DTX_P0 PCIE7_RXP/SATA0_RXP USB2P_5 USB20_P5 <38>
HDD B21 USB2
<33> SATA_CTX_DRX_N0 A21 PCIE7_TXN/SATA0_TXN AF6
<33> SATA_CTX_DRX_P0 PCIE7_TXP/SATA0_TXP USB2N_6 @ T26
AF7 @ T27
PCIE_CRX_GTX_N8 G21 USB2P_6
2 <38> PCIE_CRX_GTX_N8 PCIE_CRX_GTX_P8 PCIE8_RXN/SATA1A_RXN USB20_N7 2
<38> PCIE_CRX_GTX_P8 F21 AH1
PCIE_CTX_GRX_N8 PCIE8_RXP/SATA1A_RXP USB2N_7 USB20_P7 USB20_N7 <28>
Wigig <38> PCIE_CTX_C_GRX_N8 CC108 2 1 .1U_0402_16V7K D21 AH2 Camera
PCIE_CTX_GRX_P8 PCIE8_TXN/SATA1A_TXN USB2P_7 USB20_P7 <28>
<38> PCIE_CTX_C_GRX_P8 CC109 2 1 .1U_0402_16V7K C21
PCIE8_TXP/SATA1A_TXP AF8 USB20_N8
PCIE_CRX_GTX_N9 USB2N_8 USB20_P8 USB20_N8 <45>
<40> PCIE_CRX_GTX_N9 E22 AF9 FP
PCIE_CRX_GTX_P9 PCIE9_RXN USB2P_8 USB20_P8 <45>
<40> PCIE_CRX_GTX_P9 E23
CC90 TBT@ 1 2 0.22U_0402_16V7K PCIE_CTX_GRX_N9 B23 PCIE9_RXP AG1 USB20_N9
<40> PCIE_CTX_C_GRX_N9 PCIE_CTX_GRX_P9 PCIE9_TXN USB2N_9 USB20_P9 USB20_N9 <38>
<40> PCIE_CTX_C_GRX_P9 CC89 TBT@ 1 2 0.22U_0402_16V7K A23 AG2 LTE
PCIE9_TXP USB2P_9 USB20_P9 <38>
Thunderbolt PCIE_CRX_GTX_N10
<40> PCIE_CRX_GTX_N10 F25 AH7 AG3,AG4 PD1K for DCI warm boot fail issue (follow PCH EDS1.2)
PCIE_CRX_GTX_P10 E25 PCIE10_RXN USB2N_10 AH8
<40> PCIE_CRX_GTX_P10 PCIE10_RXP USB2P_10 2015MOW10, USB2_ID connected to GND
CC93 TBT@ 1 2 0.22U_0402_16V7K PCIE_CTX_GRX_N10 D23
<40> PCIE_CTX_C_GRX_N10 PCIE_CTX_GRX_P10 PCIE10_TXN USB2_COMP
<40> PCIE_CTX_C_GRX_P10 CC92 TBT@ 1 2 0.22U_0402_16V7K C23 AB6 RC119 1 2 113_0402_1%
PCIE10_TXP USB2_COMP AG3 USB2_ID RC130 1 2 0_0402_5%
RC120 1 2 100_0402_1% PCIE_RCOMPN F5 USB2_ID AG4 USB2_VBUSSENSE RC131 1 2 0_0402_5%
PCIE_RCOMPP E5 PCIE_RCOMPN USB2_VBUSSENSE
#543016 P.239 PCIE_RCOMPN/PCIE_RCOMPP PCIE_RCOMPP USB_OC0#
A9
BO=4 W=12 S=12 R=100ohm XDP_PRDY# D56 GPP_E9/USB2_OC0# C9 USB_OC1# USB_OC0# <39>
<6> XDP_PRDY# PROC_PRDY# GPP_E10/USB2_OC1# T166 @
XDP_PREQ# D61 D9
<6> XDP_PREQ# PROC_PREQ# GPP_E11/USB2_OC2# NFC_IRQ
PIRQA# BB11 B9 NFC_IRQ <34>
GPP_A7/PIRQA# GPP_E12/USB2_OC3# NFC_IRQ,RST# follow PDG 1.3
PCIE_CRX_DTX_N11 E28 J1 NFC_RST#
<45> PCIE_CRX_DTX_N11 PCIE_CRX_DTX_P11 PCIE11_RXN/SATA1B_RXN GPP_E4/DEVSLP0 NFC_RST# <34>
E27 J2
<45> PCIE_CRX_DTX_P11 CC60 2 1 .1U_0402_16V7K PCIE_CTX_DRX_N11 D24 PCIE11_RXP/SATA1B_RXP GPP_E5/DEVSLP1 J3
CR <45> PCIE_CTX_C_DRX_N11 PCIE_CTX_DRX_P11 PCIE11_TXN/SATA1B_TXN GPP_E6/DEVSLP2
DEVSLP2 DEVSLP2 <34>
CC62 2 1 .1U_0402_16V7K C24
<45> PCIE_CTX_C_DRX_P11 SATA_CRX_DTX_N2 E30 PCIE11_TXP/SATA1B_TXP H2
<34> SATA_CRX_DTX_N2 SATA_CRX_DTX_P2 PCIE12_RXN/SATA2_RXN GPP_E0/SATAXPCIE0/SATAGP0
F30 H3
<34> SATA_CRX_DTX_P2 SATA_CTX_DRX_N2 A25 PCIE12_RXP/SATA2_RXP GPP_E1/SATAXPCIE1/SATAGP1 G4
+3VALW_PRIM
SSD <34> SATA_CTX_DRX_N2 SATA_CTX_DRX_P2 PCIE12_TXN/SATA2_TXN GPP_E2/SATAXPCIE2/SATAGP2
3 B25 3
<34> SATA_CTX_DRX_P2 PCIE12_TXP/SATA2_TXP H1 PCH_SATALED#
GPP_E8/SATALED# PCH_SATALED# <45> +3VALW_PRIM
RC135
2 @ 1 PIRQA# 8 OF 20
10K_0402_5% SKL-U_BGA1356
@ USB_OC0# RC132 1 2 10K_0402_5%
Acer HSIO def i ne
GPIO DEVICE CONTROL
USB_OC0# USB2 Port 1,2,4 +3VS
USB_OC1# NA
PCH_SATALED# RC139 1 2 10K_0402_5%
USB_OC2# NA NFC_RST# RC138 1 2 10K_0402_5%
USB_OC3# NA DEVSLP2 RC201 1 2 10K_0402_5%
DEVSLP[2:0] Implementation
DEVSLP0 NA DEVSLP is a host-controlled hardware signal which enables a SATA host and device to
enter an ultra-low interface power state, including the possibility to completely power
DEVSLP1 SSD down host and device PHYs.
The processor provides three SATA DEVSLP signals, DEVSLP[2:0] for SKL U.
‧When high, DEVSLP requests the SATA device to enter into the DEVSLP power state.
‧When low, DEVSLP requests the SATA device to exit from the DEVSLP power state
DEVSLP2 NA and transition to active state.
SATA_GP0 NA
SATA_GP1 NA SATA General Purpose (SATAGP[2:0]) Signals
‧The processor provides three SATA general purpose input signals,SATAGP[2:0] for SKL U.
4 These signals can be configured as interlock switch inputs corresponding to a given SATA port. 4
SATA_GP2 NA ‧When used as an interlock switch status indication, this signal should be driven to 0
to indicate that the switch is closed and to a 1 to indicate that the switch is open.
‧If mechanical presence switches will not be used on the platform, SATAGP[2:0]
signals can be configured as GPP_E[2:0] GPIOs signals.
Security Classification
2014/11/10
Compal Secret Data
2016/11/10 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SKL-U(7/12)PCIE,USB,SATA
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
LA-D301P 0.2
Date: Thursday, December 17, 2015 Sheet 12 of 63
A B C D E
A B C D E
+1.0VALW_PRIM TO +1.0V_VCCSTU / +1.0VCCST
+5VALW +1.0VALW_PRIM +1.0V_VCCSTU
+1.2V_VDDQ +1.2V_VDDQ_CPU +VCCIO
For Power consumption UC1N SKL-U
Measurement Rev_0.53
CPU POWER 3 OF 4
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 JPC1
1 2 AU23 AK28
CC98
CC97
1 VDDQ_AU23 VCCIO
@ AU28 AK30
VDDQ_AU28
@ CC96 JUMP_43X118 AU35
VDDQ_AU35
2.73A VCCIO
VCCIO
AL30
2 2 AU42 AL42
.1U_0402_16V7K VDDQ_AU42 VCCIO
2 JPC2 BB23 6.35A AM28
1 2 BB32 VDDQ_BB23 VCCIO AM30
1 VDDQ_BB32 VCCIO 1
UC5 @ BB41 AM42
CC105 2 1 .1U_0402_16V7K 1 14 JUMP_43X118 BB47 VDDQ_BB41 VCCIO
2 VIN1 VOUT1 13 BB51 VDDQ_BB47 AK23
VIN1 VOUT1 VDDQ_BB51 VCCSA +VCC_SA
AK25
RC142 1 2 20K_0402_5% EN_1.0V_VCCSTU 3 12 1 2 VCCSA G23
<39,43,47,52> SYSON ON1 CT1 AM40 VCCSA G25
CC95 +1.2V_VDDQC VDDQC
0.09A VCCSA
4 11 1000P_0402_50V7K G27
VBIAS GND A18 VCCSA G28
+1.0V_VCCST VCCST
0.04A VCCSA
RC168 1 @ 2 0_0402_5% EN_1.8VS 5 10 1 2 6A J22
<40,43,44,47,52> SUSP# ON2 CT2 A22 VCCSA J23
CC94 +1.0VS_VCCSTG VCCSTG_A22
0.04A VCCSA
2 1 CC104 6 9 1000P_0402_50V7K J27
+1.8VALW_VS 7 VIN2 VOUT2 8 AL23 VCCSA K23
@ 1U_0402_6.3V6K
VIN2 VOUT2 +1.2V_VCCSFR_OC VCCPLL_OC
0.26A VCCSA
+1.8VS K25
15 K20 VCCSA K27
GPAD +1.0V_VCCSFR VCCPLL_K20
0.12A VCCSA
+1.8VALW_PRIM 1 2 K21 K28
1 2 EM5209VF_DFN14_2X3 VCCPLL_K21 VCCSA K30
VCCSA
1U_0402_6.3V6K
JPC8 1 1
AM23 VCCIO_SENSE
CC99
JUMP_43X39 T124 @
@ CC100 VCCIO_SENSE AM22 VSSIO_SENSE
VSSIO_SENSE T125 @
@
2 +1.8VALW_PRIM TO +1.8VS 2
.1U_0402_16V7K
VSSSA_SENSE
H21
H20
VSSSA_SENSE
VCCSA_SENSE VSSSA_SENSE <55>
VCCSA_SENSE <55>
14 OF 20 VCCSA_SENSE
SKL-U_BGA1356
@
2
+1.0VALW_PRIM TO +1.0VS_VCCSTG 2
+1.0VALW_PRIM
+1.0VALW_PRIM_JP
JPC4 VCCSTG and VCCIO SLEW RATE <=65us +1.2V_VDDQC
1 2 +1.2V_VDDQ_CPU
1 2 +1.0VS_VCCSTG PSC Side 543016_SKL_PDG_1_0
1U_0402_6.3V6K
Imax : 2.77 AJUMP_43X79 1
RC188 1 2 0_0402_5% RC208 1 2 0_0402_5% 1 2 10U_0603_6.3V6M +1.35V_VDDQC : 1x 1uF 0201 (Placeholder)
CC117
@ @ @ CC47
For Power consumption UC6 1x 10uF 0402
Measurement 1
2 2 VIN1 +VCCIO
+5VALW VIN2 @ J16 +1.0V_VCCSTU +1.0V_VCCST
CC107 7 6 +1.0VS_VCCSTG_IO 1 2 PSC Side
VIN thermal VOUT 1 2
.1U_0402_16V7K 1U_0402_6.3V6K 543016_SKL_PDG_1_0
2 1 3 JUMP_43X79 Imax : 2.73 A RC140 1 @ 2 0_0402_5% CC48 1 2
@ VBIAS +1.0V_VCCST : 1x 1uF 0402
SUSP# RC186 1 @ 2 SUSP#_R1 4 5
ON GND +1.0V_VCCSFR PSC Side
1U_0402_6.3V6K
0_0402_5% 1
543016_SKL_PDG_1_0
CC106
TPS22961DNYR_WSON8
RC143 1 @ 2 0_0402_5% CC55 1 2 1U_0402_6.3V6K
@
+1.0V_VCCSFR : 1x 1uF 0402
2
+1.2V_VDDQ_CPU +1.2V_VCCSFR_OC BSC Side
543016_SKL_PDG_1_0
RC141 1 @ 2 0_0402_5% CC49 1 2 1U_0402_6.3V6K +1.35V_VCCSFR_OC : 1x 1uF 0201
3 3
+1.0VALW_PRIM_JP BSC Side
U4902 543016_SKL_PDG_1_0
CC56 1 2 1U_0402_6.3V6K
1 7 +1.0VS_VCCSTG_IO +1.0VS_VCCSTG
@
+1.0VS_VCCSTG : 1x 1uF 0402 (Placeholder)
2 VIN VOUT 8
VIN VOUT
SUSP#_R1 3 6 1 2 C977
ON CT 1000P_0402_50V7K +1.2V_VDDQ_CPU
@ PSC Side BSC Side
+5VALW 4
VBIAS 5
GND 9
GND
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
AOZ1336_DFN8_2X2 1 1 1 1 1 1 1 1 1 1 1
CC37
CC41
CC54
@
CC38
CC39
CC40
CC42
CC43
CC44
CC45
CC46
@ @ @ @
+VCCIO 2 2 2 2 2 2 2 2 2 2 2
BSC Side PSC Side
543016_SKL_PDG_1_0
22U_0603_6.3V6M
22U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 1 1 1 1 1 1 1 1 1 +1.35V_VDDQ_CPU : 2x 10uF 0402 (Placeholder)
CC58
CC59
4 4
4x 1uF 0201 (Placeholder)
CC27
CC28
CC29
CC30
CC31
CC32
CC33
CC34
CC35
CC36
@
2
@
2
@
2
@
2
@
2
@
2
@
2
@
2 2 2 2 2
4x 10uF 0402
3x 22uF 0603
Security Classification Compal Secret Data Compal Electronics, Inc.
543016_SKL_PDG_1_0 Issued Date 2014/11/10 Deciphered Date 2016/11/10 Title
+VCCIO : 2x10uF 0402 (Placeholder)
4x 1uF 0201 (Placeholder) THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SKL-U(8/12)Power
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
4x 1uF 0402 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
LA-D301P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, December 17, 2015 Sheet 13 of 63
A B C D E
A B C D E
+1.0VALW_PRIM +3VALW_PRIM
+3VALW_1.8VALW_PGPPA +1.8VALW_PRIM
+1.0V_PRIM_CORE
+1.0VALW_PRIM UC1O SKL-U EC LPC/ESPI
CC91 Rev_0.53 0_0402_5% 2 ESPI@ 1 RC196
CPU POWER 4 OF 4
2 1 1U_0402_6.3V6K 0_0402_5% 2 @ 1RC197
RC192 @ 0_0603_5% C2012 Follow LA-C641P @ AB19
VCCPRIM_1P0
1 2 1 2 Near AB19 (<10 mm) AB20 0.89A AK15 +3VALW_PGPPB +3VALW_PRIM
VCCPRIM_1P0 VCCPGPPA +3VALW_1.8VALW_PGPPA
47U_0805_6.3V6M P18 AG15 +3VALW_PGPPB
VPRO@ VCCPRIM_1P0 VCCPGPPB Y16
+1.0V_PRIM_CORE VCCPGPPC +3VALW_PGPPC
AF18 Y15 +3VALW_1.8VALW_PGPPD
SPI Touch CC102 2 1 0_0402_5% 2 @ 1RC161
2 1 CC76 AF19 VCCPRIM_CORE VCCPGPPD T16
VCCPRIM_CORE
2.57A VCCPGPPE +3VALW_PGPPE 1U_0402_6.3V6K @
1 +1.0VALW_MPHYAON @ 1U_0402_6.3V6K V20
VCCPRIM_CORE VCCPGPPF
AF16 +1.8VALW_PRIM CC102 near AG15 (<3 mm) 1
+1.0VALW_PRIM near AF18 (<10 mm) V21 AD15
VCCPRIM_CORE VCCPGPPG +3VALW_PGPPG No use
+3VALW_PRIM
+3VALW_PGPPC
RC175 1 @ 2 0_0402_5% 1 2 CC87 CC85 21 DCPDSW_1P0 AL1 V19 +3VALW_PRIM
1U_0402_6.3V6K 1U_0402_6.3V6K
<BOM Structure> DCPDSW_1P0 VCCPRIM_3P3_V19
CC87 near K17 (<3 mm) +1.0VALW_MPHYAON K17 T1 +1.0VALW_DTS CC73 2 1 0_0402_5% 2 @ 1RC163
L1 VCCMPHYAON_1P0 VCCPRIM_1P0_T1 1U_0402_6.3V6K @
VCCMPHYAON_1P0 AA1 +1.8VALW_PRIM CC73 near Y16 (<10 mm)
+1.0VALW_PRIM +1.0VALW_APLL N15 VCCATS_1P8
+1.0VALW_MPHYGT VCCMPHYGT_1P0_N15 +3VALW_PRIM
N16 AK17 +3VALW_RTC +3VALW_1.8VALW_PGPPD
RC148 @ 0_0603_5% N17 VCCMPHYGT_1P0_N16 HSIO VCCRTCPRIM_3P3 +1.8VALW_PRIM
1 2 1 2 P15 VCCMPHYGT_1P0_N17 AK19
CC123
VCCMPHYGT_1P0_P15
2.1A VCCRTC_AK19 +RTCVCC
@ 22U_0603_6.3V6M P16 BB14 0_0402_5% 1 @ 2 RC206
1 2 CC118 VCCMPHYGT_1P0_P16 VCCRTC_BB14 CC103 2 1 0_0402_5% 2 @ 1RC172
@ .1U_0402_16V7K +1.0VALW_AMPHYPLL K15 BB10 CC71 1 2 .1U_0402_16V7K 1U_0402_6.3V6K <BOM Structure>
INTEL Sightings report recommends L15 VCCAMPHYPLL_1P0 HSIO DCPRTC
reserve 0.1uF for RF 5.76GHz noise VCCAMPHYPLL_1P0 A14 +3VALW_PGPPE +3VALW_PRIM
+3VALW VCCCLK1 +1.0VALW_CLK6_24TBT
+3VALW_DSW +1.0VALW_APLL V15
VCCAPLL_1P0 K19
VCCCLK2 +1.0VALW_VCCCLK2
+1.0VALW_PRIM AB17 CC74 2 1 0_0402_5% 2 @ 1RC167
RC173 1 @ 2 0_0402_5% Y18 VCCPRIM_1P0_AB17 L21 1U_0402_6.3V6K @
VCCPRIM_1P0_Y18 VCCCLK3 +1.0VALW_APLL
CC74 near T16 (<10 mm)
+3VALW_DSW AD17 N20 +1.0VALW_CLK4_F100OC
+3VM +3VALW_SPI AD18 VCCDSW_3P3_AD17 VCCCLK4 +3VALW_PRIM
AJ17 VCCDSW_3P3_AD18 L19 +3VALW_PGPPG
VCCDSW_3P3_AJ17 VCCCLK5 +1.0VALW_CLK5_F24NS
RC154 1 @ 2 0_0402_5% 0_0402_5%
+3VALW_HDA AJ19 A10 +1.0VALW_CLK6_24TBT CC83 2 1 2 @ 1RC187
VCCHDA VCCCLK6 1U_0402_6.3V6K @
+3VALW_PRIM +3VALW_HDA CC63 near AJ19 (<10 mm) AJ16 AN11 PRIMCORE_VID0
+3VALW_SPI VCCSPI GPP_B0/CORE_VID0 T136 @
AN13 PRIMCORE_VID1
2 GPP_B1/CORE_VID1 T138 @ 2
RC198 1 @ 2 0_0402_5% 1 2 CC63 +1.0VALW_SRAM AF20 CC67 2 1 +3VALW_PRIM
@ 1U_0402_6.3V6K AF21 VCCSRAM_1P0 HSIO 1U_0402_6.3V6K @
1 2 CC110 T19 VCCSRAM_1P0 CC67 near V19 (<3 mm)
@ .1U_0402_16V7K T20 VCCSRAM_1P0
INTEL Sightings report recommends VCCSRAM_1P0
reserve 0.1uF for RF 5.76GHz noise
AJ21 +1.0VALW_DTS +1.0VALW_PRIM
+3VALW_PRIM VCCPRIM_3P3_AJ21
+1.0VALW_PRIM AK20 0_0402_5% 2 @ 1RC162
VCCPRIM_1P0_AK20
+3VALW +3VALW_PRIM N18
+1.0VALW_APLLEBB VCCAPLLEBB
JPC7 +1.0V_MPHYPLL HSIO 15 OF 20 CC72 2 1 +1.8VALW_PRIM
1 2 1U_0402_6.3V6K
1 2 SKL-U_BGA1356 CC72 near AA1 (<10 mm)
JUMP_43X39 @
@ +3VALW_RTC +3VALW_PRIM
+1.0VALW_MPHYPLL
+1.0VALW_PRIM HSIO +1.0VALW_MPHYGT CC78 2 1 0_0402_5% 2 @ 1RC171
Imax : 3.5 A .1U_0402_16V7K
JPC9 RC209 @ 0_0603_5% VCCMPHYGT CC77 2 1
1 2 1 2 CC82 1 2 22U_0603_6.3V6M 1U_0402_6.3V6K
1 2 @ CC77,CC78 near AK17 (<3 mm)
JUMP_43X79 CC81 1 2 22U_0603_6.3V6M
@ @ Per 543016_SKL_U_Y_PDG_0_9
CC80 1 2 1U_0402_6.3V6K +1.0VALW_CLK6_24TBT +1.0VALW_PRIM
CC80 near N15 (<3mm)
CC81,CC82 near N15 (<10mm)
<BOM Structure>
VCCRTC does not exceed 3.2 V From PDG
RTC Battery CC86 2 1 0_0402_5% 2 @ 1RC169
1U_0402_6.3V6K @
Power Rail Voltage +RTCBATT +CHGRTC W=20mils CC86 near A10 (<3 mm)
3 +1.0VALW_AMPHYPLL DC1 3
2 +RTCVCC
+CHGRTC 3.383V(MAX) W=10mil +1.0VALW_VCCCLK2 +1.0VALW_PRIM
RC149 @ 0_0603_5% CC61 near K15 (<3 mm) 1 0_0603_5% @ RC164
1 2 CC61 1 2 1U_0402_6.3V6K W=20mils CC75 2 1 2 1
@ BAT54C(VF) 240 mV 3 1U_0402_6.3V6K @
+1.0VALW_SRAM 1 CC124 2 1
BAS40-04_SOT23-3 22U_0603_6.3V6M @
RC176 @ 0_0603_5% CC122 near AF20 (<10mm) +3VL_RTC 3.143V C151
1 2 CC122 1 2 1U_0402_6.3V6K cap Place close AK19. .1U_0402_16V7K
@ 2 +1.0VALW_CLK4_F100OC +1.0VALW_PRIM
Result : Pass 0_0603_5% @ RC190
CC125 2 1 2 1
+1.0VALW_APLLEBB 22U_0603_6.3V6M @
CC68 near N18 (<3mm)
RC156 1 @ 2 0_0402_5% CC68 1 2 1U_0402_6.3V6K +1.0VALW_CLK5_F24NS +1.0VALW_PRIM
<BOM Structure> 0_0603_5% @ RC152
2 1
Follow 543016_SKL_U_Y_PDG_0_9
+1.0VALW_PRIM +3VALW_PRIM +1.8VALW_PRIM
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
1 1 1 1 1 1
CC111
CC112
CC113
CC114
CC116
CC115
4 4
@ @ @ @ @ @
2 2 2 2 2 2
Security Classification
2014/11/10
Compal Secret Data
2016/11/10 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SKL-U(9/12)Power
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
LA-D301P 0.2
Date: Thursday, December 17, 2015 Sheet 14 of 63
A B C D E
A B C D E
VCC 27A (U 15W Dual Core GT2) VCCGT / VCCGTX(2+3e only) 40A(need confirm)
+VCC_CORE +VCC_CORE +VCC_GT +VCC_GT
UC1M SKL-U
UC1L SKL-U Rev_0.53
#5449 4 Skylake EDS P.1 0 #5449 4 Skylake EDS P.1 1
#544924 Skylake EDS P.125 Rev_0.53 CPU POWER 2 OF 4
CPU POWER 1 OF 4 VCC U(15W)-dual core GT 7A(Typ)- A(MAX) VCCGT U(15W)-dual core GT 40A(MAX)
0.55-1.15V 0.55-1.15V N70
A30 G32 A48 VCCGT N71
A34 VCC_A30 VCC_G32 G33 A53 VCCGT VCCGT R63
A39 VCC_A34 VCC_G33 G35 A58 VCCGT VCCGT R64
1 VCC_A39 VCC_G35 VCCGT VCCGT 1
A44 G37 A62 R65
AK33 VCC_A44 VCC_G37 G38 A66 VCCGT VCCGT R66
AK35 VCC_AK33 VCC_G38 G40 AA63 VCCGT VCCGT R67
AK37 VCC_AK35 VCC_G40 G42 AA64 VCCGT VCCGT R68
AK38 VCC_AK37 VCC_G42 J30 AA66 VCCGT VCCGT R69
AK40 VCC_AK38 VCC_J30 J33 AA67 VCCGT VCCGT R70
AL33 VCC_AK40 VCC_J33 J37 AA69 VCCGT VCCGT R71
AL37 VCC_AL33 VCC_J37 J40 AA70 VCCGT VCCGT T62
AL40 VCC_AL37 VCC_J40 K33 AA71 VCCGT VCCGT U65
AM32 VCC_AL40 VCC_K33 K35 AC64 VCCGT VCCGT U68
AM33 VCC_AM32 VCC_K35 K37 AC65 VCCGT VCCGT U71
AM35 VCC_AM33 VCC_K37 K38 AC66 VCCGT VCCGT W63
AM37 VCC_AM35 VCC_K38 K40 AC67 VCCGT VCCGT W64
AM38 VCC_AM37 VCC_K40 K42 AC68 VCCGT VCCGT W65
G30 VCC_AM38 VCC_K42 K43 AC69 VCCGT VCCGT W66
VCC_G30 VCC_K43
Trace Length < 25 mils VCCGT VCCGT
AC70 W67
K32 E32 AC71 VCCGT VCCGT W68
RSVD_K32 VCC_SENSE VCCSENSE <55> VCCGT VCCGT
E33 J43 W69
VSS_SENSE VSSSENSE <55> VCCGT VCCGT
#5449 4 Skylake EDS P.1 5 AK32 J45 W70
RSVD_AK32 B63 SOC_SVID_ALERT# J46 VCCGT VCCGT W71
VCCOPC 1V .8A VIDALERT# SOC_SVID_CLK VCCGT VCCGT
AB62 A63 J48 Y62
VCC OPC 1P8 1.8V 50mA P62 VCCOPC_AB62 VIDSCK D64 SOC_SVID_DAT SOC_SVID_CLK <55>
J50 VCCGT VCCGT
VCCEOPIO 0V,0.8V,1V .9A V62 VCCOPC_P62 VIDSOUT J52 VCCGT
VCCOPC_V62 G20 +1.0VS_VCCSTG J53 VCCGT AK42
H63 VCCSTG_G20 J55 VCCGT VCCGTX_AK42 AK43
VCC_OPC_1P8_H63
+1.0VS(SUSP#) VCCGT VCCGTX_AK43
J56 AK45
G61 J58 VCCGT VCCGTX_AK45 AK46
VCC_OPC_1P8_G61 J60 VCCGT VCCGTX_AK46 AK48
For CPU2+3e SKU VCCGT VCCGTX_AK48
VCCOPC_SENSE AC63 K48 AK50
2 T132 @ VSSOPC_SENSE VCCOPC_SENSE VCCGT VCCGTX_AK50 2
T133 @ AE63 K50 AK52
VSSOPC_SENSE K52 VCCGT VCCGTX_AK52 AK53
AE62 K53 VCCGT VCCGTX_AK53 AK55
AG62 VCCEOPIO K55 VCCGT VCCGTX_AK55 AK56
VCCEOPIO K56 VCCGT VCCGTX_AK56 AK58
VCCEOPIO_SENSE AL63 K58 VCCGT VCCGTX_AK58 AK60
T137 @ VSSEOPIO_SENSE VCCEOPIO_SENSE VCCGT VCCGTX_AK60
T139 @ AJ62 K60 AK70
VSSEOPIO_SENSE L62 VCCGT VCCGTX_AK70 AL43
12 OF 20
VCCGT VCCGTX_AL43
For CPU2+3e SKU
L63 AL46
SKL-U_BGA1356 L64 VCCGT VCCGTX_AL46 AL50
@ L65 VCCGT VCCGTX_AL50 AL53
L66 VCCGT VCCGTX_AL53 AL56
L67 VCCGT VCCGTX_AL56 AL60
L68 VCCGT VCCGTX_AL60 AM48
L69 VCCGT VCCGTX_AM48 AM50
L70 VCCGT VCCGTX_AM50 AM52
L71 VCCGT VCCGTX_AM52 AM53
M62 VCCGT VCCGTX_AM53 AM56
N63 VCCGT VCCGTX_AM56 AM58
N64 VCCGT VCCGTX_AM58 AU58
N66 VCCGT VCCGTX_AU58 AU63
N67 VCCGT VCCGTX_AU63 BB57
N69 VCCGT VCCGTX_BB57 BB66
SVID ALERT VCCGT VCCGTX_BB66
+1.0V_VCCST VCCGT_SENSE J70 AK62 VCCGTX_SENSE
Place the PU <55> VCCGT_SENSE VSSGT_SENSE VCCGT_SENSE VCCGTX_SENSE T155 @
J69 AL61 VSSGTX_SENSE
resistors close to CPU <55> VSSGT_SENSE VSSGT_SENSE VSSGTX_SENSE T219 @
13 OF 20
1
3 Trace Length < 25 mils SKL-U_BGA1356 3
RC179 @
56_0402_5%
2
543016 PDG0.9 P.189 Need check
SOC_SVID_ALERT# 1 2 (To VR)
SOC_SVID_ALERT#_R <55>
RC180 220_0402_5%
+1.0V_VCCST
SVID DATA Place the PU
resistors close to CPU
1
RC181
100_0402_1%
2
SOC_SVID_DAT
SOC_SVID_DAT <55> (To VR)
4 4
Security Classification
2014/11/10
Compal Secret Data
2016/11/10 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SKL-U(10/12)Power,SVID
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
LA-D301P 0.2
Date: Thursday, December 17, 2015 Sheet 15 of 63
A B C D E
A B C D E
1 1
UC1P SKL-U UC1Q SKL-U
Rev_0.53 Rev_0.53 UC1R SKL-U
GND 1 OF 3 GND 2 OF 3
GND 3 OF 3 Rev_0.53
A5 AL65 AT63 BA49 F8 L18
A67 VSS VSS AL66 AT68 VSS VSS BA53 G10 VSS VSS L2
A70 VSS VSS AM13 AT71 VSS VSS BA57 G22 VSS VSS L20
AA2 VSS VSS AM21 AU10 VSS VSS BA6 G43 VSS VSS L4
AA4 VSS VSS AM25 AU15 VSS VSS BA62 G45 VSS VSS L8
AA65 VSS VSS AM27 AU20 VSS VSS BA66 G48 VSS VSS N10
AA68 VSS VSS AM43 AU32 VSS VSS BA71 G5 VSS VSS N13
AB15 VSS VSS AM45 AU38 VSS VSS BB18 G52 VSS VSS N19
AB16 VSS VSS AM46 AV1 VSS VSS BB26 G55 VSS VSS N21
AB18 VSS VSS AM55 AV68 VSS VSS BB30 G58 VSS VSS N6
AB21 VSS VSS AM60 AV69 VSS VSS BB34 G6 VSS VSS N65
AB8 VSS VSS AM61 AV70 VSS VSS BB38 G60 VSS VSS N68
AD13 VSS VSS AM68 AV71 VSS VSS BB43 G63 VSS VSS P17
AD16 VSS VSS AM71 AW10 VSS VSS BB55 G66 VSS VSS P19
AD19 VSS VSS AM8 AW12 VSS VSS BB6 H15 VSS VSS P20
AD20 VSS VSS AN20 AW14 VSS VSS BB60 H18 VSS VSS P21
AD21 VSS VSS AN23 AW16 VSS VSS BB64 H71 VSS VSS R13
AD62 VSS VSS AN28 AW18 VSS VSS BB67 J11 VSS VSS R6
AD8 VSS VSS AN30 AW21 VSS VSS BB70 J13 VSS VSS T15
AE64 VSS VSS AN32 AW23 VSS VSS C1 J25 VSS VSS T17
AE65 VSS VSS AN33 AW26 VSS VSS C25 J28 VSS VSS T18
AE66 VSS VSS AN35 AW28 VSS VSS C5 J32 VSS VSS T2
AE67 VSS VSS AN37 AW30 VSS VSS D10 J35 VSS VSS T21
AE68 VSS VSS AN38 AW32 VSS VSS D11 J38 VSS VSS T4
AE69 VSS VSS AN40 AW34 VSS VSS D14 J42 VSS VSS U10
2 VSS VSS VSS VSS VSS VSS 2
AF1 AN42 AW36 D18 J8 U63
AF10 VSS VSS AN58 AW38 VSS VSS D22 K16 VSS VSS U64
AF15 VSS VSS AN63 AW41 VSS VSS D25 K18 VSS VSS U66
AF17 VSS VSS AP10 AW43 VSS VSS D26 K22 VSS VSS U67
AF2 VSS VSS AP18 AW45 VSS VSS D30 K61 VSS VSS U69
AF4 VSS VSS AP20 AW47 VSS VSS D34 K63 VSS VSS U70
AF63 VSS VSS AP23 AW49 VSS VSS D39 K64 VSS VSS V16
AG16 VSS VSS AP28 AW51 VSS VSS D44 K65 VSS VSS V17
AG17 VSS VSS AP32 AW53 VSS VSS D45 K66 VSS VSS V18
AG18 VSS VSS AP35 AW55 VSS VSS D47 K67 VSS VSS W13
AG19 VSS VSS AP38 AW57 VSS VSS D48 K68 VSS VSS W6
AG20 VSS VSS AP42 AW6 VSS VSS D53 K70 VSS VSS W9
AG21 VSS VSS AP58 AW60 VSS VSS D58 K71 VSS VSS Y17
AG71 VSS VSS AP63 AW62 VSS VSS D6 L11 VSS VSS Y19
AH13 VSS VSS AP68 AW64 VSS VSS D62 L16 VSS VSS Y20
AH6 VSS VSS AP70 AW66 VSS VSS D66 L17 VSS VSS Y21
AH63 VSS VSS AR11 AW8 VSS VSS D69 VSS VSS
AH64 VSS VSS AR15 AY66 VSS VSS E11
AH67 VSS VSS AR16 B10 VSS VSS E15 18 OF 20
AJ15 VSS VSS AR20 B14 VSS VSS E18
AJ18 VSS VSS AR23 B18 VSS VSS E21 SKL-U_BGA1356
AJ20 VSS VSS AR28 B22 VSS VSS E46 @
AJ4 VSS VSS AR35 B30 VSS VSS E50
AK11 VSS VSS AR42 B34 VSS VSS E53
AK16 VSS VSS AR43 B39 VSS VSS E56
AK18 VSS VSS AR45 B44 VSS VSS E6
AK21 VSS VSS AR46 B48 VSS VSS E65
AK22 VSS VSS AR48 B53 VSS VSS E71
AK27 VSS VSS AR5 B58 VSS VSS F1
3 VSS VSS VSS VSS 3
AK63 AR50 B62 F13
AK68 VSS VSS AR52 B66 VSS VSS F2
AK69 VSS VSS AR53 B71 VSS VSS F22
AK8 VSS VSS AR55 BA1 VSS VSS F23
AL2 VSS VSS AR58 BA10 VSS VSS F27
AL28 VSS VSS AR63 BA14 VSS VSS F28
AL32 VSS VSS AR8 BA18 VSS VSS F32
AL35 VSS VSS AT2 BA2 VSS VSS F33
AL38 VSS VSS AT20 BA23 VSS VSS F35
AL4 VSS VSS AT23 BA28 VSS VSS F37
AL45 VSS VSS AT28 BA32 VSS VSS F38
AL48 VSS VSS AT35 BA36 VSS VSS F4
AL52 VSS VSS AT4 F68 VSS VSS F40
AL55 VSS VSS AT42 BA45 VSS VSS F42
AL58 VSS VSS AT56 VSS VSS BA41
AL64 VSS VSS AT58 VSS
VSS VSS
16 OF 20 17 OF 20
SKL-U_BGA1356 SKL-U_BGA1356
@ @
4 4
Security Classification
2014/11/10
Compal Secret Data
2016/11/10 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SKL-U(11/12)GND
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
LA-D301P 0.2
Date: Thursday, December 17, 2015 Sheet 16 of 63
A B C D E
A B C D E
1 1
UC1S SKL-U
Rev_0.53
RESERVED SIGNALS-1
<6> CFG0 CFG0 E68 BB68 T156 @
CFG1 B67 CFG[0] RSVD_TP_BB68 BB69
<6> CFG1 CFG[1] RSVD_TP_BB69 T157 @
<6> CFG2 CFG2 D65
CFG3 D67 CFG[2] AK13
<6> CFG3 CFG[3] RSVD_TP_AK13 T158 @
<6> CFG4 CFG4 E70 AK12 T159 @
CFG5 C68 CFG[4] RSVD_TP_AK12
<6> CFG5 CFG[5]
<6> CFG6 CFG6 D68 BB2
CFG7 C67 CFG[6] RSVD_BB2 BA3
<6> CFG7 CFG[7] RSVD_BA3
<6> CFG8 CFG8 F71
CFG9 G69 CFG[8]
<6> CFG9 CFG[9]
CFG Signals <6> CFG10 CFG10 F70 AU5 T162 @
CFG11 G68 CFG[10] TP5 AT5
<6> CFG11 CFG[11] TP6 T163 @
(For Strap & XDP)
<6> CFG12 CFG12 H70
CFG13 G71 CFG[12]
<6> CFG13 CFG[13]
<6> CFG14 CFG14 H69 D5
CFG15 G70 CFG[14] RSVD_D5 D4
<6> CFG15 CFG[15] RSVD_D4 B2 UC1T SKL-U
CFG16 E63 RSVD_B2 C2
<6> CFG16 CFG[16] RSVD_C2 Rev_0.53
<6> CFG17 CFG17 F63 SPARE
CFG[17] B3
CFG18 E66 RSVD_B3 A3 AW69 F6
<6> CFG18 CFG[18] RSVD_A3 RSVD_AW69 RSVD_F6
<6> CFG19 CFG19 F66 AW68 E3
CFG[19] AW1 +1.8VALW_PRIM AU56 RSVD_AW68 RSVD_E3 C11
2 RSVD_AW1 RSVD_AU56 RSVD_C11 2
CFG_RCOMP E60 AW48 B11
CFG_RCOMP E1 C7 RSVD_AW48 RSVD_B11 A11
XDP_ITP_PMODE E8 RSVD_E1 E2 RC57 2 @ 1 +1.8VALW_PRIM_U11 U12 RSVD_C7 RSVD_A11 D12
<6> XDP_ITP_PMODE ITP_PMODE RSVD_E2 RSVD_U12 RSVD_D12
0_0402_5% 2 @ 1 U11 C12
AY2 BA4 RC58 H11 RSVD_U11 RSVD_C12 F52
AY1 RSVD_AY2 RSVD_BA4 BB4 0_0402_5% RSVD_H11 RSVD_F52
RSVD_AY1 RSVD_BB4 20 OF 20
1
D1 A4
D3 RSVD_D1 RSVD_A4 C4 CC79 SKL-U_BGA1356
RSVD_D3 RSVD_C4 @
1U_0402_6.3V6K
K46 BB5 2
RSVD_K46 TP4 T199 @ @
#544924 SKylake EDS 0.75 P.117 K45
RSVD_K45
‧RSVD - these signals should not be connected RSVD_A69
A69 CC79 near U11,U12 (<10 mm)
‧RSVD_TP - these signals should be routed to a test point AL25 B69 14MOW52, Connect U11, U12 to
AL27 RSVD_AL25 RSVD_B69
‧RSVD_NCTF - these signals are non-critical to function RSVD_AL27 1.8V for Cannonlake-U PCH
AY3 RC182 1 @ 2 0_0402_5% compatibility
and may be left un-connected C71 RSVD_AY3
B70 RSVD_C71 D71
RSVD_B70 RSVD_D71 C70
F60 RSVD_C70
RSVD_F60 C54
A52 RSVD_C54 D54
RSVD_A52 RSVD_D54
T213 @ BA70
RSVD_TP_BA70 TP1
AY4 T214 @ For 2+3e Solution
T215 @ BA68 BB3 T216 @
RSVD_TP_BA68 TP2
PM_ZVM#
J71 AY71 RC183 1 @ 2 0_0402_5% Zero Voltage Mode: Control Signal to OPC
J68 RSVD_J71 VSS_AY71 AR56 PM_ZVM#
RSVD_J68 ZVM# T225 @ VR, when low OPC VR output is 0V.
3 3
T220 @ F65 AW71 T221 @
G65 VSS_F65 RSVD_TP_AW71 AW70 PM_MSM#
T222 @ VSS_G65 RSVD_TP_AW70 T223 @ Minimum Speed Mode: Control signal to
F61 AP56 PM_MSM# T230 @ +1.0V_VCCST VccEOPIO VR (connected only in 2 VR
E61 RSVD_F61 MSM# C64 solution for OPC).
RSVD_E61 PROC_SELECT#
19 OF 20 SKL_CNL# 1 @ 2
RC184 100K_0402_5%
SKL-U_BGA1356 PROC_SELECT#
@ Processor Select: This pin is for
compatibility with future platforms. It should
Follow 544669_SKL_U_DDR3L_RVP7_schematic_rev1.0 NC with Skylake
CFG_RCOMP 1 2
RC185 49.9_0402_1%
CFG4 1 2
RC193 1K_0402_1%
4 4
Display Port Presence Strap
1 : Disabled; No Physical Display Port
CFG4 attached to Embedded Display Port
Security Classification Compal Secret Data Compal Electronics, Inc.
0 : Enabled; An external Display Port device is Issued Date 2014/11/10 Deciphered Date 2016/11/10 Title
connected to the Embedded Display Port
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SKL-U(12/12)RSVD
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
LA-D301P 0.2
Date: Thursday, December 17, 2015 Sheet 17 of 63
A B C D E
A B C D E
<7>
<7>
DDR_B_DQS#[0..7]
DDR_B_D[0..63]
Reverse Type
<7> DDR_B_DQS[0..7] 2-3A to 1 DIMMs/channel
+1.2V_VDDQ +1.2V_VDDQ
<7> DDR_B_MA[0..16]
DDR_B_BA0 JDIMM1
<7> DDR_B_BA0 DDR_B_BA1 +1.2V_VDDQ
1 2
<7> DDR_B_BA1 DDR_B_BG0 DDR_B_D14 VSS VSS DDR_B_D11
3 4
<7> DDR_B_BG0 DDR_B_BG1 DQ5 DQ4
5 6
<7> DDR_B_BG1 DDR_B_D15 VSS VSS DDR_B_D10
7 8
9 DQ1 DQ0 10
DDR_B_DQS#1 11 VSS VSS 12 +DIMM_VREF_DQ
DDR_B_DQS1 13 DQS0_C DM0*/DBI0* 14
DDR_B_CLK0 DQS0_T VSS DDR_B_D8
2
15 16
<7> DDR_B_CLK0 DDR_B_CLK#0 DDR_B_D13 VSS DQ6
17 18 RD194
<7> DDR_B_CLK#0 DDR_B_CLK1 DQ7 VSS DDR_B_D9
1 19 20 1K_0402_1% 1
<7> DDR_B_CLK1 DDR_B_CLK#1 DDR_B_D12 VSS DQ2
21 22 RD10
<7> DDR_B_CLK#1
23 DQ3 VSS 24 DDR_B_D4 0mil 2_0402_1%
DDR_B_D1 VSS DQ12
1
25 26 2 1
DDR_B_CKE0 DQ13 VSS DDR_B_D0 <7> +0.6V_B_VREFDQ
27 28
<7> DDR_B_CKE0 DDR_B_CKE1 DDR_B_D5 VSS DQ8
29 30
<7> DDR_B_CKE1 DDR_B_CS#0 DQ9 VSS DDR_B_DQS#0
31 32 1
<7> DDR_B_CS#0 DDR_B_CS#1 VSS DQS1_C DDR_B_DQS0
33 34
<7> DDR_B_CS#1 DM1*/DBI1* DQS1_T
35 36 CD21
DDR_B_D3 37 VSS VSS 38 DDR_B_D6 0.022U_0402_16V7K
SOC_SMBDATA 39 DQ15 DQ14 40 2
<8,18,33> SOC_SMBDATA SOC_SMBCLK DDR_B_D2 VSS VSS DDR_B_D7
41 42
<8,18,33> SOC_SMBCLK DQ10 DQ11
2
43 44
DDR_B_D21 45 VSS VSS 46 DDR_B_D20 RD12 RD199
DDR_B_ODT0 47 DQ21 DQ20 48
<7> DDR_B_ODT0 24.9_0402_1% 1K_0402_1%
DDR_B_ODT1 DDR_B_D17 49 VSS VSS 50 DDR_B_D16
<7> DDR_B_ODT1 DQ17 DQ16
51 52
DDR_B_DQS#2 VSS VSS
1
53 54
DDR_B_DQS2 55 DQS2_C DM2*/DBI2* 56
57 DQS2_T VSS 58 DDR_B_D19
Note: DDR_B_D23 VSS DQ22
Layout Note: 59 60
Check voltage tolerance of 61 DQ23 VSS 62 DDR_B_D18
Place near JDIMM1 VREF_DQ at the DIMM socket DDR_B_D22 63 VSS DQ18 64
65 DQ19 VSS 66 DDR_B_D28
DDR_B_D29 67 VSS DQ28 68
69 DQ29 VSS 70 DDR_B_D24
DDR_B_D25 71 VSS DQ24 72
73 DQ25 VSS 74 DDR_B_DQS#3
+1.2V_VDDQ 75 VSS DQS3_C 76 DDR_B_DQS3
77 DM3*/DBI3* DQS3_T 78
DDR_B_D30 79 VSS VSS 80 DDR_B_D31
81 DQ30 DQ31 82
DDR_B_D26 83 VSS VSS 84 DDR_B_D27
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
85 DQ26 DQ27 86
1 1 1 1 1 1 1 1 VSS VSS
87 88
89 CB5_NC CB4_NC 90
CD4
CD5
CD6
CD7
CD8
CD9
CD17
CD18
91 VSS VSS 92
2 2 2 2 2 2 2 2 93 CB1_NC CB0_NC 94
1 2 95 VSS VSS 96
6/16 INTEL suggest RD165
1 240_0402_1%
2 97 DQS8_C DM8*/DBI8* 98
RD166 240_0402_1% 99 DQS8_T VSS 100
101 VSS CB6_NC 102
103 CB2_NC VSS 104
4 as near side of the DIMM close to VDD pins VSS CB7_NC
105 106
107 CB3_NC VSS 108 DDR_DRAMRST#_R
2 +1.2V_VDDQ DDR_B_CKE0 109 VSS RESET* 110 DDR_B_CKE1 2
111 CKE0 CKE1 112
DDR_B_BG1 VDD1 VDD2 1
113 114 @
DDR_B_BG0 BG1 ACT* M_B_ACT# <7>
115 116 CD34
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
BG0 ALERT* DDR_B_ALERT# <7>
117 118 .1U_0402_16V7K
DDR_B_MA12 119 VDD3 VDD4 120 DDR_B_MA11 2
DDR_B_MA9 121 A12 A11 122 DDR_B_MA7
1 1 1 1 1 1 1 1 A9 A7
123 124 +1.2V_VDDQ
CD10
CD11
CD12
CD13
CD14
CD19
CD15
CD20
DDR_B_MA8 125 VDD5 VDD6 126 DDR_B_MA5
DDR_B_MA6 127 A8 A5 128 DDR_B_MA4
2 2 2 2 2 2 2 2 129 A6 A4 130
DDR_B_MA3 131 VDD7 VDD8 132 DDR_B_MA2
DDR_B_MA1 133 A3 A2 134
135 A1 EVENT* 136
DDR_B_CLK0 VDD9 VDD10 DDR_B_CLK1
1
137 138
DDR_B_CLK#0 139 CK0_T CK1_T 140 DDR_B_CLK#1 RD43
141 CK0_C CK1_C 142
VDD11 VDD12 470_0402_1%
143 144 DDR_B_MA0
<7> DDR_B_PARITY PARITY A0
2
DDR_DRAMRST#_R RD45 1 @ 2 0_0402_5%
DDR_B_BA1 DDR_B_MA10 DDR_DRAMRST# <7,19>
145 146
147 BA1 A10_AP 148
DDR_B_CS#0 149 VDD13 VDD14 150 DDR_B_BA0
DDR_B_MA14 151 S0* BA0 152 DDR_B_MA16
153 A14_WE* A16_RAS* 154 +DIMM_VREF_DQ
DDR_B_ODT0 155 VDD15 VDD16 156 DDR_B_MA15
DDR_B_CS#1 157 ODT0 A15_CAS* 158 DDR_B_MA13
159 S1* A13 160
DDR_B_ODT1 161 VDD17 VDD18 162
+3VS 163 ODT1 S2*/C0 164
165 VDD19 VREFCA 166
Place these caps on the VTT plane close to DIMM S3*/C1 SA2
167 168
DDR_B_D37 169 VSS VSS 170 DDR_B_D36
+0.6VS_VTT 171 DQ37 DQ36 172
DDR_B_D33 173 VSS VSS 174 DDR_B_D32
+3VS_DIMM 175 DQ33 DQ32 176
DDR_B_DQS#4 177 VSS VSS 178
DDR_B_DQS4 179 DQS4_C DM4*/DBI4* 180
181 DQS4_T VSS 182 DDR_B_D39
10U_0603_6.3V6M
10U_0603_6.3V6M
1 1 1 1 1 1 1 1 DDR_B_D38 VSS DQ39
CD30 CD31 CD32 CD33 183 184
CD22
CD23
C2142 CD28 185 DQ38 VSS 186 DDR_B_D35
2.2U_0402_6.3V6M DDR_B_D34 187 VSS DQ35 188
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
.1U_0402_16V7K DQ34 VSS
2 2 2 2 2 2 2 2 189 190 DDR_B_D45
DDR_B_D44 191 VSS DQ45 192
3 3
193 DQ44 VSS 194 DDR_B_D41
DDR_B_D40 195 VSS DQ41 196
197 DQ40 VSS 198 DDR_B_DQS#5
close to DIMM VSS DQS5_C DDR_B_DQS5
199 200
201 DM5*/DBI5* DQS5_T 202
DDR_B_D43 203 VSS VSS 204 DDR_B_D47
205 DQ46 DQ47 206
DDR_B_D42 207 VSS VSS 208 DDR_B_D46
209 DQ42 DQ43 210
DDR_B_D52 211 VSS VSS 212 DDR_B_D53
213 DQ52 DQ53 214
DDR_B_D49 215 VSS VSS 216 DDR_B_D48
217 DQ49 DQ48 218
DDR_B_DQS#6 219 VSS VSS 220
DDR_B_DQS6 221 DQS6_C DM6*/DBI6* 222
223 DQS6_T VSS 224 DDR_B_D54
DDR_B_D55 225 VSS DQ54 226
+2.5V 227 DQ55 VSS 228 DDR_B_D51
DDR_B_D50 229 VSS DQ50 230
231 DQ51 VSS 232 DDR_B_D60
DDR_B_D61 233 VSS DQ60 234
235 DQ61 VSS 236 DDR_B_D57
DDR_B_D56 237 VSS DQ57 238 +3VS
239 DQ56 VSS 240 DDR_B_DQS#7
+2.5V 241 VSS DQS7_C 242 DDR_B_DQS7 +0.6VS_VTT
243 DM7*/DBI7* DQS7_T 244
DDR_B_D59 245 VSS VSS 246 DDR_B_D63
10U_0603_6.3V6M
1 1 DQ62 DQ63
C2140 CD29 247 248
DDR_B_D58 VSS VSS DDR_B_D62
2
249 250
251 DQ58 DQ59 252 RD108
1U_0402_6.3V6K
2 2 253 VSS VSS 254
<8,18,33> SOC_SMBCLK SCL SDA SOC_SMBDATA 10K_0402_5%
<8,18,33>
+3VS_DIMM 255 256
257 VDDSPD SA0 258
VPP1 VTT
1
259 260
VPP2 SA1
1
261 RD138
GND 262
GND 0_0402_5%
CONN@ FOX_AS0A827-H2SB-7H @
2
4 4
Interleaved Memory
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2014/11/10 Deciphered Date 2016/11/10 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDR4_DIMM
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D301P
Date: Thursday, December 17, 2015 Sheet 18 of 63
A B C D E
5 4 3 2 1
+DDR_VREF_CA +DDR_VREF_CA
+DDR_VREF_CA +DDR_VREF_CA
U2 U3
U4 U5
M1 G2 DDR_A_D3 M1 G2 DDR_A_D19
VREFCA DQL0 DDR_A_D1 VREFCA DQL0 DDR_A_D17 DDR_A_D35 DDR_A_D51
0.047U_0402_25V7K
0.047U_0402_25V7K
F7 F7 M1 G2 M1 G2
DQL1 DDR_A_D2 DQL1 DDR_A_D18 VREFCA DQL0 DDR_A_D33 VREFCA DQL0 DDR_A_D49
0.047U_0402_25V7K
0.047U_0402_25V7K
H3 H3 F7 F7
DDR_A_MA0 P3 DQL2 H7 DDR_A_D0 DDR_A_MA0 P3 DQL2 H7 DDR_A_D16 DQL1 H3 DDR_A_D34 DQL1 H3 DDR_A_D50
DDR_A_MA1 A0 DQL3 DDR_A_D7 DDR_A_MA1 A0 DQL3 DDR_A_D23 DDR_A_MA0 DQL2 DDR_A_D32 DDR_A_MA0 DQL2 DDR_A_D48
1
P7 H2 P7 H2 P3 H7 P3 H7
CD124
CD125
DDR_A_MA2 A1 DQL4 DDR_A_D5 DDR_A_MA2 A1 DQL4 DDR_A_D21 DDR_A_MA1 A0 DQL3 DDR_A_D39 DDR_A_MA1 A0 DQL3 DDR_A_D55
1
R3 H8 R3 H8 P7 H2 P7 H2
CD126
CD127
DDR_A_MA3 N7 A2 DQL5 J3 DDR_A_D6 DDR_A_MA3 N7 A2 DQL5 J3 DDR_A_D22 DDR_A_MA2 R3 A1 DQL4 H8 DDR_A_D37 DDR_A_MA2 R3 A1 DQL4 H8 DDR_A_D53
DDR_A_MA4 A3 DQL6 DDR_A_D4 DDR_A_MA4 A3 DQL6 DDR_A_D20 DDR_A_MA3 A2 DQL5 DDR_A_D38 DDR_A_MA3 A2 DQL5 DDR_A_D54
2
N3 J7 N3 J7 N7 J3 N7 J3
DDR_A_MA5 A4 DQL7 DDR_A_MA5 A4 DQL7 DDR_A_MA4 A3 DQL6 DDR_A_D36 DDR_A_MA4 A3 DQL6 DDR_A_D52
2
P8 P8 N3 J7 N3 J7
DDR_A_MA6 P2 A5 DDR_A_MA6 P2 A5 DDR_A_MA5 P8 A4 DQL7 DDR_A_MA5 P8 A4 DQL7
DDR_A_MA7 R8 A6 A3 DDR_A_D10 DDR_A_MA7 R8 A6 A3 DDR_A_D26 DDR_A_MA6 P2 A5 DDR_A_MA6 P2 A5
DDR_A_MA8 R2 A7 DQU0 B8 DDR_A_D8 DDR_A_MA8 R2 A7 DQU0 B8 DDR_A_D24 DDR_A_MA7 R8 A6 A3 DDR_A_D42 DDR_A_MA7 R8 A6 A3 DDR_A_D58
D DDR_A_MA9 A8 DQU1 DDR_A_D11 DDR_A_MA9 A8 DQU1 DDR_A_D27 DDR_A_MA8 A7 DQU0 DDR_A_D40 DDR_A_MA8 A7 DQU0 DDR_A_D56 D
R7 C3 R7 C3 R2 B8 R2 B8
DDR_A_MA10 M3 A9 DQU2 C7 DDR_A_D9 DDR_A_MA10 M3 A9 DQU2 C7 DDR_A_D25 DDR_A_MA9 R7 A8 DQU1 C3 DDR_A_D43 DDR_A_MA9 R7 A8 DQU1 C3 DDR_A_D59
DDR_A_MA11 T2 A10/AP DQU3 C2 DDR_A_D14 DDR_A_MA11 T2 A10/AP DQU3 C2 DDR_A_D30 DDR_A_MA10 M3 A9 DQU2 C7 DDR_A_D41 DDR_A_MA10 M3 A9 DQU2 C7 DDR_A_D57
DDR_A_MA12 M7 A11 DQU4 C8 DDR_A_D13 DDR_A_MA12 M7 A11 DQU4 C8 DDR_A_D29 DDR_A_MA11 T2 A10/AP DQU3 C2 DDR_A_D46 DDR_A_MA11 T2 A10/AP DQU3 C2 DDR_A_D62
DDR_A_MA13 T8 A12/BC DQU5 D3 DDR_A_D15 DDR_A_MA13 T8 A12/BC DQU5 D3 DDR_A_D31 DDR_A_MA12 M7 A11 DQU4 C8 DDR_A_D45 DDR_A_MA12 M7 A11 DQU4 C8 DDR_A_D61
DDR_A_MA14 L2 A13 DQU6 D7 DDR_A_D12 DDR_A_MA14 L2 A13 DQU6 D7 DDR_A_D28 DDR_A_MA13 T8 A12/BC DQU5 D3 DDR_A_D47 DDR_A_MA13 T8 A12/BC DQU5 D3 DDR_A_D63
A14/WE DQU7 A14/WE DQU7 DDR_A_MA14 L2 A13 DQU6 D7 DDR_A_D44 DDR_A_MA14 L2 A13 DQU6 D7 DDR_A_D60
DDR_A_BA0 N2 DDR_A_BA0 N2 A14/WE DQU7 A14/WE DQU7
<7,19,20> DDR_A_BA0 DDR_A_BA1 BA0 <7,19,20> DDR_A_BA0 DDR_A_BA1 BA0 DDR_A_BA0 DDR_A_BA0
N8 B3 +1.2V_VDDQ N8 B3 +1.2V_VDDQ N2 N2 +1.2V_VDDQ
<7,19,20> DDR_A_BA1 BA1 VDD <7,19,20> DDR_A_BA1 BA1 VDD <7,19,20> DDR_A_BA0 DDR_A_BA1 BA0 <7,19,20> DDR_A_BA0 DDR_A_BA1 BA0
B9 B9 N8 B3 +1.2V_VDDQ N8 B3
VDD VDD <7,19,20> DDR_A_BA1 BA1 VDD <7,19,20> DDR_A_BA1 BA1 VDD
+1.2V_VDDQ E2 D1 +1.2V_VDDQ E2 D1 B9 B9
E7 DMU/DBIU VDD G7 E7 DMU/DBIU VDD G7 E2 VDD D1 E2 VDD D1
DML/DBIL VDD DML/DBIL VDD +1.2V_VDDQ DMU/DBIU VDD +1.2V_VDDQ DMU/DBIU VDD
J1 J1 E7 G7 E7 G7
VDD J9 VDD J9 DML/DBIL VDD J1 DML/DBIL VDD J1
VDD L1 VDD L1 VDD J9 VDD J9
DDR_A_CLK0 K7 VDD L9 DDR_A_CLK0 K7 VDD L9 VDD L1 VDD L1
<7,19> DDR_A_CLK0 DDR_A_CLK#0 CK_t VDD <7,19> DDR_A_CLK0 DDR_A_CLK#0 CK_t VDD DDR_A_CLK0 VDD DDR_A_CLK0 VDD
K8 R1 K8 R1 K7 L9 K7 L9
<7,19> DDR_A_CLK#0 DDR_A_CKE0 CK_c VDD <7,19> DDR_A_CLK#0 DDR_A_CKE0 CK_c VDD <7,19> DDR_A_CLK0 DDR_A_CLK#0 CK_t VDD <7,19> DDR_A_CLK0 DDR_A_CLK#0 CK_t VDD
K2 T9 K2 T9 K8 R1 K8 R1
<7,19,20> DDR_A_CKE0 CKE VDD <7,19,20> DDR_A_CKE0 CKE VDD <7,19> DDR_A_CLK#0 DDR_A_CKE0 CK_c VDD <7,19> DDR_A_CLK#0 DDR_A_CKE0 CK_c VDD
K2 T9 K2 T9
<7,19,20> DDR_A_CKE0 CKE VDD <7,19,20> DDR_A_CKE0 CKE VDD
A1 A1
VDDQ A9 VDDQ A9 A1 A1
VDDQ C1 VDDQ C1 VDDQ A9 VDDQ A9
VDDQ D9 VDDQ D9 VDDQ C1 VDDQ C1
VDDQ F2 VDDQ F2 VDDQ D9 VDDQ D9
VDDQ F8 VDDQ F8 VDDQ F2 VDDQ F2
DDR_A_ODT0 K3 VDDQ G1 DDR_A_ODT0 K3 VDDQ G1 VDDQ F8 VDDQ F8
<7,19,20> DDR_A_ODT0 DDR_A_CS#0 ODT VDDQ <7,19,20> DDR_A_ODT0 DDR_A_CS#0 ODT VDDQ DDR_A_ODT0 VDDQ DDR_A_ODT0 VDDQ
L7 G9 L7 G9 <7,19,20> DDR_A_ODT0 K3 G1 <7,19,20> DDR_A_ODT0 K3 G1
<7,19,20> DDR_A_CS#0 DDR_A_MA16 CS VDDQ <7,19,20> DDR_A_CS#0 DDR_A_MA16 CS VDDQ DDR_A_CS#0 ODT VDDQ DDR_A_CS#0 ODT VDDQ
L8 J2 L8 J2 L7 G9 L7 G9
DDR_A_MA15 RAS VDDQ DDR_A_MA15 RAS VDDQ <7,19,20> DDR_A_CS#0 DDR_A_MA16 CS VDDQ <7,19,20> DDR_A_CS#0 DDR_A_MA16 CS VDDQ
M8 J8 M8 J8 L8 J2 L8 J2
CAS VDDQ CAS VDDQ DDR_A_MA15 M8 RAS VDDQ J8 DDR_A_MA15 M8 RAS VDDQ J8
B2 B2 CAS VDDQ CAS VDDQ
VSS E1 VSS E1 B2 B2
VSS E9 VSS E9 VSS E1 VSS E1
VSS G8 VSS G8 VSS E9 VSS E9
DDR_A_DQS#1 A7 VSS K1 DDR_A_DQS#3 A7 VSS K1 VSS G8 VSS G8
DDR_A_DQS1 B7 DQSU_c VSS K9 DDR_A_DQS3 B7 DQSU_c VSS K9 DDR_A_DQS#5 A7 VSS K1 DDR_A_DQS#7 A7 VSS K1
DDR_A_DQS#0 F3 DQSU_t VSS M9 DDR_A_DQS#2 F3 DQSU_t VSS M9 DDR_A_DQS5 B7 DQSU_c VSS K9 DDR_A_DQS7 B7 DQSU_c VSS K9
DDR_A_DQS0 G3 DQSL_c VSS N1 DDR_A_DQS2 G3 DQSL_c VSS N1 DDR_A_DQS#4 F3 DQSU_t VSS M9 DDR_A_DQS#6 F3 DQSU_t VSS M9
DQSL_t VSS T1 DQSL_t VSS T1 DDR_A_DQS4 G3 DQSL_c VSS N1 DDR_A_DQS6 G3 DQSL_c VSS N1
MEMRST# P1 VSS MEMRST# P1 VSS DQSL_t VSS T1 DQSL_t VSS T1
RESET RESET MEMRST# P1 VSS MEMRST# P1 VSS
1 2 RU160 F9 1 2 RU161 F9 RESET RESET
240_0402_1% ZQ 240_0402_1% ZQ 1 2 RU162 F9 1 2 RU163 F9
240_0402_1% ZQ 240_0402_1% ZQ
C M_A_ACT# M_A_ACT# C
<7,19,20> M_A_ACT# L3 A2 <7,19,20> M_A_ACT# L3 A2
DDR_A_BG0 M2 ACT VSSQ A8 DDR_A_BG0 M2 ACT VSSQ A8 M_A_ACT# L3 A2 M_A_ACT# L3 A2
<7,19,20> DDR_A_BG0 BG0 VSSQ <7,19,20> DDR_A_BG0 BG0 VSSQ <7,19,20> M_A_ACT# DDR_A_BG0 ACT VSSQ <7,19,20> M_A_ACT# DDR_A_BG0 ACT VSSQ
N9 C9 N9 C9 <7,19,20> DDR_A_BG0 M2 A8 <7,19,20> DDR_A_BG0 M2 A8
DDR_A_ALERT P9 TEN VSSQ D2 DDR_A_ALERT P9 TEN VSSQ D2 N9 BG0 VSSQ C9 N9 BG0 VSSQ C9
<7,19> DDR_A_ALERT# DDR_A_PARITY ALERT VSSQ <7,19> DDR_A_ALERT# DDR_A_PARITY ALERT VSSQ DDR_A_ALERT TEN VSSQ DDR_A_ALERT TEN VSSQ
<7,19,20> DDR_A_PARITY T3 D8 <7,19,20> DDR_A_PARITY T3 D8 <7,19> DDR_A_ALERT# P9 D2 <7,19> DDR_A_ALERT# P9 D2
PAR VSSQ E3 PAR VSSQ E3 DDR_A_PARITY T3 ALERT VSSQ D8 DDR_A_PARITY T3 ALERT VSSQ D8
VSSQ VSSQ <7,19,20> DDR_A_PARITY PAR VSSQ <7,19,20> DDR_A_PARITY PAR VSSQ
T7 E8 T7 E8 E3 E3
B1 NC VSSQ F1 B1 NC VSSQ F1 T7 VSSQ E8 T7 VSSQ E8
+2.5V VPP VSSQ +2.5V VPP VSSQ NC VSSQ NC VSSQ
R9 H1 R9 H1 +2.5V B1 F1 +2.5V B1 F1
VPP VSSQ H9 VPP VSSQ H9 R9 VPP VSSQ H1 R9 VPP VSSQ H1
<7,20> DDR_A_MA[0..16] VSSQ VSSQ VPP VSSQ VPP VSSQ
96-BALL 96-BALL H9 H9
SDRAM DDR4 SDRAM DDR4 96-BALL VSSQ 96-BALL VSSQ
<7> DDR_A_DQS#[0..7]
K4A8G165WB-BCPB_FBGA96 K4A8G165WB-BCPB_FBGA96 SDRAM DDR4 SDRAM DDR4
<7> DDR_A_DQS[0..7] X76SAM@ X76SAM@ K4A8G165WB-BCPB_FBGA96 K4A8G165WB-BCPB_FBGA96
X76SAM@ X76SAM@
<7> DDR_A_D[0..63]
Data mapping
CLOCK TERMINATION +0.6VS_VTT
U2 DQ U3 DQ U4 DQ U5 DQ
DQL0 D3 DQL0 D19 DQL0 D35 DQL0 D51
DDR_A_CLK0 RU166 1 2 36_0402_1% RD47 1 @ 2 0_0402_5%
DDR_A_CLK#0 DQL1 D1 DQL1 D17 DQL1 D33 DQL1 D49
RU167 1 2 36_0402_1%
DQL2 D2 DQL2 D18 DQL2 D34 DQL2 D50
DQL3 D0 DQL3 D16 DQL3 D32 DQL3 D48
+1.2V_VDDQ
DQL4 D7 DQL4 D23 DQL4 D39 DQL4 D55
DQL5 D5 DQL5 D21 DQL5 D37 DQL5 D53
DDR_A_ALERT RD41 2 1 49.9_0402_1%
B DQL6 D6 DQL6 D22 DQL6 D38 DQL6 D54 B
INTEL suggest 50ohm 1% DQL7 D4 DQL7 DQL7 DQL7
D20 D36 D52
DQU0 D10 DQU0 D26 DQU0 D42 DQU0 D58
DQU1 D8 DQU1 D24 DQU1 D40 DQU1 D56
DQU2 D11 DQU2 D27 DQU2 D43 DQU2 D59
DDR_DRAMRST# DQU3 D9 DQU3 D25 DQU3 D41 DQU3 D57
RD46 1 @ 2 0_0402_5% MEMRST#
<7,18> DDR_DRAMRST#
DQU4 D14 DQU4 D30 DQU4 D46 DQU4 D62
1 DQU5 D13 DQU5 D29 DQU5 D45 DQU5 D61
@ CD36 DQU6 D15 DQU6 D31 DQU6 D47 DQU6 D63
.1U_0402_16V7K
2
DQU7 D12 DQU7 D28 DQU7 D44 DQU7 D60
on board ram flag
FLAG1 FLAG0
SAM 4G SA00008Z000 0 0
0 1
External DDR Thermal Sensor +1.2V_VDDQ
1 0
+3VS
CU181 1 1
0.1U_0402_16V4Z
1 2 +3VS +3VS
2
1
RD195
1.8K_0402_1% RU170 RU169
UU24 RD11 +DDR_VREF_CA 10K_0402_5% 10K_0402_5%
1 8 2.7_0402_1% @ @
VDD SCLK SOC_SML1CLK <8,21,29,43>
1
2 1
<7> +0.6V_VREFCA RAM_FLAG0 RAM_FLAG1
2
A
2 7 SOC_SML1DATA <8,21,29,43> A
D+ SDATA <11> RAM_FLAG0 RAM_FLAG1 <11>
1
3 6 1 2 +3VS 1
D- ALERT# RU165 10K_0402_5% RU173 RU172
4 5 CD24 X76SAM@ 10K_0402_5% 10K_0402_5%
THERM# GND 0.022U_0402_16V7K X76SAM@
2
2
W83L771AWG-2 TSSOP8P
1
SA00003PU00
RD13 RD200
SA00003PU00 24.9_0402_1% 1.8K_0402_1%
S IC W83L771AWG-2 TSSOP 8P SENSOR
2
LA-D301P
Security Classification Compal Secret Data
Issued Date 2014/02/14 Deciphered Date 2015/02/14 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDR4 ON BOARD CHIPS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, December 17, 2015 Sheet 19 of 63
5 4 3 2 1
5 4 3 2 1
<7,19> DDR_A_MA[0..16]
+0.6VS_VTT
RP17
DDR_A_MA9 1 8
D DDR_A_MA5 D
2 7
DDR_A_MA0 3 6
DDR_A_MA1 4 5
+1.2V_VDDQ
36_0804_8P4R_5%
CU198
CU195
CU197
CU200
CU199
CU196
CU201
CD211
CD210
CD212
CD213
CD214
CD215
CD216
CD217
CD218
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 RP18
DDR_A_MA6 1 8
DDR_A_MA11 2 7
DDR_A_MA7 3 6
DDR_A_MA4 4 5
36_0804_8P4R_5%
4 as near each on board RAM device as possible
RP19
DDR_A_MA14 1 8
DDR_A_MA15 2 7
Follow MA51 <7,19> DDR_A_BA0
DDR_A_BA0 3 6
DDR_A_BA1 4 5
<7,19> DDR_A_BA1
1 36_0804_8P4R_5%
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1 1 1 1 1
+ CU89
CD25
CD26
CD27
CD39
CD40
330U_D2_2V_Y
@ SGA00009S00
2 2 2 2 2 2 RP20
330U 2V H1.9 DDR_A_ODT0 1 8
<7,19> DDR_A_ODT0 DDR_A_CS#0
9mohm POLY <7,19> DDR_A_CS#0 DDR_A_MA16
2 7
3 6
DDR_A_MA10 4 5
36_0804_8P4R_5%
RP21
DDR_A_BG0 1 8
C <7,19> DDR_A_BG0 DDR_A_MA12 C
2 7
M_A_ACT# 3 6
<7,19> M_A_ACT# DDR_A_CKE0 4 5
<7,19> DDR_A_CKE0
36_0804_8P4R_5%
RP22
1 8
DDR_A_MA13 2 7
DDR_A_MA8 3 6
+2.5V +0.6VS_VTT 4 5
36_0804_8P4R_5%
CU206
CU203
CU205
CU208
CU207
CU204
CU209
CU210
CU216
CU212
CU213
CU218
CU215
CU214
CU217
CU211
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 RP24
DDR_A_MA3 1 8
2 7
DDR_A_MA2 3 6
DDR_A_PARITY 4 5
2 as near each on board RAM device as possible <7,19> DDR_A_PARITY
2 as near each on board RAM device as possible
36_0804_8P4R_5%
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1 1 1 1 1
CD41 CD42 CD43
CD47
CD46
B 2 2 2 2 2 B
A A
LA-D301P
Security Classification Compal Secret Data
Issued Date 2014/02/14 Deciphered Date 2015/02/14 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRIII ON BOARD CHIPS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, December 17, 2015 Sheet 20 of 63
5 4 3 2 1
A B C D E
Note: NGC6 3VSDGPU_MAIN_EN is no function GPIO I/O USAGE
UGPU1A
Part 1 of 6 +3VSDGPU_AON
GC6_FB_EN GC6_FB_EN <11> GPIO0 I GC6_FB_EN
<12> PCIE_CTX_C_GRX_P1 AG6 C6 RP2000
AG7 PEX_RX0 GPIO0 B2 10K_0804_8P4R_5%
<12> PCIE_CTX_C_GRX_N1 PEX_RX0_N GPIO1 GPIO8_OVERT
<12> PCIE_CTX_C_GRX_P2 AF7 D6 8 1 GPIO1 O MEM_VDD_CTL
AE7 PEX_RX1 GPIO2 C7 GPIO9_ALERT 7 2
<12> PCIE_CTX_C_GRX_N2 PEX_RX1_N GPIO3
AE9 F9 6 3
<12> PCIE_CTX_C_GRX_P3 PEX_RX2 GPIO4 3VSDGPU_MAIN_EN 3VSDGPU_MAIN_EN <47,60> ACIN_BUF
AF9 A3 5 4 GPIO2 O LCD_BL_PWM
<12> PCIE_CTX_C_GRX_N3 PEX_RX2_N GPIO5 GPU_EVENT#_1 GPU_EVENT#_1
AG9 A4 2 1
<12> PCIE_CTX_C_GRX_P4 PEX_RX3 GPIO6 GPU_EVENT# <11>
AG10 B6 D2011 VGA@
<12> PCIE_CTX_C_GRX_N4 PEX_RX3_N GPIO7 GPIO8_OVERT
AF10 A6 RB751V-40_SOD323-2 GPIO3 O LCD_VCC
AE10 NC OVERT F8 GPIO9_ALERT GC6@
AE12 NC GPIO9 C5 +3VSDGPU_AON
1
AF12 NC GPIO10 E7 DGPU_VID RP2001
1
AG12 NC GPIO11 D7 ACIN_BUF DGPU_VID <60> 10K_0804_8P4R_5%
GPIO4 O LCD_BL_EN
AG13 NC GPIO12 B4 PSI ACIN_BUF 2 1 GPU_EVENT#_1 8 1
GPIO
AF13 NC GPIO13 B3 PSI <60> D2000 DGPU_AC_DETECT <11,43> GPU_PEX_RST_HOLD# 7 2
AE13 NC GPIO14 C3 RB751V-40_SOD323-2 3VSDGPU_MAIN_EN 6 3
GPIO5 O 3V3_MAIN_EN
AE15 NC GPIO15 D5 VGA@ GC6_FB_EN 5 4
AF15 NC GPIO16 D4
AG15 NC GPIO17 C2 GC6@
GPIO6 I GPU_EVENT#
AG16 NC GPIO18 F7
AF16 NC GPIO19 E6
AE16 NC GPIO20 C4 GPU_PEX_RST_HOLD# GPIO7 O 3D Vision
AE18 NC GPIO21 +3VSDGPU_AON
AF18 NC AB6
AG18 NC PEX_WAKE_NC GPIO8 I SYS_PEX_RST_MON#
AG19 NC SYS_PEX_RST_MON# R2056 2 @ 1 10K_0402_5%
AF19 NC
AE19 NC I2CS_SDA 1 VGA@ 2 1.8K_0402_1%
GPIO9 I/O ALERT
R2000
AE21 NC AG3
AF21 NC NC AF4 I2CS_SCL R2001 1 VGA@ 2 1.8K_0402_1%
AG21 NC NC AF3
GPIO10 O MEM_VREF_CTL
AG22 NC NC
NC PSI R2052 2 VGA@ 1 10K_0402_5%
CV11 VGA@ 1 2 0.22U_0402_16V7K PCIE_CRX_C_GTX_P1 AC9 AE3
GPIO11 O PWM_VID
<12> PCIE_CRX_GTX_P1 PEX_TX0 NC
0.22U_0402_16V7K PCIE_CRX_C_GTX_N1
DACs
<12> PCIE_CRX_GTX_N1 CV12 VGA@ 1 2 AB9 AE4
CV13 VGA@ 1 2 0.22U_0402_16V7K PCIE_CRX_C_GTX_P2 AB10 PEX_TX0_N NC
<12> PCIE_CRX_GTX_P2 PCIE_CRX_C_GTX_N2 PEX_TX1
<12> PCIE_CRX_GTX_N2 CV14 VGA@ 1 2 0.22U_0402_16V7K AC10 GPIO12 I PWR_LEVEL
CV15 VGA@ 1 2 0.22U_0402_16V7K PCIE_CRX_C_GTX_P3 AD11 PEX_TX1_N
PCI EXPRESS
<12> PCIE_CRX_GTX_P3 PEX_TX2
<12> PCIE_CRX_GTX_N3 CV16 VGA@ 1 2 0.22U_0402_16V7K PCIE_CRX_C_GTX_N3 AC11 W5 PLTRST_VGA#
CV17 VGA@ 1 2 0.22U_0402_16V7K PCIE_CRX_C_GTX_P4 AC12 PEX_TX2_N NC AE2
<12> PCIE_CRX_GTX_P4
CV18 VGA@ 1 2 0.22U_0402_16V7K PCIE_CRX_C_GTX_N4 AB12 PEX_TX3 TSEN_VREF AF2
GPIO13 O PSI
<12> PCIE_CRX_GTX_N4 PEX_TX3_N NC
AB13
NC
2
AC13 GPIO14 I HPD_A
2 AD14 NC 2
AC14 NC GPIO8_OVERT 1 6
NC GPU_OVERT <11>
AC15 VGA@ GPIO15 I HPD_C
AB15 NC DMN66D0LDW-7_SOT363-6
AB16 NC B7 R2003 1 VGA@ 2 1.8K_0402_1% Q2000A
AC16 NC I2CA_SCL A7 R2004 1 VGA@ 2 1.8K_0402_1%
AD17 NC I2CA_SDA GPIO16 RESERVED
AC17 NC C9 R2005 1 VGA@ 2 1.8K_0402_1% PLTRST_VGA#
AC18 NC I2CB_SCL C8 R2006 1 VGA@ 2 1.8K_0402_1%
NC I2CB_SDA GPIO17 I HPD_D
I2C
AB18
NC
5
AB19 A9 R2007 1 VGA@ 2 1.8K_0402_1%
AC19 NC I2CC_SCL B9 R2008 1 VGA@ 2 1.8K_0402_1%
AD20 NC I2CC_SDA GPIO9_ALERT 4 3
GPIO18 I HPD_E
NC I2CS_SCL GPU_ALERT <11>
AC20 D9 VGA@
AC21 NC I2CS_SCL D8 I2CS_SDA DMN66D0LDW-7_SOT363-6
AB21 NC I2CS_SDA GPIO19 I HPD_F or HPD_B
Q2000B
AD23 NC
AE23 NC Place Under L6 R2023
AF24 NC C2000 0_0402_5%
GPIO20 Reserved
AE24 NC L6 +PLLVDD 1 2 .1U_0402_16V7K PLTRST_VGA# 1 @ 2 PLTRST_VGA#_R
AG24 NC PLLVDD M6 VGA@
AG25 NC SP_PLLVDD R2024 1 @ 2 0_0402_5%
GPIO21 O GPU_PEX_RST_HOLD#
NC +3VSDGPU_MAIN
N6 C2001
NC +GPU_PLLVDD 1 2 .1U_0402_16V7K GPIO22
2
VGA@
+3VSDGPU_AON 1 VGA@ 2 AE8
<10> CLK_PCIE_P0 PEX_REFCLK I2CS_SCL
R2009 10K_0402_5% AD8 1 6 GPIO23
PEG_CLKREQ# <10> CLK_PCIE_N0 PEX_REFCLK_N SOC_SML1CLK <8,19,29,43>
AC6 Place Under M6 VGA@
<10> PEG_CLKREQ# PEX_CLKREQ_N DMN66D0LDW-7_SOT363-6
PEX_TSTCLK_OUT+ AF22 GPIO24
CLK
PEX_TSTCLK_OUT Q2001A
2 @ 1 PEX_TSTCLK_OUT- AE22 C11 XTALIN
R2010 200_0402_1% PEX_TSTCLK_OUT_N XTAL_IN B10 XTALOUT
XTAL_OUT
3 PLTRST_VGA# AC7 A10 XTAL_SSIN R2012 1 VGA@ 2 10K_0402_5% 3
2 VGA@ 1 PEX_TREMP AF25 PEX_RST_N XTAL_SSIN C10 XTAL_OUTBUFF R2013 1 VGA@ 2 10K_0402_5% PLTRST_VGA#_R
R2011 2.49K_0402_1% PEX_TERMP XTAL_OUTBUFF
5
GM108-ES-S-A1_FCBGA595
@ I2CS_SDA 4 3
SOC_SML1DATA <8,19,29,43>
VGA@
DMN66D0LDW-7_SOT363-6
Q2001B
SM010019400 3000ma 33ohm@100mhz DCR 0.05
38mA +1.05VSDGPU
D2001 VGA@
GC6_FB_EN 2 +PLLVDD 1 2 27MHZ_10PF_7V27000023
GC6 2.0 function 1 1.5VS_DGPU_PWR_EN
1.5VS_DGPU_PWR_EN <47,58> L2000 CHILISIN PBY160808T-330Y-N
3 GC6@ 1 XTALOUT 3 1 XTALIN
C2003 3 1
PLL VDD GND GND
1
BAV70W_SOT323-3 VGA@
10P_0402_50V8J
10P_0402_50V8J
0.1Ux1, Ux1 1 1
R2014 22U_0603_6.3V6M VGA@ VGA@ X2000 VGA@
0ohm(ESR0.05)x1 2 4 2
R2016 200K_0402_1%
0_0402_5% GC6@ Near GPU C2004 C2005
1 NGC6@ 2 2 2
<10,47,59,60> DGPU_PWROK
2
SM01000AG00 2A 300ohm@100mhz DCR 0.1
17mA
Crystals must have a max ESR of 80 ohm
+3VSDGPU_AON VGA@
U2001 +GPU_PLLVDD 1 2
5
VGA@ L2001 HCB1608KF-301T20_2P
PLT_RST# 2
10,34,40,43,45> PLT_RST# 1
P
B 4SYS_PEX_RST_MON#
1
C2007
DGPU_HOLD_RST# Y SYS_PEX_RST_MON# <23>
1 C2006 VGA@
<11> DGPU_HOLD_RST# A
2
1
G
4 10U_0603_6.3V6M 47U_0805_6.3V6M 4
2
MC74VHC1G08DFT2G_SC70-5 R2019 R2017 VGA@ 2
3
0_0402_5% 10K_0402_5% SP PLLVDD+VID PLLVDD Near GPU
NGC6@ VGA@ 0.1Ux , 10Ux1,47Ux1
+3VSDGPU_AON
00ohm(ESR0. )x1
1
U2002
5
GC6@
SYS_PEX_RST_MON# 2
Security Classification Compal Secret Data Compal Electronics, Inc.
P
B 4 PLTRST_VGA#
GPU_PEX_RST_HOLD# 1 Y
A Issued Date 2014/11/10 Deciphered Date 2016/11/10 Title
G
R2018
MC74VHC1G08DFT2G_SC70-5 10K_0402_5%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N16X PEG 1/9
3
1 GC6@ 2 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D301P
Date: Thursday, December 17, 2015 Sheet 21 of 63
A B C D E
A B C D E
VRAM Interface
UGPU1B
1 1
MDA[15..0]
<26> MDA[15..0]
UGPU1 Part 2 of 6
MDA[31..16] CMDA[31..0] <26,27>
<26> MDA[31..16]
MDA0 E18 C27 CMDA0
MDA[47..32] MDA1 F18 FBA_D00 FBA_CMD0 C26 CMDA1
<27> MDA[47..32] FBA_D01 FBA_CMD1
MDA2 E16 E24 CMDA2
MDA[63..48] MDA3 F17 FBA_D02 FBA_CMD2 F24 CMDA3
<27> MDA[63..48] FBA_D03 FBA_CMD3
N16S-GT MDA4 D20 D27 CMDA4
SGT@ MDA5 D21 FBA_D04 FBA_CMD4 D26 CMDA5
F20 FBA_D05 FBA_CMD5 F25
SA000087F10 MDA6
FBA_D06 FBA_CMD6
CMDA6
MDA7 E21 F26 CMDA7
MDA8 E15 FBA_D07 FBA_CMD7 F23 CMDA8
UGPU1 MDA9 D15 FBA_D08 FBA_CMD8 G22 CMDA9
MDA10 F15 FBA_D09 FBA_CMD9 G23 CMDA10
MDA11 F13 FBA_D10 FBA_CMD10 G24 CMDA11
MDA12 C13 FBA_D11 FBA_CMD11 F27 CMDA12
MDA13 B13 FBA_D12 FBA_CMD12 G25 CMDA13
MDA14 E13 FBA_D13 FBA_CMD13 G27 CMDA14
N16V-GM MDA15 D13 FBA_D14 FBA_CMD14 G26 CMDA15
VGM@ MDA16 B15 FBA_D15 FBA_CMD15 M24 CMDA16
C16 FBA_D16 FBA_CMD16 M23
SA000088R20 MDA17
FBA_D17 FBA_CMD17
CMDA17
MDA18 A13 K24 CMDA18
MDA19 A15 FBA_D18 FBA_CMD18 K23 CMDA19
MDA20 B18 FBA_D19 FBA_CMD19 M27 CMDA20
MDA21 A18 FBA_D20 FBA_CMD20 M26 CMDA21
MDA22 A19 FBA_D21 FBA_CMD21 M25 CMDA22
MDA23 C19 FBA_D22 FBA_CMD22 K26 CMDA23 ODT_L CMDA2 R2093 1 VGA@ 2 10K_0402_5%
MDA24 B24 FBA_D23 FBA_CMD23 K22 CMDA24 CLK_L CMDA3 R2094 1 VGA@ 2 10K_0402_5%
MDA25 C23 FBA_D24 FBA_CMD24 J23 CMDA25 RST CMDA5 R2095 1 VGA@ 2 10K_0402_5%
MDA26 A25 FBA_D25 FBA_CMD25 J25 CMDA26 ODT_H CMDA18 R2098 1 VGA@ 2 10K_0402_5%
MDA27 A24 FBA_D26 FBA_CMD26 J24 CMDA27 CLK_H CMDA19 R2099 1 VGA@ 2 10K_0402_5%
MDA28 A21 FBA_D27 FBA_CMD27 K27 CMDA28 PVT modify 01/13
2 MDA29 B21 FBA_D28 FBA_CMD28 K25 CMDA29 DQSA, DQSA# reverse 2
MDA30 C20 FBA_D29 FBA_CMD29 J27 CMDA30
MDA31 C21 FBA_D30 FBA_CMD30 J26 CMDA31
MDA32 R22 FBA_D31 FBA_CMD31
FBA_D32 DQMA[3..0] <26>
MDA33 R24 D19 DQMA0
FBA_D33 FBA_DQM0
INTERFACE A
MDA34 T22 D14 DQMA1
MDA35 R23 FBA_D34 FBA_DQM1 C17 DQMA2
MDA36 N25 FBA_D35 FBA_DQM2 C22 DQMA3
FBA_D36 FBA_DQM3 DQMA[7..4] <27>
MDA37 N26 P24 DQMA4
FBA_D37 FBA_DQM4
MEMORY
MDA38 N23 W24 DQMA5
MDA39 N24 FBA_D38 FBA_DQM5 AA25 DQMA6
MDA40 V23 FBA_D39 FBA_DQM6 U25 DQMA7
NV 15x DG-06803-V03 MDA41
MDA42
V22
T23
FBA_D40
FBA_D41
FBA_DQM7
F19 DQSA#0
DQSA#[3..0] <26>
MDA43 U22 FBA_D42 FBA_DQS_RN0 C14 DQSA#1
MDA44 Y24 FBA_D43 FBA_DQS_RN1 A16 DQSA#2
MDA45 AA24 FBA_D44 FBA_DQS_RN2 A22 DQSA#3
FBA_D45 FBA_DQS_RN3 DQSA#[7..4] <27>
MDA46 Y22 P25 DQSA#4
MDA47 AA23 FBA_D46 FBA_DQS_RN4 W22 DQSA#5
MDA48 AD27 FBA_D47 FBA_DQS_RN5 AB27 DQSA#6
MDA49 AB25 FBA_D48 FBA_DQS_RN6 T27 DQSA#7
MDA50 AD26 FBA_D49 FBA_DQS_RN7
FBA_D50 DQSA[3..0] <26>
MDA51 AC25 E19 DQSA0
MDA52 AA27 FBA_D51 FBA_DQS_WP0 C15 DQSA1
MDA53 AA26 FBA_D52 FBA_DQS_WP1 B16 DQSA2
MDA54 W26 FBA_D53 FBA_DQS_WP2 B22 DQSA3
FBA_D54 FBA_DQS_WP3 DQSA[7..4] <27>
SM010019400 3000ma 33ohm@100mhz DCR 0.05 MDA55 Y25 R25 DQSA4
MDA56 R26 FBA_D55 FBA_DQS_WP4 W23 DQSA5
MDA57 T25 FBA_D56 FBA_DQS_WP5 AB26 DQSA6
MDA58 N27 FBA_D57 FBA_DQS_WP6 T26 DQSA7
+1.05VSDGPU MDA59 R27 FBA_D58 FBA_DQS_WP7
MDA60 V26 FBA_D59
VGA@
15+55mA MDA61 V27 FBA_D60
3 2 1 L2002 +FB_PLLAVDD MDA62 W27 FBA_D61 3
CHILISIN PBY160808T-330Y-N MDA63 W25 FBA_D62
22U_0603_6.3V6M
VGA@ VGA@ VGA@ FBA_D63 D24
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
FBA_CLK0 CLKA0 <26>
1 1 1 1 F16 D25
FB_PLLAVDD_1 FBA_CLK0_N CLKA0# <26>
P22
C2008 FB_PLLAVDD_2 N22
FBA_CLK1 CLKA1 <27>
VGA@ T97 @ D23 M22
C2011
C2010
C2009
2 2 2 2 FB_VREF_PROBE FBA_CLK1_N CLKA1# <27>
D18
H22 FBA_WCK01 C18
FB_DLLAVDD FBA_WCK01_N D17
Place Near GPU Place Under F16 P22 H22 1 VGA@ 2 FB_CLAMP F3 FBA_WCK23 D16
10K_0402_5% R2028 FB_CLAMP FBA_WCK23_N T24
FBA_WCK45 U24
60.4_0402_1% 1 @ 2 R2020FBA_CMD34 F22 FBA_WCK45_N V24
1 2 R2022FBA_CMD35 J22 FBA_CMD34 FBA_WCK67 V25
change to 1.35VSDGPU +1.5VSDGPU 60.4_0402_1% @
FBA_CMD35 FBA_WCK67_N
GM108-ES-S-A1_FCBGA595
@
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2014/11/10 Deciphered Date 2016/11/10 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N16X VRAM 2/9
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D301P
Date: Thursday, December 17, 2015 Sheet 22 of 63
A B C D E
A B C D E
UGPU1C MULTI LEVEL STRAPS
Part 3 of 6 F11
AC3 NC AD10 +3VSDGPU_AON +3VSDGPU_MAIN
AC4 NC NC AD7
Y4 NC NC B19 strap0 strap1 strap2 strap3 strap4
Y3 NC FBA_CMD32 V5
NC NC
1
AA3 V6
AA2 NC NC G1 R2029 R2030 R2031 R2032 R2033 R2035 R2036 R2037
AB1 NC NC G2 SGT@ @ @ @ @ X76@ @ @
NC NC
NC
AA1 G3 49.9K_0402_1% 4.99K_0402_1% 20K_0402_1% 4.99K_0402_1% 10K_0402_1% 30K_0402_1% 4.99K_0402_1% 4.99K_0402_1%
AA4 NC NC G4
NC NC
2
AA5 G5
1 NC NC G6
1
NC G7 STRAP0
AB5 NC V1 STRAP1 ROM_SI
AB4 NC NC V2 STRAP2 ROM_SO
AB3 NC NC W1 STRAP3 ROM_SCLK
AB2 NC NC W2 STRAP4
AD3 NC NC W3
AD2 NC NC W4
NC NC
1
AE1
AD1 NC R2038 R2039 R2040 R2041 R2042 R2044 R2045 R2046
AD4 NC @ @ @ @ @ X76@ SGT@ SGT@
NC For GC6 .0 use
AD5 D11 R2050 1 @ 2 10K_0402_5% N14x for CEC ,NC 4.99K_0402_1% 34.8K_0402_1% 15K_0402_1% 4.99K_0402_1% 10K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1%
NC BUFRST_N
N15x for GPIO8
2
D10
T2 NC
T3 NC E9 SYS_PEX_RST_MON#
NC GPIO8 SYS_PEX_RST_MON# <21>
T1
R1 NC E10
R2 NC NC
GENERAL
LVDS/TMDS
R3 NC F10
N2 NC NC
N3 NC
NC D1 STRAP0
STRAP0 D2 STRAP1
V3 STRAP1 E4 STRAP2
V4 NC STRAP2 E3 STRAP3
U3 NC STRAP3 D3 STRAP4
NC STRAP4 N16VGM Option Component N16SGT Option Component
U4 C1
T4 NC NC
T5 NC STRAP0 ---> R2029 2 VGM@1 45.3K_0402_1% SD034453280
R4 NC F6 MULTI_STRAP_REF0_GND 1 VGA@ 2 STRAP1 ---> R2039 2 VGM@1 45.3K_0402_1% SD034453280
R5 NC MULTI_STRAP_REF0_GND F4 R2051 40.2K_0402_1% STRAP2 ---> R2031 2 VGM@1 10K_0402_1% SD034100280
NC NC F5 STRAP3 ---> R2041 2 VGM@1 4.99K_0402_1% SD034499180
2 NC STRAP4 ---> R2042 2 VGM@1 45.3K_0402_1% SD034453280 2
N1 ROM_SO ---> R2036 2 VGM@1 4.99K_0402_1% SD034499180
M1 NC ROM_SCLK---> R2037 2 VGM@1 4.99K_0402_1% SD034499180
M2 NC F12
M3 NC THERMDP ROM_SI pull down 15kohm to GND for DDR3 Hynix 256mx16 VRAM, strap 0x2 ROM_SI pull down 4.99kohm to GND for DDR3 Hynix 256mx16 VRAM, strap 0x0
K2 NC E12 ROM_SI pull down 10kohm to GND for DDR3 Micron 256mx16 VRAM, strap 0x1 ROM_SI pull down 10kohm to GND for DDR3 Micron 256mx16 VRAM, strap 0x1
NC THERMDN ROM_SI pull down 25kohm to GND for DDR3 Samsung 256mx16 VRAM, strap 0x4 ROM_SI pull down 15kohm to GND for DDR3 Samsung 256mx16 VRAM, strap 0x2
K3 ROM_SI pull up 35kohm to GND for DDR3 Hynix 256mx16 VRAM, strap 0xE ROM_SI pull down 20kohm to GND for DDR3 Hynix 256mx16 VRAM, strap 0x3
K1 NC
ROM_SI pull up 30kohm to GND for DDR3 Micron 256mx16 VRAM, strap 0xD ROM_SI pull down 25kohm to GND for DDR3 Micron 256mx16 VRAM, strap 0x4
J1 NC ROM_SI pull down 30kohm to GND for DDR3 Samsung 256mx16 VRAM, strap 0x5 ROM_SI pull down 30kohm to GND for DDR3 Samsung 256mx16 VRAM, strap 0x5
NC ROM_SI pull up 25kohm to GND for DDR3 Samsung 256mx16 VRAM, strap 0xC
M4 F2 VCCSENSE_VGA
M5 NC VDD_SENSE VCCSENSE_VGA <60>
L3 NC
L4 NC
K4 NC
NC
K5
J4 NC F1 VSSSENSE_VGA For N16S-GT Multi strap table Decive ID : 0x1347
NC GND_SENSE VSSSENSE_VGA <60>
GPU VRAM RANK X76 Freq Memory Size Memory Config strap0 strap1 strap2 strap3 strap4 ROM_SI ROM_SO ROM_SCLK
Vottage
J5
NC X76629BOL07 0x5 (SA00008DN10) Hynix H5TC4G63CFR-N0C PD 30K
N4 Singal Rank
N5 NC TEST X76629BOL08 1GHz 256Mx16x4 0x1 (SA000077K20) Micron MT41J256M16HA-093G:E PD 10K
NC 2GB
P3
NC TESTMODE
AD9 TESTMODE R2054 1 VGA@ 2 10K_0402_5%
JTAG_TCK_VGA
+1.5V X76629BOL09 0x2 (SA000076P20) Samsung K4W4G1646D-BC1A PD 15K
P4 AE5 PAD @ T24
NC JTAG_TCK JTAG_TDI
JTAG_TDI
AE6
JTAG_TDO
PAD @ T1 X76629BOL10 0xC (SA00008DN10) Hynix H5TC4G63CFR-N0C PU 24.9K
AF6 PAD @ T186
JTAG_TDO JTAG_TMS
J2
NC JTAG_TMS
AD6
JTAG_RST
PAD @ T3 Dual Rank X76629BOL11 1GHz 256Mx16x8 0x1 (SA000077K20) Micron MT41J256M16HA-093G:E PD 10K
J3 AG4 R2053 1 VGA@ 210K_0402_5% 4GB
NC JTAG_TRST_N
N16S-GT X76629BOL12 0x2 (SA000076P20) Samsung K4W4G1646D-BC1A PD 15K
3 PD 4.99K 3
PD 4.99K
H3 PU 50K NC NC NC NC PD 15K
NC 0x2 (SA00008DN10) Hynix H5TC4G63CFR-N0C
H4
NC SERIAL 900MHz 256Mx16x4 PD 24.9K
D12 Singal Rank 2GB 0x4 (SA000077K20) Micron MT41J256M16HA-093G:E
ROM_CS_N B12 ROM_SI
ROM_SI +1.35V 0x5 (SA000076P20) Samsung K4W4G1646D-BC1A PD 30K
A12 ROM_SO
ROM_SO C12 ROM_SCLK PU 35K
ROM_SCLK 0xE (SA00008DN10) Hynix H5TC4G63CFR-N0C
256Mx16x8
GM108-ES-S-A1_FCBGA595 900MHz 4GB 0x4 (SA000077K20) Micron MT41J256M16HA-093G:E PD 24.9K
@ Dual Rank
0x5 (SA000076P20) Samsung K4W4G1646D-BC1A PD 30K
For N16V-GM Multi strap table Decive ID : 0x1299
GPU VRAM RANK X76 Freq Memory Size Memory Config strap0 strap1 strap2 strap3 strap4 ROM_SI ROM_SO ROM_SCLK
Vottage
X76629BOL01 0x9 (SA00008DN10) Hynix H5TC4G63CFR-N0C PU 10K
X76629BOL02 1GHz 256Mx16x4 0x1 (SA000077K20) Micron MT41J256M16HA-093G:E PD 10K
+1.5V Singal Rank
2GB
X76629BOL03 0x4 (SA000076P20) Samsung K4W4G1646D-BC1A PD 24.9K
PD 5K
0x0 (SA00008DN10) Hynix H5TC4G63CFR-N0C
900MHz 256Mx16x4 0xD (SA000077K20) Micron MT41J256M16HA-093G:E
Singal Rank 2GB PU 30K
N16V-GM PU 45.3K PD45.3K PU 10K PD 4.99K PD 45.3K PU 4.99K PU 4.99K
+1.35V 0x5 (SA000076P20) Samsung K4W4G1646D-BC1A PD 30K
4 X76629BOL04 0xA (SA00008DN10) Hynix H5TC4G63CFR-N0C PU 15K 4
900MHz 256Mx16x8
Dual Rank X76629BOL05 4GB 0xD (SA000077K20) Micron MT41J256M16HA-093G:E PU 30K
X76629BOL06
0xC (SA000076P20) Samsung K4W4G1646D-BC1A PU 24.9K
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2014/11/10 Deciphered Date 2016/11/10 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N16X STRAPS 3/9
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D301P
Date: Thursday, December 17, 2015 Sheet 23 of 63
A B C D E
A B C D E
NV 15x DG-06803-V03
1 1
change to 1.35VSDGPU +1.05VSDGPU
UGPU1D
+1.5VSDGPU 3.24A 1.275A
Part 4 of 6
B26 AA10
.1U_0402_16V7K
.1U_0402_16V7K
4.7U_0603_6.3V6K
C25 FBVDDQ_01 PEX_IOVDDQ_1 AA12
10U_0603_6.3V6M
22U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
E23 FBVDDQ_02 PEX_IOVDDQ_2 AA13
C2039
C2040
C2032
C2033
C2021
C2022
C2013
C2014
C2016
C2017
1 1 1 1 2 2 FBVDDQ_03 PEX_IOVDDQ_3 1 1 1 1
E26 AA16
F14 FBVDDQ_04 PEX_IOVDDQ_4 AA18
VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ F21 FBVDDQ_05 PEX_IOVDDQ_5 AA19 VGA@ VGA@ VGA@ VGA@
2 2 2 2 1 1 G13 FBVDDQ_06 PEX_IOVDDQ_6 AA20 2 2 2 2
G14 FBVDDQ_07 PEX_IOVDDQ_7 AA21
G15 FBVDDQ_08 PEX_IOVDDQ_8 AB22
Under GPU G16 FBVDDQ_09 PEX_IOVDDQ_9 AC23
G18 FBVDDQ_10 PEX_IOVDDQ_10 AD24
G19 FBVDDQ_11 PEX_IOVDDQ_11 AE25 Under GPU Near GPU
10U_0603_6.3V6M
G20 FBVDDQ_12 PEX_IOVDDQ_12 AF26
C2045
C2047
22U_0603_6.3V6M
1 1 FBVDDQ_13 PEX_IOVDDQ_13 Midway GPU & Power supply
G21 AF27
H24 FBVDDQ_14 PEX_IOVDDQ_14
VGA@ VGA@ H26 FBVDDQ_AON
2 2 J21 FBVDDQ_AON AA22
K21 FBVDDQ_AON PEX_IOVDD_1 AB23
L22 FBVDDQ_AON PEX_IOVDD_2 AC24
L24 FBVDDQ_19 PEX_IOVDD_3 AD25
Near GPU FBVDDQ_20 PEX_IOVDD_4
POWER
L26 AE26
M21 FBVDDQ_21 PEX_IOVDD_5 AE27
2 N21 FBVDDQ_22 PEX_IOVDD_6 2
R21 FBVDDQ_23
T21 FBVDDQ_24
V21 FBVDDQ_25 +3VSDGPU_AON
W21 FBVDDQ_26
FBVDDQ_27 G10
3V3_AON G12 56mA
.1U_0402_16V7K
1U_0402_6.3V6K
4.7U_0603_6.3V6K
3V3_AON G8
C2048
C2049
C2050
VDD33_3 2 1 1
G9
VDD33_4
VGA@ VGA@ VGA@
V7 1 2 2
W7 NC +1.5VSDGPU
AA6 NC
W6 NC D22 FB_CAL_PD_VDDQ 1 VGA@ 2
NC FB_CAL_PD_VDDQ Under GPU Near GPU
Y6 40.2_0402_1% R2078 +3VSDGPU_MAIN
NC
C24 FB_CAL_PU_GND 1 VGA@ 2
FB_CAL_PU_GND 42.2_0402_1% R2079
.1U_0402_16V7K
.1U_0402_16V7K
1U_0402_6.3V6K
4.7U_0603_6.3V6K
M7 B25 FB_CAL_TERM_GND1 VGA@ 2
C2051
C2052
C2053
C2054
NC FB_CAL_TERM_GND 2 2 1 1
N7 51.1_0402_1% R2080
T6 NC
P6 NC VGA@ VGA@ VGA@ VGA@
NC 1 1 2 2
change to 1.35VSDGPU
T7 Under GPU Near GPU
R7 IFPD_PLLVDD_2 +3VSDGPU_AON
U6 NC
R6 IFPD_RSET AA8
286mA
NC PEX_PLL_HVDD_1 AA9
PEX_PLL_HVDD_2
.1U_0402_16V7K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
3 AB8
C2034
C2035
C2036
3
PEX_SVDD_3V3 2 1 1
J7 VGA@ VGA@ VGA@
K7 NC 1 2 2
K6 NC AA14
H6 NC PEX_PLLVDD_1 AA15
J6 NC PEX_PLLVDD_2
NC Near GPU
R2075 +1.05VSDGPU
130mA 0_0603_5%
+PEX_PLLVDD 2 1
C2041
C2042
C2043
.1U_0402_16V7K
1U_0402_6.3V6K
2 1 1
4.7U_0603_6.3V6K
GM108-ES-S-A1_FCBGA595
@
VGA@ VGA@ VGA@
1 2 2
Under GPU Near GPU
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2014/11/10 Deciphered Date 2016/11/10 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N16X POWER & GND 4/9
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D301P
Date: Thursday, December 17, 2015 Sheet 24 of 63
A B C D E
A B C D E
UGPU1F
UGPU1E +VGA_CORE +VGA_CORE
Part 6 of 6
A2
A26 GND_001
Part 5 of 6
GND_057
K11
K13 K10 V18
NV 15x DG-06803-V03
AB11 GND_002 GND_058 K15 K12 VDD_001 VDD_041 V16
1
AB14 GND_003 GND_059 K17 K14 VDD_002 VDD_040 V14
1
AB17 GND_004 GND_060 L10 K16 VDD_003 VDD_039 V12
AB20 GND_005 GND_061 L12 K18 VDD_004 VDD_038 V10
AB24 GND_006 GND_062 L14 L11 VDD_005 VDD_037 U17
GND_007 GND_063 VDD_006 VDD_036
POWER
AC2 L16 L13 U15
AC22 GND_008 GND_064 L18 L15 VDD_007 VDD_035 U13
AC26 GND_009 GND_065 L2 L17 VDD_008 VDD_034 U11
AC5 GND_010 GND_066 L23 M10 VDD_009 VDD_033 T18
AC8 GND_011 GND_067 L25 M12 VDD_010 VDD_032 T16
AD12 GND_012 GND_068 L5 M14 VDD_011 VDD_031 T14
AD13 GND_013 GND_069 M11 M16 VDD_012 VDD_030 T12
AD15 GND_014 GND_070 M13 M18 VDD_013 VDD_029 T10
AD16 GND_015 GND_071 M15 N11 VDD_014 VDD_028 R17
AD18 GND_016 GND_072 M17 N13 VDD_015 VDD_027 R15
AD19 GND_017 GND_073 N10 N15 VDD_016 VDD_026 R13
AD21 GND_018 GND_074 N12 N17 VDD_017 VDD_025 R11
AD22
AE11
GND_019
GND_020
GND_075
GND_076
N14
N16
P10
P12
VDD_018
VDD_019
VDD_024
VDD_023
P18
P16
DA-06840-V03
AE14 GND_021 GND_077 N18 VDD_020 VDD_022 P14
AE17 GND_022 GND_078 P11 VDD_021
AE20 GND_023 GND_079 P13
AF1 GND_024 GND_080 P15
AF11 GND_025 GND_081 P17
GND
AF14 GND_026 GND_082 P2
AF17 GND_027 GND_083 P23
AF20 GND_028 GND_084 P26
AF23 GND_029 GND_085 P5
AF5 GND_030 GND_086 R10
AF8 GND_031 GND_087 R12 GM108-ES-S-A1_FCBGA595
AG2 GND_032 GND_088 R14 @
AG26 GND_033 GND_089 R16
B1 GND_034 GND_090 R18
B11 GND_035 GND_091 T11
2 B14 GND_036 GND_092 T13 2
B17 GND_037 GND_093 T15
B20 GND_038 GND_094 T17
B23 GND_039 GND_095 U10
B27 GND_040 GND_096 U12
B5
B8
GND_041
GND_042
GND_097
GND_098
U14
U16
DA-06925-V05
E11 GND_043 GND_099 U18
E14 GND_044 GND_100 U2
E17 GND_045 GND_101 U23
E2 GND_046 GND_102 U26
E20 GND_047 GND_103 U5
E22 GND_048 GND_104 V11
E25 GND_049 GND_105 V13
E5 GND_050 GND_106 V15
E8 GND_051 GND_107 V17
H2 GND_052 GND_108 Y2
H23 GND_053 GND_109 Y23
H25 GND_054 GND_110 Y26
H5 GND_055 GND_111 Y5
GND_056 GND_112
AA7
GND AB7
GND
GM108-ES-S-A1_FCBGA595
@
DA07075-V01
3 3
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2014/11/10 Deciphered Date 2016/11/10 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N16X POWER & GND 5/9
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D301P
Date: Thursday, December 17, 2015 Sheet 25 of 63
A B C D E
A B C D E
VRAM DDR3 chips <22,27> DQSA[7..0]
DQSA[7..0]
DQSA#[7..0]
<22,27> DQSA#[7..0]
DQMA[7..0]
<22,27> DQMA[7..0]
MDA[63..0]
<22,27> MDA[63..0]
CMDA[30..0]
<22,27> CMDA[30..0]
ZZZ
LOW BIT
1 1
ALT. GROUP PARTS GT2G HYN 256M16 A4WAD
X76@VHY
X76614BOL54
U2005 X76@ U2004 X76@
ZZZ +MEM_VREF1 M8 E3 MDA19 +MEM_VREF0 M8 E3 MDA4 Mode D
+MEM_VREF0 VREFCA DQL0 +MEM_VREF1 VREFCA DQL0
H1
VREFDQ DQL1
F7 MDA21 H1
VREFDQ DQL1
F7 MDA0 Address 0..31 32..63
F2 MDA16 F2 MDA5
DQL2 DQL2
CMDA9 N3
A0 DQL3
F8 MDA22 CMDA9 N3
A0 DQL3
F8 MDA2 CMD0 CS0_L#
CMDA11 P7 H3 MDA18 Group2 CMDA11 P7 H3 MDA7 Group0
A1 DQL4 A1 DQL4
CMDA8 P3
A2 DQL5
H8 MDA23 CMDA8 P3
A2 DQL5
H8 MDA1 CMD1
ALT. GROUP PARTS GT2G SAM-N 256M16 A4WAD CMDA25 N2 G2 MDA17 CMDA25 N2 G2 MDA6
A3 DQL6 A3 DQL6
X76@VSAM CMDA10 P8
A4 DQL7
H7 MDA20 CMDA10 P8
A4 DQL7
H7 MDA3 CMD2 ODT_L
X76614BOL58 CMDA24 P2 CMDA24 P2
A5 A5
CMDA22 R8
A6
CMDA22 R8
A6 CMD3 CKE_L
CMDA7 R2 D7 MDA10 CMDA7 R2 D7 MDA31
A7 DQU0 A7 DQU0
CMDA21 T8
A8 DQU1
C3 MDA13 CMDA21 T8
A8 DQU1
C3 MDA27 CMD4 A14 A14
CMDA6 R3 C8 MDA11 CMDA6 R3 C8 MDA30
A9 DQU2 A9 DQU2
CMDA29 L7
A10/AP DQU3
C2 MDA14 CMDA29 L7
A10/AP DQU3
C2 MDA25 CMD5 RST RST
CMDA23 R7 A7 MDA8 Group1 CMDA23 R7 A7 MDA28 Group3
A11 DQU4 A11 DQU4
CMDA28 N7
A12 DQU5
A2 MDA15 CMDA28 N7
A12 DQU5
A2 MDA26 CMD6 A9 A9
CMDA20 T3 B8 MDA9 CMDA20 T3 B8 MDA29
A13 DQU6 A13 DQU6
CMDA4 T7
A14 DQU7
A3 MDA12 CMDA4 T7
A14 DQU7
A3 MDA24 CMD7 A7 A7
CMDA14 M7 CMDA14 M7
A15/BA3 +1.5VSDGPU A15/BA3 +1.5VSDGPU CMD8 A2 A2
CMDA12 M2
BA0 VDD
B2 CMDA12 M2
BA0 VDD
B2 CMD9 A0 A0
CMDA27 N8 D9 CMDA27 N8 D9
BA1 VDD BA1 VDD
CMDA26 M3
BA2 VDD
G7 CMDA26 M3
BA2 VDD
G7 CMD10 A4 A4
K2 K2
VDD VDD
VDD
K8
VDD
K8 CMD11 A1 A1
N1 N1
VDD VDD
2
CLKA0 J7
CK VDD
N9 CLKA0 J7
CK VDD
N9 CMD12 BA0 BA0 2
CLKA0# K7 R1 CLKA0# K7 R1
CK VDD CK VDD
CMDA3 K9
CKE/CKE0 VDD
R9
+1.5VSDGPU
CMDA3 K9
CKE/CKE0 VDD
R9
+1.5VSDGPU
CMD13 WE* WE*
CMD14 A15 A15
CMDA2 K1 A1 CMDA2 K1 A1
ODT/ODT0 VDDQ ODT/ODT0 VDDQ
CMDA0 L2
CS/CS0 VDDQ
A8 CMDA0 L2
CS/CS0 VDDQ
A8 CMD15 CAS* CAS*
CMDA30 J3 C1 CMDA30 J3 C1
RAS VDDQ RAS VDDQ
CMDA15 K3
CAS VDDQ
C9 CMDA15 K3
CAS VDDQ
C9 CMD16 CS0_H#
CMDA13 L3 D2 CMDA13 L3 D2
WE VDDQ WE VDDQ
310mAVDDQ E9
VDDQ
E9 CMD17
F1 310mAVDDQ F1
VDDQ
DQSA2 F3
DQSL VDDQ
H2 DQSA0 F3
DQSL VDDQ
H2 CMD18 ODT_H
DQSA1 C7 H9 DQSA3 C7 H9
DQSU VDDQ DQSU VDDQ
CMD19 CKE_H
DQMA2 E7
DML VSS
A9 DQMA0 E7
DML VSS
A9 CMD20 A13 A13
DQMA1 D3 B3 DQMA3 D3 B3
DMU VSS DMU VSS
VSS
E1
VSS
E1 CMD21 A8 A8
G8 G8
VSS VSS
DQSA#2 G3
DQSL VSS
J2 DQSA#0 G3
DQSL VSS
J2 CMD22 A6 A6
DQSA#1 B7 J8 DQSA#3 B7 J8
DQSU VSS DQSU VSS
VSS
M1
VSS
M1 CMD23 A11 A11
M9 M9
VSS VSS
VSS
P1
VSS
P1 CMD24 A5 A5
CMDA5 T2 P9 CMDA5 T2 P9
RESET VSS RESET VSS
VSS
T1
VSS
T1 CMD25 A3 A3
ZQ1 L8 T9 ZQ0 L8 T9
ZQ/ZQ0 VSS ZQ/ZQ0 VSS
CMD26 BA2 BA2
1
1
J1
NC/ODT1 VSSQ
B1 J1
NC/ODT1 VSSQ
B1 CMD27 BA1 BA1
R2081 VGA@ L1 B9 R2082 VGA@ L1 B9
NC/CS1 VSSQ NC/CS1 VSSQ
243_0402_1% J9
NC/CE1 VSSQ
D1 243_0402_1% J9
NC/CE1 VSSQ
D1 CMD28 A12 A12
L9 D8 L9 D8
NCZQ1 VSSQ NCZQ1 VSSQ
2
2
3
VSSQ
E2
VSSQ
E2 CMD29 A10 A10 3
E8 E8
VSSQ VSSQ
VSSQ
F9
VSSQ
F9 CMD30 RAS* RAS*
G1 G1
VSSQ G9 VSSQ G9
VSSQ VSSQ Not Available
96-BALL 96-BALL LOW HIGH
SDRAM DDR3 SDRAM DDR3
H5TQ2G63BFR-11C_FBGA96 H5TQ2G63BFR-11C_FBGA96
Command Bit Default Pull-down
CLKA0 ODTx 10k
<22> CLKA0
1
DDR3 CKEx 10k
VGA@ RST 10k
R2087
2
162_0402_1% +1.5VSDGPU +1.5VSDGPU CS* No Termination
CLKA0#
<22> CLKA0#
R2085 R2086
VGA@ VGA@
1.33K_0402_1% 1.33K_0402_1%
+MEM_VREF0 +MEM_VREF1
1 1
R2091 R2092
VGA@ C2055 VGA@ C2056
+1.5VSDGPU 1.33K_0402_1% .1U_0402_16V7K 1.33K_0402_1% .1U_0402_16V7K
2 2
VGA@ VGA@
4 4
C2079
C2080
C2081
C2082
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
C2071
C2072
C2073
C2074
C2075
C2076
C2077
C2078
1 1 1 1 1 1 1 1 1 1 1 1
VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@
2 2 2 2 2 2 2 2 2 2 2 2
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2014/12/31 Deciphered Date 2016/12/31 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N16X Upper Rank0 6/9
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D301P
Date: Thursday, December 17, 2015 Sheet 26 of 63
A B C D E
A B C D E
VRAM DDR3 chips <22,26> DQSA[7..0]
DQSA[7..0]
DQSA#[7..0]
<22,26> DQSA#[7..0]
DQMA[7..0]
<22,26> DQMA[7..0]
<22,26> MDA[63..0]
MDA[63..0]
CMDA[30..0]
HIGH BIT Mode D
Address 0..31 32..63
<22,26> CMDA[30..0]
CMD0 CS0_L#
CMD1
CMD2 ODT_L
1 1
CMD3 CKE_L
U2007 X76@ U2006 X76@ CMD4 A14 A14
+MEM_VREF3 +MEM_VREF2
+MEM_VREF2
M8
VREFCA DQL0
E3 MDA35
+MEM_VREF3
M8
VREFCA DQL0
E3 MDA52 CMD5 RST RST
H1 F7 MDA37 H1 F7 MDA49
VREFDQ DQL1 VREFDQ DQL1
DQL2
F2 MDA34
DQL2
F2 MDA53 CMD6 A9 A9
CMDA9 N3 F8 MDA39 CMDA9 N3 F8 MDA50
A0 DQL3 A0 DQL3
CMDA11 P7
A1 DQL4
H3 MDA32 Group4 CMDA11 P7
A1 DQL4
H3 MDA54 Group6 CMD7 A7 A7
CMDA8 P3 H8 MDA38 CMDA8 P3 H8 MDA48
A2 DQL5 A2 DQL5
CMDA25 N2
A3 DQL6
G2 MDA33 CMDA25 N2
A3 DQL6
G2 MDA55 CMD8 A2 A2
CMDA10 P8 H7 MDA36 CMDA10 P8 H7 MDA51
A4 DQL7 A4 DQL7
CMDA24 P2
A5
CMDA24 P2
A5 CMD9 A0 A0
CMDA22 R8 CMDA22 R8
A6 A6
CMDA7 R2
A7 DQU0
D7 MDA56 CMDA7 R2
A7 DQU0
D7 MDA44 CMD10 A4 A4
CMDA21 T8 C3 MDA60 CMDA21 T8 C3 MDA40
A8 DQU1 A8 DQU1
CMDA6 R3
A9 DQU2
C8 MDA58 CMDA6 R3
A9 DQU2
C8 MDA46 CMD11 A1 A1
CMDA29 L7 C2 MDA61 CMDA29 L7 C2 MDA41
A10/AP DQU3 A10/AP DQU3
CMDA23 R7
A11 DQU4
A7 MDA57 Group7 CMDA23 R7
A11 DQU4
A7 MDA45 Group5 CMD12 BA0 BA0
CMDA28 N7 A2 MDA63 CMDA28 N7 A2 MDA43
A12 DQU5 A12 DQU5
CMDA20 T3
A13 DQU6
B8 MDA59 CMDA20 T3
A13 DQU6
B8 MDA47 CMD13 WE* WE*
CMDA4 T7 A3 MDA62 CMDA4 T7 A3 MDA42
A14 DQU7 A14 DQU7
CMDA14 M7
A15/BA3 +1.5VSDGPU
CMDA14 M7
A15/BA3 +1.5VSDGPU
CMD14 A15 A15
CMD15 CAS* CAS*
CMDA12 M2 B2 CMDA12 M2 B2
BA0 VDD BA0 VDD
CMDA27 N8
BA1 VDD
D9 CMDA27 N8
BA1 VDD
D9 CMD16 CS0_H#
CMDA26 M3 G7 CMDA26 M3 G7
BA2 VDD BA2 VDD
VDD
K2
VDD
K2 CMD17
K8 K8
VDD VDD
VDD
N1
VDD
N1 CMD18 ODT_H
CLKA1 J7 N9 CLKA1 J7 N9
CK VDD CK VDD
2
CLKA1# K7
CK VDD
R1 CLKA1# K7
CK VDD
R1 CMD19 CKE_H 2
CMDA19 K9 R9 CMDA19 K9 R9
CKE/CKE0 VDD +1.5VSDGPU CKE/CKE0 VDD +1.5VSDGPU
CMD20 A13 A13
CMDA18 K1
ODT/ODT0 VDDQ
A1 CMDA18 K1
ODT/ODT0 VDDQ
A1 CMD21 A8 A8
CMDA16 L2 A8 CMDA16 L2 A8
CS/CS0 VDDQ CS/CS0 VDDQ
CMDA30 J3
RAS VDDQ
C1 CMDA30 J3
RAS VDDQ
C1 CMD22 A6 A6
CMDA15 K3 C9 CMDA15 K3 C9
CAS VDDQ CAS VDDQ
CMDA13 L3
WE VDDQ
D2 CMDA13 L3
WE VDDQ
D2 CMD23 A11 A11
E9 310mAVDDQ E9
VDDQ
310mAVDDQ F1
VDDQ
F1 CMD24 A5 A5
DQSA4 F3 H2 DQSA6 F3 H2
DQSL VDDQ DQSL VDDQ
DQSA7 C7
DQSU VDDQ
H9 DQSA5 C7
DQSU VDDQ
H9 CMD25 A3 A3
CMD26 BA2 BA2
DQMA4 E7 A9 DQMA6 E7 A9
DML VSS DML VSS
DQMA7 D3
DMU VSS
B3 DQMA5 D3
DMU VSS
B3 CMD27 BA1 BA1
E1 E1
VSS VSS
VSS
G8
VSS
G8 CMD28 A12 A12
DQSA#4 G3 J2 DQSA#6 G3 J2
DQSL VSS DQSL VSS
DQSA#7 B7
DQSU VSS
J8 DQSA#5 B7
DQSU VSS
J8 CMD29 A10 A10
M1 M1
VSS VSS
VSS
M9
VSS
M9 CMD30 RAS* RAS*
P1 P1
CMDA5 T2 VSS P9 CMDA5 T2 VSS P9
RESET VSS RESET VSS Not Available
T1 T1
ZQ4 L8 VSS T9 ZQ5 L8 VSS T9
ZQ/ZQ0 VSS ZQ/ZQ0 VSS LOW HIGH
1
1
J1 B1 J1 B1
R2100 VGA@ L1 NC/ODT1 VSSQ B9 R2101 VGA@ L1 NC/ODT1 VSSQ B9
NC/CS1 VSSQ NC/CS1 VSSQ Command Bit Default Pull-down
243_0402_1% J9 D1 243_0402_1% J9 D1
L9 NC/CE1 VSSQ D8 L9 NC/CE1 VSSQ D8 ODTx 10k
NCZQ1 VSSQ NCZQ1 VSSQ
2
2
E2 E2
3 VSSQ E8 VSSQ E8 DDR3 CKEx 10k 3
VSSQ F9 VSSQ F9
VSSQ VSSQ RST 10k
G1 G1
VSSQ G9 VSSQ G9 CS* No Termination
VSSQ VSSQ
96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3
H5TQ2G63BFR-11C_FBGA96 H5TQ2G63BFR-11C_FBGA96
+1.5VSDGPU +1.5VSDGPU
+1.5VSDGPU R2088 R2089
VGA@ VGA@
CLKA1 1.33K_0402_1% 1.33K_0402_1%
<22> CLKA1
1
C2067
C2068
C2069
C2070
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
VGA@ +MEM_VREF2 +MEM_VREF3
C2059
C2160
C2061
C2162
C2063
C2064
C2065
C2066
1 1 1 1 1 1 1 1 1 1 1 1
R2090
162_0402_1% 1 1
VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ R2096 R2097
2
2 2 2 2 2 2 2 2 2 2 2 2 CLKA1# VGA@ C2057 VGA@ C2058
<22> CLKA1#
1.33K_0402_1% .1U_0402_16V7K 1.33K_0402_1% .1U_0402_16V7K
2 2
VGA@ VGA@
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2014/12/31 Deciphered Date 2016/12/31 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N16X Lower Rank0 8/9
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D301P
Date: Thursday, December 17, 2015 Sheet 27 of 63
A B C D E
A B C D E
+19VB +19VB +19VB
SM01000EJ00 3000ma
+19VB +INVPWR_B+
220ohm@100mhz 1 1
LCD POWER CIRCUIT LED PANEL Conn.
1
+3VS +LCDVDD
DCR 0.04 CONN@
W=60mils W=60mils C5229 C5230 C5231
U8 L14 0.1U_0402_25V6 2200P_0402_25V7K 68P_0402_50V8J ACES_50406-03071-001
W=60mils W=60mils
2
5 1 2 2 RF@ 30 35
1U_0402_6.3V6K
C140
HCB2012KF-221T30_0805 RF@ RF@ +3VS
IN OUT 1 2 29 30 G5 34
1 29 G4
2 EMC@ USB20_P7_CAMERA 28 33
GND 1 1 For Camera USB20_N7_CAMERA 28 G3
27 32
1000P_0402_50V7K
C364 @EMC@
1 1 27 G2
<BOM Structure> 4 3 C368 C365 26 31
2 EN OC .1U_0402_16V7K 68P_0402_50V8J EDP_AUXP_C 25 26 G1
1 25 1
SY6288C20AAC_SOT23-5 C367 2 2
@ @EMC@ +LCDVDD EDP_AUXN_C 24
<BOM Structure> 4.7U_0603_6.3V6K 2 2 +3VS EDP_TXN3_C 23 24
EDP_TXP3_C 22 23
<6> SOC_ENVDD EDP_TXN2_C 22
21
EDP_TXP2_C 20 21
1 1 20
+LCDVDD 19
C375 C419 18 19
.1U_0402_16V7K .1U_0402_16V7K EDP_HPD 17 18
2 2 16 17
<BOM Structure> @ 16
15
BKOFF# 14 15
SOC_BKL_PWM 13 14
12 13
11 12
+INVPWR_B+ 11
10
9 10
8 9
7 8
EDP_TXN1_C 6 7
EDP_TXP1_C 5 6
C371 1 2 .1U_0402_16V7K EDP_TXP0_C 4 5
<6> EDP_TXP0 EDP_TXN0_C EDP_TXN0_C 4
C372 1 2 .1U_0402_16V7K 3
<6> EDP_TXN0 EDP_TXP1_C SOC_BKL_PWM EDP_TXP0_C 3
C373 1 2 .1U_0402_16V7K R393 1 @ 2 100K_0402_5% 2
<6> EDP_TXP1 EDP_TXN1_C <6> SOC_BKL_PWM 2
C374 1 2 .1U_0402_16V7K 1
<6> EDP_TXN1 EDP_TXP2_C 1
C388 1 2 .1U_0402_16V7K @EMC@
<6> EDP_TXP2 EDP_TXN2_C
C376 1 2 .1U_0402_16V7K C549 1 2 220P_0402_50V7K JEDP2
<6> EDP_TXN2 EDP_TXP3_C
C387 1 2 .1U_0402_16V7K @EMC@
<6> EDP_TXP3 EDP_TXN3_C
C378 1 2 .1U_0402_16V7K BKOFF# C528 1 2 220P_0402_50V7K
<6> EDP_TXN3 <43> BKOFF#
2 2
R280 1 @ 2 10K_0402_5%
C379 1 2 .1U_0402_16V7K EDP_AUXP_C
<6> EDP_AUXP EDP_AUXN_C
<6> EDP_AUXN C377 1 2 .1U_0402_16V7K
+3VS
EDP_AUXN_C R613 2 1 100K_0402_5%
EDP_AUXP_C R614 2
@
@ 1 100K_0402_5% SP010011Z00
R407
0_0402_5%
1 @ 2 EDP_HPD
<6> CPU_EDP_HPD
R364
100K_0402_5%
2 1
3 3
Camera
USB20_N7 1 4 USB20_N7_CAMERA
<12> USB20_N7 1 4
L4904 EMI@
USB20_P7 2 3 USB20_P7_CAMERA
<12> USB20_P7 2 3
MCF12102G900-T_4P
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2014/11/10 Deciphered Date 2016/11/10 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
eDP Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D301P
Date: Thursday, December 17, 2015 Sheet 28 of 63
A B C D E
A B C D E
+3VS
L3
FBMA-L11-160808-800LMT_0603
1 2 +3VS_CRT
1 1 1 1
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
1 <6> SOC_DP1_HPD 1
C4
10U_0603_6.3V6M
C1
C2
C3
2 2 2 2
1
R2530
100K_0402_5%
20
U6
9
DVCC_33
DVCC_33
VDD_DAC_33
SOC_DP1_HPD 1
HPD
C6 1 2 .1U_0402_16V7K DP_CRT_AUXN 27 6 CRT_DATA_1
<6> SOC_DP1_AUXN DP_CRT_AUXP AUX_N VGA_SDA CRT_CLK_1 CRT_DATA_1 <30>
<6> SOC_DP1_AUXP C5 1 2 .1U_0402_16V7K 26 4
AUX_P VGA_SCL 8 PCH_CRT_HSYNC_R CRT_CLK_1 <30>
SOC_DP1_P0_C HSYNC PCH_CRT_VSYNC_R PCH_CRT_HSYNC_R <30>
<6> SOC_DP1_P0 C18 1 2 .1U_0402_16V7K 29 7
SOC_DP1_N0_C LANE0P VSYNC PCH_CRT_VSYNC_R <30>
<6> SOC_DP1_N0 C37 1 2 .1U_0402_16V7K 30
LANE0N 15 PCH_CRT_R
SOC_DP1_P1_C RED_P PCH_CRT_R <30>
<6> SOC_DP1_P1 C38 1 2 .1U_0402_16V7K 31
C39 1 2 .1U_0402_16V7K SOC_DP1_N1_C 32 LANE1P 12 PCH_CRT_G
<6> SOC_DP1_N1 LANE1N GREEN_P PCH_CRT_G <30>
10 PCH_CRT_B
+3VS BLUE_P PCH_CRT_B <30>
22 POL1_SDA
POL1_SDA POL2_SCL
4
3
2
1
C14 2 1 2.2U_0402_6.3V6M 23
POL2_SCL 75_0804_8P4R_1%
C13 2 1 .1U_0402_16V7K VCCK_12 19 2 CRT_SMB_CLK R24 1 @ 2 0_0402_5% RP23
VCCK_12 SMB_SCL 3 CRT_SMB_SDA R19 1 @ 2 0_0402_5%
C16 2 1 .1U_0402_16V7K 24 SMB_SDA
2 AVCC_33 2
5
6
7
8
C17 2 1 .1U_0402_16V7K VCCK_12 25
AVCC_12 21 LDO_EN
R9 1 2 12K_0402_1% 28 LDO_EN
RRX
18
11 XO
13 BLUE_N 17
14 GREEN_N XI/CKIN
16 GND_DAC
33 RED_N SOC_SML1CLK
EPAD_GND SOC_SML1DATA SOC_SML1CLK <8,19,21,43>
SOC_SML1DATA <8,19,21,43>
10U_0603_6.3V6M <BOM Structure>
RTD2168-CG_QFN32_5X5
2 Address:(layout guide P.11)
Please reserve slave address of
C15
0x64/0x65 and 0x68/0x69 for RTD2168’ s use
1
+3VS +3VS +3VS
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
3 3
1
@
R10
R5239
R5240
POL_SDA
2
0 1 LDO_EN:
POL2_SCL POL1_SDA LDO_EN
0 X EP *1: Internal 1.2V
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
0: External 1.2V
1
POL_SCL @
1 *ROM EEPROM
R5241
R5242
R5243
ROM: Internal ROM
2
EP: Programmed external EC
EEPROM: External ROM
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2014/11/10 Deciphered Date 2016/11/10 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Realtek RTD2168
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D301P
Date: Thursday, December 17, 2015 Sheet 29 of 63
A B C D E
A B C D E
W=40mils
CRT conn. +HDMI_5V_OUT
SM01000LU00 ( S SUPPRE_ MURATA BLM15BA220SN1D 0402)
CRT Connector
L2503 EMC@
1 BLM15BA220SN1D_2P 1
CRT_R 1 2 CRT_R_2 JCRT2
L2505 EMC@ 6
BLM15BA220SN1D_2P T99 @ 11
CRT_G 1 2 CRT_G_2 1
L2504 EMC@ 7
BLM15BA220SN1D_2P 12
CRT_B 1 2 CRT_B_2 2
8 G 16
13 17
10P_0402_50V8J
10P_0402_50V8J
10P_0402_50V8J
10P_0402_50V8J
10P_0402_50V8J
10P_0402_50V8J
G
1 1 1 1 1 1 3
9
14
C2529
C2530
C2531
C2532
C2533
C2534
T109 @ 4
2 2 2 2 2 2 10
15
5
SUYIN_070546FR015S251ZR
CONN@
L12 EMI@
BLM15BB470SN1D_2P
CRT_HSYNC 1 R2524 2 CRT_HSYNC_1 1 2 CRT_HSYNC_2
33_0402_5% L13 EMI@
BLM15BB470SN1D_2P CRT_CLK_2
CRT_VSYNC 1 R2525 2 CRT_VSYNC_1 1 2 CRT_VSYNC_2 CRT_DATA_2
33_0402_5% 1 1
@ @
C2536 C2537
2 10P_0402_50V8J 10P_0402_50V8J 2
2 2
+5VS +3VS
SELx Function
L port 1 is chose +3VS
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1 1 1 1
C782 C779 C780 C781
H port 2 is chose
3 3
2 2 2 2 DOCK_CRT_DET# R635 1 2 10K_0402_5%
+5VS +3VS
U11
PCH_CRT_R 1 16
<29> PCH_CRT_R PCH_CRT_G R 5V VDD
From RTD2168 2
<29> PCH_CRT_G PCH_CRT_B G
5 4
<29> PCH_CRT_B PCH_CRT_HSYNC_R B VDD
6 23
<29> PCH_CRT_HSYNC_R PCH_CRT_VSYNC_R H_SOURCE VDD
7 32
<29> PCH_CRT_VSYNC_R CRT_DATA_1 V_HOURCE VDD
9 To Docking
<29> CRT_DATA_1 CRT_CLK_1 10 SDA_SOURCE 27 RED_DOCK
<29> CRT_CLK_1 SCL_SOURCE R1 GREEN_DOCK RED_DOCK <44> SEL:Low
25
G1 BLUE_DOCK GREEN_DOCK <44>
0_0402_5% 22
DOCK_CRT_DET# B1 HSYNC_DOCK BLUE_DOCK <44> +HDMI_5V_OUT
2 @ 1 R550 30 20
<44> DOCK_CRT_DET# SEL H1_OUT VSYNC_DOCK HSYNC_DOCK <44>
18
+3VS V1_OUT CRT_DATA_DOCK VSYNC_DOCK <44>
12
SDA1 CRT_CLK_DOCK CRT_DATA_DOCK <44>
+3VS 0_0402_5% 2 @ 1 R549 29 14
TEST SCL1 CRT_CLK_DOCK <44>
CRT_R
1
10K_0402_5% 1 2 R762 8 26
Reserved R2 CRT_G
1
24 R302 R303
R647 R648 3 G2 21 CRT_B
4.7K_0402_5% 4.7K_0402_5% 11 GND B2 19 CRT_HSYNC To CRT CONN.2.2K_0402_5% 2.2K_0402_5%
28 GND H2_OUT 17 CRT_VSYNC SEL:High
GND V2_OUT
2
2
31 13 CRT_DATA_2
4 GND SDA2 4
2
CRT_DATA_1 33 15 CRT_CLK_2
CRT_CLK_1 GPAD SCL2
PI3V713-AZLEX_TQFN32_6X3~D
SA00004R600
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2014/02/14 Deciphered Date 2015/02/14 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRT CONN.
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D301P
Date: Thursday, December 17, 2015 Sheet 30 of 63
A B C D E
5 4 3 2 1
R183 1 2 4.7K_0201_5% DP_CFG0 R198 1 @ 2 4.7K_0201_5% PI0 R199 1 @ 2 4.7K_0201_5% PI1
+3VS +3VS +3VS
D D
R203 1 @ 2 4.7K_0201_5%
Chip operational mode configuration; Automatic EQ disable;
Internal pull down at ~150K?, 3.3V I/O. Internal pull down at ~150K?, 3.3V IO Auto test enable;
Internal pull down at ~150K?, 3.3V I/O.
L: Control switching mode (default) L: Automatic EQ enable (default) L: Auto test disable & input offset cancellation
H: Automatic switching mode H: Automatic EQ disable enable (default)
H: Auto test enable & input offset cancellation enable
M: Auto test disable & input offset cancellation disable
R185 1 @ 2 4.7K_0201_5% PC10 R189 1 @ 2 4.7K_0201_5% PC11
+3VS +3VS
R186 1 @ 2 4.7K_0201_5% R190 1 @ 2 4.7K_0201_5% R196 1 @ 2 4.7K_0201_5% PEQ
+3VS
R197 1 @ 2 4.7K_0201_5%
+3VS R187 1 @ 2 4.7K_0201_5% PC20 +3VS R191 1 @ 2 4.7K_0201_5% PC21
R188 1 @ 2 4.7K_0201_5% R194 1 @ 2 4.7K_0201_5% +3VS Programmable input equalization levels; Internal
pull down at ~150K?, 3.3V I/O.
AUX interception disable for Port y (y=1,2)
Internal pull down at ~150K?, 3.3V I/O. Output swing adjusment for Port y (y=1,2). L: default, LEQ, compensate channel loss up
C159 C160 C35 C36 to 11.5dB @ HBR2
Internal pull down at ~150K?, 3.3V I/O.
1 1 1 1 H: HEQ, compensate channel loss up to 14.5dB
L: AUX interception enable, driver configuration
0.1U_0201_10V6K
0.1U_0201_10V6K
0.01U_0402_16V7K
0.01U_0402_16V7K
is set by link training (default) L:default @ HBR2
H: AUX interception disable, driver output with H: +20% 2 2 2 2
M: LLEQ, compensate channel loss up to 8.5dB
fixed 800mv and 0dB M: -16.7% @ HBR2
M: AUX interception disable, driver output with
fixed 400mv and 0dB
C C
DP_MUX_SEL pin
Port switching control or priority configuration;
Internal pull down at ~150K?, 3.3V I/O. U23
L: Port1 is selected or with higher priority
(default) +3VS
5
VDD33
H: Port2 is selected or with higher priority 21 50
30 VDD33 OUT1_D0p 49 DP_DOCK_P0 <44>
VDD33 OUT1_D0n DP_DOCK_N0 <44>
51
57 VDD33 47
VDD33 OUT1_D1p 46 DP_DOCK_P1 <44>
OUT1_D1n DP_DOCK_N1 <44>
DPB_P0 6 45
to Docking
DPB_N0 IN_D0p OUT1_D2p DP_DOCK_P2 <44>
7 44
+3VS IN_D0n OUT1_D2n DP_DOCK_N2 <44>
DPB_P1 9 42
DDI2_CTRL_CK DPB_N1 IN_D1p OUT1_D3p DP_DOCK_P3 <44>
R5236 1 2 2.2K_0402_5% 10 41
DDI2_CTRL_DATA IN_D1n OUT1_D3n DP_DOCK_N3 <44>
R5237 1 2 2.2K_0402_5%
DPB_P2 12
DPB_N2 13 IN_D2p 40 +3VS
IN_D2n OUT2_D0p TBT_DP1_P0 <40>
39
DPB_P3 OUT2_D0n TBT_DP1_N0 <40> TBT_DP1_AUXN
15 R126 1 2 100K_0201_5%
DPB_N3 16 IN_D3p 37 DP_DOCK_AUXN R5244 1 2 100K_0201_5%
IN_D3n OUT2_D1p TBT_DP1_P1 <40>
36 TBT_DP1_N1 <40>
OUT2_D1n
35
to Alpine Ridge
OUT2_D2p TBT_DP1_P2 <40>
4 34 TBT_DP1_N2 <40>
3 IN_CA_DET OUT2_D2n
<6> CPU_HDMI_HPD IN_HPD TBT_DP1_AUXP
2 32 TBT_DP1_P3 <40> R129 1 2 100K_0201_5%
PI1 1 I2C_CTL_EN OUT2_D3p 31 DP_DOCK_AUXP R137 1 2 100K_0201_5%
Pl1/SCL_CTL OUT2_D3n TBT_DP1_N3 <40>
PI0 60
Pl0/SDA_CTL
2
26
DDI2_CTRL_CK OUT1_AUXp_SCL DP_DOCK_AUXP <44>
R5238 <6> DDI2_CTRL_CK 22 27 DP_DOCK_AUXN <44>
B DDI2_CTRL_DATA 23 IN_DDC_SCL OUT1_AUXn_SDA +3VS B
100K_0402_5% <6> DDI2_CTRL_DATA IN_DDC_SDA
DPB_AUXP 24 28
DPB_AUXN IN_AUXp OUT2_AUXp_SCL TBT_DP1_AUXP <40>
25 29
IN_AUXn OUT2_AUXn_SDA TBT_DP1_AUXN <40>
1
OUT2_CA_DET
2
R106 1 2 1M_0402_5%
DP_CFG0 59 43 R5234
CFG0 OUT1_CA_DET DP_DOCK_CAD <44>
58 48 4.7K_0402_5%
56 CFG1 OUT1_HPD DP_HPD_DOCK <44>
PC10
PC11 55 PC10 33 OUT2_CA_DET
PC11 OUT2_CA_DET
1
PC20 54 38
PC20 OUT2_HPD TBT_DP1_HPD <40>
PC21 53
PC21 18 1 @ 2
11 SW 8 DP_DOCK_SEL <44>
PEQ 0_0402_5% R5235
19 GND PEQ 14
52 GND PD 17 CEXT C57 1 2 2.2U_0402_6.3V6M
61 GND CEXT 20 REXT R1101 1 2 4.99K_0402_0.5%
PAD(GND) REXT
PS8338BQFN60GTR-A0_QFN60_5X9
CPU_DP2_N0 C300 2 1 0.1U_0402_16V7K DPB_N0
<6> CPU_DP2_N0
CPU_DP2_P0 C299 2 1 0.1U_0402_16V7K DPB_P0
<6> CPU_DP2_P0
CPU_DP2_N1 C277 2 1 0.1U_0402_16V7K DPB_N1
<6> CPU_DP2_N1
CPU_DP2_P1 C278 2 1 0.1U_0402_16V7K DPB_P1
<6> CPU_DP2_P1
A
CPU_DP2_N2 C276 2 1 0.1U_0402_16V7K DPB_N2 A
<6> CPU_DP2_N2
CPU_DP2_P2 C301 2 1 0.1U_0402_16V7K DPB_P2
<6> CPU_DP2_P2
CPU_DP2_N3 C298 2 1 0.1U_0402_16V7K DPB_N3
<6> CPU_DP2_N3
CPU_DP2_P3 C302 2 1 0.1U_0402_16V7K DPB_P3
<6> CPU_DP2_P3
DDI2_AUX_DN C285 2 1 0.1U_0402_16V7K DPB_AUXN
<6> DDI2_AUX_DN
DDI2_AUX_DP DPB_AUXP
<6> DDI2_AUX_DP
C289 2 1 0.1U_0402_16V7K
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2014/09/08 Deciphered Date 2013/10/28 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P32-DP MUX
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D301P 0.4(X01)
Date: Thursday, December 17, 2015 Sheet 31 of 63
5 4 3 2 1
A B C D E
the onrigial BOM structure of R630, R631, R633, R665, R667, R668, R669, R671
is EMI@ , @ is for short pad only
1 2
R630 0_0402_1%
HDMI_CLK+ HDMI_R_CK+
<32,40> HDMI_CLK+ @
HDMI_CLK- HDMI_R_CK-
1
<32,40> HDMI_CLK- 1
R631 1 2 0_0402_1%
R633 1 2 0_0402_1%
HDMI_TX0+ @ HDMI_R_D0+
<32,40> HDMI_TX0+
HDMI_TX0+ 1 2 R861 475_0402_1%
<32,40> HDMI_TX0+ HDMI_TX0- 1 2 R862 475_0402_1%
<32,40> HDMI_TX0- HDMI_TX1+ 1 2 R863 475_0402_1%
<32,40> HDMI_TX1+ HDMI_TX1- 1 2 R864 475_0402_1%
<32,40> HDMI_TX1-
HDMI_TX2+ 1 2 R865 475_0402_1% HDMI_TX0- HDMI_R_D0-
<32,40> HDMI_TX2+ HDMI_TX2- <32,40> HDMI_TX0-
1 2 R866 475_0402_1%
<32,40> HDMI_TX2- HDMI_CLK+ 1 2 R867 475_0402_1%
<32,40> HDMI_CLK+ HDMI_CLK- 1 2 R868 475_0402_1% R665 1 2 0_0402_1%
<32,40> HDMI_CLK-
@
3
Q2020B R667 1 2 0_0402_1%
DMN66D0LDW-7_SOT363-6
5 HDMI_TX1+ @ HDMI_R_D1+
+3VS <32,40> HDMI_TX1+
4
2 2
HDMI_TX1- HDMI_R_D1-
<32,40> HDMI_TX1-
R668 1 2 0_0402_1%
R669 1 2 0_0402_1%
HDMI_TX2+ @ HDMI_R_D2+
<32,40> HDMI_TX2+
Q2020A
DMN66D0LDW-7_SOT363-6
HDMI_HPD 1 6 HDMI_R_HPD
<40> HDMI_HPD
HDMI_TX2- HDMI_R_D2-
<32,40> HDMI_TX2-
1
2
2
R5172 R4
1M_0402_5% 20K_0402_5% R671 1 2 0_0402_1%
+HDMI_5V_OUT
+5VS U53 @
2
3
W=40mils
+3VS OUT
1
1
3 IN C802
3
2 0.1U_0402_16V4Z
GND 2
AP2330W-7_SC59-3
HDMI connector
+HDMI_5V_OUT L30ESDL5V0C3-2_SOT23-3 JHDMI1
HDMI_R_SDATA 3 HDMI_R_HPD 19
1 18 HP_DET
HDMI_R_SCLK +HDMI_5V_OUT +5V
2 17
HDMI_R_SDATA 16 DDC/CEC_GND
HDMI_R_SCLK SDA
2
D10 @ESD@ 15
14 SCL
+3VS Reserved
<BOM Structure> R338 R337 13
HDMI_R_CK- CEC
5
Q2019B 2.2K_0402_5% 2.2K_0402_5% 12 20
DMN66D0LDW-7_SOT363-6 11 CK- GND 21
CK_shield GND
1
HDMI_SCLK 4 3 HDMI_R_SCLK HDMI_R_CK+ 10 22
<40> HDMI_SCLK HDMI_R_D2- CK+ GND
9 23
8 D0- GND
HDMI_SDATA 1 6 HDMI_R_SDATA HDMI_R_D2+ 7 D0_shield
<40> HDMI_SDATA HDMI_R_D1- 6 D0+
Q2019A 5 D1-
DMN66D0LDW-7_SOT363-6 HDMI_R_D1+ 4 D1_shield
+3VS D1+
2
<BOM Structure> HDMI_R_D0- 3
2 D2-
HDMI_R_D0+ 1 D2_shield
4 D2+ 4
SUYIN_100042GR019M27SZL
CONN@
DC232000S00
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2014/11/10 Deciphered Date 2016/11/10 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDMI CONN.
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
LA-D301P 0.2
Date: Thursday, December 17, 2015 Sheet 32 of 63
A B C D E
A B C D E
+3VS
HDD Board Conn +3VS
0.01U_0402_16V7K
0.1U_0402_16V7K
1 1
R12
4.7K_0402_5%
C7
C8
@ 2 2
U1
JHDD1
2
7 10
EN VDD 20 1
1 SATA_CTX_DRX_P0 C9 2 1 0.01U_0402_16V7K SATA_PTX_C_DRX_P0 1 VDD RDSATA_PTX_DRX_P0C279 1 2 0.01U_0402_16V7K RDSATA_PTX_C_DRX_P0 2 1 1
<12> SATA_CTX_DRX_P0 SATA_CTX_DRX_N0 SATA_PTX_C_DRX_N0 2 A_INp RDSATA_PTX_DRX_N0C280 1 RDSATA_PTX_C_DRX_N0 2
C10 2 1 0.01U_0402_16V7K 6 R11 1 X76TI@ 2 4.99K_0402_1% 2 0.01U_0402_16V7K 3
<12> SATA_CTX_DRX_N0 A_INn NC 3
16 R755 1 2 1K_0402_5% 4
SATA_CRX_DTX_P0 C11 2 1 0.01U_0402_16V7K SATA_PRX_C_DTX_P0 5 NC RDSATA_PRX_DTX_N0C281 1 2 0.01U_0402_16V7K RDSATA_PRX_C_DTX_N0 5 4
<12> SATA_CRX_DTX_P0 SATA_CRX_DTX_N0 C12 2 1 0.01U_0402_16V7K SATA_PRX_C_DTX_N0 4 B_OUTp 9 A_DE RDSATA_PRX_DTX_P0C282 1 2 0.01U_0402_16V7K RDSATA_PRX_C_DTX_P0 6 5
<12> SATA_CRX_DTX_N0 B_OUTn A_PRE0 8 B_DE 7 6
B_EQ1 19 B_PRE0 8 7
+3VS
A_EQ1 17 A_PRE1 15 RDSATA_PTX_DRX_P0 9 8
B_PRE1 A_OUTp 14 RDSATA_PTX_DRX_N0 10 9
A_EQ2 18 A_OUTn 11 10
+3VS 3 TEST 11 RDSATA_PRX_DTX_P0 +5VS +5VS_HDD 12 11
B_EQ2 13 GND B_INp 12 RDSATA_PRX_DTX_N0 J2 13 12
R15 1 @ 2 4.7K_0402_5% A_DE 21 GND B_INn +5VS_HDD 1 2 14 13
EPAD 15 14
1 2 4.7K_0402_5% B_DE 16 15
R17 @ SN75LVCP601RTJR_A.4_TQFN20_4X4 100mils JUMP_43X118
17 16
SA00003ZX00 @
R14 1 @ 2 4.7K_0402_5% B_EQ1 X76TI@ G_INT2 18 17
19 18
0.1U_0402_16V4Z
C286
1000P_0402_50V7K
C287
R11 1 1 1
R20 1 @ 2 4.7K_0402_5% A_EQ1 U1 C284 20 19
21 20
R22 1 @ 2 4.7K_0402_5% A_EQ2 10U_0805_10V4Z @ 22 G1
2 2 2 23 G2
R13 1 @ 2 4.7K_0402_5% B_EQ2 24 G3
7.5K +-5% 0402 G4
PS8527CTQFN20GTR2-A1 X76PAR@ ACES_50406-02071-001
2
X76PAR@ SD028750180 CONN@ 2
R21 1 @ 2 4.7K_0402_5% A_DE SA00007JU10
SP010016L00
R16 1 @ 2 4.7K_0402_5% B_DE
R18 1 X76PAR@2 4.7K_0402_5% B_EQ1
R5247 1 2 4.7K_0402_5% A_EQ1
R23 1 2 0_0402_5% A_EQ2
R5248 1 2 0_0402_5% B_EQ2
+3VS
APS G-Sensor
1
+3VS
R523
3 0_0402_5% U26 @ 3
1 C633 1 2 10U_0603_6.3V6M
Vdd_IO
2
8
4 CS 14 C628 1 2 0.1U_0402_16V4Z
<8,18> SOC_SMBCLK 6 SCLSPC Vdd
<8,18> SOC_SMBDATA 7 SDA/SDI/SDO 0_0402_5% @ R524
R521 1 @ 2 10K_0402_5% SDO/SA0 11 1 2 G_INT
+3VS INT1 G_INT <11>
R522 1 2 10K_0402_5% 16 9 2 1 G_INT2
15 ADC1 INT2 0_0402_5% @ R5251
13 ADC2 10 0810 add for customer's request
ADC3 RES
2
3 NC 5
NC GND 12
GND
LIS3DHTR_LGA16_3X3
SA00004VF00
LIS3DH
SA0 ->0, Address is 0011 000 (0x30h)
SA0 ->1, Address is 0011 001 (0x32h)
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2014/02/14 Deciphered Date 2015/02/14 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDD & G-Sensor
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D301P
Date: Thursday, December 17, 2015 Sheet 33 of 63
A B C D E
5 4 3 2 1
+3VS +3VS_SSD_NGFF
JSSD1
1 2 J13
GND 3.3VAUX +3VS_SSD_NGFF
3 4 1 2
5 GND 3.3VAUX 6
7 PERn3 N/C 8 JUMP_43X118
PERp3 N/C 1 1
9 10 @
11 GND DAS/DSS# 12 C834 C835
13 PETp3 3.3VAUX 14 4.7U_0603_6.3V6K 0.1U_0402_16V4Z
15 PETn3 3.3VAUX 16 2 2
D 17 GND 3.3VAUX 18 D
19 PERn2 3.3VAUX 20
21 PERp2 N/C 22
23 GND N/C 24
25 PETp2 N/C 26
27 PETn2 N/C 28
29 GND N/C 30
31 PERn1 N/C 32
33 PERp1 N/C 34
35 GND N/C 36
37 PETn1 N/C 38 R657 1 @ 2 0_0402_5%
PETp1 DEVSLP DEVSLP2 <12>
39 40
SATA_CRX_DTX_P2 C836 1 2 0.01U_0402_16V7K SATA_PRX_DTX_P2_C 41 GND N/C 42 R670 1 2 0_0402_5%
<12> SATA_CRX_DTX_P2 SATA_CRX_DTX_N2 SATA_PRX_DTX_N2_C PERn0/SATA B+ N/C
C837 1 2 0.01U_0402_16V7K 43 44
<12> SATA_CRX_DTX_N2 45 PERp0/SATA B- N/C 46
SATA_CTX_DRX_N2 C838 1 2 0.01U_0402_16V7K SATA_PTX_DRX_N2_C 47 GND N/C 48 R659
<12> SATA_CTX_DRX_N2 SATA_CTX_DRX_P2 SATA_PTX_DRX_P2_C PETn0/SATA A- N/C NGFF_SSD_RST#_R1
C839 1 2 0.01U_0402_16V7K 49 50 @ 2 0_0402_5%
PLT_RST# <10,21,40,43,45>
<12> SATA_CTX_DRX_P2 51 PETp0/SATA A+ PERST# 52
53 GND CLKREQ# 54
55 REFCLKn PEWake# 56
57 REFCLKp N/C 58
GND N/C
R660
59 60 SUSCLK_SSD 1 @ 2 0_0402_5%
SSD_DET# N/C SUSCLK SUSCLK <10,38>
61 62
<11> SSD_DET# 63 PEDET 3.3VAUX 64
65 GND 3.3VAUX 66
GND 3.3VAUX +3VS_SSD_NGFF
67
GND
C 69 68 C
MTG77 MTG76
LTCX005V800
BELLW_80159-3221
BELLW_80159-3221_67P-T
+3VS
+3VALW +3V_NFC
+3VS +5VALW +5V_BST_NFC
2
R638 R639 @ @
Q53A 499_0402_1% 499_0402_1% 0_0603_5% 1 2 R663 0_0603_5% 1 2 R637
2
DMN66D0LDW-7_SOT363-6
+5VS +3VS
1
SOC_SML0CLK 6 1 SML0CLK_NFC
<8,35> SOC_SML0CLK
0_0603_5% 1 2 R662 0_0603_5% 1 2 R640
B 1 @ 2 B
R643 0_0402_5%
5
SOC_SML0DATA 3 4 SML0DATA_NFC
<8,35> SOC_SML0DATA +3V_NFC
Q53B CONN@
DMN66D0LDW-7_SOT363-6 HB_A511510-SCHR22
NFC_DET# 1
1 @ 2 <11> NFC_DET# 2 1
R642 0_0402_5% 3 2
4 3
NFC_DFU 5 4
<11> NFC_DFU NFC_RESET# 6 5
7 6
+3V_NFC +3V_NFC SML0CLK_NFC 8 7
SML0DATA_NFC 9 8
10 9
R664 1 @ 2 NFC_RESET# 11 10
+3V_NFC <12> NFC_IRQ 12 11
+5V_BST_NFC 12
1
0_0402_5% 13
@ TU12 13
1
14
R644 @ 15 14
15
5
U58 10K_0402_5% R413 16
1 5 100K_0402_5% GND 17
VCC
NC VCC GND
2
1
<12> NFC_RST# IN1
2
4 2 JNFC1
PLT_RST_BUF# 2 OUT IN A 4 NFC_RESET#
GND
<10,35,38> PLT_RST_BUF# IN2 3 Y
GND
1
U57 SA00004BV00
3
MC74VHC1G08DFT2G_SC70-5 R414 @ NL17SZ07DFT2G_SC70-5
A R641 100K_0402_5% @ A
0_0402_5%
2
1 @ 2
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2014/02/14 Deciphered Date 2015/02/14 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
mSATA & NFC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
LA-D301P 1A
Date: Thursday, December 17, 2015 Sheet 34 of 63
5 4 3 2 1
5 4 3 2 1
UL1 UL1 UL1
+3VALW +3V_LAN
0_0603_5% 1 @ 2 RL2
60mil 60mil
S IC WGI219LM SLKJ3 A0 QFN 48P PHY ABO ! S IC WGI219LM QREF A0 QFN 48P PHY ABO ! S IC WGI219V SLKJ5 A1 QFN 48P PHY ABO ! UL3
@ @ 5 1
IN OUT
SA000081G50 UL1 SA000081G30 SA000093420
2
+3V_LAN CLKREQ_PCIE#1 48 13 LAN_MIDI0+ GND
<10> CLKREQ_PCIE#1 CLK_REQ_N MDI_PLUS0 LAN_MIDI0- 1 LAN_PWR_ON 4
1 @ 2 36 14 1U_0402_6.3V6K 3
<10,34,38> PLT_RST_BUF# PE_RST_N MDI_MINUS0 CL15 EN OC
RL1 0_0402_5%
44 17 LAN_MIDI1+ SY6288C20AAC_SOT23-5
<10> CLK_PCIE_P1 45 PE_CLKP MDI_PLUS1 18 LAN_MIDI1- 2
<10> CLK_PCIE_N1 PE_CLKN MDI_MINUS1
PCIE
MDI
RL138 0.1U_0402_10V7K 1 2 CL1 PCIE_CRX_C_DTX_P5 38 20 LAN_MIDI2+
D <12> PCIE_CRX_DTX_P5 2 CL2 PCIE_CRX_C_DTX_N5 PETp MDI_PLUS2 LAN_MIDI2- D
@ 10K_0402_5% 0.1U_0402_10V7K 1 39 21
<12> PCIE_CRX_DTX_N5 PETn MDI_MINUS2
41 23 LAN_MIDI3+
<12> PCIE_CTX_C_DRX_P5 PERp MDI_PLUS3 LAN_MIDI3-
2
42 24
LAN_DISABLE_N_R <12> PCIE_CTX_C_DRX_N5 PERn MDI_MINUS3
+3V_LAN From EC
LAN_SCLK 28 6
LAN_SDATA SMB_CLK SVR_EN_N High act i ve.
31
SMBUS
SMB_DATA EN threshold voltage min:1. V typ:1.6V max: .0V
1 RL4 1 2 4.7K_0402_5% Current limit threshold 1.5~ .8A
RSVD1_VCC3P3
NOTE: LANWAKE_N must be connected LAN_PME# 2 5 + V LAN Rising t i me must >0. 5 ms and <100 ms
to PCH's LAN_WAKE# pin. <10> LAN_PME# LAN_DISABLE_N 1 @ 2 LAN_DISABLE_N_R 3 LANWAKE_N VDD3P3_IN
<10> LAN_DISABLE_N LAN_DISABLE_N 4
22U_0603_6.3V6M
RL5 0_0402_5% 1 2 1
VDD3P3_4
0.1U_0402_16V4Z
CL13
CL4
LAN_PWR_ON
CL14
15 1U_0402_10V6K
LAN_LINK# 26 VDD3P3_15 19
LAN_ACTIVITY# 0_0402_5% LAN_R_ACTIVITY# LED0 VDD3P3_19 2 1 2
NOTE: LAN_DISABLE_N must be connected 1 @ 2 RL6 27
25 LED1 VDD3P3_29
29
LED
to PCH's GPIO12/LAN_PHY_PWR_CTRL pin LED2 RL14 1 2 1K_0402_5%
LAN_PWR_EN <43>
47
VDD0P9_47 46
TL1 @ JTAG_TDI_LAN 32 VDD0P9_46 37
TL2 @ JTAG_TDO_LAN 34 JTAG_TDI VDD0P9_37
TL3 @ JTAG_TMS_LAN 33 JTAG_TDO 43
JTAG
TL4 @ JTAG_TCK_LAN 35 JTAG_TMS VDD0P9_43
JTAG_TCK 11
VDD0P9_11
LAN_XTALO RL8 1 @ 2 LAN_XTALO_R 9 40 +0.9V_PHY_CORE
0_0402_5% LAN_XTALI 10 XTAL_OUT VDD0P9_40 22
XTAL_IN VDD0P9_22 16
VDD0P9_16 8
RL9 1 2 1K_0402_5% 30 VDD0P9_8
25MHZ_10PF_7V25000014 TEST_EN
RL10 1 2 3.01K_0402_1% 12 7 +0.9V_LAN_OUT 2 1 LL1
3 1 RBIAS CTRL0P9 4.7UH_PG031B-4R7MS_1.1A_20%
C 3 1 49 C
10U_0603_6.3V6M
GND GND VSS_EPAD 2 1 1
22U_0603_6.3V6M
CL7
0.1U_0402_16V4Z
CL8
1 1
NOTE: Total requirement Cout>=20uF. ESR<50mohm.
CL9
CL5 CL6 @ WGI219LM-QREF-A0_QFN48_6X6
10P_0402_50V8J 4 YL1 2 10P_0402_50V8J
1 2 2
2 2
@ LAYOUT NOTE: Place LL1, CL7, CL8, CL9, and close to PHY
Connect RBIAS through a 3.01 kΩ 1%
pull-down resistor to ground and then
place it no more than one half inch
(0.5” ) away from the PHY. PD SEL Function
L L Ax to Bx; LEDAx to LEDBx
L H Ax to Cx; LEDAx to LEDCx
H X Hi-Z
0.1U_0402_16V4Z
+3V_LAN
CL10
1 1
CL11
1
CL12
LAN Switch
0.1U_0402_16V4Z
+3V_LAN 2 2 2
0.1U_0402_16V4Z
39
30
21
14
8
4
1
B RL16 RL15 UL2 B
RL19 1 @ 2 0_0402_5% LAN_PME# 499_0402_1% 499_0402_1%
VDD
VDD
VDD
VDD
VDD
VDD
VDD
<10,40> PCH_PCIE_WAKE# 2
38
B0+ LAN_MIDI3-_DOCK <44>
37
B0- LAN_MIDI3+_DOCK <44>
1
SOC_SML0CLK 6 1 LAN_SCLK LAN_MIDI3- 2
<8,34> SOC_SML0CLK A0+ 34
LAN_MIDI3+ B1+ LAN_MIDI2-_DOCK <44>
QL2A 3 33
A0- B1- LAN_MIDI2+_DOCK <44>
DMN66D0LDW-7_SOT363-6
5
29
LAN_MIDI2- B2+ LAN_MIDI1-_DOCK <44> To Docking.
6 28
SOC_SML0DATA 3 4 LAN_SDATA A1+ B2- LAN_MIDI1+_DOCK <44>SEL:Low
+3V_LAN <8,34> SOC_SML0DATA LAN_MIDI2+ 7 25
A1- B3+ LAN_MIDI0-_DOCK <44>
QL2B 24
B3- LAN_MIDI0+_DOCK <44>
DMN66D0LDW-7_SOT363-6
RL7 1 2 10K_0402_5% DET_SIG#_R LAN_MIDI1- 9 17
A2+ LEDB0 18 LAN_ACTIVITY#_DOCK <44>
LAN_MIDI1+ LEDB1 LAN_LINK#_DOCK <44>
10 41
RL12 @1 2 10K_0402_5% JTAG_TMS_LAN A2- LEDB2
NOTE: Default SMBus LAN_MIDI0- 11 C0+
36
35
LAN_MIDI3-_RJ45 <36>
RL11 @1 2 10K_0402_5% JTAG_TCK_LAN Address is 0xC8 A3+ C0- LAN_MIDI3+_RJ45 <36>
LAN_MIDI0+ 12 32
A3- C1+ LAN_MIDI2-_RJ45 <36>
31
C1- LAN_MIDI2+_RJ45 <36>
SMBUS PULL-UP OPTIONS DET_SIG#_R RL13 1
@
2 0_0402_5% 13 27
To RJ45 conn
<6,44> DET_SIG#_R SEL C2+ 26 LAN_MIDI1-_RJ45 <36> SEL:High
C2- LAN_MIDI1+_RJ45 <36>
SMBUS SPEED RL15 & RL16 LAN_LINK# 15 23
LAN_ACTIVITY# LEDA0 C3+ LAN_MIDI0-_RJ45 <36>
16 22
LEDA1 C3- LAN_MIDI0+_RJ45 <36>
1MHz(Defaul setting) 499ohm 42
LEDA2 19
5 LEDC0 20
PD LEDC1 40
LEDC2
2
43
RL18 PAD_GND
A 10K_0402_5% A
1
PI3L720ZHEX_TQFN42_9X3P5~D
SA00003B200
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2014/02/14 Deciphered Date 2015/02/14 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LAN Intel I219
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
Custom 1A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D301P
Date: Thursday, December 17, 2015 Sheet 35 of 63
5 4 3 2 1
5 4 3 2 1
TR1
LAN Connector
BOTH_GST5009-E-LF
SP050006B10
TR1 JRJ1
1 24
TCT1 MCT1 12
D D
LAN_MIDI0+_RJ45 2 23 RJ45_MIDI0+ RJ45_MIDI3- 8 GND
<35> LAN_MIDI0+_RJ45 TD1+ MX1+ PR4- 11
LAN_MIDI0-_RJ45 3 22 RJ45_MIDI0- RJ45_MIDI3+ 7 GND
<35> LAN_MIDI0-_RJ45 TD1- MX1- PR4+
4 21 RJ45_MIDI1- 6
TCT2 MCT2 PR2-
LAN_MIDI1+_RJ45 5 20 RJ45_MIDI1+ RJ45_MIDI2- 5
<35> LAN_MIDI1+_RJ45 TD2 MX2+ PR3-
LAN_MIDI1-_RJ45 6 19 RJ45_MIDI1- RJ45_MIDI2+ 4
<35> LAN_MIDI1-_RJ45 TD2- MX2- PR3+
7 18 RJ45_MIDI1+ 3
TCT3 MCT3 PR2+ 40mil
LAN_MIDI2+_RJ45 8 17 RJ45_MIDI2+ RJ45_MIDI0- 2
<35> LAN_MIDI2+_RJ45 TD3+ MX3+ PR1- 10
LAN_MIDI2-_RJ45 9 16 RJ45_MIDI2- RJ45_MIDI0+ 1 GND
<35> LAN_MIDI2-_RJ45 TD3- MX3- PR1+ 9
10 15 GND
TCT4 MCT4
LAN_MIDI3+_RJ45 11 14 RJ45_MIDI3+ SINGA_2RJ1660-000111F
<35> LAN_MIDI3+_RJ45 TD4+ MX4+
LAN_MIDI3-_RJ45 12 13 RJ45_MIDI3-
<35> LAN_MIDI3-_RJ45 TD4- MX4- CONN@
DC234007U00
1 1 1 1 350UH_IH-160
C335 C336 C337 C338 SP050006F00
@
0.1U_0402_16V4Z 0.1U_0402_16V4Z
C 2 2 2 2 C
0.1U_0402_16V4Z 0.1U_0402_16V4Z
C339
RJ45_GND
8
7
6
5
RP3 1 2LANGND
Place close to TCT pin 75_0804_8P4R_1% 1000P_1206_2KV7K
RJ45_GND EMI@
1
2
3
4
1
3
2
JP2500
@EMC@
D31 B88069X9231T203_4P5X3P2-2
SCA00002M00
2
RJ45_GND MESC5V02BD03_SOT23-3
ESD@
7/2 Add JP2500,J15 for EMI request
40mil
1
B B
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2014/02/14 Deciphered Date 2015/02/14 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LAN Magnetic & RJ45
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D301P
Date: Thursday, December 17, 2015 Sheet 36 of 63
5 4 3 2 1
A B C D E
7/2 change to PBY160808T for EMI request
40mil RC227 PBY160808T-121Y-N_2P JSPK1
+5VS +VDDA BEEP# 2 RC226 1 BEEP#_R 1 2 MONO_IN SPKL+ 1 EMC@ 2 SPKL+_1 1
60milRC229 @ 0_0603_5% 60mil <9> BEEP#
CC1 1U_0402_6.3V6K SPKL- 1 2 SPKL-_1 2 1
1 2 22K_0402_5% EMC@ 2
1 RC228 PBY160808T-121Y-N_2P
2
CC2 4.75V 1 3
EC_BEEP# 2 RC33 1 CC3 RC230 DC4 4 G1
<43> EC_BEEP# G2
0.1U_0402_16V4Z 4.7K_0402_5% AZ5125-02S.R7G_SOT23-3
2 22K_0402_5% 100P_0402_50V8J 3800-F02N-00R
(output = 300 mA) 2
Int. Speaker Conn. CONN@
1
@ESD@
7/1 Vendor suggest to DGND DC2
POP 2 1 HDA_RST#_R
<44> POP
SM010014520 3000ma 220ohm@100mhz DCR 0.04 +PVDD_HDA
1
@
40mil RB751V-40-YS_SOD323-2
LC1 2 1 0.1U_0402_16V4Z 0.1U_0402_16V4Z
1 +VDDA 1
FBMA-L11-201209-221LMA30T_0805 1 1 1
CC5 CC6
CC4
10U_0805_10V4Z DC3
2 2 2 2 1 EC_MUTE#
Place near Pin41 Place near Pin46 RB751V-40-YS_SOD323-2
SM010014520 3000ma 220ohm@100mhz DCR 0.04
LC2 2 1 10U_0603_6.3V6M +1.8VS_VDDA20mil
+1.8VS
FBMA-L11-201209-221LMA30T_0805
1 1
CC7 CC126
Combo Jack
2 2 HD Audio Codec JHP1
0.1U_0402_16V4Z COMBO_MIC 3
Place near Pin40 SM010015410 300ma 80ohm@100mhz DCR 0.3 7/2 change to 0ohm for EMI request 6
LC4
20mil +3VS_DVDD 10U_0603_6.3V6M 1 2 HP_LEFT RC69 1 2 60.4_0603_5% HPOUT_L_1 LC111 2 0_0603_5% HPOUT_L_2 1
+AVDD_HDA +3VS
HCB1608KF-121T30 _0603 EMI@
LC6 HP_RIGHT RC68 1 2 60.4_0603_5% HPOUT_R_1 LC121 2 0_0603_5% HPOUT_R_2 2
1 2 0.1U_0402_16V4Z
20mil 1
CC127
1
CC128
1
CC129 EMI@ 4
+VDDA HP_PLUG#
HCB1608KF-121T30 _0603 1 1 1
0.1U_0402_16V4Z
CC130 CC131 CC132 2 2 2 5
2
10U_0805_10V4Z 0.1U_0402_16V4Z
2 2 2 DC5
Place near Pin1, 9
0.1U_0402_16V4Z AZ5125-02S.R7G_SOT23-3 SINGA_2SJ-E960-001F
Place near Pin26
26
40
41
46
36
9
UC4
ESD@
DVDD_IO
CPVDD
DVDD
AVDD1
AVDD2
PVDD1
HP_DR_L HP_DC_L
PVDD2
2 1 CC1371 2 24
<44> HP_DOCK_L LINE2_L
RC231 1K_0402_5% 4.7U_0603_6.3V6K
2 1 HP_DR_R CC1381 2 HP_DC_R 23
<44> HP_DOCK_R LINE2_R 35mA
1
RC14 1K_0402_5% 4.7U_0603_6.3V6K 42 SPKL+ +MIC1_VREFOL
2 2 1 MIC2_DR_L CC1391 2 MIC2_DC_L 17
68mA 600mA SPK_OUT_L+
2
<44> MIC2_DOCK_L MIC2_L
RC236 1K_0402_5% 4.7U_0603_6.3V6K
2 1 MIC2_DR_R CC1401 2 MIC2_DC_R 18 43 SPKL-
<44> MIC2_DOCK_R MIC2_R SPK_OUT_L-
RC237 1K_0402_5% 4.7U_0603_6.3V6K
1 LINE1_R_L CC1351 LINE1_C_L
2
2 2 22 45 SPKR+
<44> LINE1_LEFT LINE1_L SPK_OUT_R+ SPKR+ <39>
RC234 1K_0402_5% 4.7U_0603_6.3V6K RC18
2 1 LINE1_R_R CC1361 2 LINE1_C_R 21 2.2K_0402_5%
<44> LINE1_RIGHT LINE1_R MIC1_C_L
RC235 1K_0402_5% 4.7U_0603_6.3V6K 44 SPKR- CC1511 2
MIC1_C_L SPK_OUT_R- SPKR- <39>
19 LC7 2.2U_0402_6.3V6M
MIC1_L HP_LEFT COMBO_MIC MIC1_C_R
1
32 RC19 1 @ 2 0_0402_5% 1 2 EMI@ 2 1 CC1521 2
MIC1_C_R 20 HPOUT_L NBQ100505T-800Y-N RC244 1K_0402_5% 2.2U_0402_6.3V6M
MIC1_R 33 HP_RIGHT
35 HPOUT_R
1 CBN HDA_SDIN0_AUDIO 1 RC25
8 2
SDATA_IN HDA_SDIN0 <9>
CC141 33_0402_5%
2.2U_0402_6.3V6M 37 5
2 CBP SDATA_OUT HDA_SDOUT_R <9> MIC1_JD
10mil
2
29 10
+MIC2_VREFO MIC2_VREFO SYNC HDA_SYNC_R <9>
RC32 RC30
11 HDA_RST#_R
HDA_RST#_R <9> 22K_0402_5% 22K_0402_5%
Combo Mic @ T168 10mil 30 RESETB
MIC1_VREFO_R D
1
6
BCLK HDA_BIT_CLK_R <9>
1
31 Q25 2
+MIC1_VREFOL MIC1_VREFO_L @EMI@ @EMI@ 2N7002E_SOT23-3
4.7U_0402_6.3V6M
G
CC1421 2 27 1 2 1 2 CC143 S
LDO1_CAP
1
10U_0603_6.3V6M RC239 0_0402_5% 22P_0402_50V8J
CC430
CC1441 2 39
10U_0603_6.3V6M LDO2_CAP 2 DMIC_DATA
GPIO0/DMIC_DATA For EMI HP_PLUG#
2
CC1451 2 7 2 @ 1 RC20
10U_0603_6.3V6M LDO3_CAP 3 DMIC_CLK 0_0402_5%
RC22 2 1 20K_0402_1% 15 GPIO1/DMIC_CLK
JDREF 47 EC_MUTE#
PD# EC_MUTE# <43>
CC1461 2 2.2U_0402_6.3V6M CPVEE 34 12 MONO_IN
CPVEE PCBEEP
SENSE_A 10mil 13 16
SENSE_B 14 SENSE A MONO_OUT 38
SENSE B AVSS2
3
28 CODEC_VREF CC1471 2 0.1U_0402_16V4Z 3
AUDIO_MUTE# 48 VREF
<43> AUDIO_MUTE# SPDIFO 10mil CC1481 2 2.2U_0402_6.3V6M
4
DVSS AVSS1
25
CC1491 2 10U_0603_6.3V6M
SM01000II00
LC9 EMI@
Digital MIC CONN
49 @ FCM1005KF-301T01 _2P
GND 1 2 DMIC_CLK_R
Place next pin28
DGND ALC3225-CG_MQFN48_6X6 2
SA000064R00 CC150
22P_0402_50V8J
SM010028800 2000ma 120ohm@100mhz DCR 0.1
@RF@
1
Place near
codec +3VS EMI@
LC10 JDMIC1
1 2 +3VS_DMIC +3VS_DMIC 1
HCB1608KF-121T30 _0603 DMIC_CLK_R 2 1
1 DMIC_DATA_R 2
3 5
HP_PLUG# RC241 2 1 39.2K_0402_1% SENSE_A J5 J7 C5232 4 3 G1 6
JUMP_43X39 JUMP_43X39 0.1U_0402_50V6K 4 G2
MIC1_JD RC242 2 1 20K_0402_1% 1 2 1 2 2 RF@ ACES_50208-0040N-001
@ 1 2 @ 1 2
RC243 2 1 10K_0402_1% J6 J10 SP02000K200
CONN@
<44> LINEIN_JD
JUMP_43X39 JUMP_43X39
1 2 1 2
@ 1 2 @ 1 2
RC27 2 1 39.2K_0402_1% SENSE_B J8 J9
<44> HP_DOCK_DET
JUMP_43X39 JUMP_43X39
RC28 2 1 20K_0402_1% 1 2 1 2
<44> MIC2_DOCK_DET
@ 1 2 @ 1 2
R488 1 @ 2 33_0402_5% DMIC_CLK_R
<9> PCH_DMIC_CLK DMIC_DATA_R
RC29 2 1 10K_0402_1% GND GNDA GND GNDA <9> PCH_DMIC_DATA R485 1 @ 2 33_0402_5%
<44> DOCK_CODEC_DET
DMIC_CLK R486 1 2 0_0402_5%
DMIC_DATA R487 1 2 0_0402_5%
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/07/20 Deciphered Date 2013/07/20 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HD Audio Codec_ALC3225X
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D301P
Date: Thursday, December 17, 2015 Sheet 37 of 63
A B C D E
A B C D E
Wireless LAN KEY E +3VS_WLAN
JNGFF1
1 2
USB20_P5 3 GND_1 3.3VAUX_2 4
<12> USB20_P5 USB20_N5 USB_D+ 3.3VAUX_4
USB2 P5 5 6
+3VS 60mil +3VS_WLAN <12> USB20_N5
7 USB_D- LED1# 8
@ T3801
R212 (For BT) 9 GND_7 PCM_CLK 10
1 @ 2 0_0805_5% 11 SDIO_CLK PCM_SYNC 12
13 SDIO_CMD PCM_OUT 14
1 1 1 SDIO_DAT0 PCM_IN
C458 @ 15 16
SDIO_DAT1 LED2# @ T3802
C459 C460 17 18 PH +3VS at SOC side, for win7 USB3 debug
19 SDIO_DAT2 GND_18 20
NGFF WL+BT+WIGIG (KEY E)
4.7U_0603_6.3V6K .1U_0402_16V7K
2 2 2 21 SDIO_DAT3 UART_WAKE 22 1 @ 2UART_2_CRXD_DTXD
<BOM Structure> SDIO_WAKE UART_TX UART_2_CRXD_DTXD <11>
.1U_0402_16V7K 23 R625 0_0402_5%
<BOM Structure> SDIO_RST
1 24 1 @ 2UART_2_CTXD_DRXD 1
UART_RX UART_2_CTXD_DRXD <11>
25 26 R626 0_0402_5%
PCIE_CTX_C_DRX_P6 GND_33 UART_RTS
2
27 28 R873 1 @ 2 0_0402_5%
<12> PCIE_CTX_C_DRX_P6 PCIE_CTX_C_DRX_N6 PET_RX_P0 UART_CTS CL_RST#_R E51TXD_P80DATA <43>
29 30 1 2 R158
+3VS_WLAN <12> PCIE_CTX_C_DRX_N6 PET_RX_N0 CLink_RST CL_DATA_R CL_RST# <8>
31 32 R4451VPRO@ 0_0402_5%
2 100K_0402_5%
+3VALW PCIE_CRX_DTX_P6 GND_39 CLink_DATA CL_CLK_R CL_DATA <8>
(link to PICE Port 4) <12> PCIE_CRX_DTX_P6 33 34 R4441VPRO@ 0_0402_5%
2
PCIE_CRX_DTX_N6 PER_TX_P0 CLink_CLK CL_CLK <8>
U9 PCIE X1 35 36 R443VPRO@ 0_0402_5%
W=60mils <12> PCIE_CRX_DTX_N6 PER_TX_N0 COEX3 @ T3803
1
5 1 37 38
1U_0402_6.3V6K
C165
IN OUT CLK_PCIE_P2 GND_45 COEX2 @ T3804
1 39 40 T3805
<10> CLK_PCIE_P2 CLK_PCIE_N2 REFCLK_P0 COEX1 @
SUSCLK_R
2 41 42 R5252 2 @ 1 0_0402_5%
GND <10> CLK_PCIE_N2 REFCLK_N0 SUSCLK(32KHz) WL_RST#_R SUSCLK <10,34>
43 44 R440 1 @ 2 0_0402_5%
CLKREQ_PCIE#2 GND_51 PERST0# E51RXD_P80CLK_R PLT_RST_BUF# <10,34,35,38>
4 3 (From PCH CLKOUT5) 45 46 R872 2 @ 1 0_0402_5%
2 EN OC <10> CLKREQ_PCIE#2 WLAN_PME# CLKREQ0# W_DISABLE2# WL_OFF# E51RXD_P80CLK <43>
PCIE CLK 47 48
<38,43> WLAN_PME# PEWAKE0# W_DISABLE1# WL_OFF# <43>
SY6288C20AAC_SOT23-5 49 50
51 GND_57 I2C_DAT 52
<12> PCIE_CTX_C_GRX_N8 RSVD/PCIE_RX_P1 I2C_CLK @ T3809 E51RXD_P80CLK mulitplexed with
53 54
<12> PCIE_CTX_C_GRX_P8
55 RSVD/PCIE_RX_N1 I2C_IRQ 56
@ T3810 BT_ON function
<43> WLAN_ON PCIE_CRX_GTX_N8 GND_63 RSVD_64 @ T3811
WG_RST#_R
57 58 R441 1 @ 2 0_0402_5%
<12> PCIE_CRX_GTX_N8 PCIE_CRX_GTX_P8 RSVD/PCIE_TX_P1 RSVD_66 PLT_RST_BUF# <10,34,35,38>
<12> PCIE_CRX_GTX_P8
59 60
RSVD/PCIE_TX_N1 RSVD_68 WG_PME# CLKREQ_PCIE#5 <10>
61 62 R442 1 @ 2 0_0402_5%
GND_69 RSVD_70 WLAN_PME# <38,43>
<10> CLK_PCIE_N5 63 64
65 RSVD_71 3.3VAUX_72 66
<10> CLK_PCIE_P5 RSVD_73 3.3VAUX_74
67
GND_75 68
69 GND1
GND2
BELLW_80152-3221
R3809 CONN@
2 1 WLAN_PME#
+3VS_WLAN
10K_0402_5% SP070013E00
2 2
3G_CONFIG3 1
JMINI2
2
+3VS_3G
+3VALW TO +3VS_3G
TU155 @ R401 1 3G@ 2 10K_0402_5%
+3VS_3G 3 CONFIG_3 3.3V 4 +3VALW +3VS_3G
5 Ground 3.3V 6 JSIM1 CONN@ U52
R406 2 3G@ 1 10K_0402_5% WAKE_OUT_WWAN USB20_P9_L 7 Ground Power_On_Off 8 3G_OFF# DMN3030LSS-13_SOP8L-8
USB20_N9_L 9 USB_D+ W_DISABLE# 10
3G_OFF# <38,43>
4 8 8 1
240mil
11 USB_D- LED# UIM_CLK 3 RFU RFU 7 UIM_DATA 7 2
4.7U_0603_6.3V6K
Ground UIM_RST CLK I/O
2
2 6 2 6 3
UIM_PWR 1 RST VPP 5 5
C812
3G@ R616
3G_CONFIG0 13 12 VCC GND 470_0603_5%
TU156 @WAKE_OUT_WWAN CONFIG_0 Reserved
TU157 @ 15 14 3G@ 3G@
2 10K_0402_5% BODYSAR_DET# Wake_On_WWAN# Reserved
4
R402 1 17 16 TAI_CPMPAT5-08GLBS1ZZ4H0 1
+3VS_3G BODYSAR_N Reserved GPS_DISABLE#
6 1
3G@ 19 18 LTCX0060A00
21 Ground GPS_DISABLE# 20
23 NC Reserved 22 UIM_RST
25 NC UIM-RESET 24 UIM_CLK 470K_0402_5%
10mil
3 27 Ground UIM-CLK 26 UIM_DATA 3G@
20mil 2 R620 1 3G_PWR_ON#_R 2 3G_PWR_ON# 3
NC UIM-DATA UIM_PWR UIM_CLK +19VB
29 28 C523 33P_0402_50V8K 3G@
MINI_DET# 31 NC UIM-PWR 30 3G@ Q51A
<11> MINI_DET# Ground NC UIM_RST
1
3
33 32 C524 33P_0402_50V8K 3G@ DMN66D0LDW-7_SOT363-6
35 NC Reserved 34 3G@ 3G@
NC Reserved UIM_DATA 1
37 36 C525 33P_0402_50V8K C813
33P_0402_50V8K C520 @ 39 Ground Reserved 38 3G@ 3G_PWR_ON# 5 0.1U_0603_25V7K
NC Reserved UIM_PWR <43> 3G_PWR_ON#
330P_0402_50V7K 2 1 C445 @ 41 40 C526 33P_0402_50V8K 3G@
330P_0402_50V7K 2 1 C446 @ 43 NC Reserved 42 Q51B 2
Ground NC
4
330P_0402_50V7K 2 1 C447 @ 45 44 3G@ DMN66D0LDW-7_SOT363-6
330P_0402_50V7K 2 1 C448 @ 47 NC NC 46 C809 1 2 1U_0402_10V6K
49 NC NC 48
ANT_TUNE_0_AP R621 1 @ 2 0_0402_5% ANT_TUNE_0 51 Ground NC 50
TU149 @ ANT_TUNE_1_AP ANT_TUNE_1 ANTCTL0 NC
TU150 @ R622 1 @ 2 0_0402_5% 53 52
ANT_TUNE_2_AP R623 1 @ 2 0_0402_5% ANT_TUNE_2 55 ANTCTL1 Reserved 54
TU151 @ ANT_TUNE_3_AP ANT_TUNE_3 ANTCTL2 Reserved
TU152 @ R624 1 @ 2 0_0402_5% 57 56
R416 1 3G@ 2 10K_0402_5% 3G_RESET# 59 ANTCTL3 Reserved 58 +3VS_3G
+3VS_3G 3G_CONFIG1 Reset# SIM_DET
TU153 @ 61 60
63 CONFIG_1 NC 62 MCF12102G900-T_4P
65 Ground 3.3V 64 USB20_P9_D 2 3 USB20_P9_L
3G_CONFIG2 67 Ground 3.3V 66 2 3
TU154 @ CONFIG_2 3.3V
69 68 L37 EMI@ +3VS_3G
GND GND USB20_N9_D 1 4 USB20_N9_L
1 4 3G@ 3G@ 3G@ 3G@
BELLW_80149-3223_67P CONN@
USB20_N9 R420 1 @ 2 0_0402_5% USB20_N9_D
220U 4V Y D2 ESR15M
220U 4V Y D2 ESR15M
220U 4V Y D2 ESR15M
R419 2 @ 1 10K_0402_5%
33P_0402_50V8K
330P_0402_50V7K
USB20_P9 USB20_P9_D +3VALW
R421 1 @ 2 0_0402_5%
22U_0805_6.3V6M
1 1 1
0.1U_0402_16V4Z
3G@ 3G@ 3G@
@EMI@ C522
1U_0402_10V6K
2 1 1 1
R418 2 @ 1 10K_0402_5% + + +
C444
C807
C803
C804
C805
3G_OFF# <38,43>
U59
C806
C808
USB20_N9 1 10 R417 2 @ 1 10K_0402_5%
<12> USB20_N9 USB20_P9 Y+ SEL 9 +3VS 1 2 2 2 2 2 2
2
<12> USB20_P9 Y- Vdd 8 +3VALW
3
GND OE 7 USB20_N9_D
Truth Table
4
5 M- D+ 6 USB20_P9_D
M+ D-
SEL OE# Y+ Y-
@ PI3USB102ZLEX_TQFN10_1P6X1P3
2
R318 X H Hi-Z Hi-Z
0_0402_5%
@
4
L L M+ M- 4
1
H L D+ D-
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2014/02/14 Deciphered Date 2015/02/14 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
mini Card & LTE CONN.
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D301P
Date: Thursday, December 17, 2015 Sheet 38 of 63
A B C D E
A B C D E
USB20_N2 U2DN2_L
<12> USB20_N2 +5VALW +USB3_VCCA
1 4 U33 W=40mils
1 4 1 8
L36 EMI@ 2 GND VOUT 7
2 3 3 VIN VOUT 6
2 3 4 VIN VOUT 5 USB_OC0#
<39,43,44> USB_PWR_EN# EN FLG USB_OC0# <12,39>
MCF12102G900-T_4P
USB20_P2 U2DP2_L SY6288D10CAC _MSOP8
<12> USB20_P2
0.1U_0402_16V4Z
C395
1 SA00004KB10
1 1
2
+USB3_VCCA
For ESD request
JUSB1
D37 9
MCF12102G900-T_4P 1 1
ESD@ W=80mils U3TXDP2
SSTX+
U3RXDN2 10 9 U3RXDN2 1
PCH_USB3_RX2_P 2 3 U3RXDP2 U3TXDN2 8 VBUS
<12> PCH_USB3_RX2_P 2 3 1 2 SSTX-
2 2 9 8 U2DP2_L 3
470P_0402_50V7K
C399
U3RXDP2 U3RXDP2 C398
L48 EMI@ + 7 D+
PCH_USB3_RX2_N 1 4 4 4 U2DN2_L GND
U3RXDN2 U3TXDN2 7 7 U3TXDN2 100U_B2_6.3VM_R35M 2 10
<12> PCH_USB3_RX2_N 1 4 1 D- GND
U3RXDP2 6 11
5 5 2 SSRX+ GND
U3TXDP2 6 6 U3TXDP2 4 12
U3RXDN2 5 GND GND 13
3 3 SSRX- GND
8 CONN@
L05ESDL5V0NA-4 SLP2510P8
+USB3_VCCA
MCF12102G900-T_4P D44 ESD@
PCH_USB3_TX2_P 2 1 PCH_USB3_TX2_P_C 2 3 U3TXDP2 U2DP2_L 3 6
<12> PCH_USB3_TX2_P 2 3 I/O2 I/O4
C798 0.1U_0402_16V7K
L49 EMI@
PCH_USB3_TX2_N 2 1 PCH_USB3_TX2_N_C 1 4 U3TXDN2
<12> PCH_USB3_TX2_N 1 4
C799 0.1U_0402_16V7K 2 5
2 GND VDD 2
1 4 U2DN2_L
I/O1 I/O3
AZC099-04SP.R7G_SOT23-6
USB3.0 Conn.(MB)
SC300003S00 0810 for ESD request, change to SC300003S00
use SC300001G00's footprint
IO Board Conn(For FFC,FPC)
+3VALW R666 1 @ 2 0_0402_5%
+3VS R661 1 @ 2 0_0402_5%
JIO1
+3VALW 20mil(250mA) +3V_USB +3V_USB
20mil
USB_OC0#
1
1
2
<12,39> USB_OC0# 2
U60 3
<12> PCH_USB3_RX1_N 3
5 1 4
IN OUT <12> PCH_USB3_RX1_P 4
5
2 6 5
GND 2 <12> PCH_USB3_TX1_N 6
7
<12> PCH_USB3_TX1_P 7
1 4 3 C832 8
C833 EN OC USB20_P1 9 8
<12> USB20_P1 9
1U_0402_10V6K @ SY6288C20AAC_SOT23-5 @ 1 4.7U_0603_6.3V6K USB20_N1 10
<12> USB20_N1 10
@ 11
3 2 12 11 3
<12> PCH_USB3_RX4_N 12
13
<12> PCH_USB3_RX4_P 13
14
15 14
<13,43,47,52> SYSON <12> PCH_USB3_TX4_N 15
16
<12> PCH_USB3_TX4_P 16
17
USB20_P4 18 17
<12> USB20_P4 18
USB20_N4 19
<12> USB20_N4 19
20
21 20
<43> USB_CHARGE_2A# USB_PWR_EN# 21
22
<39,43,44> USB_PWR_EN# 22
23
<43,44> USB_CHARGE_CB0 USB_CEN 23
24
<43> USB_CEN 24
SPKR- 25
<37> SPKR- 25
SPKR+ 26
<37> SPKR+ 26
27
<43,44> SELCDP 27
+5VALW 28
29 28
29
1
30
C5233 31 30 34
0.1U_0402_25V6 32 31 GND2 33
32 GND1
2
EMI@
ACES_51547-03201-W01
CONN@
1
C5240
68P_0402_50V8J
RF@
2
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2014/02/14 Deciphered Date 2015/02/14 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
USB3.0 & SSD
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D301P
Date: Thursday, December 17, 2015 Sheet 39 of 63
A B C D E
5 4 3 2 1
U5004A
PCIE_CTX_C_GRX_P9 Y23 V23 PCIE_CRX_C_GTX_P9 0.22U_0402_16V7K 2 1 TBT@ C5223 PCIE_CRX_GTX_P9
<12> PCIE_CTX_C_GRX_P9 PCIE_CTX_C_GRX_N9 Y22 PCIE_RX0_P PCIE_TX0_P V22 PCIE_CRX_C_GTX_N9 2 1 TBT@ C5224 PCIE_CRX_GTX_N9 PCIE_CRX_GTX_P9 <12>
0.22U_0402_16V7K
<12> PCIE_CTX_C_GRX_N9 PCIE_RX0_N PCIE_TX0_N PCIE_CRX_GTX_N9 <12>
PCIE_CTX_C_GRX_P10T23 P23 PCIE_CRX_C_GTX_P10 0.22U_0402_16V7K 2 1 TBT@ C5225 PCIE_CRX_GTX_P10
<12> PCIE_CTX_C_GRX_P10 PCIE_CTX_C_GRX_N10T22 PCIE_RX1_P PCIE_TX1_P P22 PCIE_CRX_C_GTX_N10 0.22U_0402_16V7K 2 1 TBT@ C5226 PCIE_CRX_GTX_N10 PCIE_CRX_GTX_P10 <12>
PCIe GEN3
<12> PCIE_CTX_C_GRX_N10 PCIE_RX1_N PCIE_TX1_N PCIE_CRX_GTX_N10 <12>
PCIE X2 Bus
(Link to CPU Port 1~4) M23 K23
M22 PCIE_RX2_P PCIE_TX2_P K22
PCIE_RX2_N PCIE_TX2_N
D D
H23 F23
H22 PCIE_RX3_P PCIE_TX3_P F22
PCIE_RX3_N PCIE_TX3_N
V19 L4 TBT_RST#_R 0_0402_5% 2 TBT@ 1 From CPU pin BB8
PCIE CLK <10> CLK_PCIE_P3 PCIE_REFCLK_100_IN_P PERST_N
R5188 PLT_RST# <10,21,34,43,45>
(From PCH CLKOUT0) T19
<10> CLK_PCIE_N3 1 TBT@ 2 0_0402_5% CLKREQ_PCIE#3_R AC5 PCIE_REFCLK_100_IN_N N16 PCIE_RBIAS
R5112 R5125 1 TBT@ 2 3.01K_0402_1%
<10> CLKREQ_PCIE#3 PCIE_CLKREQ_N PCIE_RBIAS
C4016 TBT@ 1 2 0.1U_0402_16V7K TBT_DP1_P0_C AB7 R2 DPSRC_ML0+ C4027 TBT@ 1 2 0.1U_0402_16V7K HDMI_TX0+
<31> TBT_DP1_P0 TBT_DP1_N0_C DPSNK0_ML0_P DPSRC_ML0_P HDMI_TX0+ <32>
C4015 TBT@ 1 2 0.1U_0402_16V7K AC7 R1 DPSRC_ML0- C4026 TBT@ 1 2 0.1U_0402_16V7K HDMI_TX0-
<31> TBT_DP1_N0 DPSNK0_ML0_N DPSRC_ML0_N HDMI_TX0- <32>
C4023 TBT@ 1 2 0.1U_0402_16V7K TBT_DP1_P1_C AB9 N2 DPSRC_ML1+ C4029 TBT@ 1 2 0.1U_0402_16V7K HDMI_TX1+
<31> TBT_DP1_P1 TBT_DP1_N1_C DPSNK0_ML1_P DPSRC_ML1_P HDMI_TX1+ <32>
<31> TBT_DP1_N1 C4022 TBT@ 1 2 0.1U_0402_16V7K AC9 N1 DPSRC_ML1- C4028 TBT@ 1 2 0.1U_0402_16V7K HDMI_TX1-
DPSNK0_ML1_N DPSRC_ML1_N HDMI_TX1- <32>
SOURCE PORT 0
TBT_DP1_P2_C L2 DPSRC_ML2+ C4031 TBT@ 1 HDMI_TX2+
SINK PORT 0
<31> TBT_DP1_P2 C4020 TBT@ 1 2 0.1U_0402_16V7K AB11 2 0.1U_0402_16V7K
TBT_DP1_N2_C DPSNK0_ML2_P DPSRC_ML2_P HDMI_TX2+ <32>
<31> TBT_DP1_N2 C4018 TBT@ 1 2 0.1U_0402_16V7K AC11 L1 DPSRC_ML2- C4030 TBT@ 1 2 0.1U_0402_16V7K HDMI_TX2-
DPSNK0_ML2_N DPSRC_ML2_N HDMI_TX2- <32>
C4021 TBT@ 1 2 0.1U_0402_16V7K TBT_DP1_P3_C AB13 J2 DPSRC_ML3+ C4033 TBT@ 1 2 0.1U_0402_16V7K HDMI_CLK+
from PS8338 <31> TBT_DP1_P3 TBT_DP1_N3_C DPSNK0_ML3_P DPSRC_ML3_P HDMI_CLK+ <32>
C4019 TBT@ 1 2 0.1U_0402_16V7K AC13 J1 DPSRC_ML3- C4032 TBT@ 1 2 0.1U_0402_16V7K HDMI_CLK-
<31> TBT_DP1_N3 DPSNK0_ML3_N DPSRC_ML3_N HDMI_CLK- <32>
C4025 TBT@ 1 2 0.1U_0402_16V7K TBT_DP1_AUXP_C Y11 W19
+3.3V_LC <31> TBT_DP1_AUXP TBT_DP1_AUXN_C DPSNK0_AUX_P DPSRC_AUX_P
C4024 TBT@ 1 2 0.1U_0402_16V7K W11 Y19
<31> TBT_DP1_AUXN DPSNK0_AUX_N DPSRC_AUX_N
AA2 G1 HDMI_HPD
<31> TBT_DP1_HPD DPSNK0_HPD DPSRC_HPD HDMI_HPD <32>
TBT_DP1_CTRL_CLK Y5 N6 DPSRC_RBIAS R5154 1 TBT@ 2 14K_0402_1%
<6> TBT_DP1_CTRL_CLK TBT_DP1_CTRL_DATA R4 DPSNK0_DDC_CLK DPSRC_RBIAS
R5126 R5127 R5128 R5129 <6> TBT_DP1_CTRL_DATA DPSNK0_DDC_DATA
1
U1
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
GPIO_0 TBT_I2C_SDA <42>
AB15 U2
TBT@ TBT@ TBT@ TBT@
DDC:3.3V AC15 DPSNK1_ML0_P GPIO_1 V1 TBT_EE_WP_N TBT_I2C_SCL <42>
PU @ SOC side DPSNK1_ML0_N GPIO_2 TBT_TMU_CLK_OUT
LC GPIO
+3.3V_LC V2
GPIO_3 TBT_PCIE_WAKE_N @ T32
JTAG1 AB17 W1 R5185 1 TBT@ 2 0_0402_5% PCH_PCIE_WAKE# <10,35>
to CPU BB15 pin
DPSNK1_ML1_P GPIO_4 TBT_CIO_PLUG_EVENT#
2
1 AC17 W2 TBT_CIO_PLUG_EVENT# <8>
to CPU GPP_D0 (SCI function pin)
TBT_TDI 2 1 DPSNK1_ML1_N GPIO_5 Y1 HDMI_SDATA
TBT_TMS 2 GPIO_6 HDMI_SCLK HDMI_SDATA <32>
3 AB19 Y2
TBT_TCK 3 DPSNK1_ML2_P GPIO_7 TBT_SRC_CFG1 HDMI_SCLK <32>
SINK PORT 1
4 AC19 AA1
C TBT_TDO 5 4 DPSNK1_ML2_N GPIO_8 J4 C
5 POC_GPIO_0 TBT_POC_GPIO_1 TBTA_I2C_INT <42>
6 AB21 E2
6 DPSNK1_ML3_P POC_GPIO_1 RTD3_USB_PWR_EN_R
POC GPIO
AC21 D4 R5189 1 TBT@ 2 0_0402_5% From CPU GPP_D2
DPSNK1_ML3_N POC_GPIO_2 TBT_FORCE_PWR_R RTD3_USB_PWR_EN <8>
7 H4 R5190 1 TBT@ 2 0_0402_5% From_CPU_GPP_22 (GPO pin)
GND POC_GPIO_3 TBT_FORCE_PWR <8>
8 Y12 F2 BATLOW# R5186 1 TBT@ 2 0_0402_5% TBT_BATLOW# <8>
From CPU GPP_D21
GND W12 DPSNK1_AUX_P POC_GPIO_4 D2 SLP_S3# R5187 1 TBT@ 2 0_0402_5%
DPSNK1_AUX_N POC_GPIO_5 RTD3_CIO_PWR_EN_R SUSP# <13,43,44,47,52>
ACES_50228-0067N-001 F1 R5191 1 TBT@ 2 0_0402_5% RTD3_CIO_PWR_EN <8>
Y6 POC_GPIO_6 From CPU GPP_D3
CONN@ DPSNK1_HPD TBT_TEST_EN
E1 R5123 1 TBT@ 2 100_0402_5%
TBT_SNK1_DDC_CLK Y8 TEST_EN
SNK0_CONFIG1 DPSNK1_DDC_CLK TBT_TEST_PWG
Misc
+3VS_TBT N4 AB5 R5124 1 TBT@ 2 100_0402_5%
DPSNK1_DDC_DATA TEST_PWR_GOOD Y2802
2 TBT@ 1 DPSNK_RBIAS Y18 F4 25MHZ_12PF_7V25000012
DPSNK_RBIAS RESET_N TBT_RESET_N <42>
R5153 14K_0402_1%
TBT_TDI Y4 D22 TBT_XTAL_25_IN 1 3
HDMI_SCLK R5201 2 TBT@ 1 2.2K_0402_5% TBT_TMS V4 TDI XTAL_25_IN D23 TBT_XTAL_25_OUT 1 3
HDMI_SDATA TBT_TCK TMS XTAL_25_OUT 1 GND GND 1
R5202 2 TBT@ 1 2.2K_0402_5% T4
RTD3_CIO_PWR_EN_R 2 TBT@ 1 TBT_TDO W4 TCK AB3
RTD3_USB_PWR_EN_R
R5141 10K_0402_5%
TDO MISC EE_DI TBT_EE_DI <42> C5108
2
TBT@
4
C5109
R5142 2 TBT@ 1 10K_0402_5% AC4 20P_0402_50V8 20P_0402_50V8
TBT_RBIAS EE_DO TBT_EE_DO <42> 2 2
2 TBT@ 1 H6 AC3 TBT_EE_CS_N <42> TBT@ TBT@
R5098 4.75K_0402_0.5% TBT_RSENSE J6 RBIAS EE_CS_N AB4
+3.3V_TBT_SX RSENSE EE_CLK TBT_EE_CLK <42>
A15 B7
TBT_I2C_SDA <42> USB3_A_TRX_DTX_P1 PA_RX1_P PB_RX1_P DPSRC_ML0+
R5137 2 TBT@ 1 2.2K_0402_5% B15 A7
TBT_I2C_SCL <42> USB3_A_TRX_DTX_N1 PA_RX1_N PB_RX1_N
R5138 2 TBT@ 1 2.2K_0402_5% 1
TBT_PCIE_WAKE_N 2 @ 1 C5179 TBT@ 1 2 0.22U_0201_6.3V6M USB3_A_TTX_DRX_P1 A17 A9
1P 50V C NPO 0201
R5249 10K_0402_5% <42> USB3_A_TTX_C_DRX_P1 C5126
TBT_CIO_PLUG_EVENT# R5133 2 TBT@ 1 10K_0402_5% C5180 TBT@ 1 2 0.22U_0201_6.3V6M USB3_A_TTX_DRX_N1 B17 PA_TX1_P PB_TX1_P B9
SLP_S3# <42> USB3_A_TTX_C_DRX_N1 PA_TX1_N PB_TX1_N
R5135 2 TBT@ 1 10K_0402_5% @
BATLOW# R5134 2 TBT@ 1 10K_0402_5% <42> USB3_A_TTX_C_DRX_P0 C5181 TBT@ 1 2 0.22U_0201_6.3V6M USB3_A_TTX_DRX_P0 A19 A11 DPSRC_ML0- 2
TBTA_I2C_INT R5131 2 TBT@ 1 10K_0402_5% C5182 TBT@ 1 2 0.22U_0201_6.3V6M USB3_A_TTX_DRX_N0 B19 PA_TX0_P PB_TX0_P B11
TBT_POC_GPIO_1 <42> USB3_A_TTX_C_DRX_N0 PA_TX0_N PB_TX0_N DPSRC_ML1+
R5136 2 TBT@ 1 10K_0402_5%
TBT_SRC_CFG1 2 TBT@ 1 B21 A13
TBT PORTS
R5144 10K_0402_5% <42> USB3_A_TRX_DTX_P0 1
CFG1 PU is HDMI MODE A21 PA_RX0_P PB_RX0_P B13
1P 50V C NPO 0201
<42> USB3_A_TRX_DTX_N0 C5121
PA_RX0_N PB_RX0_N
Port A
PORT B
6/16 INTEL suggest add 1pF
C5183 TBT@ 1 2 0.1U_0402_16V7K TBT_A_AUX_P Y15 Y16 @
<42> TBT_A_AUX_P_C TBT_A_AUX_N PA_DPSRC_AUX_P PB_DPSRC_AUX_P DPSRC_ML1- 2
B
<42> TBT_A_AUX_N_C C5184 TBT@ 1 2 0.1U_0402_16V7K W15 W16 B
PA_DPSRC_AUX_N PB_DPSRC_AUX_N
E20 E19 DPSRC_ML2+
<42> TBT_A_USB20_P PA_USB2_D_P PB_USB2_D_P
D20 D19 1
<42> TBT_A_USB20_N PA_USB2_D_N PB_USB2_D_N
1P 50V C NPO 0201
C5118
A5 B4 PB_LSTX
<42> TBTA_LSTX PA_LSTX PB_LSTX PB_LSRX
A4 B5 @
POC
POC
TBT_TMU_CLK_OUT <42> TBTA_LSRX PA_LSRX PB_LSRX PB_DPSRC_HPD DPSRC_ML2- 2
R5139 1 TBT@ 2 100K_0402_5%
<42> TBTA_HPD
M4 G2
TBT_FORCE_PWR_R R5140 1 TBT@ 2 100K_0402_5% PA_DPSRC_HPD PB_DPSRC_HPD
2 TBT@ 1 PA_USB2_RBIAS H19 F19 PB_USB2_RBIAS 1 TBT@ 2 DPSRC_ML3+
PS8338 Internal PD R5099 499_0402_1% PA_USB2_RBIAS PB_USB2_RBIAS R5100 499_0402_1%
TBT_DP1_HPD 1
R5143 1 @ 2 100K_0402_5% AC23 D6
1P 50V C NPO 0201
C5117
AB23 THERMDA MONDC_SVR
TBTA_LSTX R5147 1 TBT@ 2 1M_0402_1% THERMDA A23 @
TBTA_HPD R5145 1 TBT@ 2 100K_0402_5% V18 ATEST_P B23 DPSRC_ML3- 2
TBTA_LSRX R5148 1 TBT@ 2 1M_0402_1% PCIE_ATEST ATEST_N
TBT_SNK1_DDC_CLK 1 2 AC1 E18
SNK0_CONFIG1
R5146 TBT@ 100K_0402_5%
TEST_EDM DEBUG USB2_ATEST +3.3V_FLASH
R5149 1 TBT@ 2 100K_0402_5%
L15 W13
N15 FUSE_VQPS_64 MONDC_DPSNK_0
FUSE_VQPS_128 W18
C23 MONDC_DPSNK_1
PB_LSTX MONDC_CIO_0 1
1
R5150 1 TBT@ 2 100K_0402_5% C22 AB2
3.3K_0402_5%
PB_LSRX R5151 1 TBT@ 2 100K_0402_5% MONDC_CIO_1 MONDC_DPSRC R5104 R5103 R5102 C4036 R5101
PB_DPSRC_HPD R5152 1 TBT@ 2 100K_0402_5% AR4C_FC-CSP337 3.3K_0402_5% 3.3K_0402_5% 0.1U_0402_10V7K 3.3K_0402_5%
TBT@ 2
TBT@ TBT@ TBT@ TBT@
U5005
@ TBT_EE_CS_N
2
follow SP ref sch v0.998 1 8
TBT_EE_DO 2 CS# VCC 7
TBT_EE_WP_N 3 DO(IO1) HOLD#(IO3) 6 TBT_EE_CLK
4 WP#(IO2) CLK 5 TBT_EE_DI
GND DI(IO0)
W25Q80DVSSIG_SO8
TBT@
A A
U5004 For DVT
S IC DSL6340 SLL3Z B1 THUNDERBOLT ABO !
TBT@
SA000090N80 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2014/10/24 Deciphered Date 2015/12/31 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Alpine Ridge
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D301P
Date: Thursday, December 17, 2015 Sheet 40 of 63
5 4 3 2 1
5 4 3 2 1
+3VALW +3.3V_TBT_SX
1 2
R1581 0_0603_5%
2
@
R1582
0_0603_5%
+3.3V_LC +3.3V_TBT_SX +3.3V_TBT_S0 +3VS_TBT
+3VS +3VS_TBT TBT@
1
1 2
R1579 0_0603_5%
0.1U_0201_6.3V6K
1U_0201_6.3V6K
1U_0201_6.3V6K
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
TBT@
1 1 1 1 1 1 1
Option 1 for wake support over TBT: C5143 C5144 C5146 C5147 C5148 C5149 C5150
1.Connect R1581 and R1582,
2.Simple BIOS implementation TBT@ TBT@ TBT@ TBT@ TBT@ TBT@ TBT@
D 2 2 2 2 2 2 2 D
Option 2 for wake support over TBT:
1.Connect R1581 and R1579
R13
2.Bios need to implement Sx emtry pre-notice flow by PCIe2TBT +0.9V_DP
R6
H9
F8
U5004B
Option 3 No wake support at all from AR L8 A2
VCC3P3_SX
VCC3P3A
VCC3P3_LC
VCC3P3_S0
1. Connect R1579 and R41582
L11 VCC0P9_DP VCC3P3_SVR A3
1U_0201_6.3V6K
1U_0201_6.3V6K
1U_0201_6.3V6K
1U_0201_6.3V6K
1U_0201_6.3V6K
1U_0201_6.3V6K
1U_0201_6.3V6K
L12 VCC0P9_DP VCC3P3_SVR B3
1 1 1 1 1 1 1 VCC0P9_DP VCC3P3_SVR
C5110 C5111 C5112 C5113 C5114 C5115 C5116 M8
T11 VCC0P9_DP
TBT@ TBT@ TBT@ TBT@ TBT@ TBT@ TBT@ T12 VCC0P9_DP L9 +0.9V_SVR
2 2 2 2 2 2 2 L6 VCC0P9_DP VCC0P9_SVR M9
1U_0201_6.3V6K
1U_0201_6.3V6K
1U_0201_6.3V6K
1U_0201_6.3V6K
1U_0201_6.3V6K
1U_0201_6.3V6K
1U_0201_6.3V6K
M6 VCC0P9_ANA_DPSRC VCC0P9_SVR E12
VCC0P9_ANA_DPSRC VCC0P9_SVR_ANA 1 1 1 1 1 1 1
V11 E13 C5151 C5152 C5153 C5154 C5155 C5136 C5135
V12 VCC0P9_ANA_DPSNK VCC0P9_SVR_ANA F11
+0.9V_PCIE V13 VCC0P9_ANA_DPSNK VCC0P9_SVR_ANA F12 TBT@ TBT@ TBT@ TBT@ TBT@ TBT@ TBT@ Share same GND plane
VCC0P9_ANA_DPSNK VCC0P9_SVR_ANA F13 2 2 2 2 2 2 2
M13 VCC0P9_SVR_ANA F15
M15 VCC0P9_PCIE VCC0P9_SVR_ANA J9
1U_0201_6.3V6K
1U_0201_6.3V6K
1U_0201_6.3V6K
1U_0201_6.3V6K
M16 VCC0P9_PCIE VCC0P9_SVR_SENSE
1 1 1 1 VCC0P9_PCIE
C5122 C5123 C5124 C5125 L19 L4903 0.6UH_MND-04ABIR60M-XGL_20%
N19 VCC0P9_ANA_PCIE_1 C1 TBT_SVR_IND 1 2
TBT@ TBT@ TBT@ TBT@ L18 VCC0P9_ANA_PCIE_1 SVR_IND C2 TBT@
2 2 2 2 M18 VCC0P9_ANA_PCIE_2 SVR_IND D1
47U_0603_6.3V
47U_0603_6.3V
47U_0603_6.3V
VCC0P9_ANA_PCIE_2 SVR_IND 1 1 1
+0.9V_USB N18
C1403
C1404
C1405
6/3, Change PN
VCC
VCC0P9_ANA_PCIE_2
R15 A1
to SHI000MD00 TBT@ TBT@ TBT@
R16 VCC0P9_USB SVR_VSS B1 2 2 2
1U_0201_6.3V6K
1U_0201_6.3V6K
+0.9V_CIO VCC0P9_USB SVR_VSS B2
1 1 SVR_VSS
C5129 C5130 R8
R9 VCC0P9_CIO
TBT@ TBT@ R11 VCC0P9_CIO
2 2 R12 VCC0P9_CIO F18 +0.9V_LVR_OUT
1U_0201_6.3V6K
1U_0201_6.3V6K
1U_0201_6.3V6K
VCC0P9_CIO VCC0P9_LVR H18
10U_0402_6.3V6M
10U_0402_6.3V6M
1U_0201_6.3V6K
1U_0201_6.3V6K
1 1 1 +3.3V_ANA_PCIE VCC0P9_LVR
C5138 C5137 C5139 L16 J11 1 1 1 1
+3.3V_ANA_USB2 J16 VCC3P3_ANA_PCIE VCC0P9_LVR H11 C5161 C5160 C5119 C5120
C
TBT@ TBT@ TBT@ VCC3P3_ANA_USB2 VCC0P9_LVR_SENSE C
2 2 2 A6 V5
1U_0201_6.3V6K
1U_0201_6.3V6K
TBT@ TBT@ TBT@ TBT@
A8 VSS_ANA VSS_ANA V6 2 2 2 2
1 1 VSS_ANA VSS_ANA
C5141 C5142 A10 V8
A12 VSS_ANA VSS_ANA V9
TBT@ TBT@ A14 VSS_ANA VSS_ANA V15
2 2 A16 VSS_ANA VSS_ANA V16
A18 VSS_ANA VSS_ANA V20
A20 VSS_ANA VSS_ANA W5
A22 VSS_ANA VSS_ANA W6
B6 VSS_ANA VSS_ANA W8
B8 VSS_ANA VSS_ANA W9
B10 VSS_ANA VSS_ANA W20
B12 VSS_ANA VSS_ANA W22
B14 VSS_ANA VSS_ANA W23
B16 VSS_ANA VSS_ANA Y9
B18 VSS_ANA VSS_ANA Y13
B20 VSS_ANA VSS_ANA Y20
B22 VSS_ANA VSS_ANA AA22
D8 VSS_ANA VSS_ANA AA23
D9 VSS_ANA VSS_ANA AB6
D11 VSS_ANA VSS_ANA AB8
D12 VSS_ANA VSS_ANA AB10
+3.3V_TBT_S0 +3VS_TBT D13 VSS_ANA VSS_ANA AB12
D15 VSS_ANA VSS_ANA AB14
L64 D16 VSS_ANA VSS_ANA AB16
GND
1UH +-20% LQM18PN1R0MFHD D18 VSS_ANA VSS_ANA AB18
1 2 E8 VSS_ANA VSS_ANA AB20
E9 VSS_ANA VSS_ANA AB22
1U_0201_6.3V6K
TBT@
E11 VSS_ANA VSS_ANA AC6
47U_0603_6.3V
47U_0603_6.3V
1 1 1 VSS_ANA VSS_ANA
E15 AC8
C1401
C1402
C5145
E16 VSS_ANA VSS_ANA AC10
TBT@ TBT@ TBT@ E22 VSS_ANA VSS_ANA AC12
2 2 2 E23 VSS_ANA VSS_ANA AC14
F9 VSS_ANA VSS_ANA AC16
B F16 VSS_ANA VSS_ANA AC18 B
F20 VSS_ANA VSS_ANA AC20
G22 VSS_ANA VSS_ANA AC22
G23 VSS_ANA VSS_ANA D5
H1 VSS_ANA VSS E4
H2 VSS_ANA VSS E5
H12 VSS_ANA VSS E6
H13 VSS_ANA VSS F5
H15 VSS_ANA VSS F6
H16 VSS_ANA VSS H5
H20 VSS_ANA VSS H8
J5 VSS_ANA VSS J8
J18 VSS_ANA VSS J12
J19 VSS_ANA VSS J13
J20 VSS_ANA VSS J15
J22 VSS_ANA VSS L13
J23 VSS_ANA VSS M11
K1 VSS_ANA VSS M12
K2 VSS_ANA VSS N8
L5 VSS_ANA VSS N9
L20 VSS_ANA VSS N11
L22 VSS_ANA VSS N12
L23 VSS_ANA VSS N13
M1 VSS_ANA VSS T6
M2 VSS_ANA VSS T8
M5 VSS_ANA VSS T9
M19 VSS_ANA VSS T13
M20 VSS_ANA VSS T15
N5 VSS_ANA VSS T16
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
N20 VSS_ANA VSS T18
N22 VSS_ANA VSS AB1
N23 VSS_ANA VSS AC2
VSS_ANA VSS
AR4C_FC-CSP337
P1
P2
R5
R18
R19
R20
R22
R23
T1
T2
T5
T20
U22
U23
A A
@
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2014/10/24 Deciphered Date 2015/12/31 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Alpine Ridge-POWER
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
LA-D301P 0.1
Date: Thursday, December 17, 2015 Sheet 41 of 63
5 4 3 2 1
5 4 3 2 1
+3VALW +3VALW_PD
R5193 1 @ 2 0_0402_5%
1
C93 +5VALW +5VALW_PD
0.1U_0402_10V6K
2 R1580 @ 0_0805_5%
D TBT@ +TBTA_VBUS +TBTA_VBUS D
1 2
JUSB2
A1 B12
GND GND
<40> USB3_A_TTX_C_DRX_P0 A2 B11 USB3_A_TRX_DTX_P0 <40>
+5VALW_PD +20V_HV_SYS A3 SSTXP1 SSRXP1 B10
<40> USB3_A_TTX_C_DRX_N0 SSTXN1 SSRXN1 USB3_A_TRX_DTX_N0 <40>
A4 B9 0.47U_0201_25V 2 1 C5202
0.47U_0201_25V 2 1 C5201 VBUS VBUS TBT@
TBTA_CC1 A5 B8 TBTA_SBU2
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
4.7U_0805_50VAK
1 1 1 1 1 TBT@
CC1 RFU2
3
C5191 C5192 C5193 C5194 C5195
TBT_A_USB20_PT TBT_A_USB20_NB
1
A6 B7
TBT@ TBT@ TBT@ TBT@ @ C34 D36 TBT_A_USB20_NT A7 DP1 DN2 B6 TBT_A_USB20_PB
2 2 2 2 2 1U_0603_25V6K ESD@ DN1 DP2
Bottom
2
TBT@ TBTA_SBU1 A8 B5 TBTA_CC2
RFU1 CC2
TOP
L03ESDL5V0CC3-2_SOT23-3
0.47U_0201_25V 2 1 C5196 A9 B4 0.47U_0201_25V 2 1 C5197
TBTA_LDO_BMC TBT@ VBUS VBUS TBT@
+1.8VD_TBTA_LDO A10 B3
<40> USB3_A_TRX_DTX_N1 SSRXN2 SSTXN2 USB3_A_TTX_C_DRX_N1 <40>
1
+1.8VA_TBTA_LDO A11 B2
<40> USB3_A_TRX_DTX_P1 SSRXP2 SSTXP2 USB3_A_TTX_C_DRX_P1 <40>
1 1 1
C5199 C5200 A12 B1
C5198 GND GND
2.2U_0603_10V6K
2.2U_0603_10V6K
2.2U_0402_16V6K TBT@ TBT@
2 2 2 1 4
TBT@ +3VALW_PD GND GND
2 3
5 GND GND 6
GND GND
1
10U_0402_6.3V6M
C5203 JAE_DX07S024JJ2
C
CONN@ C
TBT@
2
H10
C11
D11
A11
B11
B10
A10
H1
B1
K1
A2
E1
A6
A7
A8
B7
B9
A9
U5007
F1
VIN_3V3
HV_GATE1
HV_GATE2
LDO_1V8D
LDO_BMC
PP_5V0
PP_5V0
PP_5V0
PP_5V0
SENSEN
VDDIO
LDO_1V8A
PP_CABLE
PP_HV
PP_HV
PP_HV
PP_HV
SENSEP
I2C_ADDR
D1 +3.3V_TBT_SX_R
<40> TBT_I2C_SDA I2C_SDA1
<40> TBT_I2C_SCL
D2
C1 I2C_SCL1
<40> TBTA_I2C_INT I2C_IRQ1_N
R5210 1 @ 2 0_0402_5% TBTA_I2C_SDA1 A5 USB3_A_TTX_C_DRX_P0 D17 1 TBT@ 2
<43,49,50> EC_SMB_DA1 TBTA_I2C_SCL1 I2C_SDA2 +3.3V_FLASH
<43,49,50> EC_SMB_CK1 R5209 1 @ 2 0_0402_5% B5 H11
B6 I2C_SCL2 VBUS J10 PESD5V0H1BSF SOD962
<43> PD_IRQ# I2C_IRQ2_N VBUS
PD_IRQ# PU at EC side J11
VBUS USB3_A_TTX_C_DRX_N0
1
B2 K11 D18 1 TBT@ 2
R5250 C2 GPIO0 VBUS
GPIO1 1
@TBT@ 10K_0402_5% D10 1 PESD5V0H1BSF SOD962 ESD@ D29
G11 GPIO2 C5204 TBTA_SBU1 6 3 TBT_A_USB20_PT
C10 GPIO3 C5205 USB3_A_TRX_DTX_P0 D19 1 TBT@ 2 I/O4 I/O2
<40> TBTA_HPD GPIO4 1U_0402_6.3V6K
2
E10 H2 2
GPIO5 VOUT_3V3 TBT@ 10U_0603_10V6M
G10 2 PESD5V0H1BSF SOD962 +5VALW
GPIO6 TBT@
D7 5 2
H6 GPIO7 USB3_A_TRX_DTX_N0 D20 1 TBT@ 2 VDD GND
GPIO8 G1
A3 LDO_3V3 PESD5V0H1BSF SOD962
<40> TBT_EE_CLK SPI_CLK TBT_A_USB20_NT 4 TBTA_CC1
<40> TBT_EE_DI
B4 1
A4 SPI_MOSI USB3_A_TTX_C_DRX_P1 D21 1 TBT@ 2 I/O3 I/O1
<40> TBT_EE_DO SPI_MISO TBT_A_USB20_PT
<40> TBT_EE_CS_N B3 K6 AZC099-04SP.R7G_SOT23-6
SPI_SS_N C_USB_TP L6 TBT_A_USB20_NT PESD5V0H1BSF SOD962 SC300003S00
L5 C_USB_TN
<40> TBT_A_USB20_P USB_RP_P USB3_A_TTX_C_DRX_N1 SC300003S00
<40> TBT_A_USB20_N K5 D34 1 TBT@ 2
USB_RP_N AZC099-04SP.R7G_SOT23-6
2 1 PD_UART E2 K7 TBT_A_USB20_PB ESD101-B1-02ELS_TSSLP-2-4-2 TBTA_SBU2 1 4 TBT_A_USB20_NB
1M_0402_5% R5165 F2 UART_TX C_USB_BP L7 TBT_A_USB20_NB I/O1 I/O3
B TBT@ UART_RX C_USB_BN TBT@ USB3_A_TRX_DTX_P1 D23 1 TBT@ 2 B
F4 C550 2 1 220P_0402_50V7K +5VALW
G4 SWD_DATA ESD101-B1-02ELS_TSSLP-2-4-2 2 5
SWD_CLK L9 TBTA_CC1 GND VDD
C_CC1 L10 TBTA_CC2 USB3_A_TRX_DTX_N1 D24 1 TBT@ 2
C_CC2 TBT@
2 TBT@ 1 TBT_MRESET E11 C551 2 1 220P_0402_50V7K ESD101-B1-02ELS_TSSLP-2-4-2 TBT_A_USB20_PB 3 6 TBTA_CC2
R5162 100K_0402_5% MRESET I/O2 I/O4
K9 RPD_G1 R5207 1 @ 2 0_0402_5% D30 ESD@
R5192 1 @ 2 0_0402_5% L4 RPD_G1 K10 RPD_G2 R5208 1 @ 2 0_0402_5%
<40> TBTA_LSTX TBT_LSTX/R2P RPD_G2
<40> TBTA_LSRX R5194 1 @ 2 0_0402_5% K4
TBT_LSRX/P2R
TBT@ +3.3V_FLASH
+3.3V_TBT_SX R5163 2 TBT@ 1 100K_0402_5% TBTA_DIG_AUD_P L3 E4 DEBUG_CTL1 R5161 2 1 10K_0402_5%
R5164 2 TBT@ 1 100K_0402_5% TBTA_DIG_AUD_N K3 DIG_AUD_P/DEBUG3 DEBUG_CTL1 D5 DEBUG_CTL2 R5166 2 1 10K_0402_5%
DIG_AUD_N/DEBUG4 DEBUG_CTL2 TBT@
1
R5170 R5167 2 TBT@ 1 100K_0402_5% TBTA_DEBUG1 L2
R5168 2 TBT@ 1 100K_0402_5% TBTA_DEBUG2 K2 DEBUG1
100K_0402_5%
DEBUG2
TBT@ TBTA_SBU1
K8 R5197 1 @ 2 0_0402_5%
C_SBU1
2
<40> TBT_A_AUX_P_C J1
J2 AUX_P L8 R5198 1 @ 2 0_0402_5% TBTA_SBU2
<40> TBT_A_AUX_N_C AUX_N C_SBU2
1
+3.3V_FLASH
R5171 1 @ 2 BUSPOWER# F10
R5196 0_0402_5% BUSPOWER_N F11 R5203 1 @ 2 0_0402_5%
100K_0402_5% RESET_N TBT_RESET_N <40>
TBT@ TBTA_ROSC G2
R_OSC
2
+1.8VS
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
1 TBT@ 2 1 TBT@ 2 R5173 EC_TBTA_RESET <43>
1
R5204 0_0402_5% 0_0402_5%
R5169 TBT@
A1
D6
E5
E6
E7
F5
G5
H4
H5
B8
D8
E8
F6
F7
F8
G6
G7
G8
H7
H8
L1
L11
2
15K_0402_1% TPS65982_BGA96
R5205 TBT@
A 0_0402_5% A
2
@
1
TI suggest reserve 0ohm to 1.8V,3.3V,GND
SS
1
C5212
0.22U_0402_10V4Z
2
TBT@ Security Classification
2014/10/24
Compal Secret Data
2015/12/31 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PD+Type C
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
LA-D301P 0.1
Date: Thursday, December 17, 2015 Sheet 42 of 63
5 4 3 2 1
A B C D E
+3VLP_EC +3VLP_ECA Board ID
+3VLP L4901 <BOM Structure> +3VLP_EC
JP4901 FBMA-L11-160808-800LMT_0603
1 2 1 2 +3VLP_ECA
1 2
2
JUMP_43X39 R4902
+3VALW_1.8VALW_PGPPA Ra
.1U_0402_16V7K
.1U_0402_16V7K
@ 1 1 1 100K_0402_1%
C4901
C4902
1
C4907
0_0402_5%
1
AD_BID
1
For Power consumption <BOM Structure>
<BOM Structure>
R4952
.1U_0402_16V7K
2 2 @ 2
Measurement 0_0402_5% <BOM Structure>
1
@ 1
R4953 ECAGND R4903
ECAGND <49>
2
Rb C4908
2
1 +3VCC_LPC 1
20K_0402_1% .1U_0402_16V7K
2
@
2
111
125
22
33
96
67
9
U4901
Analog Board ID definition,
VCC0
VCC_LPC
VCC
VCC
VCC
VCC
AVCC
Please see page 3.
ESPI Bus Pin : 1~5.7.8.10.12.14
LPC Bus Pin : 3~5.7.8.10.12.13 SUSPWRDNACK 1 21 EC_VCCST_PG_R
<10> SUSPWRDNACK EC_KBRST# GATEA20/GPIO00 EC_VCCST_PG/GPIO0F EC_BEEP# EC_VCCST_PG_R <10,47>
2 23
TPM_SERIRQ KBRST#/GPIO01 BEEP#/GPIO10 FAN_PWM EC_BEEP# <37>
3 26
<8,45> TPM_SERIRQ LPC_FRAME# 4 SERIRQ EC_FAN_PWM/GPIO12 27 DGPU_AC_DETECT FAN_PWM <46>
<8,45> LPC_FRAME# LPC_AD3_R LPC_FRAME# PWM Output AC_OFF/GPIO13 DGPU_AC_DETECT <11,21>
5
<8,45> LPC_AD3_R LPC_AD2_R 7 LPC_AD3
<8,45> LPC_AD2_R LPC_AD1_R 8 LPC_AD2 63 BATT_TEMP USB_CHARGE_CB0 2 1
@
<8,45> LPC_AD1_R LPC_AD0_R 10 LPC_AD1 VCIN1_BATT_TEMP/AD0/GPIO38 64 3G_OFF# BATT_TEMP <49,50>
LPC_AD0LPC & MISC
4.7K_0402_5% R4943
<8,45> LPC_AD0_R VCIN1_BATT_DROP/AD1/GPIO39 65 ADP_I 3G_OFF# <38>
ESPI_CLK_R 12 ADP_I/AD2/GPIO3A 66 AD_BID ADP_I <49,50>
For turn off internal LPC module of KB9032
<8> ESPI_CLK_R PLT_RST# CLK_PCI_EC AD Input AD_BID/AD3/GPIO3B WLAN_PME# R4943 for 9032 only
ESPI@ 13 75
1 2 PLT_RST# <10,21,34,40,45> PLT_RST# EC_RST# 37 PCIRST#/GPIO05 AD4/GPIO42 76 SLP_LAN# WLAN_PME# <38>
<46> EC_RST# EC_SCI# 20 EC_RST# AD5/GPIO43 SLP_LAN# <10>
R4950 47K_0402_5% Combine w/ SMI OPMODE(PIN70 Internal Pull High) :
<6> EC_SCI# WLAN_ON EC_SCI#/GPIO0E
38 Pull Up : Intel eSPI Master Attached Flash Sharing Topology
1 2 <38> WLAN_ON CLKRUN#/GPIO1D
C4916 @EMC@ 100P_0402_50V8J 68 LAN_PWR_EN --> For KB9032 Only.
<45> KSI[0..7] DA0/GPIO3C USB_CHARGE_CB0 LAN_PWR_EN <35> Pull Down : Intel Legacy Wire-OR share ROM.
DA Output EN_DFAN1/DA1/GPIO3D 70
55 71 FAN_VSET USB_CHARGE_CB0 <39,44> --> For KB9022/9032 Use
Reserved for ESD 2014/9/17 KSI0
KSI0/GPIO30 DA2/GPIO3E FAN_VSET <46>
KSI1 56 72 KB_BL_EN
AC_IN KSI1/GPIO31 DA3/GPIO3F KB_BL_EN <45>
1 2 KSI2 57
C4915 100P_0402_50V8J KSI3 58 KSI2/GPIO32 83 EC_MUTE#
59 KSI3/GPIO33 EC_MUTE#/PSCLK1/GPIO4A 84 USB_PWR_EN# EC_MUTE# <37>
KSI4
KSI5 60 KSI4/GPIO34 USB_EN#/PSDAT1/GPIO4B 85 USB_CEN USB_PWR_EN# <39,44>
2 @EMC@ @EMC@ 2
2 1 2 1 ESPI_CLK_R 61 KSI5/GPIO35 PSCLK2/GPIO4C 86 PM_SLP_S0# USB_CEN <39>
KSI6
KSI6/GPIO36 PS2 Interface PSDAT2/GPIO4D TP_CLK PM_SLP_S0# <6,10> SYS_PWROK_R
C4910 R4904 33_0402_5% KSI7 62 87 1 @ 2 SYS_PWROK <10>
<45> KSO[0..17] KSO0 39 KSI7/GPIO37 TP_CLK/GPIO4E 88 TP_DATA TP_CLK <43,45>
22P_0402_50V8J R4956 0_0402_5%
40 KSO0/GPIO20 TP_DATA/GPIO4F TP_DATA <43,45>
KSO1
KSO2 41 KSO1/GPIO21
KSO3 42 KSO2/GPIO22 97 ENBKL +3VS
KSO3/GPIO23 ENKBL/GPXIOA00 3G_PWR_ON# ENBKL <6>
R4951 KSO4 43 98
44 KSO4/GPIO24 WOL_EN/GPXIOA01 99 ME_EN 3G_PWR_ON# <38>
KSO5
KSO5/GPIO25 Int. K/B
0_0402_5%
EC_KBRST# ME_EN/GPXIOA02 VCIN0_PH ME_EN <9>
1 @ 2 KSO6 45 109
<8> EC_KBRST#_R KSO7 46 KSO6/GPIO26 Matrix VCIN0_PH1/GPXIOD00 VCIN0_PH <49>
47 KSO7/GPIO27 PD_IRQ# R634 1 PD@ 2 10K_0402_5%
KSO8
KSO8/GPIO28 SPI Device Interface TP_CLK
KSO9 48 119 SELCDP R5245 1 2 4.7K_0402_5%
49 KSO9/GPIO29 MISO/GPIO5B 120 MUTE_LED# SELCDP <39,44> <43,45> TP_CLK TP_DATA
KSO10 R5246 1 2 4.7K_0402_5%
+3VLP_EC KSO10/GPIO2A MOSI/GPIO5C SLP_WLAN# MUTE_LED# <45> <43,45> TP_DATA
KSO11 50 SPI Flash ROM SPICLK/GPIO58 126
51 KSO11/GPIO2B 128 PKEY_LED# SLP_WLAN# <10>
KSO12
1 2 2.2K_0402_5% EC_SMB_CK1 52 KSO12/GPIO2C SPICS#/GPIO5A PKEY_LED# <45>
R490 KSO13
R491 1 2 2.2K_0402_5% EC_SMB_DA1 KSO14 53 KSO13/GPIO2D
R636 1 2 10K_0402_5% USB_CEN KSO15 54 KSO14/GPIO2E 73 PD_IRQ# +3VLP_EC
KSO15/GPIO2F EC_CIR_RX/AD6/GPIO40 SYS_PWROK_R PD_IRQ# <42>
KSO16 81 74
KSO17 82 KSO16/GPIO48 SYS_PWROK/AD7/GPIO41 89 USB1_CEN
KSO17/GPIO49 GPIO50 90 BATT_BLUE_LED# USB1_CEN <44> LID_SW# R618 1 2 100K_0402_1%
EC_RSMRST# BATT_CHG_LED#/GPIO52 91 CAP_LED# BATT_BLUE_LED# <45>
EC_SMB_CK1 77 CAPS_LED#/GPIO53 92 PWR_LED# CAP_LED# <45>
<42,49,50> EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CLK1/GPIO44 GPIO PWR_LED#/GPIO54 BATT_AMB_LED# PWR_LED# <44,45>
1 10P_0402_50V8J 78 93
<42,49,50> EC_SMB_DA1 SOC_SML1CLK 79 EC_SMB_DAT1/GPIO45 BATT_LOW_LED#/GPIO55 95 SYSON BATT_AMB_LED# <45>
C5251 PU at CPU <8,19,21,29>
side
<8,19,21,29>
SOC_SML1CLK
SOC_SML1DATA
SOC_SML1DATA 80 EC_SMB_CLK2/GPIO46 SYSON/GPIO56 121 USB2_CHARGE_2A# SYSON <13,39,47,52>
USB2_CHARGE_2A# <44>
For Thermal Portect Shutdown
EC_SMB_DAT2/GPIO47 VR_ON/GPIO57 127 USB_CHARGE_2A# D2012
2 DPWROK_EC/GPIO59 USB_CHARGE_2A# <39>
SM Bus RB751V-40_SOD323-2
3V_EN
MAINPWON 1 2
PM_SLP_S3# 6 100 EC_RSMRST# 3V_EN <47,51>
<BOM Structure>
<6,10,47> PM_SLP_S3# PM_SLP_A# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXIOA03 EC_TBTA_RESET EC_RSMRST# <6,10>
14 101
3 <6,10> PM_SLP_A# GPIO07 GPXIOA04 VCIN1_ADP_PROCHOT EC_TBTA_RESET <42> 3V_EN_R 3
SPOK 15 102 1 <BOM 2Structure> R4901 1 <BOM 2Structure>
<51,54> SPOK AUDIO_MUTE# 16 GPIO08 VCIN1_ADP_PROCHOT/GPXIOA05 103 VCOUT1_PROCHOT VCIN1_ADP_PROCHOT <49>
R492 1M_0402_5%
<37> AUDIO_MUTE# NUM_LED# GPIO0A VCOUT1_PROCHOT#/GPXIOA06
17 104 MAINPWON 1K_0402_5%
EC_RST# <45> NUM_LED# WL_OFF# 18 GPIO0B VCOUT0_MAIN_PWR_ON/GPXIOA07 105 BKOFF# MAINPWON <49,51>
<38> WL_OFF# AC_PRESENT GPIO0C BKOFF#/GPXIOA08 COMM_LED# BKOFF# <28>
19 GPIO GPO 106
<10> AC_PRESENT USB1_CHARGE_2A# AC_PRESENT/GPIO0D GPXIOA09 3V_EN_R COMM_LED# <45>
25 107
.1U_0402_16V7K
1 <44> USB1_CHARGE_2A# FAN_SPEED1 PWM2/GPIO11 PCH_PWR_EN/GPXIOA10 USB2_CEN
28 108
<46> FAN_SPEED1 VR_ON FAN_SPEED1/GPIO14 PWR_VCCST_PG/GPXIOA11 USB2_CEN <44>
29 R4960
<47,55> VR_ON E51TXD_P80DATA 30 FANFB1/GPIO15 0_0402_5%
C5227
2 <38> E51TXD_P80DATA E51RXD_P80CLK 31 EC_TX/GPIO16 110 AC_IN 1 VCOUT1_PROCHOT
@ 08/10 add for abnormal shutdown <BOM 2Structure>
<38> E51RXD_P80CLK PCH_PWROK EC_RX/GPIO17 VCIN1_AC_IN/GPXIOD01 EC_ON AC_IN <50>
32 112
<10> PCH_PWROK PWR_SUSP_LED# 34 PCH_PWROK/GPIO18 EC_ON/GPXIOD02 114 EC_ON <51> DGPU_AC_DETECT SW_PROCHOT#
ON/OFF#
<45> PWR_SUSP_LED# VR_PWRGD 36 SUSP_LED#/GPIO19 ON/OFF#/GPXIOD03 115 LID_SW# ON/OFF# <6,45>
<55> VR_PWRGD NUM_LED#/GPIO1A GPI LID_SW#/GPXIOD04 LID_SW# <45>
116 SUSP#
SUSP#/GPXIOD05 SW_PROCHOT# SUSP# <13,40,44,47,52>
3
117
GPXIOD06 118 H_PECI_R 1 <BOM Structure>
2
PBTN_OUT# PECI/GPXIOD07 H_PECI <6>
122 R4944 43_0402_1%
<6,10> PBTN_OUT# PM_SLP_S4# 123 PBTN_OUT#/GPIO5D 124 VCOUT1_PROCHOT 2 5 VCOUT1_PROCHOT
<6,10,47> PM_SLP_S4# PM_SLP_S4#/GPIO5E V18R/VCC_IO2 +3VLP_EC Q2010A Q2010B
AGND
DMN66D0LDW-7_SOT363-6 DMN66D0LDW-7_SOT363-6
GND
GND
GND
GND
GND
4
@ @
2015/1/9 acer require:
KB9022QD_LQFP128_14X14
reserved protect circuit when
11
24
35
94
113
ECAGND 69
20mil
CO-LAY with KB9032QA (SA000080J00) adaptor 107% happen
BATT_TEMP
C4909 1<BOM 2Structure>
100P_0402_50V8J
For abnormal shutdown L4902 2 1
FBMA-L11-160808-800LMT_0603
D25 <BOM Structure>
RB751V-40_SOD323-2 R4936 1 @ 2 0_0402_5% VR_HOT#
1 2 EC_RSMRST# VR_HOT# <55>
4 SPOK 4
D26 H_PROCHOT# R4938 1 @ 2 0_0402_5% SW_PROCHOT#
<6,50> H_PROCHOT#
RB751V-40_SOD323-2
1 2 PCH_PWROK
D27
RB751V-40_SOD323-2 Security Classification Compal Secret Data Compal Electronics, Inc.
1 2 EC_VCCST_PG_R
Issued Date 2014/11/10 Deciphered Date 2016/11/10 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
EC ENE KB9022
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
LA-D301P 0.2
Date: Friday, December 18, 2015 Sheet 43 of 63
A B C D E
2 1
+3VS
1
R127
1M_0402_5% @
2
JDOCK3 1K_0402_5% DP_DOCK_CAD
1 2 SYS_IN# 2 1 R547
LAN_MIDI0+_DOCK 1 2
2
3 4
<35> LAN_MIDI0+_DOCK LAN_MIDI0-_DOCK 3 4 LAN_ACTIVITY#_DOCK +3V_LAN width=10 mil
5 6 R124
<35> LAN_MIDI0-_DOCK 7 5 6 8 LAN_LINK#_DOCK LAN_ACTIVITY#_DOCK <35>
7 8 LAN_LINK#_DOCK <35> 1M_0402_5%
LAN_MIDI1+_DOCK 9 10
<35> LAN_MIDI1+_DOCK LAN_MIDI1-_DOCK 11 9 10 12 DP_DOCK_SEL DP_DOCK_CAD <31>
<35> LAN_MIDI1-_DOCK 11 12 DP_DOCK_SEL <31>
1
13 14
LAN_MIDI2+_DOCK 15 13 14 16 USB1_CEN <43>
<35> LAN_MIDI2+_DOCK LAN_MIDI2-_DOCK 17 15 16 18 USB2_CEN <43>
<35> LAN_MIDI2-_DOCK 19 17 18 20 USB1_CHARGE_2A# <43>
LAN_MIDI3+_DOCK 21 19 20 22 USB2_CHARGE_2A# <43>
<35> LAN_MIDI3+_DOCK LAN_MIDI3-_DOCK 23 21 22 24 DOCK_CRT_DET# <30>
<35> LAN_MIDI3-_DOCK 25 23 24 26
27 25 26 28 CRT_DATA_DOCK
29 27 28 30 CRT_CLK_DOCK CRT_DATA_DOCK <30>
31 29 30 32 CRT_CLK_DOCK <30>
33 31 32 34 RED_DOCK
B 35 33 34 36 RED_DOCK <30> B
37 35 36 38 BLUE_DOCK
39 37 38 40 BLUE_DOCK <30>
41 39 40 42 GREEN_DOCK
43 41 42 44 GREEN_DOCK <30>
45 43 44 46 HSYNC_DOCK
47 45 46 48 VSYNC_DOCK HSYNC_DOCK <30>
49 47 48 50 VSYNC_DOCK <30>
51 49 50 52
53 51 52 54 DP_HPD_DOCK
55 53 54 56 DP_HPD_DOCK <31>
57 55 56 58 DP_DOCK_P0_R R649 1 EMI@ 2 0_0402_5% DP_DOCK_P0_C C290 2 1 0.1U_0402_16V7K DP_DOCK_P0
59 57 58 60 DP_DOCK_N0_R DP_DOCK_N0_C DP_DOCK_N0 DP_DOCK_P0 <31>
R650 1 EMI@ 2 0_0402_5% C291 2 1 0.1U_0402_16V7K
61 59 60 62 DP_DOCK_N0 <31>
63 61 62 64 DP_DOCK_P1_R R651 1 EMI@ 2 0_0402_5% DP_DOCK_P1_C C292 2 1 0.1U_0402_16V7K DP_DOCK_P1
65 63 64 66 DP_DOCK_N1_R DP_DOCK_N1_C DP_DOCK_N1 DP_DOCK_P1 <31>
R652 1 EMI@ 2 0_0402_5% C293 2 1 0.1U_0402_16V7K
<37> DOCK_CODEC_DET LINEIN_JD 67 65 66 68 DP_DOCK_N1 <31>
<37> LINEIN_JD MIC2_DOCK_DET 69 67 68 70 DP_DOCK_P2_R DP_DOCK_P2_C DP_DOCK_P2
R653 1 EMI@ 2 0_0402_5% C295 2 1 0.1U_0402_16V7K
<37> MIC2_DOCK_DET HP_DOCK_DET 71 69 70 72 DP_DOCK_N2_R DP_DOCK_N2_C DP_DOCK_N2 DP_DOCK_P2 <31>
R654 1 EMI@ 2 0_0402_5% C294 2 1 0.1U_0402_16V7K
<37> HP_DOCK_DET 73 71 72 74 DP_DOCK_N2 <31>
<37> POP 75 73 74 76 DP_DOCK_P3_R DP_DOCK_P3_C DP_DOCK_P3
R655 1 EMI@ 2 0_0402_5% C296 2 1 0.1U_0402_16V7K
LINE1_RIGHT 77 75 76 78 DP_DOCK_N3_R DP_DOCK_N3_C DP_DOCK_N3 DP_DOCK_P3 <31>
R656 1 EMI@ 2 0_0402_5% C297 2 1 0.1U_0402_16V7K
<37> LINE1_RIGHT LINE1_LEFT 79 77 78 80 DP_DOCK_N3 <31>
<37> LINE1_LEFT 81 79 80 82 DP_DOCK_AUXN
MIC2_DOCK_R 81 82 DP_DOCK_AUXP DP_DOCK_AUXN <31>
83 84
<37> MIC2_DOCK_R MIC2_DOCK_L 83 84 DP_DOCK_AUXP <31>
85 86
<37> MIC2_DOCK_L 87 85 86 88
HP_DOCK_R 89 87 88 90
<37> HP_DOCK_R HP_DOCK_L 91 89 90 92
<37> HP_DOCK_L 93 91 92 94
95 93 94 96
97 95 96 98 ON/OFFBTN#
+MIC2_VREFO 97 98 DET_SIG# DET_SIG#_R ON/OFFBTN# <45>
99 100 0_0402_5% 2 @ 1 R546
101 99 100 102 DOCK_SPOK# DET_SIG#_R <6,35>
103 101 102 104 USB_PWR_EN#
105 103 104 106 SUSP# USB_PWR_EN# <39,43> SUSP#
107 105 106 108 PWR_LED# SUSP# <13,40,43,47,52>
109 107 108 110 PWR_LED# <43,45>
111 109 110 112 USB_CHARGE_CB0 <39,43>
1U_0402_6.3V6K
C814
111 112 SELCDP <39,43> 1
113 114
<12> PCH_USB3_TX3_P 113 114
115 116
<12> PCH_USB3_TX3_N 115 116
117 118
119 117 118 120 2
121 119 120 122
<12> PCH_USB3_RX3_N 123 121 122 124
<12> PCH_USB3_RX3_P 125 123 124 126
USB20_P3_L 127 125 126 128
USB20_N3_L 129 127 128 130
131 129 130 132
133 131 132 134
135 133 134 136
137 135 136 138
139 137 138 140
141 139 140 142
143 141 142 144
USB20_N3 143 144
<12> USB20_N3
145 149
MCF12102G900-T_4P 146 GND1 PWR2 150 MB_VIN
2 3 USB20_N3_L 147 PWR1 PWR2 151
2 3 PWR1 PWR2 1
148 152 C5245
L38 EMI@ PWR1 GND2 EMI@
1 4 USB20_P3_L 153 159 .1U_0402_16V7K
1 4 154 Shield_G Shield_G 160 2
155 Shield_G Shield_G 161
A 156 Shield_G Shield_G 162 USB_PWR_EN# USB_CHARGE_CB0 SELCDP A
USB20_P3 157 Shield_G Shield_G 163
<12> USB20_P3 Shield_G Shield_G
158 164 1 1 1
Shield_G Shield_G C5244 C5243 C5242
EMI@ EMI@ EMI@
JAE_WD2F144WB5R400 .1U_0402_16V7K .1U_0402_16V7K .1U_0402_16V7K
CONN@ 2 2 2
SP0300013A0
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2014/02/14 Deciphered Date 2015/02/14 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
E Series Dcok CONN.
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
LA-D301P 1A
Date: Thursday, December 17, 2015 Sheet 44 of 63
2 1
A B C D E
TPM
+3VALW R742 +3VALW_TPM +3VS R741 +3VS_TPM KB
0_0603_5%
1 2
0_0603_5%
1 2 Conn. KB Backlight Conn
JKB1
28
10U_0603_6.3V6M
0.1U_0402_16V4Z
10U_0603_6.3V6M
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1 1 1 1 1 1 GND2 27
26 GND1
C889
C890
C891
C892
C893
C894
KSO0
KSI[0..7] KSO1 25 26
2 2 2 2 2 2 KSI[0..7] <43> 24 25 +5VALW
KSO2
KSO[0..17] KSO3 23 24
KSO[0..17] <43> 22 23
KSO4
KSO5 21 22
1 21 1
1
near pin5 KSO6 20 +5VS CONN@
near pin10, 19, 24 +3VS +3VS KSO7 19 20 ACES_50504-0040N-001
KSO8 18 19 R511 3 1 +5VS_BL 4 6
D
KSO9 17 18 100K_0402_5% 3 4 G2 5
1 1 17
C5235 C5236 KSO10 16 Q23 DMG2301U-7_SOT23-3 2 3 G1
16 1 2
2
68P_0402_50V8J 68P_0402_50V8J KSO11 15
G
15 1
2
U67 RF@ RF@ KSO12 14
5 2 2 KSO13 13 14 JBL1
VSB +3VALW_TPM 13
1 10 KSO14 12
2 GPIO0/XOR_OUT VDD 19 KSO15 11 12
GPIO1 VDD +3VS_TPM 11
GPIO3/BADD with Internal PH (default) 6 24 +3VS closed JKB1 need to place 2 68p CAPs KSO16 10
0_0402_5% 1 @ 2 R739 TPM_BADD 9 GPIO2/GPX VDD KSO17 9 10 KB_BL_EN#
PM_CLKRUN# 15 GPIO3/BADD 8 KSI0 8 9
<8> PM_CLKRUN# GPIO4/CLKRUN# TEST 7 8
KSI1
LPC_AD0_R 26 KSI2 6 7
<8,43> LPC_AD0_R LPC_AD1_R LAD0/MISO 6 D
1
23 KSI3 5
<8,43> LPC_AD1_R LPC_AD2_R LAD1/MOSI 5
20 3 KSI4 4 2 Q24
<8,43> LPC_AD2_R LPC_AD3_R LAD2/SPI_IRQ# NC 4 <43> KB_BL_EN
<8,43> LPC_AD3_R 17 12 KSI5 3 G 2N7002E_SOT23-3
LAD3 NC 13 KSI6 2 3
S
NC 2
3
14 KSI7 1
LPCPD# had internal PH 28 NC 1
CK_LPC_TPM LPCPD#
<8> CK_LPC_TPM LPC_FRAME#
21
LCLK/SCLK BADD SELECTION ACES_50565-0260N-001_26P
22 CONN@
<8,43> LPC_FRAME# PLT_RST# 16 LRFAME#/SCS# 4
<10,21,34,40,43,45> PLT_RST# LRSET#/SPI_RST# GND
SP01001IE00
TPM_SERIRQ
<8,43> TPM_SERIRQ 27
SERIRQ GND
11 0 EEh - EFh
7 18
PP GND 25
GND
*1 7Eh - 7Fh
NPCT650AA0WX_TSSOP28
SA00007IO00
@EMC@ @EMC@
CK_LPC_TPM R740 1 2 33_0402_5% C886 1 2 22P_0402_50V8J
2 2
+3VS
ON/OFF BTN Lid Switch/B TP Conn.
1 1
(Hall Effect Switch) C5237
68P_0402_50V8J
C480
0.1U_0402_16V4Z
+3VLP RF@ RF@
2 2 +3VS
JTP1
2
4 6
R513 3 4 G2 5
<43> TP_DATA 2 3 G1
100K_0402_5%
<43> TP_CLK 2
1
JLID1 1
Test Only
1
SW1 @ D28 1 ACES_50504-0040N-001
SMT1-05-A_4P 2 2 1 CONN@
1 3 1 ON/OFF# <6,43> 3 2 5
ON/OFFBTN#
<43> LID_SW# 3 G1
3 +3VLP 4 6
2 4 4 G2
SP01000Z300
BAV70W_SOT323-3 ACES_50504-0040N-001
CONN@
6
5
@
0_0402_5% 2 @ 1 R548 SP01000Z300
07/26 Add
+3VALW +3VALW
3
CardReader Board FP Board Function Board Reserve for Draco_SL 3
1
+3VS
R5254 R5255
1 470K_0402_5% 470K_0402_5%
C5238 Draco@ Draco@
68P_0402_50V8J +3VALW
MUTE_LED#
2
RF@
2
JREAD1 +3VS COMM_LED# JFUN1
1 C5239 1
PCIE_CTX_C_DRX_P11 2 1 0.1U_0402_16V7K PWR_LED# 2 1
<12> PCIE_CTX_C_DRX_P11 PCIE_CTX_C_DRX_N11 3 2 2 1 <43,44,45> PWR_LED# MUTE_LED# 3 2
<12> PCIE_CTX_C_DRX_N11 3 <43> MUTE_LED# PKEY_LED# 3
4 JFP1 4
CLK_PCIE_CARD 5 4 1 <43> PKEY_LED# COMM_LED# 5 4
EMI@
<10> CLK_PCIE_CARD CLK_PCIE_CARD# 5 USB20_N8 1 <43> COMM_LED# NUM_LED# 5
6 2 6
<10> CLK_PCIE_CARD# 6 <12> USB20_N8 USB20_P8 2 <43> NUM_LED# CAP_LED# 6
7 3 5 7
PCIE_CRX_DTX_P11 8 7 <12> USB20_P8 4 3 G1 6 <43> CAP_LED# 8 7
<12> PCIE_CRX_DTX_P11 PCIE_CRX_DTX_N11 8 4 G2 8
9 KSO0 9
<12> PCIE_CRX_DTX_N11 10 9 <43> KSO0 10 9
+5VALW ACES_50504-0040N-001 KSI3
CLKREQ_PCIE#4 10 <43> KSI3 10
11 CONN@ KSI4 11
<10> CLKREQ_PCIE#4 PLT_RST# 11 <43> KSI4 11
12 KSI5 12
<10,21,34,40,43,45> PLT_RST# 13 12 <43> KSI5 13 12
D22 @ESD@ ON/OFFBTN#
<43,44,45> PWR_LED# 13 USB20_N8 <44> ON/OFFBTN# 13
14 3 6 14
<43> PWR_SUSP_LED# 15 14 I/O2 I/O4 15 14
<43> BATT_BLUE_LED# BATT_AMB_LED# 15 15
16 16
<43> BATT_AMB_LED# 16 PWR_LED# 16
17 19 0.1U_0402_16V4Z C820 1 2 ESD@
<12> PCH_SATALED# 18 17 G1 20 2 5 1 2 MUTE_LED# 17
+3VS +3VS 0.1U_0402_16V4Z C821 ESD@
18 G2 GND VDD 0.1U_0402_16V4Z C822 1 2 ESD@ PKEY_LED# 18 GND
ACES_50505-0184N-001 0.1U_0402_16V4Z C823 1 2 ESD@ COMM_LED# GND
CONN@ 0.1U_0402_16V4Z C824 1 2 ESD@ NUM_LED# ACES_51524-0160N-001
BATT_AMB_LED# USB20_P8 1 4 0.1U_0402_16V4Z C825 1 2 ESD@ CAP_LED# CONN@
I/O1 I/O3
1
C831 AZC099-04S.R7G_SOT23-6 0.1U_0402_16V4Z C826 1 2 @ KSO0 SP01001C600
0.1U_0402_16V4Z 0.1U_0402_16V4Z C827 1 2 @ KSI3
ESD@ 0.1U_0402_16V4Z C828 1 2 @ KSI4 07/26 Add
2 0.1U_0402_16V4Z C829 1 2 @ KSI5
0.1U_0402_16V4Z C830 1 2 ESD@ ON/OFFBTN#
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2014/02/14 Deciphered Date 2015/02/14 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
KB/TP/LID/TPM/FUN/FP/CARD
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
LA-D301P 1A
Date: Thursday, December 17, 2015 Sheet 45 of 63
A B C D E
FAN Conn WIFI Stand off 3G Stand off SSD Stand off FAN Stand off
20mil R514
1
@ 0_0603_5%
2 +5VS_FAN
C895
1 2
H1 H2 H3 H4 H5
+5VS H_3P3 H_3P3 H_3P3 H_3P8 H_3P8
2
4.7U_0603_6.3V6K
R761
1
0_0603_5% U68
@ 1 8
2 EN GND 7
1 +VCC_FAN1 3 VIN GND 6 @ @ @ @ @
FAN_VSET 4 VOUT GND 5
<43> FAN_VSET VSET GND
NCT3942S SOP 8P
SA00005CA00
+3VS H8 H11 H15 H16 H17
H_2P5 H_2P5 H_3P0 H_2P5 H_2P5
1
R515
1
10K_0402_5%
CONN@
ACES_88266-04001_4P
@ @ @ @ @
2
+VCC_FAN1 4 6
FAN_SPEED1 3 4 G2 5
<43> FAN_SPEED1 FAN_PWM 2 3 G1 H18 H19 H20 H21 H22 H23 H24
<43> FAN_PWM
1 2 H_3P0N H_3P0N H_4P0 H_4P0 H_4P0 H_4P0 H_4P0 H25 H26
1 H_5P0X3P0N H_3P5X3P0N
JFAN1
SP02000K200
1
+VCC_FAN1 10U_0805_10V4Z 1 2 C481
@ @ @ @ @ @ @ @ @
0.1U_0402_16V4Z 1 2 C896
locate MB
+RTCVCC +3VLP +3VLP
EC_RST# <43>
1
DU2 R415
BAV70W_SOT323-3 10K_0402_5%
6
2
DMN66D0LDW-7_SOT363-6
1
2
2 Q52A
1
3
1
0.1U_0402_16V4Z
10K_0402_5%
C370
R525
<49> BI
5
1
2
Q22 Q52B
D
4
1
2N7002E_SOT23-3 DMN66D0LDW-7_SOT363-6
2
SW2
G FD1 FD2
2
S 1 3 1
3
R527 C369
1M_0402_5% 0.1U_0402_16V4Z 4 2 @ @
1
2 SN100009500 FIDUCIAL_C40M80 FIDUCIAL_C40M80
1
DTSJ-62N-Q-T-R_4P
FD3 FD4
@ @
1
FIDUCIAL_C40M80 FIDUCIAL_C40M80
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2014/02/14 Deciphered Date 2015/02/14 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
FAN & Screw
Document Number Re v
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D301P
Date: Thursday, December 17, 2015 Sheet 46 of 63
A B C D E
DC & VGA Interface For Power Of f Sequence
+3VALW
+1.2V_VDDQ +5VALW Q2014B <BOM Structure>
DMN66D0LDW-7_SOT363-6
1
U5008 @ J36
+3VS_OUT 1
2
+3VALW 1 14 2 +3VS R1000 4 3
VIN1 VOUT1 1 2 EC_VCCST_PG_R <10,43>
2
R927 2 13 R573 R554 100K_0402_5%
0_0402_5% VIN1 VOUT1 JUMP_43X118 470_0603_5% 100K_0402_5% <BOM Structure> For tCPU28 1us(max)
SUSP# 1 @ 2 3VS_ON 3 12 1 2 @ @
ON1 CT1
5
C976 1000P_0402_50V7K PM_SLP_S3
1
C980 1 2 +5VALW 4 11
VBIAS GND
1
+1.2V_VDDQ_R
5
1
@ .1U_0402_16V7K SYSON# Q2014A 1
R926 2 @ 1 0_0402_5% 5VS_ON 5 10 1 2 DMN66D0LDW-7_SOT363-6
ON2 CT2
3
C967 1000P_0402_50V7K <BOM Structure> 4 3
VR_ON <43,55>
+5VALW 6 9 @ J37 2
VIN2 VOUT2 +5VS_OUT 1 <6,10,43> PM_SLP_S3#
C979 1 2 7 8 2 +5VS Q2013B <BOM Structure>
For tCPU17 1us(max)
@ .1U_0402_16V7K VIN2 VOUT2 1 2 SYSON# 2 5 SYSON DMN66D0LDW-7_SOT363-6
SYSON <13,39,43,52>
1
15 JUMP_43X118 Q40A Q40B
GPAD DMN66D0LDW-7_SOT363-6 DMN66D0LDW-7_SOT363-6
4
EM5209VF_DFN14_2X3 @ @
2
1 6 SUSP#
For tCPU18 1us(max)
+3VALW Q2013A <BOM Structure>
DMN66D0LDW-7_SOT363-6
+5VALW +0.6VS_VTT
1
U5009 C5250
1
+3VALWP 1 14 4.7U_0603_6.3V6K
R5257 2 VIN1 VOUT1 13 @ R552 R566 +3VALW
0_0402_5% VIN1 VOUT1 2 100K_0402_5% @ @ 470_0603_5% Q2016B <BOM Structure>
2 @ 1 3V_EN_R1 3 12 1 2 DMN66D0LDW-7_SOT363-6
<43,51> 3V_EN ON1 CT1
1
C5248 @ 1000P_0402_50V7K
+0.675VS_VTT_R
2
C5246 1 2 +3VALWP 4 11 R1002 4 3 SYSON
@ .1U_0402_16V7K VBIAS GND 100K_0402_5%
SUSP For tPLT15 1us(max)
5 10 <BOM Structure>
ON2 CT2
5
6 9 PM_SLP_S4
7 VIN2 VOUT2 8
VIN2 VOUT2
6
+3VS +5VALW 2 5 SUSP Q2016A
<13,40,43,44,52> SUSP#
15 Q2006B DMN66D0LDW-7_SOT363-6
GPAD
1
Q2006A @ <BOM Structure>
4
2
EM5209VF_DFN14_2X3 R555 @ DMN66D0LDW-7_SOT363-6 2
<6,10,43> PM_SLP_S4#
2
R5259 R5258 @ 10K_0402_5%
2 470_0603_5% 100K_0402_5% @ 2
1
DMN66D0LDW-7_SOT363-6
2
1
3VS_R 3VS_ON#
3
3VS_ON# 5 2 SUSP#
SUSP#
Q2021B Q2021A
DMN66D0LDW-7_SOT363-6 DMN66D0LDW-7_SOT363-6
4
+5VALW +1.05VSDGPU
2
+ VS to + VSDGPU AON for GPU
+3VALW to +3VM for Intel AMT R1001
100K_0402_5%
R574
47_0603_5%
VGA@ VGA@
20mil(68mA)
1
+3VSDGPU_AON
DGPU_PWROK# +1.05VSDGPU_R
3 +3VS 3
6
U12 100mil(1.5A)
5 1 +3VM +3VALW
IN OUT R645 @ VGA@ VGA@
2 1 2 DGPU_PWROK 5 2 DGPU_PWROK#
GND 2 <10,21,59,60> DGPU_PWROK
Q2008A
DGPU_PWR_EN 4 3 C621 0_0603_5% Q2008B DMN66D0LDW-7_SOT363-6
EN OC 2
1
2 VGA@ DMN66D0LDW-7_SOT363-6
C620 SY6288C20AAC_SOT23-5 1 4.7U_0603_6.3V6K C811
4.7U_0603_6.3V6K VGA@ VPRO@
VGA@ 1 4.7U_0603_6.3V6K
1
+5VALW +1.5VSDGPU
+5VALW +VGA_CORE
2
+ VS to + VSDGPU MAIN for GC6- .0 R998 R571
2
100K_0402_5% 47_0603_5%
+3VSDGPU_MAIN R994 R572 @ @
+3VSDGPU_AON 100K_0402_5% 47_0603_5%
1
R213 @ @
0_0805_5% 1.5VS_DGPU_PWR_EN# +1.5VSDGPU_R
1
1 NGC6@ 2 DGPU_PWR_EN# +VGA_CORE_R
6
+3VS
3
U14
5 1 1.5VS_DGPU_PWR_EN 5 2 1.5VS_DGPU_PWR_EN#
IN OUT <21,58> 1.5VS_DGPU_PWR_EN
100mil(1.5A) Q45A
2 DGPU_PWR_EN#
2
2 2 2 5 Q45B DMN66D0LDW-7_SOT363-6
GND <11> DGPU_PWR_EN
1
4 C624 Q2007A R999 DMN66D0LDW-7_SOT363-6 @ 4
GC6@ 4 3 C625 Q2007B DMN66D0LDW-7_SOT363-6 100K_0402_5% @
EN OC
4
1
2
1U_0402_6.3V6K GC6@ DMN66D0LDW-7_SOT363-6 @ @
1 SY6288C20AAC_SOT23-5 1 4.7U_0603_6.3V6K @
1
GC6@ R996
100K_0402_5%
@
<21,60> 3VSDGPU_MAIN_EN
1
3VSDGPU_MAIN_EN From GPU
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2014/11/10 Deciphered Date 2016/11/10 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC Interface
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D301P
Date: Friday, December 18, 2015 Sheet 47 of 63
A B C D E
A B C D E
2015/7/8
PD101 and PD102 SCS00002F00 change to SCS00002M00
+19V_VIN
PD101
2
1 1 1
MB_VIN 3
@ PJP101 PDS5100H-13_POWERDI5-3
ACES_87302-0401-003
6 EMI@ PL101 PD102
GND 5 FBMA-L11-322513-151LMA50T_1210 2
GND 4 DC_IN_S1 1 2 DC_IN_S2 1
4 3 3
3 2
2 1 PDS5100H-13_POWERDI5-3
1
1
EMI@ PC101 EMI@ PC102
1000P_0603_50V7K 1000P_0603_50V7K
2
EMI
2 2
1 2
PR101
+3VLP 0_0402_5% +CHGRTC
@
3 3
- @ PBJ101
ML1220T13RE + PR102
560_0603_5%
PR103
560_0603_5%
2 1 +RTC 1 2 +RTC_R 1 2
+RTCBATT
4 4
Security Classification
2014/11/10
Compal Secret Data
2016/11/10 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR DCIN / Pre-charge
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
B4DBU M/B LA-D301P 0.1
Date: Thursday, December 17, 2015 Sheet 48 of 63
A B C D E
A B C D E
@ PJP201
ACES_50290-0100N
10 PR202
9 100_0402_1% PR203 +3VLP
8 EC_SMDA 1 2 100_0402_1%
7 EC_SMCA EC_SMB_DA1 <42,43,50> 1 2
6 EC_SMB_CK1 <42,43,50>
TH
1 5 BI+ 1
4 PR217
0.1U_0603_25V7K
3
1
200K_0402_1%
2 2 1
@ PC205
1 +3VLP
1
10K_0402_1%
@ PR215
2
1
+VMB
1K_0402_1%
100K_0402_1%
10K_0402_1%
@ PR214
1
PR212
1
PR213
EMI@ PL201
2
FBMA-L11-322513-151LMA50T_1210
2
1 2
@
@ PU201
BATT+
2
1 8 G718_TMSNS1
BATT_TEMP <43,50> VCC TMSNS1
2
1
G718_RHYST1
1
1
PR201 2 7 2 1
EMI@ PC201 EMI@ PC206 0_0402_5% GND RHYST1
1000P_0402_50V7K 0.01U_0402_25V7K MAINPWON 3 6 G718_TMSNS2 @ PR216
<43,51> MAINPWON OT1 TMSNS2
2
1
47K_0402_1%
2
4 5
@ PH202
100K_0402_1%_NCP15WF104F03RC
OT2 RHYST2
EMI @ G718TM1U_SOT23-8
2
(Common Part)
SL200002H00
BI <46>
2 2
PH1 under CPU botten side :
CPU thermal protection at 92 +-3 degree C
Recovery at 56 +-3 degree C
+3VLP_ECA
1
3 3
PR204
16.9K_0402_1%
PR206
19.1K_0402_1%
2
1 2
2015/07/09 update ADP_I <43,50> VCIN0_PH <43>
For KB9022
sense 20mΩ Active Recovery (Common Part)
SL200002H00
PC203 must close to EC pin
1
VCIN1_ADP_PROCHOT <43>
2
65W PR206 PH201
100K_0402_1%_NCP15WF104F03RC
@ PC203
0.1U_0402_25V6
19.1K ohm
1
84.5W,0.61V 65W,0.47V
1
PR208
SD034191280
2
10K_0402_1% T202@
2
T201@
ECAGND <43>
T202 T201 must close to PH201
4 4
Security Classification
2014/11/10
Compal Secret Data
2016/11/10 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-BATTERY CONN/OTP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
B4DBU M/B LA-D301P 0.1
Date: Thursday, December 17, 2015 Sheet 49 of 63
A B C D E
A B C D E
PR302
D PQ302 BATT+_CHG
1
1M_0402_1% PQ301
2 1Inverse_GATE 2 2N7002KW_SOT323-3
2014/9/25 +19VB AON7506_DFN33-8-5
G 1
PR303 S PR304 10m ohm chang -->20m ohm 2
3
3M_0402_5% 5 3
2 1
+19V_P1 +19V_P2 SD00000S120
PQ303 PQ304
MDU1512RH_POWERDFN56-8-5 AON7506_DFN33-8-5 PR304 +19V_CHG
4
1 1 0.02_1206_1% @ PJ301
2 2 JUMP_43X79
5 3 3 5 1 4 1 2
+19V_VIN 1 2 PC302
1 BATFET_GATE
2 3ACN
ACP 0.022U_0603_25V7K
0.047U_0603_25V7M
1 1
4
1 2
ACFET_GATE
RBFET_GATE
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
1
10U_0805_25V6K
PC303
68P_0402_50V8J
10_0402_1%
2
1
@ PC304
@EMI@ PC306
EMI@ PC307
PC308
PC309
1000P_0603_50V7
@PC305
PC312
PR307
4.02K_0402_1%
2
1
2
PC310 PC311
PC301
4.7_0603_1%
1
0.1U_0603_25V7K 0.1U_0402_25V6 0.01U_0402_25V7K
PR301
PR306
2 1 1 2 1 2
2
2
1
2
BATDRV_CHGR
2014/9/30
PC301 change to SE025102K80 PR308
4.02K_0402_1% BATSRC_CHGR
1 2 ACDRV_CHGR
PR305
2014/9/30 4.02K_0402_1%
PC301 change to SE025102K81 2 1 CMSRC_CHGR
+19V_VIN
PD301 @ PC313
S SCH DIO BAS40CW SOT-323 1000P_0402_50V7K
3 PR312 10_1206_5% 1 2 2015/7/27
+19V_VIN 1 VCC_CHGR_R 2 1 PC316 change to SE000006S80
422K_0402_1%
ACDRV_CHGR
1
+19VB 2
PC314 1U_0603_25V6K +6V_CHG_REGN
PR311
2 1 PC316 PQ305
MDV1528URH_PDFN33-8-5
5
2 ACDET PU301 2.2U_0603_16V6K 2
2
1 2
ACDRV
ACP
ACN
VCC_CHGR 28
VCC PR314
2200P_0402_25V7K
66.5K_0402_1%
CMSRC_CHGR 3
1
24 0_0603_5%
CMSRC REGN 2DH_CHGR_R 4
1
PC317 1
PR313
6 PR316 0.047U_0603_25V7M
PC315
ACDET 25 BST_CHGR 1 2BST_CHGR_R 1 2
BTST
2
1 2 EC_SMB_DA1_CHGR 11
<42,43,49> EC_SMB_DA1 PR317
SDA
0_0603_5% (Common Part)
2
0_0402_5%
Choke 2.2uH SH00000YV00 BATT+
3
2
1
1 2
PR315 EC_SMB_CK1_CHGR 12 26 UG_CHGR PR318
<42,43,49> EC_SMB_CK1 @ SCL HIDRV @
0_0402_5% PL301 0.01_1206_1%
ACPRN_CHGR 5 2.2UH_PCMB063T-2R2MS_8A_20%
<43,49> ADP_I @ ACOK
PC318 100P_0603_50V8 27 LX_CHGR 1 2 1 4
1 2 1 2
PR333 ADPI_CHGR 7 PHASE
0_0402_5% IADP 2 3
IDCHG_CHGR 23 LG_CHGR
1
1 2 8
4.7_1206_5%
@ IDCHG LODRV
MDV1527URH_POWERDFN33-8-5
5
@ PR331 PR320 @ 316K_0402_1%
@
@EMI@ PR319
PC319 100P_0603_50V8 1 2PMON_CHGR 9 1 2
10U_0805_25V6K
10U_0805_25V6K
<55> PSYS_MON PMON +5VALW
PC327 0_0402_5% 10 22 PR332 316K_0402_1% SRP SRN
/PROCHOT GND
1SNUB_CHGR 2
1
1 2 1 2
PC320
PC321
+3VLP 4
0.1U_0402_25V6 PR321 PR322 100K_0402_1%
@
2
0_0402_5% 13 21 ILIM_CHGR 1 2
1 2PROCHOT#_CHGR CMPIN ILIM PR323
680P_0603_50V7K
<6,43> H_PROCHOT# 14 10_0402_1%
CMPOUT
3
2
1
20 SRP_CHGR 1 2
@EMI@ PC323
SRP
PQ306
15 19 SRN_CHGR 1 2
<43,49> BATT_TEMP /BATPRES SRN
2
3 PR324 3
16 18 BATDRV_CHGR 10_0402_1% PC324
/TB_STAT BATDRV 0.1U_0402_25V6
29 17 BATSRC_CHGR 1 2
PWPD BATSRC
BQ24780RUYR_WQFN28_4X4
0.1U_0402_25V6
0.1U_0402_25V6
PC326
1
PC325
2
2
+6V_CHG_REGN
1
PR325
10K_0402_1%
PR326
10K_0402_1%
2
1 2 ACPRN_CHGR
<43> AC_IN
1
4 PR327 4
12K_0402_1%
2
Security Classification
2014/11/10
Compal Secret Data
2016/11/10 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BQ24780
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
B4DBU M/B LA-D301P 0.1
Date: Thursday, December 17, 2015 Sheet 50 of 56
A B C D E
A B C D E
PR402
499K_0402_1%
ENLDO_3V5V 1 2
+19VB
1
150K_0402_1%
PR404
EN1 and EN2 dont't floating
2
PU401
1 @ PJ403 SY8286BRAC_QFN20_3X3 PC401 1
JUMP_43X79 0.1U_0603_25V7K
1 2 +19VB_3V BST_3V 1 2BST_3V_R
PR401 1 2
+19VB 1 2
2200P_0402_50V7K
0_0603_5% 5*5*3 Common part SH000016800
10U_0805_25V6K
@EMI@ PC403
0.1U_0402_25V6
@
1
EMI@ PC404
PC405
PL402
BS
IN
IN
IN
IN
1.5UH_PCMB053T-1R5MS_6A_20%
2
LX_3V6 20 LX_3V 1 2
LX LX +3VALWP
7 19
4.7_1206_5%
@EMI@ PR405
GND LX
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
1
1
8 18
+3VALWP GND GND
PC407
PC408
PC409
PC410
9 17
PG LDO +3VLP
2
3V_SN 2
1
10 16
NC NC
1
Check pull up resistor of SPOK at HW side PC411
OUT
EN2
EN1
21
NC
4.7U_0603_6.3V6M
FF
GND
2
PR406
680P_0603_50V7K
100K_0402_5%
11
12
13
14
15
1
3.3V LDO 150mA~300mA
@EMI@ PC412
2
Vout is 3.234V~3.366V
<43,54> SPOK
2
ENLDO_3V5V PC402 PR403
Ipeak=7A
PR414 0_0402_5%
+3VALWP_EN
1000P_0402_25V8J
3V_FB
1K_0402_5% Imax=4.9A
1 2 1 2 3V_FB_C 1 2
<43,47> 3V_EN Iocp=10A
2 2
@ PR415 0_0402_5%
5V_EN 1 2
@ PJ404 +19VB_5V PC418
JUMP_43X79 0.1U_0603_25V7K
1 2 +19VB_5V BST_5V1 2 BST_5V_R 1
PR408 2
+19VB 1 2 0_0603_5%
@
1
2200P_0402_50V7K
5*5*3 Common part SH000016800
10U_0805_25V6K
10U_0805_25V6K
PU402
SY8288CRAC_QFN20_3X3
BS
IN
IN
IN
IN
0.1U_0402_25V6
LX_5V 6
1
20
PC414
PC415
EMI@ PC416
@EMI@ PC417
PL404
LX LX 1.5UH_PCMB053T-1R5MS_6A_20%
7 19 LX_5V 1 2
GND LX +5VALWP
2
8 18
4.7_1206_5%
@EMI@ PR409
@
GND GND
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
PC419 4.7U_0603_6.3V6M
VCC_5V
1
9 17 1 2
PG VCC
PC420
PC421
PC422
PC423
PC424
PC425
1 PG_5V
3 10 16 3
NC NC
2
OUT
LDO
2
EN2
EN1
21 @ @
FF
GND
5V_SN
PR413 @
11
12
13
14
15
0_0402_5% 5V LDO 150mA~300mA
680P_0603_50V7K
@EMI@ PC426
4.7U_0603_6.3V6M
VL
2
SPOK
1
1
PC427
ENLDO_3V5V
2
2
5V_EN
Vout is 4.998V~5.202V
PC413 PR407
1000P_0402_25V8J 1K_0402_5%
Ipeak=7A
5V_FB 1 2 5V_FB_C1 2 Imax=4.9A
Iocp=10A
@ PJ401
+3VALWP 1 2 +3VALW
PR410 1 2
2.2K_0402_5% JUMP_43X118
1 2
<43> EC_ON
@ PR411
4 0_0402_5% 4
1 2 @ PJ402
<43,49> MAINPWON +5VALWP 1
1 2
2 +5VALW
5V_EN JUMP_43X118
1M_0402_1%
4.7U_0402_6.3V6M
1
Security Classification Compal Secret Data Compal Electronics, Inc.
1
PR412
PC428
Issued Date 2014/11/10 Deciphered Date 2016/11/10 Title
PWR-3.3VALWP/5VALWP
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
2
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
B4DBU M/B LA-D301P 0.1
Date: Thursday, December 17, 2015 Sheet 51 of 56
A B C D E
A B C D E
Module model information
RT8207M_V1.mdd For Single layer
RT8207M_V2.mdd For Dual layer
1 1
Pin19 need pull separate from +1.2VP.
+19VB_1.2VP If you have +1.2V and +0.6V sequence question, 0.6Volt +/- 5%
@ PJ506 you can change from +1.2VP to +1.2VS. TDC 0.7A
JUMP_43X79
1 2 +19VB_1.2VP PR502 Peak Current 1A
+19VB 1 2 2.2_0603_5%
0.1U_0402_25V6
BST_1.2VP_R 1 2 BST_1.2VP
+1.2VP
10U_0805_25V6K
10U_0805_25V6K
1
@EMI@ PC502
2200P_0402_50V7K
1
PC504
PC505
1
EMI@ PC503
UG_1.2VP
2
+0.6VSP
0.1U_0603_25V7K
2
LX_1.2VP
PC506
10U_0603_6.3V6M
10U_0603_6.3V6M
5
1
PC507
PC508
16
17
18
19
20
2
PU501
2
Change PR503 to 17.8K ohm
BOOT
VTT
VLDOIN
PHASE
UGATE
4 21
OCP setting 9.6A PAD
Choke 1.5uH SH000016700 LG_1.2VP 15 1
Common Part 7*7*3 PQ503 LGATE VTTGND
Update Pc510 change MDV1528URH_PDFN33-8-5
1
2
3
14 2
to Common Part PL502 PR503 PGND VTTSNS
SF000006S00 20141227 1.5UH_PCMC063T-1R5MN_9A_20% 17.8K_0402_1%
1 2 LX_1.2VP 1 2 CS_1.2VP 13 3
+1.2VP PC509 CS RT8207MZQW_WQFN20_3X3 GND
5
1U_0402_10V6K
1 2VDDP_1.2VP 12 4 VTTREF_1.2VP
@EMI@ PR504 PR505 VDDP VTTREF
1
330U_2.5V_M
4.7_1206_5% 5.1_0603_5%
+ VDD_1.2VP
+5VALW 1 2 11 5
+1.2VP
PC510
VDD VDDQ
1SNB_1.2VP 2
1
4 PC516
PGOOD
1U_0402_10V6K
TON
2
1
0.033U_0402_16V7K
2.2_0402_1%
FB
S5
S3
2
PQ502
SI7716ADN-T1-GE3_POWERPAK8-5
PC517
1
2
3
10
6
PR511
@EMI@ PC518
FB_1.2VP
680P_0402_50V7K
TON_1.2VP
2
2
2
EN_1.2VP
PR506
EN_0.6VSP
change PQ502 form 7506 6.19K_0402_1%
+5VALW PR507 1 2
to 7716, 20150108 887K_0402_1% +1.2VP
+19VB_1.2VP 1 2
1
Vout=0.75V* (1+Rup/Rdown)
PR508 =0.75*(1+(6.19/10))
10K_0402_1%
1 @ PR501
2 =1.2V
<13,39,43,47,52> SYSON
2
0_0402_5%
1
@ PC501
0.1U_0402_10V7K
2
@ PR509
0_0402_5% @ PJ501
<13,40,43,44,47> SUSP# 1 2 JUMP_43X118
1 2 +1.2V_VDDQ
+1.2VP 1 2
@ PJ505
<7> SM_PG_CTRL 1 @ PR510
2 JUMP_43X118
0_0402_5% 1 2 +1.2V_VDDQ
+1.2VP 1 2
1
MOSFET: 3x3 DFN @ PC519
H/S Rds(on): 23.2mohm(Typ), 27.8mohm(Max) 0.1U_0402_10V7K @ PJ502
Idsm: 10.1A@Ta=25C, 8.1A@Ta=70C
2
Mode Level +0.675VSP VTTREF_1.35V JUMP_43X39
+0.6VSP 1 2
S5 L off off 1 2 +0.6VS_VTT
S3 L off on L/S Rds(on): 13.5mohm(Typ), 16.5mohm(Max)
S0 H on on Idsm: 12A@Ta=25C, 9.5A@Ta=70C
Note: S3 - sleep ; S5 - power off Choke: 7x7x3
Rdc=14mohm(Typ), 15mohm(Max)
EN_2.5VP
Switching Frequency: 285kHz 1 PR512
2
SYSON <13,39,43,47,52>
0_0402_5%
Ipeak=8A
@
0.1U_0402_16V7K
Iocp~9.6A
1
3 3
1
OVP: 110%~120% PR513
PC520
VFB=0.75V, Vout=1.2V 1M_0402_5%
MOSFET footprint: SIS412DN
2
2
PU502
9 3.8x3.8xH1.8
1 PGND 8
FB SGND DCR: 20~25mohm
@ PJ503 2 7 PL503 Idc / Isat: 3.8A
JUMP_43X79 PG EN 1UH_PH041H-1R0MS_3.8A_20%
1 2 VIN_2.5VP 3 6 LX_2.5VP 1 2
+3VALW 1 2 IN LX +2.5VP
4 5 SH00000YG00
68P_0402_50V8J
22U_0805_6.3VAM
22U_0805_6.3VAM
PGND NC
1
22U_0603_6.3V6M
22U_0603_6.3V6M
@EMI@ PR514
4.7_0603_5%
1
PC526
PC521
PC522
1
SY8003ADFC DFN 8P PR515
Rup Iocp : 3.7A
PC523
PC524
2
SA00007QP00 36.5K_0402_1%
2
FSW : 1MHz
2
2
FB_2.5VP
SNUB_2.5VP
5/29 add PC526 Rdown
In order to avoid capacitor decay PJ504
@
1
680P_0402_50V7K
1
1 2
+2.5VP +2.5V
@EMI@ PC525
PR516 1 2
11.5K_0402_1%
JUMP_43X79
2
Vout=0.6V* (1+Rup/Rdown)
2.504V= 0.6V*(1+36.5K/11.5K)
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2014/11/10 Deciphered Date 2016/11/10 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+1.2VP/+0.6VSP/+2.5VP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. B4DBU M/B LA-D301P
Date: Thursday, December 17, 2015 Sheet 52 of 63
A B C D E
A B C D E
EN pin don't floating
+19VB 1VALW
1 1
@EMI@ PR605 @EMI@ PC602
4.7_1206_5% 680P_0603_50V7K @ PJ601
1 2 SNB_1VALW 1 2 JUMP_43X118
@ PJ602 PU601 (Common Part) 1 2
1 2 +19VB_1VALW 2 9 PC603 +1.0VALWP 1 2 +1.0VALW_PRIM
+19VB 1 2 IN PG 0.1U_0603_25V7K SH00000YE00
10U_0805_25V6K
0.1U_0402_25V6
JUMP_43X79 3 1 BST_1VALW 1 @ 2 BST_1VALW_R1
PR606 2 PL602
IN BS
2200P_0402_50V7K
1
1
0_0603_5% 1UH_11A_20%_7X7X3_M
EMI@ PC604
@EMI@ PC605
PC606
LDO_3V_1VALW LX_1VALW
4
IN LX
6 1 2
+1.0VALWP
2
5 19
14K_0402_1%
330P_0402_50V7K
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
IN LX
1
1
1
330U_2.5V_M
1
1
@ PR607 7 20
PR608
PC608
PC609
PC610
PC611
PC612
GND LX +
0_0402_5%
Rup
PC615
8 14 FB_1VALW
GND FB
2
ILMT_1VALW LDO_3V_1VALW
2
2
18 17 @ 2
GND VCC
EN_1VALW
1
1
11 10
EN NC
@ PR609
ILMT_1VALW
PC613 FB = 0.6V
1
0_0402_5% 13 12 2.2U_0402_6.3V6M
ILMT NC
2
+3VALW 15
BYP NC
16
Rdown PR610
2
20K_0402_1%
21
PAD
2
SY8288RAC_QFN20_3X3 Pin 7 BYP is for CS.
1
The current limit is set to 8A ,12A ,16A, when this pin Common NB can delete +3VALW and PC15
PC614
is pull low, floating or pull high 1U_0402_6.3V6K
2
Vout=0.6V* (1+Rup/Rdown)
=0.6*(1+(14/20))
Vout=1.02V 2%
2
Ipeak=9.8A 2
@ Imax=6.86A
1 2
PR602
0_0402_5%
+1.8VALW_PG <54> Iocp=12A
@ PR603
10K_0402_1%
EN_1VALW 1 2
+3VALW
1
@ PC601
PR601 0.22U_0402_10V6K
1M_0402_1%
2
2
3 3
4 4
Security Classification
2014/11/10
Compal Secret Data
2016/11/10 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+1.0VALWP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
B4DBU M/B LA-D301P 0.1
Date: Thursday, December 17, 2015 Sheet 53 of 63
A B C D E
A B C D E
1 1
Module model information
SY8032_V2.mdd
@ PJ702
JUMP_43X79
1 2
+1.8VALWP 1 2 +1.8VALW_PRIM
VIN_1.8VALW
PC702
22U_0603_6.3V6M
FB=0.6V
2 2
1 2 PU701
SY8032ABC_SOT23-6
@ PJ701 PL701
JUMP_43X79 1UH_2.8A_30%_4X4X2_F
1 2 VIN_1.8VALW 4 3 LX_1.8VALW 1 2
+3VALW 1 2 IN LX +1.8VALWP
5 2
<53> +1.8VALW_PG PG GND
PR702
68P_0402_50V8J
1
100K_0402_1% 6 1
PR703
20K_0402_1%
22U_0603_6.3V6M
22U_0603_6.3V6M
FB EN
1
1 2
PC703
+3VALW
4.7_0603_5%
1
+1.8VALWP:
PR704
PC704
PC705
Imax=0.19A Ipeak=0.27A
2
@EMI@
EN_1.8VALW IOCP=3.9A
2
1 2
@ PR705
<43,51> SPOK
2
0_0402_5%
Rup
SNB_1.8VALW
1
FB_1.8VALW
1
PR701 @ PC701
1M_0402_1% 0.1U_0402_16V7K
1
PC706
680P_0402_50V7K
2
10K_0402_1%
1
Rdown
PR707
@EMI@
2
2
Vout=0.6V* (1+Rup/Rdown)
Note: Vout=0.6V* (1+(20/10))=1.8V
When design Vin=5V, please stuff snubber
to prevent Vin damage
3 3
4 4
Security Classification
2014/11/10
Compal Secret Data
2016/11/10 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SY8032
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
B4DBU M/B LA-D301P 0.1
Date: Thursday, December 17, 2015 Sheet 54 of 63
A B C D E
A B C D E
PR803
100_0402_1%
1 2
+VCC_SA
1 PC803 PC802 1
1000P_0402_50V7K 0.01U_0402_25V7K PR802
1 2 VSPP_1b 1 2
<13> VCCSA_SENSE @ PR804 1.5K_0402_1%
COMP_1b_CPU
1 2COMP_1b_CPU_C
1 2
0_0402_5%
Change
PR808 to 24.9k ohm
PR805
2.61K_0402_1%
PR822 to 24.9k ohm
1 2 VSP_1b PR846 to 2.43k ohm
PR867 to 2.43k ohm
PC804 PR842 to 36.5k ohm
5/29 Change 15P_0402_50V8J PR836 to 71.5k ohm
PR807 to 1K ohm 1 2 PR859 to 10k ohm
1
PC805 PC807 to 2200P 20150225
1000P_0402_50V7K
PR807
11K_0402_1%2VSN_1b
2
CSN_1b <56>
PC807
1
2200P_0402_50V7K
1 2VSNN_1b
@ PR806 1 2 PH802
<13> VSSSA_SENSE
0_0402_5% 100K_0402_1%_NCP15WF104F03RC
Close to SA choke
1000P_0402_50V7K
4700P_0402_25V7K
2
PR809
24.9K_0402_1%
<50> PSYS_MON
0.015u_0402_25V7K
1
2
100_0402_1%
SA_Chock Temp
2
1
1 2
PC809
PC833
1
PR808
PC806
2
2
PR810 PR811
100_0402_1% 20K_0402_1%
1
1 2 1 2
+VCC_GT
15K_0402_1%
ILIM_1b_CPU
PR816
1 2 VSP_2ph
<15> VCCGT_SENSE @ PR812
2
0_0402_5%
1
8/18 Change CSP_1b_CPU
PC808 PR814 to 806 ohm 2 1
SW_1b <56>
1000P_0402_50V7K PR818
<15> VSSGT_SENSE PC810 to 3300P
2
8.25K_0603_1%
PR815
2 IOUT_1b_CPU 2 1 2
100_0402_1% @ PR814 806_0402_1%
1 2 1 2
PR813
VSNN_2ph 1 2 VSN_2ph PR819 113K_0402_1% +3VS
0_0402_5% PR821
1 2 10K_0402_1%
1 2
1DIFOUT_2ph_CPU_R 1
PC810 PC811 220P_0402_50V7K
49.9_0402_1%
3300P_0402_50V7-K
VR_PWRGD <43>
+1.0V_VCCSTclose
PR817
1K_0402_1%
1
VR_ON_CPU 1 to the longer distance phase(81208 or 81210)
2
2
PR863 0_0402_5% Alert,Data,Clk. PR829
VR_ON <43,47>
470P_0402_50V7K
8.25K_0603_1%
PR820
1 2
110_0402_1%
24.9K_0402_1%
SW_1a <56>
100_0402_1%
45.3_0402_1%
0.1U_0402_16V7K
2
1
Close to VGT1 choke PWM_1b <56>
110_0402_1%
1
1
23E@ PR825 23E@ PR833
PC812
470P_0402_50V7K
2
1
110K_0402_1% 15.4K_0402_1%
PR828
1
PH803
PC815
DRVON <56>
4.75K_0402_1%
THERM_ 220K 5% 0402
PC813
GT_Chock_Temp
2
2
1 2 @
PR823
PR826
2
2
1COMP_2ph_CPU_C
PR822
PR824
PR866
IOUT_2ph_CPU 1
VR_HOT# <43>
8/18 Change PR834 @ PR835
49
48
47
46
45
44
43
42
41
40
39
38
37
22@ PR825 PR830 PC818 to 150P 22@ PR833 49.9_0402_1% 15K_0402_1%
2 CORE_Chock_Temp
15P_0402_50V8J
1000P_0402_50V7K
1
69.8K_0603_1% 165K_0402_1% PR831 12.4K_0402_1% 1 2 1
SOC_SVID_CLK <15>
VSN_2ph
VSP_2ph
VSP_1b
VSN_1b
COMP_1b
ILIM_1b
CSN_1b
CSP_1b
IOUT_1b
EN
TAB
PSYS
VR_RDY
SWN_GT1
1
1 2 1 2 1
75K_0402_1% 2 1 2 Close to VCORE choke
2200P_0402_25V7K
PC819
150P_0402_50V8J
0.033U_0402_16V7K
1 36 PR860 470P_0402_50V7K
PC814
DIFOUT_2ph_CPU IOUT_2ph PWM_1b
2
2 35 1 0_0402_5%
2 1 2
PC816
FB_2ph_CPU DIFFOUT_2ph DRVON SOC_SVID_ALERT#_R <15>
1
1
PC817 3 34 SCLK
PC818
COMP_2ph_CPU FB_2ph SCLK
1
1000P_0402_50V7K 4 PU801 33 ALERT# PR862 PH804
ILIM_2ph_CPU COMP_2ph ALERT#
2
5 32 SDIO 1 10_0402_1%
2 100K_0402_1%_NCP15WF104F03RC
PC834
CSCOMP_2ph_CPU ILIM_2ph SDIO VR_HOT#_CPU SOC_SVID_DAT <15>
2
2
6 NCP81208 31 1 2 2 1
PC820
CSSUM_2ph_CPU CSCOMP_2ph VR_HOT# IOUT_1a_CPU
2
7 30 PR869 100_0402_1% PR836 71.5K_0402_1%
CSSUM_2ph IOUT_1a CSP_1a_CPU
2
8 29
<56> CSN_GT1 CSP2_2ph_CPU 9 CSREF_2ph CSP_1a
1 2 28
+5VS PR868
CSP1_2ph_CPU 10 CSP2_2ph CSN_1a 27 ILIM_1a_CPU CSN_1a <56>
ROSC_COREGT
GT_High Side_Temp TSENSE_2ph_CPU 11 CSP1_2ph ILIM_1a COMP_1a_CPU
ADDR_VBOOT
0_0402_5% 1 @ 2
PR864 26
RSOC_SAUS
TSENSE_1ph
TSENSE_2ph COMP_1a
ICCMAX_2ph
0.1U_0402_16V7K
5/29 Change 0_0402_5% 1 2 12 25
+19VB
ICCMAX_1a
ICCMAX_1b
PWM1_2ph
PWM2_2ph
VRMP VSN_1a
1
PC821 to 0.1U PR801 PC824 5/29 Change
PWM_1a
VSP_1a
1K_0402_1% 3300P_0402_50V7-K PC824 to 3300P
0.015u_0402_25V7K
1
1
1 2
PC821
PR842
VCC
36.5K_0402_1%
15P_0402_50V8J
0.1U_0402_16V7K
2
1
PR840 PC826
VRMP_CPU
100K_0402_1%_NCP15WF104F03RC
1000P_0402_50V7K
1
100_0402_1% 1000P_0402_50V7K
PC829
PC825
VSN_1a_CPU_R 1
2
1
1
2
@ PR865 2 1
VSN_1a_CPU
13
14
15
16
17
18
19
20
21
22
23
24
2
1 2 0_0402_5%
PC822
PH801
61.9K_0402_1%
2
1
PC827 PR843 806_0402_1%
1COMP_1a_CPU_C
2
1
8/18 Change
RSOC_SAUS_CPU
ROSC_COREGT_CPU
ICCMAX_1a_CPU
ICCMAX_2ph_CPU
ICCMAX_1b_CPU
TSENSE_1ph_CPU
ADDR_VBOOT_CPU
0.01U_0402_50V7K
1
PR843 to 806 ohm PC828
PC801
VSSSENSE <15>
2
VCC_CPU
1000P_0402_50V7K
PR844
2
3 3
2
PR845 2.26K_0402_1% 1 0 0 度C PR846
VSP_1a_CPU
2.43K_0402_1%
VSP_1a_CPU_R
1 2 Close to VGT1 MOS 1 2 1 2
@ PR847
<56> SWN_GT1 VCCSENSE <15>
0_0402_5%
1 2
+5VS PR850
2_0402_1%
PR848
24K_0402_1%
1
2.49K_0402_1%
33.2K_0402_1%
2
1
PR854
1
PR853
PC831 1 2VSP_1a_CPU_C
1 2 2 1
1U_0603_10V6K PC830 PR851 +VCC_CORE
2
2
1000P_0402_50V7K PR867 2.43K_0402_1% 100_0402_1%
2
1 2 CORE_High Side_Temp
@ PR852
0_0402_5%
Close to VCORE MOS
PWM_1a <56>
1000P_0402_50V7K
1
23E@ PR856
52.3K_0402_1% PH805
61.9K_0402_1%
2
1
100K_0402_1%_NCP15WF104F03RC
PC832
2
PR855
10K_0402_1%
PR856 48.7K_0402_1%
PR858 15.8K_0402_1%
2
PR857 90.9K_0402_1%
1
1
1
1
2
2
PR859
2
2
22@
8/18 Change
PR858 to 15.8K ohm
PWM1_2ph <56>
5/29 Change
PR857 to 90.9K ohm
4 4
Security Classification
2014/11/10
Compal Secret Data
2016/11/10 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
IMVP8, NCP81206
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D
B4DBU M/B LA-D301P 0.1
Date: Thursday, December 17, 2015 Sheet 55 of 63
A B C D E
A B C D E
+19VB
+19VB_CPU
InputCapacitor:
10uF_0805_X5R_25V VCC_CORE:
@ PJ9001 Imax=20.3A Ipeak=29A Iocp=38A
1 2
1 2
VCCGT:
10U_0805_25V6K
10U_0805_25V6K
1 1 JUMP_43X79
Imax=21.7A Ipeak=31A Iocp=40A
2200P_0402_50V7K
@EMI@ PC9015
EMI@ PC9003
MDU1516URH_POWERDFN56-8-5
33U_25V_M
33U_25V_M
0.1U_0402_25V6
1 1
1
PR9001 PC9001 + +
PC9014
PC9002
PC9079
PC9004
5
1
2.2_0603_5% 0.22U_0603_16V7K VCCSA:
1 2 BST_VCORE_R 1 2 Imax=3.15A Ipeak=4.5A Iocp=13.3A
2
2 2
2
4
PU9001
NCP81253MNTBG_DFN8_2X2
(Common Part) +VCC_CORE
PQ9002
BST_VCORE 1 8 HG_VCORE SH000011H00 7*7*4
BST DRVH
3
2
1
PL9001 0.22UH 20% FDUE0640J -H 25A
2 7 SW_VCORE 1 4
<55> PWM_1a PWM SW
<55> DRVON 3 6 2 3
EN GND
MDU1511RH_POWERDFN56-8-5
@EMI@ PR9002
4 5
+5VS
4.7_1206_5%
VCC
PAD
DRVL
1
1
PC9049
CSN_1a <55>
4.7U_0603_6.3V6K
LG_VCORE 4 DCR=0.98m ohm +-5%
2
Common part SH000011H00
2
SNB_VCORE
3
2
1
PQ9003
SW_1a <55>
PC9073
680P_0603_50V7K
1
2
@EMI@
PR9005 PC9083 +19VB_CPU
2.2_0603_5% 0.22U_0603_16V7K
10U_0805_25V6K
10U_0805_25V6K
2200P_0402_50V7K
BST_GT_R 1
2 1 2 2 InputCapacitor: 2
EMI@ PC9086
MDU1516URH_POWERDFN56-8-5
10uF_0805_X5R_25V
@EMI@ PC9085
0.1U_0402_25V6
1
1
PC9087
PC9088
2
2
5
PU9003
NCP81151MNTBG_DFN8_2X2 (Common Part) +VCC_GT
BST_GT 1 9 4
PQ9005
BST FLAG SH000011H00 7*7*4
2 8 HG1_GT
<55> PWM1_2ph PWM DRVH PL9005 0.22UH 20% FDUE0640J -H 25A
DRVON 3 7 SW1_GT 1 4 +VCC_GT
EN SW
3
2
1
DCR=0.98m ohm +-5%
4 6 2 3
+5VS VCC GND Common part SH000011H00
5
5 PR9009 10_0402_1%
MDU1511RH_POWERDFN56-8-5
@EMI@ PR9010
DRVL CSN_GT1_R
1
1 2
4.7_1206_5%
CSN_GT1 <55>
1
PC9090
4.7U_0603_6.3V6K
2
LG1_GT 4 SWN_GT1 <55>
2
SNB_GT
3
2
1
PQ9007
InputCapacitor:
PC9092
680P_0603_50V7K
1
10uF_0805_X5R_25V +19VB_CPU
10U_0805_25V6K
10U_0805_25V6K
2200P_0402_50V7K
2
EMI@ PC9118
@EMI@
@EMI@ PC9117
0.1U_0402_25V6
3 3
1
1
PC9115
PC9116
PR9013 PC9119
2
2.2_0603_5% 0.22U_0603_16V7K
1 2 BST_SA_R 1 2
HG_SA
AON7934
Rds(on)=12.4~15.8m ohm
PU9004 PQ9008
4
NCP81253MNTBG_DFN8_2X2 AON7934_DFN3X3A8-10 DCR=4~4.2m ohm +-5%
Common part SH00000ID00 +VCC_SA
D1
D1
D1
G1
BST_SA 1 8
BST DRVH PL9006 0.47UH 20% MMD-06CZ 17.5A
2 7 10 9 SW_SA 1 4
<55> PWM_1b PWM SW D1 D2/S1
DRVON 3 6 2 3
@EMI@ PR9014
EN GND
G2
S2
S2
S2
4.7_1206_5%
1
4 5
+5VS VCC
PAD
DRVL
5
8
1
9
PC9154
CSN_1b <55>
4.7U_0603_6.3V6K
2
2
SNB_SA
SW_SA SW_1b <55>
LG_SA
PC9155
680P_0603_50V7K
1
2
4 4
@EMI@
Security Classification
2014/11/10
Compal Secret Data
2016/11/10 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power Train
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
B4DBU M/B LA-D301P 0.1
Date: Thursday, December 17, 2015 Sheet 56 of 63
A B C D E
1
0.1
Rev
63
of
57
Compal Electronics, Inc.
Sheet
B4DBU M/B LA-D301P
E
E
Thursday, December 17, 2015
Power Train
Document Number
+VCC_SA
PC9162
1U_0201_4V6M
+VCC_SA
1 2
Date:
Title
PC9125 PC9141 PC9161
Size
22U_0603_6.3V6M 22U_0603_6.3V6M 1U_0201_4V6M
C
1 2 1 2 1 2
1uF_0201*7
PC9124 PC9140 PC9160
22U_0603_6.3V6M 22U_0603_6.3V6M 1U_0201_4V6M
1 2 1 2 1 2
PC9123 PC9139 PC9159
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
@
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
unpop: 22uF_0603*6
22U_0603_6.3V6M 22U_0603_6.3V6M 1U_0201_4V6M
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
1 2 1 2 1 2
2016/11/10
PC9122 PC9138 PC9158
@
22U_0603_6.3V6M 22U_0603_6.3V6M 1U_0201_4V6M
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
22uF_0603*6
1 2 1 2 1 2
PC9121 PC9137 PC9157
@
@
20140703
22U_0603_6.3V6M 22U_0603_6.3V6M 1U_0201_4V6M
1 2 1 2 1 2
PC9120 PC9136 PC9156
@
22U_0603_6.3V6M 22U_0603_6.3V6M 1U_0201_4V6M
Deciphered Date
1 2 1 2 1 2
Compal Secret Data
D
D
2014/11/10
+VCC_GT
+VCC_GT
PC9143
@
PC9104 PC9114 PC9135 PC9171 PC9153 1U_0201_4V6M
@
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 1U_0201_4V6M
@
Security Classification
1 2
1 2 1 2 1 2 1 2 1 2 PC9142
@
PC9103 PC9113 PC9134 PC9169 PC9152 1U_0201_4V6M
@
Issued Date
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 1U_0201_4V6M
1 2
1 2 1 2 1 2 1 2 1 2 PC9184
PC9102 PC9112 PC9133 PC9164 PC9151 1U_0201_4V6M
@
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 1U_0201_4V6M
1 2
1 2 1 2 1 2 1 2 1 2 PC9185
@
PC9101 PC9111 PC9132 PC9163 PC9150 1U_0201_4V6M
@
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 1U_0201_4V6M
1 2
1 2 1 2 1 2 1 2 1 2 PC9182
PC9100 PC9110 PC9131 PC9167 PC9149 1U_0201_4V6M
@
@
C
C
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 1U_0201_4V6M
1uF_0201*11
1uF_0201*9
1 2
1 2 1 2 1 2 1 2 1 2 PC9183
PC9099 PC9109 PC9130 PC9165 PC9148 1U_0201_4V6M
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 1U_0201_4V6M
比 ,
1 2
1 SE00000UC00.
1 2 1 2 1 2 1 2 1 2 PC9181
PC9098 PC9108 PC9129 PC9168 PC9147 1U_0201_4V6M
比
@
SE00000U200比
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 1U_0201_4V6M
1 2
1 2 1 2 1 2 1 2 1 2 PC9178
PC9097 PC9107 PC9128 PC9170 PC9146 1U_0201_4V6M
@
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 1U_0201_4V6M
22uF_0603*30
unpop: 22uF_0603*8
1 2
1 2 1 2 1 2 1 2 1 2
PC9096 PC9106 PC9127 PC9145 PC9176
@
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 1U_0201_4V6M 1U_0201_4V6M
1 2 1 2 1 2 1 2 1 2
PC9095 PC9105 PC9126 PC9093 330U_D2_2V_Y PC9144 PC9175
@
故 1u_020
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 1U_0201_4V6M 1U_0201_4V6M
1u_0201
20150709
+
1
1 2 1 2 1 2 1 2 1 2
D2*1
(Common Part)
SGA00009S00
+VCC_CORE
B
PC9021 PC9038 PC9062 PC9052 PC9026 PC9048 PC9072 PC9078
+VCC_CORE
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M
1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2
PC9008 PC9037 PC9061 PC9051 PC9013 PC9047 PC9071 PC9077
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M
0201_3PCS, 330uF_R9_2PCS
1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2
PC9007 PC9036 PC9060 PC9050 PC9025 PC9046 PC9070 PC9076
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M
1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2
PC9020 PC9035 PC9059 PC9180 PC9012 PC9045 PC9069 PC9075
@
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M
1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2
Total VCORE Output Capacitor:
PC9019 PC9034 PC9058 PC9179 PC9024 PC9044 PC9068 PC9074
@
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M
1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2
PC9018 PC9033 PC9057 PC9177 PC9023 PC9043 PC9067 PC9172
@
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M
1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2
PC9006 PC9032 PC9056 PC9022 PC9042 PC9066 PC9173
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M
UNPOP 0603_8PCS,
22uF_0603_28PCS
1 2 1 2 1 2 1 2 1 2 1 2 1 2
1uF_0201_35PCS
PC9017 PC9031 PC9055 PC9011 PC9041 PC9065 PC9174
@
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M
2015/07/09
1 2 1 2 1 2 1 2 1 2 1 2 1 2
PC9005 PC9030 PC9054 PC9028 PC9010 PC9040 PC9064
@
A
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 330U_D2_2V_Y 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M
+
1
1 2 1 2 1 2 1 2 1 2 1 2
PC9016 PC9029 PC9053 PC9027 PC9009 PC9039 PC9063
@
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 330U_D2_2V_Y 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M
+
1
1 2 1 2 1 2 1 2 1 2 1 2
(Common Part)
SGA00009S00
1
4
A B C D E
1 1
2 @VGA_EMI@ PR1004
4.7_1206_5%
@VGA_EMI@ PC1003
680P_0603_50V7K
Imax=5.25A, Ipeak=7.5A, Iocp:10.88A 2
1 2SNB_1.5VSDGPUP
1 2
VGA@
@ PJ1001 PU1001 (Common Part)
1 2+19VB_1.5VSDGPUP 2 9 VGA@ PC1001
+19VB 1 2 IN PG @VGA@ 0.1U_0603_25V7K
SH00000YE00
3 1 BST_1.5VSDGPUP
1 2BST_1.5VSDGPUP_R 1 2
JUMP_43X79 PR1001 PL1002 VGA@
1.527V 1.8%
2200P_0402_50V7K
10U_0805_25V6K
0.1U_0402_25V6
IN BS
1
0_0603_5% 1UH_PCMB063T-1R0MS_12A_20%
@VGA_EMI@ PC1004
VGA@ PC1007
LX_1.5VSDGPUP
4 6 1 2
+1.5VSDGPUP
VGA_EMI@ PC1006
IN LX
2
5 19
VGA@ PR1005
PC1009
PC1010
VGA@ PC1011
VGA@ PC1012
VGA@ PC1013
VGA@ PC1014
30.9K_0402_1%
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
IN LX
VGA@ PC1008
VGA@ PC1015
330P_0402_50V7K
1
1
7 20
GND LX
8 14 FB_1.5VSDGPUP
GND FB
2
VGA@
VGA@
2
LDO_3V_1.5VSDGPUP
18
GND VCC
17
Rup
1.5VS_DGPU_EN
1
11 10 VGA@ PC1016
EN NC
ILMT_1.5VSDGPUP
2.2U_0402_6.3V6M FB = 0.6V
1
13 12
ILMT NC
2
VGA@ PR1006
20K_0402_1%
15 16 PJ1002
@
+3VALW BYP NC 1 2
+1.5VSDGPUP 1 2 +1.5VSDGPU
1
21
1U_0402_6.3V6K
PAD
2
Rdown JUMP_43X118
VGA@ PC1017
SY8286RAC_QFN20_3X3
3 3
2
Pin 7 BYP is for CS.
Common NB can delete +3VALW and PC15
LDO_3V_1.5VSDGPUP Brand
VGA Name VRAM Size Voltage VFB=0.6V
Vout=0.6V* (1+Rup/Rdown)
1
@VGA@ PR1007 VGA@ PR1002 Vout=0.6V* (1+(30.9/20))=1.527
0_0402_5%
1.5VS_DGPU_EN
40.2K_0402_1%
1 2 N16S-GT NV940 2GB 1.5V
1.5VS_DGPU_PWR_EN <21,47>
2
ILMT_1.5VSDGPUP
VGA@ PC1002
0.1U_0402_16V7K
1
VGA@ PR1003 Change PR1002 from
@VGA@ PR1008 1M_0402_1%
10K to 40.2K for non
2
0_0402_5%
GC6. 20141219
2
The current limit is set to 6.5A, 9.5A or 12.5A when this pin
4 is pull low, floating or pull high 4
Security Classification
2014/11/10
Compal Secret Data
2016/11/10 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
1.5VSDGPUP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A3
B4DBU M/B LA-D301P 0.1
Date: Thursday, December 17, 2015 Sheet 58 of 63
A B C D E
1 1
Module model information
SY8032_V2.mdd
@ PJ1102
JUMP_43X79
1 2
+1.05VSDGPUP 1 2 +1.05VSDGPU
VIN_1.05VS
VGA@ PC1102 (Common Part)
22U_0603_6.3V6M
2
SH00000YG00 4*4*2 2
1 2 VGA@ PU1101
SY8032ABC_SOT23-6
@ PJ1101 VGA@ PL1101
JUMP_43X79 1UH_2.8A_30%_4X4X2_F
1 2 VIN_1.05VS 4 3 LX_1.05VS 1 2
+3VS 1 2 IN LX +1.05VSDGPUP
5 2
@VGA_EMI@ PR1101
PG GND
68P_0402_50V8J
6 1
VGA@ PR1102
VGA@PC1103
PC1105
7.68K_0402_1%
22U_0603_6.3V6M
22U_0603_6.3V6M
FB EN
VGA@ PC1104
4.7_0603_5%
1
2
2
@VGA@
EN_1.05VS
2
1 2
PR1103
VGA@
<10,21,47,60> DGPU_PWROK
2
0_0402_5%
Rup
1SNUB_1.05VS
1
@VGA@ PR1104 @VGA@
VGA@ PR1105
1M_0402_1%
FB_1.05VS
1
10K_0402_1% PC1106
1 2 0.1U_0402_16V7K
+3VSDGPU_AON
@VGA_EMI@ PC1101
VGA@ PR1106
680P_0402_50V7K
2
1
10K_0402_1%
2
Rdown
2
Note:
When design Vin=5V, please stuff snubber
to prevent Vin damage
Vout=0.6V* (1+Rup/Rdown)
=>0.6V*(1+(7.68/10)=1.061 (1.01%)
3 Imax= 0.77A, Ipeak= 1.1A , Iocp=3.5A 3
4 4
Security Classification
2014/11/10
Compal Secret Data
2016/11/10 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SY8032
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
B4DBU M/B LA-D301P 0.1
Date: Thursday, December 17, 2015 Sheet 59 of 63
A B C D E
A B C D E
unmount PRV5 for 2 phase select +19VB_VGA
PSI : PSI <21>
<21>
NOGC6@ PR1202
1 phase with DEM 0V to 0.8V
DGPU_VID
20K_0402_1% @ PJ1201
1 phase with CCM 1.2V to 1.8V +3VS VGA_EN 1 2 +19VB_VGA 1 2
2 phase with CCM 2.4V to 5.5V +3VSDGPU_AON 1 2 +19VB
@VGA@ PR1203
JUMP_43X79
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_16V7K
EN High Threshold = 1.6V GC6@ PR1206
PR1205
VGA@ PC1209
10K_0402_5%
10K_0402_5%
2
1
20K_0402_1%
0_0402_5%
1
1 2
@VGA_EMI@ PC1205
0.1U_0402_25V6
PR1204
VGA@ PC1202
VGA@ PC1203
VGA@ PC1204
VGA@ PC1207
3VSDGPU_MAIN_EN <21,47>
2200P_0402_50V7K
1
1
VGA@ PR1208
2
20K_0402_1%
VGA_EMI@ PC1208
2
2
VREF_VGA 2 1
@VGA@
MDU1516URH_POWERDFN56-8-5
1
2
5
@VGA@
VGA@ PR1211
2K_0402_1%
2 1REFADJ_R VGA@ PR1207
0_0603_5%
1 VGA@PR1210 VGA@ PR1209 UG1_VGA 1 2 UG1_VGA_R 4 1
18K_0402_1%
1
20K_0402_1%
2 1REFADJ
PSI_VGA
@VGA@
PQ1201
3
2
1
BST1_VGA 1 2 BST1_VGA_R
PR1201 PL1202
2
1
VGA@ 0_0603_5% VGA@
REFIN_VGA_R
PC1210
LX1_VGA
0.22UH_PCME064T-R22MS0R985_28A_20% +VGA_CORE
1
2700P_0402_50V7K VGA@ PC1201 1 2
UGATE1
BOOT1
VID
PSI
EN
5
0.1U_0603_25V7K
2
MDU1511RH_POWERDFN56-8-5
@VGA_EMI@
680P_0402_50V7K 4.7_1206_5%
@VGA@ 6 20 LX1_VGA
REFADJ PHASE1
2
PR1212
1 1 1
330U_D2_2V_Y
330U_D2_2V_Y
330U_D2_2V_Y
PR1224
0_0402_5% REFIN_VGA 7 19 LG1_VGA 4 + + +
VGA@ PC1211
VGA@ PC1212
VGA@ PC1220
REFIN LGATE1
1SNUB_VGA1 1
VGA@ PC1213
0.1U_0603_25V7K @VGA@
1
2 VREF_VGA PVCC_VGA 2 2 2
1
1 8 18 1 2
PR1213
+5VS
PR1214
NVVDD_GND_SENSE_R VREF VGA@ PU1201 PVCC 0_0402_5%
@VGA_EMI@
13K_0402_1%
3
2
1
1
RT8812AGQW_WQFN20_3X3
PQ1202
TON_VGA 9 17 LG2_VGA VGA@ PC1214
PC1215
TON LGATE2 1U_0603_10V6K
2
+19VB 2 1
VGA@
+19VB VGA@ PR1215 10 16
RGND PHASE2
2
UGATE2
332K_0402_1%
PGOOD
BOOT2
2015/06/10 PR1215 change to 332K ohm
VSNS
+19VB_VGA
GND
FSW= 450K Hz PR1216
SS
MDU1516URH_POWERDFN56-8-5
LX2_VGA
5
100_0402_1%
21
11
12
13
14
15
1 2
NVVDD_GND_SENSE_R
1
SS_VGA
@VGA@ PR1218 VGA@ PC1216 UG2_VGA_R 4
0_0402_5% 0.1U_0603_25V7K
2
1 2 @VGA@
<23> VSSSENSE_VGA BST2_VGA
1 1 2 BST2_VGA_R
PR1217
2 @VGA@ PC1218 0_0603_5% PL1203
PQ1203
2
3
2
1
1
@VGA@ PC1217 .1U_0402_16V7K VGA@
@VGA@ 0.22UH_PCME064T-R22MS0R985_28A_20% +VGA_CORE
2
@VGA@ PR1220 1000P_0402_50V7K UG2_VGA 1 2
PR1219 UG2_VGA_R LX2_VGA 1 2
2
0_0402_5% 0_0603_5%
1 2
@VGA_EMI@
<23> VCCSENSE_VGA
4.7_1206_5%
5
2
MDU1511RH_POWERDFN56-8-5
DGPU_PWROK <10,21,47,59>
PR1222
PR1221 N16S-GT EDP continuous:26A peak: 51A
100_0402_1% VGA@ PR1223 L side Rds(on): 2.7mohm(Typ), 3.3mohm(Max)
1 2 NVVDD_SENSE_R 10K_0402_5%
+VGA_CORE Idsm: 70A@Ta=25C, 40A@Ta=70C
1SNUB_VGA21
LG2_VGA
2 1 +3VS 4
CHOKE:0.22uH, DCR 0.98m ohm, L/2 over 65A
680P_0402_50V7K
@VGA_EMI@
FSW = 450Khz
PC1219
3
2
1
(R=332K-->450Khz)
PQ1204
Imax=35A
Ipeak-51A
2
OCP = 63A
OVP=1.9(min), 2.1mohm(Max)
PWM-VID Spec and component Values
+VGA_CORE
PWM-VID Spec Config B Config C Config D
Vmin 0.6V 0.65V 0.9V
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
VGA@ PC1320
VGA@ PC1338
VGA@ PC1322
VGA@ PC1323
VGA@ PC1324
VGA@ PC1325
VGA@ PC1326
VGA@ PC1327
VGA@ PC1328
VGA@ PC1329
Vmax 1.2V 1.15V 1.15V
1
1
Vboot 0.9V 0.9V 1.028V
2
2
Voltage step 6.25mV 25mV 12.5mV +VGA_CORE
+VGA_CORE Near GPU Core
N of Voltage level 96 20 20
Rrefadj PR 20K 39K 27K
1U_0402_10V7
1U_0402_10V7
1U_0402_10V7
1U_0402_10V7
47U_0805_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
3 3
PC1330
PC1331
PC1332
PC1333
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
VGA@ PC1334
VGA@ PC1335
VGA@ PC1336
VGA@ PC1337
VGA@ PC1339
VGA@ PC1340
VGA@ PC1341
VGA@ PC1342
VGA@ PC1343
VGA@ PC1344
VGA@ PC1345
1
22U_0603_6.3V6M
PC1321
Rref1 PR 20K 30K 7.5K
1
1
Rboot PR 2K 3K 0
2
2
2
Rref2=PR1209 PR 18K 24K 6.2K
@RF@_VGA@
@RF@_VGA@
@RF@_VGA@
@RF@_VGA@
VGA@
+PR1212 PR 0 3K 1.74K
C PC 2.7nf 1.8nf 5.6nf
N16S-GT
N16V-GM
4 4
Security Classification
2014/11/10
Compal Secret Data
2016/11/10 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
NVIDIA VGA_CORE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
B4DBU M/B LA-D301P 0.1
Date: Thursday, December 17, 2015 Sheet 60 of 63
A B C D E
A B C D E
1K
1K
+3VS
BH10 SOC_SMBCLK
SO-DIMM 1
BG12 SOC_SMBDATA
SO-DIMM 2
1
Skylake 1
SOC
XDP
SOC_SML0CLK 499
499
+3VS
SOC_SML0DATA
1K
1K
+3VS
SOC_SML1CLK
SOC_SML0DATA
2 2
2.2K
2.2K
+3VLP_EC
77 EC_SMB_CK1 100 ohm 7
SCL1 BATTERY
78 EC_SMB_DA1 100 ohm 6
SDA1 CONN
0 ohm EC_SMB_CK1_CHGR
12
0 ohm EC_SMB_DA1_CHGR
11 Charger
KBC SCL2 79 SOC_SML1CLK
SDA2 80 SOC_SML0DATA
3
KB9022 3
1.8K
1.8K +3VSDGPU_AON
I2CS_SCL
2N7002DW I2CS_SDA VGA
4 4
Security Classification
2014/11/10
Compal Secret Data
2016/11/10 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SMBUS_Routing_Table
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
B4DBU M/B LA-D301P 0.1
Date: Thursday, December 17, 2015 Sheet 61 of 63
A B C D E
5 4 3 2 1
Version change list (P.I.R. List) Page 1 of 1
for PWR
Item Fixed Issue Reason for change Rev. PG# Modify List Date Phase
01 Design Change. X1 Code : SE158225K80 02 50 PC316 change to SE000006S80 8/25 DVT
D D
02 PR814 and PR843 change to 806 ohm.
PR858 change to 15.8K ohm.
55 PC810 change 3300P.
03 Design Change. ON FAE suggest to modify Parts 02 57 8/25 DVT
PC818 change to 150P.
Add PC 9008, PC9031, and PC9007.
04
05 Design Change. For Type-C function 03 51 PU402 change to SA00008YM00 10/7 PVT
06 Design Change. Change 0 ohm to short pad. 03 PR1001, PR101, PR1103, PR1201, PR1204, PR1213, PR1217, PR1219, PR1224, PR201,
PR315, PR316, PR317, PR333, PR401, PR408, PR501, PR510, PR512, PR602, PR606
07 PR705, PR804, PR806, PR812, PR813, PR847, PR852, PR864, PR865 change to short pad 10/22 PVT
08
09
C C
10
11
12
13
14
B B
14
A A
Security Classification
2014/11/10
Compal Secret Data
2016/11/10 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PIR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
B4DBU M/B LA-D301P 0.1
Date: Thursday, December 17, 2015 Sheet 62 of 63
5 4 3 2 1
5 4 3 2 1
EVT->DVT 1015
1. Change below items to short pad :
0810 RC238,RC245,RC55,RC56,RC12,RC130,RC131,
1. Remove RPC8 RC168,RC186,RC188,RC208,RC140,RC143,RC141,
2. Change the BOM structure of CD36 and CD34 to @ RC192,RC175,RC148,RC173,RC154,RC198,RC209,
3. Change UL3's part number to SA000028Y10 RC149,RC176,RC156,RC197,RC161,RC163,RC172,
4. Change U67's part number to SA00007IO10 RC167,RC187,RC162,RC171,RC169,RC164,RC190,
5. Add U5004's part number SA00008E710 RC152,RD45,RD47,RD46,R550,R549,R23,R5248,
D
6. Change U5007's BOM structure to TBT@ R664,RC229,RC19,RC20,R486,R487,R873,R441, D
7. Change U1's part number to SA00007UJ10 R442,R661,R5193,R1580,R5210,R5209,R5192,
8. Remove U61, C818 R5194,R5197,R5198,R4953,R514,R645,
9. Change BOM structure of RC62 and RC63 to POP 2. Change U5007's part number to SA00008C310
10. Connect RC18.2 to Codec PIN 31 (for MIC function)
11. Remove RC240 1016
12. Add C5227 1. Update power schematic 1016
13. Add R5251, R5252
14. Change D44's part number to SC300003S00 1016a
15. change BOM structure PC@ to @ 1. Add R5254, R5255 for Draco_SL reserve
0812 1018
1. JLID1. 4 Connecto to +3VLP 1.Change R23, R5248, RC130, RC131, R486, R487 back to 0ohm resistor
2. change type C connector's part number to LTCX006Z3BL
3. remove D16 1027
1. Change U67's part number to SA00007IO00
0813 2. SUSCLK R5252 POP->@
1. change type C connector JUSB2's footprint from lotes_ausb0139-p001a_24 to JAE_DX07S024XJ1_24P-T 3. R5250 TBT@->@TBT@
4. Add LAN Chip UL1 R3 Part Number SA000081G50
0817 5. Replace SP050006F00 to SP050006B10
C
1.change back TYPE C connector to SP011504212 C
2.change D29 and D30's part number to SC300003S00, same as D44 PVT->PreMP
3.remove R630,R631,R633,R665,R667,R668,R669,R671 1209
4.C5126,C5121,C5118,C5117 change to @ for HDMI 1. Change R1581 to @
5.C5201,C5202,C5197,C5196 change to 0201 for TBT 2. Change R1579 to TBT@
6.Add C5239 0.1u on +3VS (JFP1) for EMI 3. Change U60 to @
7.C480,C633 change to RF@ for RF 4. Change UC3's to 3VM
8.ADD C5237 68P on +3VS(JTP1) for RF 5. BOARD ID Change to PreMP Value
9.ADD C5238 68P on +3VS(JFP1) for RF 6. Add RC248, RC249
10.ADD C5232 68P on +3VS(JDMIC) for RF
11.ADD C5229, C5230, C5231 0.1u+2200p+68p on +19VB for RF 1216
12.ADD C5235, C5236 68P*2 on +3VS(JKB) FOR RF 1. R525 changes to 10K
13.ADD C5228, R5253 0OHM+22P (RPC9) FOR RF 2. C5232 changes to 0.1U
14.ADD C5233 0.1u on +5VALW(JIO1) for EMI 3. PIN UC1.R10 connect to +3VALW_PRIM with 2.2K resistor
15.ADD C5240 68P on +5VALW(JIO1) for RF 4. add U5008 for 3VALW and 3VALWP
16.ADD C5241 @RF@ for RF
17.Change C5241's connection to ESPI_CLK_R 1217
18. Change R5173's connection to EC_TBTA_RESET 1. U5009.4 Connect to 3VLAWP
2. Add Q2021, R5258, R5259 for Discharge
0818 3. Q2021.3 Connect to SUSP#
B 1. Change C5227 to @ B
2. Change C633 to @ 1218
3. Change C5179~C5182 package to 0201 1. Add C5251 for EC_RSMRST#
4. Modify the connection of U26.9(G_INT2)
0819
1. Change package of R630, R631, R633, R665, R667, R668, R669, R671 to short pad
2. Add C5242, C5243, C5244, C5245 for EMI
3. Change package of U5005 to SOP8
4. R1579-->@, R1581-->POP
DVT->PVT
1008
1. C5244, C5243, C5242, C5245 change to EMI@
2. D17, D18, D19, D20, D21, D34, D23, D24 Change to SC40000AT00
3. R443, R444, R445 change to vpro@
4. R4903 change to 15K for DVT Board ID
5. R1579-->@, R1581-->POP
6. R5203-->@, R5173-->POP
A 7. UL3, U60 Change to SA000079400 A
8. SW1-->@
9. CL14 change to 0603
10. JREAD1 PIN10's connection from +3VALW to +5VALW
11. CD41, CD42, CD43 change to 0402
12 add 16M BIOS ROM on UC2 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2014/11/10 Deciphered Date 2016/11/10 Title
1012
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HW PIR
1. Connect DET_SIG#_R to UCPU1 pin AY5 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
LA-D301P 0.1
Date: Friday, December 18, 2015 Sheet 63 of 63
5 4 3 2 1
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