Unit I -Basic Structure of

Computers
C.Bala Subramanian,
AP/CSE,
KLU

C.Bala Subramanian, AP/CSE, KLU 1

Functional Units

C.Bala Subramanian, AP/CSE, KLU 2

Functional Units
Arithmetic
Input and
logic

Memory

Output Control

I/O Processor

Figure 1.1. Basic functional units of a computer.

C.Bala Subramanian, AP/CSE, KLU 3
Information Handled by a
Computer
 Instructions/machine instructions
 Govern the transfer of information within a computer as
well as between the computer and its I/O devices
 Specify the arithmetic and logic operations to be
performed
 Program
 Data
 Used as operands by the instructions
 Source program
 Encoded in binary code – 0 and 1
C.Bala Subramanian, AP/CSE, KLU 4
Memory Unit
 Store programs and data
 Two classes of storage
 Primary storage
 Fast
 Programs must be stored in memory while they are being executed
 Large number of semiconductor storage cells
 Processed in words
 Address
 RAM and memory access time
 Memory hierarchy – cache, main memory
 Secondary storage – larger and cheaper

C.Bala Subramanian, AP/CSE, KLU 5

Arithmetic and Logic Unit
(ALU)
 Most computer operations are executed in
ALU of the processor.
 Load the operands into memory – bring them
to the processor – perform operation in ALU
– store the result back to memory or retain in
the processor.
 Registers
 Fast control of ALU

C.Bala Subramanian, AP/CSE, KLU 6

Control Unit
 All computer operations are controlled by the control
unit.
 The timing signals that govern the I/O transfers are
also generated by the control unit.
 Control unit is usually distributed throughout the
machine instead of standing alone.
 Operations of a computer:
 Accept information in the form of programs and data through an
input unit and store it in the memory
 Fetch the information stored in the memory, under program control,
into an ALU, where the information is processed
 Output the processed information through an output unit
 Control all activities inside the machine through a control unit

C.Bala Subramanian, AP/CSE, KLU 7

Basic Operational
Concepts

C.Bala Subramanian, AP/CSE, KLU 8

Review
 Activity in a computer is governed by instructions.
 To perform a task, an appropriate program
consisting of a list of instructions is stored in the
memory.
 Individual instructions are brought from the memory
into the processor, which executes the specified
operations.
 Data to be used as operands are also stored in the
memory.

C.Bala Subramanian, AP/CSE, KLU 9

A Typical Instruction
 Add LOCA, R0
 Add the operand at memory location LOCA to the
operand in a register R0 in the processor.
 Place the sum into register R0.
 The original contents of LOCA are preserved.
 The original contents of R0 is overwritten.
 Instruction is fetched from the memory into the
processor – the operand at LOCA is fetched and
added to the contents of R0 – the resulting sum is
stored in register R0.

C.Bala Subramanian, AP/CSE, KLU 10

Separate Memory Access and
ALU Operation
 Load LOCA, R1
 Add R1, R0
 Whose contents will be overwritten?

C.Bala Subramanian, AP/CSE, KLU 11

Connection Between the
Processor and the Memory
Memory

MAR MDR
Control

PC R0

R1
Processor
IR

ALU
Rn - 1

n general purpose
registers

C.Bala Subramanian, AP/CSE, KLU 12

Figure 1.2. Connections between the processor and the memory.
Registers
 Instruction register (IR)
 Program counter (PC)
 General-purpose register (R0 – Rn-1)
 Memory address register (MAR)
 Memory data register (MDR)

C.Bala Subramanian, AP/CSE, KLU 13

Typical Operating Steps
 Programs reside in the memory through input
devices
 PC is set to point to the first instruction
 The contents of PC are transferred to MAR
 A Read signal is sent to the memory
 The first instruction is read out and loaded
into MDR
 The contents of MDR are transferred to IR
 Decode and execute the instruction
C.Bala Subramanian, AP/CSE, KLU 14
Typical Operating Steps
(Cont’)
 Get operands for ALU
 General-purpose register
 Memory (address to MAR – Read – MDR to ALU)
 Perform operation in ALU
 Store the result back
 To general-purpose register
 To memory (address to MAR, result to MDR – Write)
 During the execution, PC is
incremented to the next instruction
C.Bala Subramanian, AP/CSE, KLU 15
Interrupt
 Normal execution of programs may be preempted if
some device requires urgent servicing.
 The normal execution of the current program must
be interrupted – the device raises an interrupt
signal.
 Interrupt-service routine
 Current system information backup and restore (PC,
general-purpose registers, control information,
specific information)

C.Bala Subramanian, AP/CSE, KLU 16

Bus Structures
 There are many ways to connect different
parts inside a computer together.
 A group of lines that serves as a connecting
path for several devices is called a bus.
 Address/data/control

C.Bala Subramanian, AP/CSE, KLU 17

Bus Structure
 Single-bus

Input Output Memory Processor

Figure 1.3. Single-bus structure.

C.Bala Subramanian, AP/CSE, KLU 18

Speed Issue
 Different devices have different
transfer/operate speed.
 If the speed of bus is bounded by the slowest
device connected to it, the efficiency will be
very low.
 How to solve this?
 A common approach – use buffers.

C.Bala Subramanian, AP/CSE, KLU 19

Performance

C.Bala Subramanian, AP/CSE, KLU 20

Performance
 The most important measure of a computer is
how quickly it can execute programs.
 Three factors affect performance:
 Hardware design
 Instruction set
 Compiler

C.Bala Subramanian, AP/CSE, KLU 21

Performance
 Processor time to execute a program depends on the hardware
involved in the execution of individual machine instructions.

Main Cache
memory memory Processor

Bus

Figure 1.5. The processor cache.

C.Bala Subramanian, AP/CSE, KLU 22
Performance
 The processor and a relatively small cache
memory can be fabricated on a single
integrated circuit chip.
 Speed
 Cost
 Memory management

C.Bala Subramanian, AP/CSE, KLU 23

Processor Clock
 Clock, clock cycle, and clock rate
 The execution of each instruction is divided
into several steps, each of which completes
in one clock cycle.
 Hertz – cycles per second

C.Bala Subramanian, AP/CSE, KLU 24

Basic Performance Equation
 T – processor time required to execute a program that has been
prepared in high-level language
 N – number of actual machine language instructions needed to
complete the execution (note: loop)
 S – average number of basic steps needed to execute one
machine instruction. Each step completes in one clock cycle
 R – clock rate
 Note: these are not independent to each other

N S
T
R
How to improve T?

C.Bala Subramanian, AP/CSE, KLU 25

Pipeline and Superscalar
Operation
 Instructions are not necessarily executed one after
another.
 The value of S doesn’t have to be the number of
clock cycles to execute one instruction.
 Pipelining – overlapping the execution of successive
instructions.
 Add R1, R2, R3
 Superscalar operation – multiple instruction
pipelines are implemented in the processor.
 Goal – reduce S (could become <1!)

C.Bala Subramanian, AP/CSE, KLU 26

Clock Rate
 Increase clock rate
 Improve the integrated-circuit (IC) technology to make
the circuits faster
 Reduce the amount of processing done in one basic step
(however, this may increase the number of basic steps
needed)
 Increases in R that are entirely caused by
improvements in IC technology affect all
aspects of the processor’s operation equally
except the time to access the main memory.

C.Bala Subramanian, AP/CSE, KLU 27

CISC and RISC
 Tradeoff between N and S
 A key consideration is the use of pipelining
 S is close to 1 even though the number of basic steps
per instruction may be considerably larger
 It is much easier to implement efficient pipelining in
processor with simple instruction sets
 Reduced Instruction Set Computers (RISC)
 Complex Instruction Set Computers (CISC)

C.Bala Subramanian, AP/CSE, KLU 28

Compiler
 A compiler translates a high-level language program
into a sequence of machine instructions.
 To reduce N, we need a suitable machine instruction
set and a compiler that makes good use of it.
 Goal – reduce N×S
 A compiler may not be designed for a specific
processor; however, a high-quality compiler is
usually designed for, and with, a specific processor.

C.Bala Subramanian, AP/CSE, KLU 29

Performance Measurement
 T is difficult to compute.
 Measure computer performance using benchmark programs.
 System Performance Evaluation Corporation (SPEC) selects and
publishes representative application programs for different application
domains, together with test results for many commercially available
computers.
 Compile and run (no simulation)
 Reference computer

Running time on the reference computer

SPEC rating 
Running time on the computer under test
n 1
SPEC rating  (  SPEC i ) n

i 1

C.Bala Subramanian, AP/CSE, KLU 30

Multiprocessors and
Multicomputers
 Multiprocessor computer
 Execute a number of different application tasks in parallel
 Execute subtasks of a single large task in parallel
 All processors have access to all of the memory – shared-memory
multiprocessor
 Cost – processors, memory units, complex interconnection networks
 Multicomputers
 Each computer only have access to its own memory
 Exchange message via a communication network – message-
passing multicomputers

C.Bala Subramanian, AP/CSE, KLU 31

Chapter 2. Machine
Instructions and
Programs

C.Bala Subramanian, AP/CSE, KLU 32

Objectives
 Machine instructions and program execution,
including branching and subroutine call and return
operations.
 Number representation and addition/subtraction in
the 2’s-complement system.
 Addressing methods for accessing register and
memory operands.
 Assembly language for representing machine
instructions, data, and programs.
 Program-controlled Input/Output operations.
C.Bala Subramanian, AP/CSE, KLU 33
Number, Arithmetic
Operations, and
Characters

C.Bala Subramanian, AP/CSE, KLU 34

Signed Integer
 3 major representations:
Sign and magnitude
One’s complement
Two’s complement
 Assumptions:
4-bit machine word
16 different values can be represented
Roughly half are positive, half are negative

C.Bala Subramanian, AP/CSE, KLU 35

Sign and Magnitude
Representation
-7 +0
-6 1111 0000 +1
1110 0001
-5 +2 +
1101 0010
-4 1100 0011 +3 0 100 = + 4

-3 1011 0100 +4 1 100 = - 4

1010 0101
-2 +5 -
1001 0110
-1 1000 0111 +6
-0 +7
High order bit is sign: 0 = positive (or zero), 1 = negative
Three low order bits is the magnitude: 0 (000) thru 7 (111)
Number range for n bits = +/-2n-1 -1
Two representations for 0
C.Bala Subramanian, AP/CSE, KLU 36
One’s Complement
Representation
-0 +0
-1 1111 0000 +1
1110 0001
-2 +2 +
1101 0010
-3 1100 0011 +3 0 100 = + 4

-4 1011 0100 +4 1 011 = - 4

1010 0101
-5 +5 -
1001 0110
-6 1000 0111 +6
-7 +7
 Subtraction implemented by addition & 1's complement
 Still two representations of 0! This causes some problems
 Some complexities in addition
C.Bala Subramanian, AP/CSE, KLU 37
Two’s Complement
Representation
-1 +0
-2 1111 0000 +1
1110 0001
-3 +2 +
like 1's comp 1101 0010
except shifted -4 1100 0011 +3 0 100 = + 4
one position
clockwise -5 1011 0100 +4 1 100 = - 4
1010 0101
-6 +5 -
1001 0110
-7 1000 0111 +6
-8 +7

 Only one representation for 0

 One more negative number than positive
number
C.Bala Subramanian, AP/CSE, KLU 38
 Binary, Signed-Integer
Representations
B Values represented
Page 28
Sign and
b3 b2b1b0 magnitude 1's complement 2's complement

0 1 1 1 + 7 +7 + 7
0 1 1 0 + 6 +6 + 6
0 1 0 1 + 5 +5 + 5
0 1 0 0 + 4 +4 + 4
0 0 1 1 + 3 +3 + 3
0 0 1 0 + 2 +2 + 2
0 0 0 1 + 1 + 1 + 1
0 0 0 0 + 0 +0 + 0
1 0 0 0 - 0 -7 - 8
1 0 0 1 - 1 -6 - 7
1 0 1 0 - 2 -5 - 6
1 0 1 1 - 3 -4 - 5
1 1 0 0 - 4 -3 - 4
1 1 0 1 - 5 -2 - 3
1 1 1 0 - 6 - 1 - 2
1 1 1 1 - 7 -0 - 1

C.Bala Subramanian, AP/CSE, KLU 39

Figure 2.1. Binary, signed-integer representations.
Addition and Subtraction – 2’s
Complement
4 0100 -4 1100
+3 0011 + (-3) 1101
If carry-in to the high
order bit = 7 0111 -7 11001
carry-out then ignore
carry

if carry-in differs from 4 0100 -4 1100

carry-out then overflow
-3 1101 +3 0011
1 10001 -1 1111

Simpler addition scheme makes twos complement the most common

choice for integer number systems within digital systems
C.Bala Subramanian, AP/CSE, KLU 40
 2’s-Complement Add and
Subtract Operations
(a) 0010 ( + 2) (b) 0100 ( + 4)
+ 0011 ( + 3) + 1010 (- 6 )
Page 31 (- 2 )
0101 ( + 5) 1110
(c) 1011 (- 5) (d) 0111 ( + 7)
+ 1110 (- 2) + 1101 ( - 3)
1001 (- 7) 0100 ( + 4)
(e) 1101 (- 3) 1101
- 1001 (- 7 ) + 0111
0100 ( + 4)
(f) 0010 ( + 2) 0010
- 0100 ( + 4) + 1100
1110 ( - 2)
(g) 0110 ( + 6) 0110
- 0011 ( + 3) + 1101
0011 ( + 3)
(h) 1001 ( - 7) 1001
- 1011 (- 5) + 0101
1110 ( - 2)
(i) 1001 (- 7) 1001
- 0001 ( + 1) + 1111
1000 ( - 8)
(j) 0010 ( + 2) 0010
- 1101 ( - 3) + 0011
0101 ( + 5)
C.Bala Subramanian, AP/CSE, KLU 41
Figure 2.4. 2's-complement Add and Subtract operations.
Overflow - Add two positive numbers to get a
negative number or two negative numbers to
get a positive number

-1 +0 -1 +0
-2 1111 0000 +1 -2 1111 0000 +1
1110 0001 1110 0001
-3 +2 -3
1101 1101 +2
0010 0010
-4 -4
1100 0011 +3 1100 0011 +3
-5 1011 -5 1011
0100 +4 0100 +4
1010 1010
-6 0101 -6 0101
1001
+5 +5
0110 1001
0110
-7 1000 0111 +6 -7 1000 +6
0111
-8 +7 -8 +7

5 + 3 = -8 -7 - 2 = +7
C.Bala Subramanian, AP/CSE, KLU 42
Overflow Conditions
0111 1000
5 0101 -7 1001
3 0011 -2 1100
-8 1000 7 10111
Overflow Overflow
0000 1111
5 0101 -3 1101
2 0010 -5 1011
7 0111 -8 11000
No overflow No overflow
Overflow when carry-in to the high-order bit does not equal carry out
C.Bala Subramanian, AP/CSE, KLU 43
 Sign Extension
 Task:
 Given w-bit signed integer x

 Convert it to w+k-bit integer with same value

 Rule:
 Make k copies of sign bit:

 X  = xw–1 ,…, xw–1 , xw–1 , xw–2 ,…, x0

w
X • • •
k copies of MSB

• • •

X • • • • • •
k
C.Bala Subramanian, AP/CSE, KLU w 44
Sign Extension Example

short int x = 15213;

int ix = (int) x;
short int y = -15213;
int iy = (int) y;

Decimal Hex Binary

x 15213 3B 6D 00111011 01101101
ix 15213 00 00 C4 92 00000000 00000000 00111011 01101101
y -15213 C4 93 11000100 10010011
iy -15213 FF FF C4 93 11111111 11111111 11000100 10010011

C.Bala Subramanian, AP/CSE, KLU 45

Memory Locations,
Addresses, and
Operations

C.Bala Subramanian, AP/CSE, KLU 46

Memory Location, Addresses,
and Operation
n bits
first word
 Memory consists
second word
of many millions of
storage cells,
•
each of which can •
•
store 1 bit.
 Data is usually i th word
accessed in n-bit
groups. n is called •
word length. •
•

last word
C.Bala Subramanian, AP/CSE, KLU 47

Figure 2.5. Memory words.

Memory Location, Addresses,
and Operation
 32-bit word length example
32 bits

b 31 b 30 b1 b0

•
•
•
Sign bit: b 31= 0 for positive numbers
b 31= 1 for negative numbers

(a) A signed integer

8 bits 8 bits 8 bits 8 bits

ASCII ASCII ASCII ASCII

character character character
C.Bala Subramanian, AP/CSE, KLU
character 48

(b) Four characters

Memory Location, Addresses,
and Operation
 To retrieve information from memory, either for one
word or one byte (8-bit), addresses for each location
are needed.
 A k-bit address memory has 2k memory locations,
namely 0 – 2k-1, called memory space.
 24-bit memory: 224 = 16,777,216 = 16M (1M=220)
 32-bit memory: 232 = 4G (1G=230)
 1K(kilo)=210
 1T(tera)=240

C.Bala Subramanian, AP/CSE, KLU 49

Memory Location, Addresses,
and Operation
 It is impractical to assign distinct addresses
to individual bit locations in the memory.
 The most practical assignment is to have
successive addresses refer to successive
byte locations in the memory – byte-
addressable memory.
 Byte locations have addresses 0, 1, 2, … If
word length is 32 bits, they successive words
are located at addresses 0, 4, 8,…
C.Bala Subramanian, AP/CSE, KLU 50
Big-Endian and Little-Endian
Assignments
Big-Endian: lower byte addresses are used for the most significant bytes of the word
Little-Endian: opposite ordering. lower byte addresses are used for the less significant
bytes of the word
Word
address Byte address Byte address

0 0 1 2 3 0 3 2 1 0

4 4 5 6 7 4 7 6 5 4

• •
• •
• •

k k k k k k k k k k
2 -4 2 -4 2 -3 2 - 2 2 - 1 2 - 4 2 - 1 2 - 2 2 -3 2 -4

(a) Big-endian assignment (b) Little-endian assignment

C.Bala Subramanian, AP/CSE, KLU 51
Figure 2.7. Byte and word addressing.
Memory Location, Addresses,
and Operation
 Address ordering of bytes
 Word alignment
 Words are said to be aligned in memory if they
begin at a byte addr. that is a multiple of the num
of bytes in a word.
 16-bit word: word addresses: 0, 2, 4,….
 32-bit word: word addresses: 0, 4, 8,….
 64-bit word: word addresses: 0, 8,16,….
 Access numbers, characters, and character
strings
C.Bala Subramanian, AP/CSE, KLU 52
Memory Operation
 Load (or Read or Fetch)
 Copy the content. The memory content doesn’t change.
 Address – Load
 Registers can be used
 Store (or Write)
 Overwrite the content in memory
 Address and Data – Store
 Registers can be used

C.Bala Subramanian, AP/CSE, KLU 53

Instruction and
Instruction
Sequencing

C.Bala Subramanian, AP/CSE, KLU 54

“Must-Perform” Operations
 Data transfers between the memory and the
processor registers
 Arithmetic and logic operations on data
 Program sequencing and control
 I/O transfers

C.Bala Subramanian, AP/CSE, KLU 55

Register Transfer Notation
 Identify a location by a symbolic name
standing for its hardware binary address
(LOC, R0,…)
 Contents of a location are denoted by placing
square brackets around the name of the
location (R1←[LOC], R3 ←[R1]+[R2])
 Register Transfer Notation (RTN)

C.Bala Subramanian, AP/CSE, KLU 56

Assembly Language Notation
 Represent machine instructions and
programs.
 Move LOC, R1 = R1←[LOC]
 Add R1, R2, R3 = R3 ←[R1]+[R2]

C.Bala Subramanian, AP/CSE, KLU 57

CPU Organization
 Single Accumulator
 Result usually goes to the Accumulator
 Accumulator has to be saved to memory quite
often
 General Register
 Registers hold operands thus reduce memory
traffic
 Register bookkeeping
 Stack
 Operands and result are always in the stack
C.Bala Subramanian, AP/CSE, KLU 58
Instruction Formats
 Three-Address Instructions
 ADD R1, R2, R3 R3 ← R1 + R2
 Two-Address Instructions
 ADD R1, R2 R2 ← R1 + R2
 One-Address Instructions
 ADD M AC ← AC + M[AR]
 Zero-Address Instructions
 ADD TOS ← TOS + (TOS – 1)

Opcode C.Bala
Operand(s) or Address(es)
Subramanian, AP/CSE, KLU 59
Instruction Formats
Example: Evaluate (A+B)  (C+D)
 Three-Address
1. ADD A, B, R1 ; R1 ← M[A] + M[B]
2. ADD C, D, R2 ; R2 ← M[C] + M[D]
3. MUL R1, R2, X ; M[X] ← R1  R2

C.Bala Subramanian, AP/CSE, KLU 60

Instruction Formats
Example: Evaluate (A+B)  (C+D)
 Two-Address
1. MOV A,R1 ; R1 ← M[A]
2. ADD B,R1 ; R1 ← R1 + M[B]
3. MOV C, R2 ; R2 ← M[C]
4. ADD D,R2 ; R2 ← R2 + M[D]
5. MUL R1, R2 ; R2 ← R1  R2
6. MOV R2, X ; M[X] ← R2

C.Bala Subramanian, AP/CSE, KLU 61

Instruction Formats
Example: Evaluate (A+B)  (C+D)
 One-Address
1. LOAD A ; AC ← M[A]
2. ADD B ; AC ← AC + M[B]
3. STORET ; M[T] ← AC
4. LOAD C ; AC ← M[C]
5. ADD D ; AC ← AC + M[D]
6. MUL T ; AC ← AC  M[T]
7. STOREX ; M[X] ← AC

C.Bala Subramanian, AP/CSE, KLU 62

Using Registers
 Registers are faster
 Shorter instructions
 The number of registers is smaller (e.g. 32
registers need 5 bits)
 Potential speedup
 Minimize the frequency with which data is
moved back and forth between the memory
and processor registers.

C.Bala Subramanian, AP/CSE, KLU 63

 Instruction Execution and
Straight-Line Sequencing
Address Contents

i
Assumptions:
Begin execution here Move A,R0
i+4
3-instruction
program
- One memory operand
Add B,R0
i+8
segment per instruction
Move R0,C
- 32-bit word length
- Memory is byte
addressable
A - Full memory address
can be directly specified
in a single-word instruction
B Data for
the program
Two-phase procedure
-Instruction fetch
-Instruction execute
C
Page 43

C.Bala Subramanian, AP/CSE, KLU 64

Figure 2.8. A program for C  [A] + [B].
 i Move NUM1,R0
i+4 Add NUM2,R0

Branching i+8 Add NUM3,R0

•
•
•
i + 4n - 4 Add NUM n,R0
i + 4n Move R0,SUM

•
•
•
SUM
NUM1
NUM2

•
•
•
NUM n

C.Bala Subramanian, AP/CSE, KLU 65

Figure 2.9. A straight-line program for adding n numbers.
 Move N,R1
Clear R0

Branching LOOP
Determine address of
"Next" number and add
Program "Next" number to R0
loop
Decrement R1
Branch>0 LOOP
Branch target
Move R0,SUM

Conditional branch
•
•
•
SUM
N n
NUM1

Figure 2.10. Using a loop to add n numbers. NUM2

•
•
•
NUM nAP/CSE, KLU
C.Bala Subramanian, 66
Condition Codes
 Condition code flags
 Condition code register / status register
 N (negative)
 Z (zero)
 V (overflow)
 C (carry)
 Different instructions affect different flags

C.Bala Subramanian, AP/CSE, KLU 67

Conditional Branch
Instructions
 Example: A: 11110000

 A: 1 1 1 1 0 0 0 0 +(−B): 1 1 1 0 1 1 0 0
 B: 0 0 0 1 0 1 0 0 11011100

C=1 Z=0
S=1
V=0

C.Bala Subramanian, AP/CSE, KLU 68

Status Bits

Cn-1
A B

Cn ALU
F
V Z S C
Fn-1

Zero Check

C.Bala Subramanian, AP/CSE, KLU 69

Addressing
Modes

C.Bala Subramanian, AP/CSE, KLU 70

Generating Memory Addresses
 How to specify the address of branch target?
 Can we give the memory operand address
directly in a single Add instruction in the loop?
 Use a register to hold the address of NUM1;
then increment by 4 on each pass through
the loop.

C.Bala Subramanian, AP/CSE, KLU 71

Addressing Modes

Opcode Mode ...

 Implied
 AC is implied in “ADD M[AR]” in “One-Address”
instr.
 TOS is implied in “ADD” in “Zero-Address” instr.
 Immediate
 The use of a constant in “MOV R1, 5”, i.e. R1 ←
5
 Register
 Indicate which register holds the operand
C.Bala Subramanian, AP/CSE, KLU 72
Addressing Modes
 Register Indirect
 Indicate the register that holds the number of the
register that holds the operand R1
MOV R1, (R2)
R2 = 3
 Autoincrement / Autodecrement
 Access & update in 1 instr. R3 = 5

 Direct Address
 Use the given address to access a memory
location

C.Bala Subramanian, AP/CSE, KLU 73

Addressing Modes
 Indirect Address
 Indicate the memory location that holds the
address of the memory location that holds the
data
AR = 101

100
101 0 1 0 4
102
103
104 1 1 0 A

C.Bala Subramanian, AP/CSE, KLU 74

Addressing Modes

 Relative Address
0
 EA = PC + Relative Addr 1
PC = 2 2

100
AR = 100
101
102 1 1 0 A
Could be Positive or 103
Negative 104
(2’s Complement)

C.Bala Subramanian, AP/CSE, KLU 75

 Addressing Modes
 Indexed
 EA = Index Register + Relative Addr

Useful with XR = 2
“Autoincrement” or
“Autodecrement”
+

100
AR = 100
101
Could be Positive or
Negative 102 1 1 0 A
(2’s Complement) 103
104

C.Bala Subramanian, AP/CSE, KLU 76

 Addressing Modes
 Base Register
 EA = Base Register + Relative Addr

Could be Positive or AR = 2
Negative
(2’s Complement)
+

100 0 0 0 5
BR = 100
101 0 0 1 2
102 0 0 0 A
Usually points to 103 0 1 0 7
the beginning of 104 0 0 5 9
an array

C.Bala Subramanian, AP/CSE, KLU 77

 Addressing Modes
Name Assem bler syn tax Addressing function
 The different
ways in which Immediate #V alue Op erand = Value
the location of
an operand is Register Ri EA = R i
specified in Absolute (Direct) LOC EA = LOC
an instruction
are referred Indirect (R i ) EA = [R i ]
to as (LOC) EA = [LOC]
addressing
modes. Index X(R i) EA = [R i ] + X

Base with index (R i ,R j ) EA = [R i ] + [R j ]

Base with index X(R i,R j ) EA = [R i ] + [R j ] + X
and offset

Relative X(PC) EA = [PC] + X

Autoincremen t (R i )+ EA = [R i ] ;
Incremen t R i

Autodecrement  (R i )
C.Bala Subramanian, AP/CSE, KLU
Decremen t R i ; 78
EA = [R i]
Indexing and Arrays
 Index mode – the effective address of the operand
is generated by adding a constant value to the
contents of a register.
 Index register
 X(Ri): EA = X + [Ri]
 The constant X may be given either as an explicit
number or as a symbolic name representing a
numerical value.
 If X is shorter than a word, sign-extension is needed.

C.Bala Subramanian, AP/CSE, KLU 79

Indexing and Arrays
 In general, the Index mode facilitates access
to an operand whose location is defined
relative to a reference point within the data
structure in which the operand appears.
 Several variations:
(Ri, Rj): EA = [Ri] + [Rj]
X(Ri, Rj): EA = X + [Ri] + [Rj]

C.Bala Subramanian, AP/CSE, KLU 80

Relative Addressing
 Relative mode – the effective address is determined
by the Index mode using the program counter in
place of the general-purpose register.
 X(PC) – note that X is a signed number
 Branch>0 LOOP
 This location is computed by specifying it as an
offset from the current value of PC.
 Branch target may be either before or after the
branch instruction, the offset is given as a singed
num.
C.Bala Subramanian, AP/CSE, KLU 81
Additional Modes
 Autoincrement mode – the effective address of the operand is
the contents of a register specified in the instruction. After
accessing the operand, the contents of this register are
automatically incremented to point to the next item in a list.
 (Ri)+. The increment is 1 for byte-sized operands, 2 for 16-bit
operands, and 4 for 32-bit operands.
 Autodecrement mode: -(Ri) – decrement first
Move N,R1
Move #NUM1,R2 Initialization
Clear R0
LOOP Add (R2)+,R0
Decrement R1
Branch>0 LOOP
Move R0,SUM

C.Bala Subramanian, AP/CSE, KLU 82

Figure 2.16. The Autoincrement addressing mode used in the program of Figure 2.12.
Assembly
Language

C.Bala Subramanian, AP/CSE, KLU 83

Types of Instructions
 Data Transfer Instructions
Name Mnemonic Data value is
Load LD not modified
Store ST
Move MOV
Exchange XCH
Input IN
Output OUT
Push PUSH
Pop POP

C.Bala Subramanian, AP/CSE, KLU 84

 Data Transfer Instructions
Mode Assembly Register Transfer
Direct address LD ADR AC ← M[ADR]
Indirect address LD @ADR AC ← M[M[ADR]]
Relative address LD $ADR AC ← M[PC+ADR]
Immediate operand LD #NBR AC ← NBR
Index addressing LD ADR(X) AC ← M[ADR+XR]
Register LD R1 AC ← R1
Register indirect LD (R1) AC ← M[R1]
Autoincrement LD (R1)+ AC ← M[R1], R1 ← R1+1

C.Bala Subramanian, AP/CSE, KLU 85

 Data Manipulation Instructions
 Arithmetic Name Mnemonic
Increment INC
 Logical & Bit Manipulation Decrement DEC
Add ADD
 Shift Subtract SUB
Multiply MUL
Divide DIV
Name Mnemonic Add with carry ADDC
Clear CLR Subtract with borrow SUBB
Complement COM Negate NEG
Name Mnemonic
AND AND Logical shift right SHR
OR OR Logical shift left SHL
Exclusive-OR XOR Arithmetic shift right SHRA
Clear carry CLRC Arithmetic shift left SHLA
Set carry SETC Rotate right ROR
Complement carry COMC Rotate left ROL
Enable interrupt EI Rotate right through carry RORC
C.Bala Subramanian, AP/CSE, KLU 86
Disable interrupt DI Rotate left through carry ROLC
Program Control Instructions
Name Mnemonic
Branch BR
Jump JMP
Skip SKP
Subtract A – B but
Call CALL don’t store the result

Return RET
Compare
CMP
(Subtract) 10110001
Test (AND) TST
00001000

Mask
00000000
C.Bala Subramanian, AP/CSE, KLU 87
Conditional Branch
Instructions

Mnemonic Branch Condition Tested Condition

BZ Branch if zero Z=1
BNZ Branch if not zero Z=0
BC Branch if carry C=1
BNC Branch if no carry C=0
BP Branch if plus S=0
BM Branch if minus S=1
BV Branch if overflow V=1
BNV Branch if no overflow V=0

C.Bala Subramanian, AP/CSE, KLU 88

 Basic
Input/Output
Operations

C.Bala Subramanian, AP/CSE, KLU 89

I/O
 The data on which the instructions operate
are not necessarily already stored in memory.
 Data need to be transferred between
processor and outside world (disk, keyboard,
etc.)
 I/O operations are essential, the way they are
performed can have a significant effect on the
performance of the computer.

C.Bala Subramanian, AP/CSE, KLU 90

Program-Controlled I/O
Example
 Read in character input from a keyboard and
produce character output on a display screen.
 Rate of data transfer (keyboard, display, processor)
 Difference in speed between processor and I/O device
creates the need for mechanisms to synchronize the
transfer of data.
 A solution: on output, the processor sends the first
character and then waits for a signal from the display
that the character has been received. It then sends the
second character. Input is sent from the keyboard in a
similar way.

C.Bala Subramanian, AP/CSE, KLU 91

Program-Controlled I/O
Example
Bus

Processor
DATAIN DATAOUT

SIN SOUT
- Registers
- Flags Keyboard Display
- Device interface

Figure 2.19 Bus connection for processor

, keyboard, and display
.

C.Bala Subramanian, AP/CSE, KLU 92

Program-Controlled I/O
Example
 Machine instructions that can check the state
of the status flags and transfer data:
READWAIT Branch to READWAIT if SIN = 0
Input from DATAIN to R1

WRITEWAIT Branch to WRITEWAIT if SOUT = 0

Output from R1 to DATAOUT

C.Bala Subramanian, AP/CSE, KLU 93

Program-Controlled I/O
Example
 Memory-Mapped I/O – some memory
address values are used to refer to peripheral
device buffer registers. No special
instructions are needed. Also use device
status registers.

READWAIT Testbit #3, INSTATUS

Branch=0 READWAIT
MoveByte DATAIN, R1

C.Bala Subramanian, AP/CSE, KLU 94

 Program-Controlled I/O
Example
 Assumption – the initial state of SIN is 0 and the
initial state of SOUT is 1.
 Any drawback of this mechanism in terms of
efficiency?
 Two wait loopsprocessor execution time is wasted
 Alternate solution?
 Interrupt

C.Bala Subramanian, AP/CSE, KLU 95

 Stacks

C.Bala Subramanian, AP/CSE, KLU 96

Home Work
 For each Addressing modes mentioned
before, state one example for each
addressing mode stating the specific benefit
for using such addressing mode for such an
application.

C.Bala Subramanian, AP/CSE, KLU 97

Stack Organization

Current
Top of Stack
 LIFO TOS 0
Last In First Out 1
2
3
4
5
SP 6 0 1 2 3
7 0 0 5 5
FULL EMPTY 8 0 0 0 8
9 0 0 2 5
Stack Bottom 10 0 0 1 5
Stack
C.Bala Subramanian, AP/CSE, KLU 98
Stack Organization

Current 1 6 9 0
Top of Stack
 PUSH TOS 0
SP ← SP – 1 1
M[SP] ← DR 2
3
If (SP = 0) then (FULL ← 1) 4
EMPTY ← 0 5 1 6 9 0
SP 6 0 1 2 3
7 0 0 5 5
FULL EMPTY 8 0 0 0 8
9 0 0 2 5
Stack Bottom 10 0 0 1 5
Stack
C.Bala Subramanian, AP/CSE, KLU 99
Stack Organization
Current
Top of Stack
 POP TOS 0
DR ← M[SP] 1
SP ← SP + 1 2
3
If (SP = 11) then (EMPTY ← 1) 4
FULL ← 0 5 1 6 9 0
SP 6 0 1 2 3
7 0 0 5 5
FULL EMPTY 8 0 0 0 8
9 0 0 2 5
Stack Bottom 10 0 0 1 5
Stack
C.Bala Subramanian, AP/CSE, KLU 100
Stack Organization
 Memory Stack
 PUSH PC 0
1
SP ← SP – 1 2
M[SP] ← DR
 POP AR 100
DR ← M[SP] 101
102
SP ← SP + 1
200
SP 201
202

C.Bala Subramanian, AP/CSE, KLU 101

Reverse Polish Notation
 Infix Notation
A+B
 Prefix or Polish Notation
+AB
 Postfix or Reverse Polish Notation (RPN)
AB+
(2) (4)  (3) (3)  +
RPN (8) (3) (3)  +
AB+CD ABCD+
(8) (9) +
17
C.Bala Subramanian, AP/CSE, KLU 102
Reverse Polish Notation
 Example
(A + B)  [C  (D + E) + F]

(A B +) (D E +) C  F + 

C.Bala Subramanian, AP/CSE, KLU 103

Reverse Polish Notation

 Stack Operation
(3) (4)  (5) (6)  +
PUSH 3
PUSH 4
6
MULT
PUSH 5 30
4
5
PUSH 6
3
42
12
MULT
ADD
C.Bala Subramanian, AP/CSE, KLU 104
 Additional
Instructions

C.Bala Subramanian, AP/CSE, KLU 105

Logical Shifts
 Logical shift – shifting left (LShiftL) and shifting right
(LShiftR)
C R0 0

before: 0 0 1 1 1 0 . . . 0 1 1

after: 1 1 1 0 . . . 0 1 1 0 0

(a) Logical shift left LShiftL #2,R0

0 R0 C

before: 0 1 1 1 0 . . . 0 1 1 0

after: 0 0 0 1 1 1 0 . . . 0 1

(b) Logical C.Bala

shift r ight LShiftR
Subramanian, AP/CSE, KLU #2,R0 106
Arithmetic Shifts

R0 C

before: 1 0 0 1 1 . . . 0 1 0 0

after: 1 1 1 0 0 1 1 . . . 0 1

(c) Ar ithmetic shift right AShiftR #2,R0

C.Bala Subramanian, AP/CSE, KLU 107

 C R0

before: 0 1 1 1 0 . . . 0 1 1

Rotate
0

after: 1 1 1 0 . . . 0 1 1 0 1

(a) Rotate left without carry RotateL #2,R0

C R0

before: 0 0 1 1 1 0 . . . 0 1 1

after: 1 1 1 0 . . . 0 1 1 0 0

(b) Rotate left with carry RotateLC #2,R0

R0 C

before: 0 1 1 1 0 . . . 0 1 1 0

after: 1 1 0 1 1 1 0 . . . 0 1

(c) Rotate right without carry RotateR #2,R0

R0 C

before: 0 1 1 1 0 . . . 0 1 1 0

after: 1 0 0 1 1 1 0 . . . 0 1

(d) Rotate right with carry RotateRC #2,R0

C.Bala Subramanian, AP/CSE, KLU 108
Figure 2.32. Rotate instructions.
Multiplication and Division
 Not very popular (especially division)
 Multiply Ri, Rj
Rj ← [Ri] х [Rj]
 2n-bit product case: high-order half in R(j+1)
 Divide Ri, Rj
Rj ← [Ri] / [Rj]
Quotient is in Rj, remainder may be placed in R(j+1)

C.Bala Subramanian, AP/CSE, KLU 109

Encoding of
Machine
Instructions

C.Bala Subramanian, AP/CSE, KLU 110

Encoding of Machine
Instructions
 Assembly language program needs to be converted into machine
instructions. (ADD = 0100 in ARM instruction set)
 In the previous section, an assumption was made that all
instructions are one word in length.
 OP code: the type of operation to be performed and the type of
operands used may be specified using an encoded binary pattern
 Suppose 32-bit word length, 8-bit OP code (how many instructions
can we have?), 16 registers in total (how many bits?), 3-bit
addressing mode indicator.
 Add R1, R2 8 7 7 10
 Move 24(R0), R5
OP code Source Dest Other info
 LshiftR #2, R0
 Move #$3A, R1
 Branch>0 LOOP (a) One-word instruction

C.Bala Subramanian, AP/CSE, KLU 111

Encoding of Machine
Instructions
 What happens if we want to specify a memory
operand using the Absolute addressing mode?
 Move R2, LOC
 14-bit for LOC – insufficient
 Solution – use two words

OP code Source Dest Other info

Memory address/Immediate operand

(b) Two-word instruction

C.Bala Subramanian, AP/CSE, KLU 112

Encoding of Machine
Instructions
 Then what if an instruction in which two operands
can be specified using the Absolute addressing
mode?
 Move LOC1, LOC2
 Solution – use two additional words
 This approach results in instructions of variable
length. Complex instructions can be implemented,
closely resembling operations in high-level
programming languages – Complex Instruction Set
Computer (CISC)
C.Bala Subramanian, AP/CSE, KLU 113
Encoding of Machine
Instructions
 If we insist that all instructions must fit into a single
32-bit word, it is not possible to provide a 32-bit
address or a 32-bit immediate operand within the
instruction.
 It is still possible to define a highly functional
instruction set, which makes extensive use of the
processor registers.
 Add R1, R2 ----- yes
 Add LOC, R2 ----- no
 Add (R3), R2 ----- yes
C.Bala Subramanian, AP/CSE, KLU 114