Digital Logic Circuit Design Project
Digital Logic Circuit Design Project
Digital Design
Design project
Course: EE200
Instructor's name:
Semester:
Due date:
1
EE200: Digital Design
Problem
A committee is composed of a chairman (C), a senior member (S), and a member (M).
The rules of the committee state that:
• The vote of the member (M) will be counted as 1 vote
• The vote of the senior member will be counted as 2 votes.
• The vote of the chairman will be counted as 4 votes.
Each of these persons has a switch to close (“l”) when voting yes and to open (“0”) when voting no.
It is necessary to design a circuit that displays the total number of votes for each issue.
Conditions:
• If all members vote no for an issue the display should be blank.
• If all members vote yes for an issue, the display should be 0.
• Otherwise the display shows a decimal number equal to the number of 'yes' votes.
Use four 4x1 multiplexers to design the logic and a seven-segment display (decoder embedded) to
display the required number.
Use following representation for multiplexer and seven-segment display (decoder embedded) to draw
your circuit using logic works.
Marking Scheme:
• Truth table (2 Marks)
• Circuit Diagram (3 Marks)
2
EE200: Digital Design
C S M W X Y Z a b c d e f g
0 0 0 1 1 1 1 0 0 0 0 0 0 0
0 0 1 0 0 0 1 0 1 1 0 0 0 0
0 1 0 0 0 1 0 1 1 0 1 1 0 1
0 1 1 0 0 1 1 1 1 1 1 0 0 1
1 0 0 0 1 0 0 0 1 1 0 0 1 1
1 0 1 0 1 0 1 1 0 1 1 0 1 1
1 1 0 0 1 1 0 0 0 1 1 1 1 1
1 1 1 0 0 0 0 1 1 1 1 1 1 0
W X Y Z
0 M' M' 0
0 1 0 M
0 0 1 M
3
EE200: Digital Design