VERILOG HDL

Chapter 9

Verilog Behavioral Modeling

Trương Phong Tuyên

 Verilog HDL Abstraction Levels

• Behavioral Models: Higher level

of modeling where behavior of
logic is modeled.
• RTL Models: Logic is modeled
at register level.
• Structural Models: Logic is
modeled at both register level
and gate level.

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 Procedural Blocks

• Verilog behavioral code is inside procedure blocks,

but there is an exception: some behavioral code
also exist outside procedure blocks. We can see
this in detail as we make progress.
• There are two types of procedural blocks in
Verilog:
 initial: initial blocks execute only once at time zero (start
execution at time zero).
 always: always blocks loop to execute over and over
again; in other words, as the name suggests, it executes
always.
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Example - initial

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 Example - always

 In an always block, when the trigger event occurs, the code inside
begin and end is executed; then once again the always block waits for
next event triggering. This process of waiting and executing on event is
repeated till simulation stops.

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 Procedural Assignment Statements

• Procedural assignment statements assign

values to reg, integer, real, or time
variables and can not assign values to nets
(wire data types)
• You can assign to a register (reg data type)
the value of a net (wire), constant, another
register, or a specific value.

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Example-Bad Procedural Assignment

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Example-Good Procedural Assignment

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 Procedural Assignment Groups

• If a procedure block contains more than one

statement, those statements must be
enclosed within
 Sequential begin - end block
 Parallel fork - join block

• When using begin-end, we can give name to

that group. This is called named blocks.

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 Example - "begin-end"

 begin-end: clk gets 0 after 1 time unit, reset gets 0 after 11 time units,
enable after 16 time units, data after 19 units. All the statements are executed
sequentially.
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 Example - "fork-join"

 fork-join: clk gets its value after 1 time unit, reset after 10 time units,
enable after 5 time units, data after 3 time units. All the statements are
executed in parallel.
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 Sequential Statement Groups

• The begin - end keywords:

 Group several statements together.
 Cause the statements to be evaluated
sequentially (one at a time)
► Any timing within the sequential groups is relative to
the previous statement.
► Delays in the sequence accumulate (each delay is
added to the previous delay)
► Block finishes after the last statement in the block.

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Example - Sequential

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 Parallel Statement Groups

• The fork - join keywords:

 Group several statements together.
 Cause the statements to be evaluated in parallel
(all at the same time).
► Timing within parallel group is absolute to the
beginning of the group.
► Block finishes after the last statement completes
(Statement with highest delay, it can be the first
statement in the block).

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Example - Parallel

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Example - Mixing "begin-end" and
"fork - join"

Block name

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 Blocking and Nonblocking
Assignment

• Blocking assignments are executed in the order

they are coded, hence they are sequential. Since
they block the execution of next statement, till the
current statement is executed, they are called
blocking assignments. Assignment are made with
"=" symbol. Example a = b;
• Nonblocking assignments are executed in parallel.
Since the execution of next statement is not
blocked due to execution of current statement, they
are called nonblocking statement. Assignments are
made with "<=" symbol. Example a <= b;

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Example - Blocking and Nonblocking

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 The Conditional Statement if-else
• The if - else statement controls the execution of other
statements. In programming language like C, if - else
controls the flow of program. When more than one
statement needs to be executed for an if condition, then we
need to use begin and end as seen in earlier examples.

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Example- simple if

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Example- if-else

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Example- nested-if-else-if

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Example- nested-if-else-if (cont.)

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 The Case Statement
• The case statement compares an expression to a series of
cases and executes the statement or statement group
associated with the first matching case:
 Case statement supports single or multiple statements.
 Group multiple statements using begin and end keywords.
• Syntax of a case statement look as shown below.
case()
< case1 > : < statement >
< case2 > : < statement >
.....
default : < statement >
endcase

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Example- case

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 Example- case without default

A group of cases where

each case statement is
seperated by comma (",")

 The example above shows how to specify multiple case items as a single case item.
 The Verilog case statement does an identity comparison (like the === operator); one can
use the case statement to check for logic x and z values as shown in the example below.

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Example- case with x and z

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 Looping Statements

• Looping statements appear inside procedural

blocks only.
• Verilog has four looping statements like any
other programming language.
 forever
 repeat
 while
 for

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 The forever Statement

• The forever loop executes continually, the loop

never ends. Normally we use forever statements in
initial blocks.
• syntax :
forever < statement >
• One should be very careful in using a forever
statement: if no timing construct is present in the
forever statement, simulation could hang. The next
example is one such application, where a timing
construct is included inside a forever statement.
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Example - Free running clock
generator

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 The repeat Statement

• The repeat loop executes < statement > a

fixed < number > of times.
syntax:
repeat (< number >) < statement >

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Example- repeat

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 The while Loop Statement

• The while loop executes as long as an <

expression > evaluates as true. This is the
same as in any other programming
language.
syntax:
while (< expression >) < statement >

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Example- while

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 The for Loop Statement
• The for loop is the same as the for loop used in any other
programming language.
• Executes an < initial assignment > once at the start of the loop.
• Executes the loop as long as an < expression > evaluates as
true.
• Executes a < step assignment > at the end of each pass
through the loop.
• syntax:
for (< initial assignment >; < expression >; < step assignment >) < statement >

 Note: Verilog does not have ++ operator as in the case of C

language.

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Example - for

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 Continuous Assignment Statements

• Continuous assignment statements drive nets (wire data

type). They represent structural connections.
• They are used for modeling Tri-State buffers.
• They can be used for modeling combinational logic.
• They are outside the procedural blocks (always and initial
blocks).
• The continuous assign overrides any procedural
assignments.
• The left-hand side of a continuous assignment must be net
data type.
• Syntax:
assign (strength, strength) #(delay) net = expression;

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Example - One bit Adder

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Example - Tri-state buffer

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 Propagation Delay
• Continuous assignments may have a delay specified; only
one delay for all transitions may be specified. A
minimum:typical:maximum delay range may be specified.

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 Procedural Block Control
• Procedural blocks become active at simulation time zero. Use level
sensitive event controls to control the execution of a procedure.

 Any change in either d or enable satisfies the event control and allows the
execution of the statements in the procedure. The procedure is sensitive to any
change in d or enable. 41
 Combo Logic using Procedural Coding

• To model combinational logic, a procedure block

must be sensitive to any change on the input.
There is one important rule that needs to be
followed while modeling combinational logic.
• If you use conditional checking using "if", then you
need to mention the "else" part. Missing the else
part results in a latch.
• If you don't like typing the else part, then you must
initialize all the variables of that combo block as
soon as it enters.

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Example - One bit Adder

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Example - 4-bit Adder

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Example - Ways to avoid Latches -
Cover all conditions

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Example - Ways to avoid Latches -
Snit the variables to zero

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 Sequential Logic using Procedural Coding
• To model sequential logic, a procedure block must be
sensitive to positive edge or negative edge of clock. To
model asynchronous reset, procedure block must be
sensitive to both clock and reset. All the assignments to
sequential logic should be made through nonblocking
assignments.
• Sometimes it's tempting to have multiple edge triggering
variables in the sensitive list: this is fine for simulation. But
for synthesis this does not make sense, as in real life, flip-
flop can have only one clock, one reset and one preset (i.e.
posedge clk or posedge reset or posedge preset).
• One common mistake the new beginner makes is using
clock as the enable input to flip-flop. This is fine for
simulation, but for synthesis, this is not right.
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Example - Bad coding
Using two clocks

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Example - D Flip-flop with async reset
and async preset

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Example - D Flip-flop with sync reset
and sync preset

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 A procedure can't trigger itself
• One cannot trigger the block with a variable that block assigns value
or drives.

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Example – Multiple Blocks

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 Named Blocks
• Blocks can be named by adding : block_name after the
keyword begin. Named blocks can be disabled using the
'disable' statement.

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Example - Named Blocks

In this example, BIT_DETECT is

the named block and it is
disabled whenever the bit
position is detected.

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The End