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THD Analysis of Cascaded H-Bridge Multi-Level

Inverter

Gurcharan Singh Vijay Kumar Garg

U.I.E.T. Kurukshetra University Kurukshetra U.I.E.T. Kurukshetra University Kurukshetra

Kurukshetra (Haryana), India Kurukshetra (Haryana), India

guru653@gmail.com vkgarg2015@kuk.ac.in

Abstract— The traditional inverters have the drawbacks of II. MULTILEVEL INVERTER
Harmonics as well as Total Harmonic Distortion (THD). The
analysis of THD and harmonics are studied in this paper by using A multi-level inverter is an electronically operated device.
MATLAB simulation. The cascaded H-bridge multi-level inverter In multi-level inverter we deal with more than 2-level voltage
configuration is used. The used configurations contain less number to generate a smooth and stepped waveform of output voltage,
of switches and produce lesser harmonics in the output voltage. more than 2-level output voltage is having lower ݀‫ݒ‬Ȁ݀‫ ݐ‬ratio as
The harmonics and THD at the output of cascaded H-bridge well as lower harmonic distortions. The smoothness of the
inverter of different levels i.e., three-level, five-level, seven-level, output voltage is in proportion with the voltage levels, with
nine-level and eleven-level are studied and compared. The
increase in the voltage levels the output waveform becomes
cascaded H-bridge multi-level inverter topology quashes the THD
and harmonics. more smooth.
Keywords— cascaded multi-level inverter; MOSFETs; voltage Various topologies of multi-level inverters are available.
stress; neutral point converter; harmonics; THD The variance is in the working of switches and the source input
voltage to the multi-level inverters. The three most common
I. INTRODUCTION topologies are:
The consumption of electricity is growing day by day. Due A. Diode-Clamped Inverter
to deficiency in fossil fuels and problems in the environment
caused by traditional power generation, renewable energy Firstly, it was projected by “Akagi, Takashi and Nabae in
becomes very popular and demanding. Renewable energy 1981 and also known as neutral point converter. Clamping
sources offer the advantage of being pollution free. There is a diodes are used by the diode clamped multi-level inverters to
need for conditioning the output of renewable energy sources bound voltage stress of the devices. A ݊ level inverter requires
which improve its performance, power quality and overall ሺʹ݊ െ ʹሻ switching devices, ሺ݊ െ ͳሻ input voltage source
efficiency. To connect the renewable energy sources with the andሺ݊ െ ͳሻ ‫ כ‬ሺ݊ െ ʹሻ operating diodes. As in Fig.1, a five-
electricity grid there should be matching in voltage and level diode clamped or neutral clamped multi-level”inverter is
frequency with the help of inverters. To achieve this the shown. It consists of 4 voltage input DC sources, 8 switches and
multilevel inverter is employed. Now a“question occurs in our 12 diodes.
mind why we need multi-level inverter when a 2-level B. Flying Capacitor / Capacitor Clamped Multi-level
traditional inverter can also convert DC into AC. The answer is Inverter
as, a 2-level inverter generates the output with two levels of
The configuration topology in this inverter is rather alike to
voltage, assume that ܸ݀ܿ is provided as an input to a
the preceding one, excluding“for the variance that here
conventional inverter then we will have +ܸ݀ܿ and –ܸ݀ܿ at capacitors are used to limit voltage instead of diodes. A݊ level
output to form AC voltage. Nevertheless, this method is
flying capacitor inverter consists of ሺʹ݊ െ ʹሻ switching devices
generating AC effectively but it has some disadvantages like it
with ሺ݊ െ ͳሻ ‫ כ‬ሺ݊ െ ʹሻȀʹ flying capacitors in order to limit
produces harmonic distortions in the voltage at output and has
voltage. As in Fig. 2, a five level flying capacitor or capacitor
a high voltage stress ݀‫ݒ‬Ȁ݀‫ ݐ‬in comparison”with multi-level
clamped multi-level inverter is shown. It consists of 4 input DC
inverter.
voltage sources, 8 switches and 6 clamping”capacitors. This is
Also some“medium voltage utility applications and drives also called capacitor clamped multi-level inverter because the
need megawatt power level and medium voltage. For a grid of clamping is done by the flying capacitors.
medium voltage, it is difficult to connect only one power
C. Cascaded H-bridge Multi-level Inverter
semiconductor switch directly. consequently, a multi-level
inverter configuration has been introduced. A multi-level The idea of this kind of inverter is“grounded on connections
inverter achieves high power ratings as well as enables the use of H-bridge inverters in cascaded manner to produce a
of”renewable energy sources. sinusoidal output voltage. The voltage at output is the addition

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of the voltages produced by all cells. In this kind of inverters

formula of the number of levels of voltage at output is ሺʹ݊ ൅
ͳሻ, where ݊ represents the number of cells. The switching of
the switches is chosen in a way to minimize the THD. It also
requires lesser quantity of components in comparison with the
flying capacitor and diode clamped multi-level inverters. Hence
the weight and the price of this kind of inverter is lesser than
the other two types. As in Fig. 3, a five level cascaded”H-bridge
multi-level inverter is shown. It consists of 2 input DC voltage
sources and 8 switching devices.

Fig. 3 Cascaded H-bridge multi-level inverter

III. SIMULATION WORK

The“simulation work is done in the MATLAB SIMULINK.
We have made the three-level, five-level, seven-level, nine-
level and eleven-level inverter in MATLAB by using MOSFET
as a switch, it works according to gate pulse which is given
through pulse generator. We have connected the 4 MOSFETs
in such a manner to make an H-bridge cell. According to the
formula of cascaded H-bridge multi-level inverter we can
produce desired levels as the formula is ሺʹ݊ ൅ ͳሻ where ݊ is
no. Of cells. So that we can produce desired levels just by
adding the H-bridge cells according to our desired levels.
Therefore, one H-bridge cell for 3 levels, two for 5 levels, three
for 7 levels, four for 9 levels and five for 11 levels are connected
in cascaded manner. We have produced these levels by using
pulse generator just by varying its pulse”width percentage and
providing phase delay through the pulse generators.
Fig. 1 Diode clamped multi-level inverter A. Three Level H-bridge Inverter
In three level H-bridge inverter, we have provided an
operating time period of 0.02 seconds by using a pulse
generator to the all four MOSFETs in H-bridge cell as shown
in Fig. 4.

Fig. 2 Flying capacitors multi-level inverter Fig. 4 Simulink diagram of single phase three-level H-bridge inverter

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Fig. 5 Output waveform of three level H-bridge inverter

We have provided 0.001 second phase delay to one cross

pair of MOSFETs and 0.011 seconds phase delay to another Fig. 7 THD percentage of five level H-bridge inverter
cross pair of MOSFETs. The pulse width percentage given to
all four MOSFETs is 50%. The output waveform is shown in
Fig. 5 and THD is shown in the Fig. 6. The THD is 32.49%.
The applied input DC voltage is 230 volts.

Fig. 6 THD percentage of three level H-bridge inverter

B. Five Level H-bridge Inverter Fig. 8 Simulink diagram of single phase five level H-bridge inverter
In five level H-bridge inverter, two H-bridge cells are
connected in a cascaded manner so that it provides us five level
output voltage at the output end. Two cells consist of eight
MOSFETs, four each cell. The both of two cell will operate for
a time period of 0.02 seconds and the phase delay is provided
in the first cell is 0.001 second to one cross pair of MOSFETs
and 0.011 seconds to another cross pair of MOSFETs. The
pulse width percentage is given to all four MOSFETs of the first
cell is 60%. In the second cell the phase delay given to one cross
pair of MOSFETs is 0.002 seconds and the phase delay is given
to another pair of MOSFETs is 0.012 seconds. The pulse width
percentage given to all four MOSFETs of the second cell is
40%. The THD in this inverter is 28.51% that is shown in Fig.
7. The Simulink diagram is shown in Fig. 8 and the output
waveform is shown in Fig. 9. The total given input DC voltage
Fig. 9 Output waveform of five level H-bridge inverter
is 230 volts.

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C. Seven Level H-bridge Inverter

In seven level H-bridge inverter we required three H-bridge
cells so that we would be able to produce required levels at the
output end. In the first cell and second cell phase delay is given
similarly as in five level H-bridge inverter and the pulse width
percentage is similar too. But in cell third the phase delay is
given to one cross pair is 0.003 seconds and phase delay given
to another cross pair of MOSFETs is 0.013 seconds. The pulse
width percentage is in the third cell is 20%. All bridge cells will
operate for a time period of 0.02 seconds. The output waveform
is shown in Fig. 10. The total input given voltage is 230volt dc.
The Simulink diagram is shown in Fig. 11. The THD in this
inverter is 26.84% and the THD is shown in Fig. 12.

Fig. 12 THD percentage of seven level H-bridge inverter

D. Nine Level H-bridge Inverter

In nine level H-bridge inverter we have four H-bridge cells
connected in a cascaded manner to get nine level output voltage
at the output end. The phase delay provided to the MOSFETs
of first, second, and third H-bridge cells is similar to seven level
H-bridge inverter. But the phase delay in the fourth cell for the
one cross pair of MOSFETs is 0.004 seconds and for another
cross pair of MOSFETs is 0.014 seconds. The pulse width
percentage for the first, second, third and fourth H-bridge cells
Fig. 10 Output waveform of seven level H-bridge inverter is 40, 30, 20, 10 respectively. The output waveform is shown in
Fig. 13.

Fig. 13 Output waveform of nine level H-bridge inverter

Fig. 11 Simulink diagram of single phase seven level H-bridge inverter Fig. 14 THD percentage of nine level H-bridge inverter

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The total input dc voltage is 230 volts. The operating time

period for all cells is 0.02 seconds. The THD in this inverter is
23.54% as shown in Fig. 14. The Simulink diagram is shown in
Fig. 15.

Fig. 17 THD percentage of eleven level H-bridge inverter

The operating time period for all five H-bridge cells is 0.021
seconds. The total input DC voltage is 230 volts. The output
waveform is shown in Fig. 16. The THD in this inverter is
10.84% shown in Fig. 17. The Simulink diagram is shown in
Fig. 18.

Fig. 15 Simulink diagram of single phase nine level H-bridge inverter

E. Eleven Level H-bridge Inverter

In eleven level H-bridge inverter we have five H-bridge
cells are connected in a cascaded manner to generate eleven
levels output voltage at the output end. The phase delay for the
MOSFETs of first, second, third and fourth H-bridge cells is
similar to that of nine level H-bridge inverter. But in fifth H-
bridge cell the delay provided to the one cross pair of
MOSFETs is 0.005 sec and phase delay provided to the another
cross pair of MOSFETs is 0.015 seconds. The pulse width
percentage for first, second, third, fourth and fifth H-bridge
cells is 50, 40, 30, 20, 10 respectively.

Fig. 18 Simulink diagram of single phase 11 level H-bridge inverter

IV. CONCLUSION
The“cascaded H-bridge multi-level inverter is better than
the diode clamped multi-level inverter as well as flying
Fig. 16 Output waveform of eleven level H-bridge inverter capacitor multi-level inverter as it consists of less components,

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