Problems 693

(a) For inputs grounded and output held at 0 V (by negative 5V

CHAPTER 9
feedback, not shown) find the emitter currents of all
transistors. 3.3 k
(b) Calculate the gain of the amplifier with RL = 1 k!. 8.2 k
68 k
9.120 A BJT differential amplifier, biased to have re = 50 ! Q2
and utilizing two 50-! emitter resistors and 5-k! loads, drives
vi Q1 Q3
a second differential stage biased to have re = 25 !. All BJTs

PROBLEMS
have β = 100. What is the voltage gain of the first stage? Also vo
find the input resistance of the first stage, and the current gain 33 k 5.6 k
4.7 k 2.4 k
from the input of the first stage to the collectors of the second
stage.
5V
9.121 In the multistage amplifier of Fig. 9.41, emitter
resistors are to be introduced—100 ! in the emitter lead of Figure P9.124
each of the first-stage transistors and 25 ! for each of the
(a) Find the dc bias current in each of the three transistors.
! !
second-stage transistors. What is the effect on input resistance,
Also find the dc voltage at the output. Assume !VBE ! =
the voltage gain of the first stage, and the overall voltage gain?
0.7 V, β = 100, and neglect the Early effect.
Use the bias values found in Example 9.7.
(b) Find the input resistance and the output resistance.
D 9.122 Consider the circuit of Fig. 9.41 and its output (c) Use the current-gain method to evaluate the voltage gain
resistance. Which resistor has the most effect on the output v o /v i .
resistance? What should this resistor be changed to if the
9.125 For the current mirror in Fig. P9.125, replace the
output resistance is to be reduced by a factor of 2? What
transistors with their hybrid-π models and show that:
will the amplifier gain become after this change? What
other change can you make to restore the amplifier gain to 1
Ri = "r
approximately its prior value? gm1 o1
! " #
D 9.123 (a) If, in the multistage amplifier of Fig. 9.41, the ! 1
Ais ! Ais ! 1−
ideal gm1 ro1
resistor R5 is replaced by a constant-current source ! 1 mA, !
such that the bias situation is essentially unaffected, what does !
Ais ! = gm2 /gm1
ideal
the overall voltage gain of the amplifier become? Assume
Ro = ro2
that the output resistance of the current source is very high.
Use the results of Example 9.8. where Ais denotes the short-circuit current gain.
(b) With the modification suggested in (a), what is the effect
of the change on output resistance? What is the overall gain of
the amplifier when loaded by 100 ! to ground? The original
amplifier (before modification) has an output resistance of ii
152 ! and a voltage gain of 8513 V/V. What is its gain when Ri i osc
loaded by 100 !? Comment. Use β = 100.
Ro
*9.124 Figure P9.124 shows a three-stage amplifier in which
Q1 Q2
the stages are directly coupled. The amplifier, however,
utilizes bypass capacitors, and, as such, its frequency response
falls off at low frequencies. For our purposes here, we shall
assume that the capacitors are large enough to act as perfect
short circuits at all signal frequencies of interest. Figure P9.125

= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
 694 Chapter 9 Differential and Multistage Amplifiers

**9.126 The MOS differential amplifier shown in VOV , show that the CMRR is given by
PROBLEMS

Fig. P9.126 utilizes three current mirrors for signal

transmission: Q4−Q6 has a transmission factor of 2 [i.e., $ %2
(W/L)6 /(W/L)4 = 2], Q3−Q5 has a transmission factor of 1, CMRR = 4 VA /VOV
and Q7−Q8 has a transmission factor of 2. All transistors
! ! are
sized to operate at the same overdrive! voltage, !VOV !. All
! (e) Find the input! CM ! range! and! the output linear range in
! !
transistors have the same Early voltage VA . terms of VDD , !Vt !, and !VOV !.
CHAPTER 9

VDD D ***9.127 For the circuit shown in Fig. P9.127, which uses
a! folded
! cascode involving transistor Q3 , all transistors have
!VBE ! = 0.7 V for the currents involved, VA = 200 V, and
Q5 Q3 Q4 Q6
β = 100. The circuit is relatively conventional except for
Q5 , which operates in a Class B mode (we will study this
in Chapter 12) to provide an increased negative output swing
Q1 Q2 for low-resistance loads.
vo
5V

QF QG
Q7 Q8 1
F 2
G
QE Q3
VDD 1
E
Figure P9.126
v Q1 Q2 Q4
R D
(a) Provide in tabular form the values of ID , gm , and ro of each vO
of the eight transistors in terms of I, VOV , and VA . C Q5
(b) Show that the differential voltage gain Ad is given by IREF v
A B
$ %
Ad = 2gm1 ro6 " ro8 = VA /VOV QB QC
QA QD
(c) Show that the CM gain is given by 1 2 1 10
! ! ro6 " ro8 1
!Acm ! ! 5V
RSS gm7 ro7
Figure P9.127
where RSS is the output resistance of the bias current ! !
source I. [Hint: Replace each of Q1 and Q2 together (a) Perform a bias calculation assuming !VBE ! = 0.7 V,
with their source resistance 2RSS with a controlled high β, VA = ∞, v + = v − = 0 V, and v O is stabilized by
current-source v icm /2RSS and an output resistance. For feedback to about 0 V. Find R so that the reference current
each current mirror, the current transfer ratio is given by IREF is 100 µA. What are the voltages at all the labeled
" # nodes?
1 (b) Provide in tabular form the bias currents in all transistors
Ai ! Ai (ideal) 1 −
gm ro
together with gm and ro for the signal transistors (Q1 , Q2 ,
where gm and ro are the parameters of the input transistor Q3 , Q4 , and Q5 ) and ro for QC , QD , and QG .
of the mirror. (see Problem 9.125 above.)] (c) Now, using β = 100, find the voltage gain v o /(v + − v − ),
(d) If the current source I is implemented using a simple and in the process, verify the polarity of the input
mirror and the MOS transistor is operated at the same terminals.

= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
 Problems 695

(d) Find the input and output resistances. (g) For what load resistance connected to ground is the output

CHAPTER 9
(e) Find the input common-mode range for linear operation. negative voltage limited to −1 V before Q7 begins to
(f) For no load,
! what! is the range of available output voltages, conduct?
assuming !VCEsat ! = 0.3 V? (h) For a load resistance one-tenth of that found in (g), what
(g) Now consider the situation with a load resistance is the output signal swing?
connected from the output to ground. At the positive
and negative limits of the output signal swing, find

PROBLEMS
the smallest load resistance that can be driven if one or 5V
the other of Q1 or Q2 is allowed to cut off.
1W 2W 4W
QF Q3 Q4
D ***9.128 In the !CMOS ! op amp shown in Fig. P9.128, all
F G
MOS devices have !Vt ! = 1V, µn Cox = 2 µp Cox = 40 µA/V2 , QE H
! ! Q5
!VA ! = 50 V, and L = 5 µm. Device widths are indicated on 1W
E 2W
the diagram as multiples of W, where W = 5 µm. Q6
v Q1 Q2
10W
(a) Design R to provide a 10-µA reference current. 1W 1W 20W vO
(b) Assuming v O = 0 V, as established by external feedback, R v C Q7 D
perform a bias analysis, finding all the labeled node IREF
B
voltages, and VGS and ID for all transistors.
(c) Provide in table form ID , VGS , gm , and ro for all devices. A
$ % QA
(d) Calculate the voltage gain v o / v + − v − , the input QB QC QD
1W 2W 1W 5W
resistance, and the output resistance.
(e) What is the input common-mode range? 5V
(f) What is the output signal range for no load? Figure P9.128

= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem