IT18302-Computer Organization and Architecture-Lecture Notes

IT18302 – Computer Organization and Architecture

Lecture Notes

Unit 1- BASIC COMPUTER ORGANIZATION AND DESIGN

Instruction codes, Computer registers, computer instructions, Timing and Control, Instruction cycle, Memory-Reference
Instructions, Input-output and interrupt, Complete computer description, Design of Basic computer, design of
Accumulator Unit.

Instruction Codes
 The Internal organization of a digital system is defined by the sequence of microoperations it performs on data
stored in its registers. The user of a computer can control the process by means of a program
 A program is a set of instructions that specify the operations, operands, and the processing sequence.
 A computer instruction is a binary code that specifies a sequence of micro-operations for the computer. Each
computer has its unique instruction set.
 Instruction codes and data are stored in memory. The computer reads each instruction from memory and places it
in a control register. The control unit interprets the binary code of the instruction and proceeds to execute it by
issuing a sequence of micro-operations.
 An Instruction code is a group of bits that instructs the computer to perform a specific operation (sequence of
microoperations). It is divided into parts (basic part is the operation part).
 The operation code of an instruction is a group of bits that defines certain operations such as add, subtract, shift,
and complement. The number of bits required for the operation code depends on the total number of operations
available in the computer. 2n (or little less) distinct operations  n bit operation code

 An operation must be performed on some data stored in processor registers or in memory. An instruction code
must therefore specify not only the operation, but also the location of the operands (in registers or in the
memory), and where the result will be stored (registers/memory). Memory words can be specified in
instruction codes by their address.
 Processor registers can be specified by assigning to the instruction another binary code of k bits that specifies
one of 2k registers.
 Each computer has its own particular instruction code format. Instruction code formats are conceived by
computer designers who specify the architecture of the computer.

Stored Program Organization

An instruction code is usually divided into operation code, operand address, addressing mode, etc. The simplest
way to organize a computer is to have one processor register (accumulator AC) and an instruction code format with
two parts (op code, address)

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Indirect Address
There are three Addressing Modes used for address portion of the instruction code:
 Immediate: the operand is given in the address portion (constant)
 Direct: the address points to the operand stored in the memory
 Indirect: the address points to the pointer (another address) stored in the memory that references the
operand in memory
One bit of the instruction code can be used to distinguish between direct & indirect addresses

• Effective address: the address of the operand in a computation-type instruction or the target address in a branch-
type instruction
• The pointer can be placed in a processor register instead of memory as done in commercial computers

Computer Registers
Computer instructions are normally stored in consecutive memory locations and executed sequentially one at a
time. The control reads an instruction from a specific address in memory and executes it, and so on. This type of
sequencing needs a counter to calculate the address of the next instruction after execution of the current instruction is
completed. It is also necessary to provide a register in the control unit for storing the instruction code after it is read
from memory. The computer needs processor registers for manipulating data and a register for holding a memory
address.

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DR 16 Data Register Holds memory operand

AR 12 Address Register Holds address for memory
AC 16 Accumulator Processor register
IR 16 Instruction Register Holds instruction code
PC 12 Program Counter Holds address of instruction
TR 16 Temporary Register Holds temporary data
INPR 8 Input Register Holds input character
OUTR 8 Output Register Holds output character

Computer Registers-Common Bus System

 S2S1S0: Selects the register/memory that would use the bus.

 LD (load): When enabled, the particular register receives the data from the bus during the next clock pulse transition.
 E (extended AC bit): flip-flop holds the carry.
 DR, AC, IR, and TR: have 16 bits each.
 AR and PC: have 12 bits each since they hold a memory address.
 When the contents of AR or PC are applied to the 16-bit common bus, the four most significant bits are set to zeros.
 When AR or PC receives information from the bus, only the 12 least significant bits are transferred into the register.
 INPR and OUTR: communicate with the eight least significant bits in the bus.
 INPR: Receives a character from the input device (keyboard,…etc) which is then transferred to AC.
 OUTR: Receives a character from AC and delivers it to an output device (say a Monitor).
 Five registers have three control inputs: LD (load), INR (increment), and CLR (clear). Register  binary counter
with parallel load and synchronous clear.

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 IT18302-Computer Organization and Architecture-Lecture Notes

Computer Registers-Memory Address

The input data and output data of the memory are connected to the common bus. But the memory address is
connected to AR. Therefore, AR must always be used to specify a memory address. By using a single register for the
address, we eliminate the need for an address bus that would have been needed otherwise.
• Register  Memory: Write operation
• Memory  Register: Read operation (note that AC cannot directly read from memory!!)
Note that the content of any register can be applied onto the bus and an operation can be performed in the adder and
logic circuit during the same clock cycle.
• The transition at the end of the cycle transfers the content of the bus into the destination register, and the output of
the adder and logic circuit into the AC.
• For example, the two microoperations
DR←AC and AC←DR (Exchange) can be executed at the same time
This is done by:
1- place the contents of AC on the bus (S2S1S0=100)
2- enabling the LD (load) input of DR
3- Transferring the contents of the DR through the adder and logic circuit into AC
4- enabling the LD (load) input of AC
All during the same clock cycle. The two transfers occur upon the arrival of the clock pulse transition at the end of the
clock cycle.

Computer Instructions

Hex Code
Symbol I=0 I=1 Description
AND 0xxx 8xxx AND memory word to AC
ADD 1xxx 9xxx Add memory word to AC
LDA 2xxx Axxx Load AC from memory
STA 3xxx Bxxx Store content of AC into memory
BUN 4xxx Cxxx Branch unconditionally
BSA 5xxx Dxxx Branch and save return address
ISZ 6xxx Exxx Increment and skip if zero
CLA 7800 Clear AC
CLE 7400 Clear E
CMA 7200 Complement AC
CME 7100 Complement E
CIR 7080 Circulate right AC and E
CIL 7040 Circulate left AC and E
INC 7020 Increment AC

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SPA 7010 Skip next instr. if AC is positive

SNA 7008 Skip next instr. if AC is negative
SZA 7004 Skip next instr. if AC is zero
SZE 7002 Skip next instr. if E is zero
HLT 7001 Halt computer
INP F800 Input character to AC
OUT F400 Output character from AC
SKI F200 Skip on input flag
SKO F100 Skip on output flag
ION F080 Interrupt on
IOF F040 Interrupt off

Computer Instructions - Instruction Set Completeness

• The set of instructions are said to be complete if the computer includes a sufficient number of instructions in each
of the following categories:
– Arithmetic, logical, and shift instructions
– Instructions for moving information to and from memory and processor registers
– Program control instructions together with instructions that check status conditions
– Input & output instructions
–
Timing & Control
 The timing for all registers in the basic computer is controlled by a master clock generator. The clock pulses are
applied to all flip-flops and registers in the system, including the flip-flops and registers in the control unit
 The clock pulses do not change the state of a register unless the register is enabled by a control signal (i.e., Load).
 The control signals are generated in the control unit and provide control inputs for the multiplexers in the common
bus, control inputs in processor registers, and microoperations for the accumulator.
 There are two major types of control organization:
Hardwired control
Micro programmed control
 In the hardwired organization, the control logic is implemented with gates, flip-flops, decoders, and other digital
circuits.In the microprogrammed organization, the control information is stored in a control memory (if the design
is modified, the microprogram in control memory has to be updated).
The Control Unit for the basic computer

Generated by 4-bit sequence counter and 4x16 decoder

- The SC can be incremented or cleared.
- Example: T0, T1, T2, T3, T4, T0, T1, . . .

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Assume: At time T4, SC is cleared to 0 if decoder output D3 is active.

D3T4: SC  0
T0 T1 T2 T3 T4 T0
Clock

T0

T1

T2

T3

T4

D3

CLR
SC

A memory read or writes cycle will be initiated with the rising edge of a timing signal. Assume that: memory cycle
time < clock cycle time! So, a memory read or write cycle initiated by a timing signal will be completed by the time
the next clock goes through its positive edge. The clock transition will then be used to load the memory word into a
register. The memory cycle time is usually longer than the processor clock cycle  wait cycles
• T0: AR←PC
– Transfers the content of PC into AR if timing signal T0 is active
– T0 is active during an entire clock cycle interval
– During this time, the content of PC is placed onto the bus (with S2S1S0=010) and the LD (load) input of
AR is enabled
– The actual transfer does not occur until the end of the clock cycle when the clock goes through a positive
transition
– This same positive clock transition increments the sequence counter SC from 0000 to 0001
– The next clock cycle has T1 active and T0 inactive

Instruction Cycle
A program is a sequence of instructions stored in memory. The program is executed in the computer by going through
a cycle for each instruction (in most cases).
Each instruction in turn is subdivided into a sequence of sub-cycles or phases
Instruction Cycle Phases:
1- Fetch an instruction from memory
2- Decode the instruction
3- Read the effective address from memory if the instruction has an indirect address
4- Execute the instruction
This cycle repeats indefinitely unless a HALT instruction is encountered
Fetch and Decode
• Initially, the Program Counter (PC) is loaded with the address of the first instruction in the program
• The sequence counter SC is cleared to 0, providing a decoded timing signal T0
• After each clock pulse, SC is incremented by one, so that the timing signals go through a sequence T0, T1, T2, and
so on
– T0: AR←PC (this is essential!!)
The address of the instruction is moved to AR.
– T1: IR←M[AR], PC←PC+1
The instruction is fetched from the memory to IR , and the PC is incremented.
– T2: D0,…, D7←Decode IR(12-14), AR←IR(0-11), I←IR(15)
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BC Instruction cycle: [Fetch Decode [Indirect] Execute]*

T0: AR  PC (S0S1S2=010, T0=1)

T1: IR M [AR], PC PC + 1 (S0S1S2=111, T1=1)
T2: D0, . . . , D7 Decode IR(12-14), AR IR(0-11), I IR(15)

Determine The Type Of Instruction:

D'7IT3: AR  M[AR]
D'7I'T3:Nothing
D7I'T3: Execute a register-reference instr.
D7IT3: Execute an input-output instr.

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Register Reference Instructions:

Register Reference Instructions are identified when
- D7 = 1, I = 0
- Register Ref. Instr. is specified in B0 ~ B11 of IR
- Execution starts with timing signal T3

r = D7 I’ T3 => Register Reference Instruction

Bi = IR(i) , i=0,1,2,...,11, the ith bit of IR.
r: SC  0
CLA rB11: AC  0
CLE rB10: E0
CMA rB9: AC  AC’
CME rB8: E  E’
CIR rB7: AC  shr AC, AC(15)  E, E  AC(0)
CIL rB6: AC  shl AC, AC(0)  E, E  AC(15)
INC rB5: AC  AC + 1
SPA rB4: if (AC(15) = 0) then (PC  PC+1)
SNA rB3: if (AC(15) = 1) then (PC  PC+1)
SZA rB2: if (AC = 0) then (PC  PC+1)
SZE rB1: if (E = 0) then (PC  PC+1)
HLT rB0: S  0 (S is a start-stop flip-flop)

Memory Reference Instructions:

Symbol OperationDecoder Symbolic Description
AND D0 AC  AC  M[AR]
ADD D1 AC  AC + M[AR], E  Cout
LDA D2 AC  M[AR]
STA D3 M[AR]  AC
BUN D4 PC  AR
BSA D5 M[AR]  PC, PC  AR + 1
ISZ D6 M[AR]  M[AR] + 1, if M[AR] + 1 = 0 then PC  PC+1
- The effective address of the instruction is in AR and was placed there during timing signal T2 when I = 0, or during
timing signal T3 when I = 1
- Memory cycle is assumed to be short enough to be completed in a CPU cycle
- The execution of MR Instruction starts with T4
AND to AC
D0T4: DR  M[AR] Read operand
D0T5: AC  AC  DR, SC  0 AND with AC
ADD to AC
D1T4: DR  M[AR] Read operand
D1T5: AC  AC + DR, E  Cout, SC  0 Add to AC and store carry in E
LDA: Load to AC
D2T4: DR  M[AR]
D2T5: AC  DR, SC  0
STA: Store AC
D3T4: M[AR]  AC, SC  0
BUN: Branch Unconditionally
D4T4: PC  AR, SC  0
BSA: Branch and Save Return Address
M[AR]  PC, PC  AR + 1

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BSA: executed in a sequence of two micro-operations:

D5T4: M[AR]  PC, AR  AR + 1
D5T5: PC  AR, SC  0
ISZ: Increment and Skip-if-Zero
D6T4: DR  M[AR]
D6T5: DR  DR + 1
D6T6: M[AR]  DR, if (DR = 0) then (PC  PC + 1), SC  0

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Input-Output and Interrupt

• Instructions and data stored in memory must come from some input device.Computational results must be
transmitted to the user through some output device.
• For the system to communicate with an input device, serial information is shifted into the input register INPR. To
output information, it is stored in the output register OUTR

.
• INPR and OUTR communicate with a communication interface serially and with the AC in parallel. They hold an
8-bit alphanumeric information.
• I/O devices are slower than a computer system  we need to synchronize the timing rate difference between the
input/output device and the computer.
• FGI: 1-bit input flag (Flip-Flop) aimed to control the input operation.FGI is set to 1 when a new information is
available in the input device and is cleared to 0 when the information is accepted by the computer
• FGO: 1-bit output flag used as a control flip-flop to control the output operation. If FGO is set to 1, then this
means that the computer can send out the information from AC. If it is 0, then the output device is busy and the
computer has to wait!
The process of input information transfer:
• Initially, FGI is cleared to 0
• An 8-bit alphanumeric code is shifted into INPR (Keyboard key strike) and the input flag FGI is set to 1
• As long as the flag is set, the information in INPR cannot be changed by another data entry
• The computer checks the flag bit; if it is 1, the information from INPR is transferred in parallel into AC
and FGI is cleared to 0
• Once the flag is cleared, new information can be shifted into INPR by the input device (striking another
key)
The process of outputting information:
• Initially, the output flag FGO is set to 1
• The computer checks the flag bit; if it is 1, the information from AC is transferred in parallel to OUTR
and FGO is cleared to 0
• The output accepts the coded information (prints the corresponding character)
• When the operation is completed, the output device sets FGO back to 1
• The computer does not load a new data information into OUTR when FGO is 0 because this condition
indicates that the output device is busy to receive another information at the moment!!
Needed for:
 Transferring information to and from AC register
 Checking the flag bits
 Controlling the interrupt facility
The control unit recognize it when D7=1 and I = 1. The remaining bits of the instruction specify the particular
operation. Executed with the clock transition associated with timing signal T3
Input-Output instructions are summarized as
D7IT3 = p
IR(i) = Bi, i = 6, …, 11

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INPpB11: AC(0-7)  INPR, FGI  0 Input char. to AC

OUT pB10: OUTR  AC(0-7), FGO  0 Output char. from AC
SKIpB9: if(FGI = 1) then (PC  PC + 1) Skip on input flag
SKO pB8: if(FGO = 1) then (PC  PC + 1) Skip on output flag
ION pB7: IEN  1 Interrupt enable on
IOFpB6: IEN  0 Interrupt enable off

Program Interrupt
 The process of communication just described is referred to as Programmed Control Transfer
 The computer keeps checking the flag bit, and when it finds it set, it initiates an information transform (this is
sometimes called Polling). This type of transfer is in-efficient due to the difference of information flow rate
between the computer and the I/O device
 The computer is wasting time while checking the flag instead of doing some other useful processing task.
 An alternative to the programmed controlled procedure is to let the external device inform the computer when
it is ready for the transfer. This type of transfer uses the interrupt facility. While the computer is running a
program, it does not check the flags. Instead:
o When a flag is set, the computer is immediately interrupted from proceeding with the current program
o The computer stops what it is doing to take care of the input or output transfer
o Then, it returns to the current program to continue what it was doing before the interrupt
 The interrupt facility can be enabled or disabled via a flip-flop called IEN. The interrupt enable flip-flop IEN
can be set and cleared with two instructions (IOF, ION):
o IOF: IEN  0 (the computer cannot be interrupted)
o ION: IEN  1 (the computer can be interrupted)
 Another flip-flop (called the interrupt flip-flop R) is used in the computer’s interrupt facility to decide when to
go through the interrupt cycle. So, the computer is either in an Instruction Cycle or in an Interrupt Cycle.
 The interrupt cycle is a hardware implementation of a branch and save return address operation (BSA). The
return address available in PC is stored in a specific location where it can be found later when the program
returns to the instruction at which it was interrupted. This location may be a processor register, a memory
stack, or a specific memory location
 For our computer, we choose the memory location at address 0 as a place for storing the return address.
Control then inserts address 1 into PC:
o this means that the first instruction of the interrupt service routine should be stored in memory at
address 1,
o or, the programmer must store a branch instruction that sends the control to an interrupt service
routine!!

• IEN, R  0: no more interruptions can occur until the interrupt request from the flag has been serviced.The
service routine must end with an instruction that re-enables the interrupt (IEN  1) and an instruction to return to

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the instruction at which the interrupt occurred. The instruction that returns the control to the original program is
"indirect BUN 0" .
• Example: the computer is interrupted during execution of the instruction at address 255

The fetch and decode phases of the instruction cycle must be : (Replace T0, T1, T2  R'T0, R'T1, R'T2 (fetch and
decode phases occur at the instruction cycle when R = 0)
• Interrupt Cycle:
– RT0: AR  0, TR  PC
– RT1: M[AR]  TR, PC  0
– RT2: PC  PC + 1, IEN  0, R  0, SC  0
• Register transfers for the Interrupt Cycle

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Complete Computer Description

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Design of Basic Computer

o A memory unit: 4096 x 16.
o Registers: AR, PC, DR, AC, IR, TR, OUTR, INPR, and SC
o Flip-Flops (Status): I, S, E, R, IEN, FGI, and FGO
o Decoders:
 a 3x8 Opcode decoder
 a 4x16 timing decoder
o Common bus: 16 bits
o Control logic gates
o Adder and Logic circuit: Connected to AC
The control logic gates are used to control:
o Inputs of the nine registers
o Read and Write inputs of memory
o Set, Clear, or Complement inputs of the flip-flops
o S2, S1, S0 that select a register for the bus
o AC Adder and Logic circuit

• Control of registers and memory

– The control inputs of the registers are LD (load), INR (increment), and CLR (clear)
– To control AR We scan table to find out all the statements that change the content of AR:
• R’T0: AR  PC LD(AR)
• R’T2: AR  IR(0-11) LD(AR)
• D’7IT3: AR  M[AR] LD(AR)
• RT0: AR  0 CLR(AR)
• D5T4: AR  AR + 1 INR(AR)

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– Control Gates associated with AR

– To control the Read input of the memory we scan the table again to get these:
• D0T4: DR  M[AR]
• D1T4: DR  M[AR]
• D2T4: DR  M[AR]
• D6T4: DR  M[AR]
• D7′IT3: AR  M[AR]
• R′T1: IR  M[AR]
 Read = R′T1 + D7′IT3 + (D0 + D1 + D2 + D6 )T4

– Control of Single Flip-flops (IEN for example)

– pB7: IEN  1 (I/O Instruction)
– pB6: IEN  0 (I/O Instruction)
– RT2: IEN  0 (Interrupt)
where p = D7IT3 (Input/Output Instruction)
– If we use a JK flip-flop for IEN, the control gate logic will be as shown in the following slide:

J K Q(t+1)

0 0 Q(t)

0 1 0

1 0 1

1 1 Q’(t)

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• Control of Common bus is accomplished by placing an encoder at the inputs of the bus selection logic and
implementing the logic for each encoder input

• To select AR on the bus then x1 must be 1. This is happen when:

• D4T4: PC  AR
• D5T5: PC  AR
•  x1 = D4T4 + D5T5

x1 x2 x3 x4 x5 x6 x7 S2 S1 S0 selected register
0 0 0 0 0 0 0 0 0 0 none
1 0 0 0 0 0 0 0 0 1 AR
0 1 0 0 0 0 0 0 1 0 PC
0 0 1 0 0 0 0 0 1 1 DR
0 0 0 1 0 0 0 1 0 0 AC
0 0 0 0 1 0 0 1 0 1 IR
0 0 0 0 0 1 0 1 1 0 TR
0 0 0 0 0 0 1 1 1 1 Memory

• For x7:
– X7 = R′T1 + D7′IT3 + (D0 + D1 + D2 + D6 )T4 where it is also applied to the read input

Design of Accumulator Logic

Circuits associated with AC

All the statements that change the content of AC

D0T5: AC  AC  DR AND with DR
D1T5: AC AC + DR Add with DR
D2T5: AC DR Transfer from DR
pB11: AC(0-7) INPR Transfer from INPR
rB9: AC AC’ Complement
rB7 : AC shr AC, AC(15) E Shift right

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rB6 : AC shl AC, AC(0) E Shift left

rB11 : AC 0 Clear
rB5 : AC AC + 1 Increment

Gate structures for controlling the LD, INR, and CLR of AC

Adder and Logic Circuit

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