Correlation Radiometer ASIC

Keywords: Correlation radiometer, radiometer ASIC, Earth observation, polyphase filter, ADC

Technical Summary Operational Capabilities (Expected)

The project relies on previously developed correlation
The ASIC facilitates the radiometer system to reduce its weight,
radiometer solution which included an analog processing part
power consumption, cost and complexity by applying DSP
on an ASIC, while the DSP part was implemented on an FPGA.
instead on analog signal processing. Specific capabilities
Previous solution was able to operate at 0.004% duty cycle. This
include:
project aims to develop an ASIC including entire (analog and
• Input signal bandwidth 20GHz (I/Q, total)
digital) processing for microwave correlation radiometers
• Input signal level -30dBm to 0dBm
operating at 100% duty cycle (Fig.1). These instruments are
• Sampling rate up to 20GS/s
required for space and airborne Earth observation missions. The
• Four 2-bit ADCs sampling at up to 20GS/s
DSP block the ASIC employs can be reprogrammed to adopt
• Digitizer ENOB > 1.5-bit
specific parameters of the filter block (Fig.2). Bandpass filters on
• 64 sub-band PFB with programmable coefficients
the ASIC split up the digitized quadrature IF input signals into
• ASIC power consumption < 1.6W
bands (up to 31). Further, the signals are cross-correlated within
• 64 sub-band PFB with programmable coefficients
each band, and the resultant data is shipped out in a convenient
• Cross-correlation of signals as: II, QQ, IQ and QI
format. The ASIC will be offered as a separate component and
separately within each band
as an IP block for integration into SoCs.
• 4x16 totalizers counting the number of occurrences
of each 2-bit input signal values (-3, -1, 1, 3)
LPF
ASIC • Accumulation time from 0.1ms to 100ms
LNA LPF Analog Data
Out
• An integrated 10GHz PLL
Frontend DSP • An I2C interface for control, diagnostics and readout
LO ϕ · AGC
· ADC
·
·
Filter • 15 x 15 BGA package (12.8mm x 12.8 mm)
LPF ·
·
Totalizer
Cross-Correlator
MUX
Development Objectives
• Fabrication technology 28nm & Milestones
CMOS
· Data Interface Pacific Microchip Corp. has demonstrated the feasibility,
LPF
LNA
designed, fabricated, packaged, and tested the 1st prototype
chip. Further, the chip is expected to be modified to address
Clock Control Interface
identified issues (subject to availability of funds), retested, and
Figure 1. The ASIC in the correlation radiometer system.
its 2nd prototype will be provided for customers.
ASIC, 1st Prototype FPGA Data Out The project includes the following milestones:
Analog Frontend DSP
◊ 1. Feasibility is proven based on simulations
◊ 2. Prototype ASIC chip is designed and taped out
New ASIC ◊ 3. Prototype chip is fabricated/tested
IA 0-10GHz 4x[Magn, Sign]
XC
VGA
4xTI
2-bit ADC
8
4:8 8:64
64-ch PFB
#64 of 64
◊ 4. Final/customized chip is designed and taped out
64x2b

rst
2 x 19b

4GHz AGC
DAC Manual control + Totalizer
◊ 5. Final chip is fabricated, tested, and sales are started
64x2x2b

QA 0-10GHz 4xTI 8
4x[Magn, Sign]
j
+
VGA 2-bit ADC 4:8 8:64 -
64x2b

rst

◊3 ◊5
4GHz AGC
DAC Manual control
Data Interface

2 x 2b
4x5GHz

Skew
Φ Φ control
MUX

clk_demux Time skew

◊4
2.5GHz

◊1 ◊2
and Adjustable Adj
Phase Totalizers
10GHz comparator Coefficients XC
/2 detector Thresh
and sync clk_demux offset
circuit 2.5GHz
calibrations
4x5GHz

Φ Skew
Φ control
2 x 2b
4x[Magn, Sign]
IB 4xTI rst
2 x 19b

8 64-ch PFB
VGA 2-bit ADC 4:8 8:64
64x2b

4GHz
DAC AGC +
Manual control +
-
Controls and
Diagnostics
2022 2023 2024 2025 2026
64x2x2b

QB 4xTI 8
rst
4x[Magn, Sign]
j
Totalizer
VGA 2-bit ADC 4:8 8:64
64x2b

Bands: 64 x 312.5MHz Registers

4GHz
DAC AGC #1 of 64

DSP
Manual control

1GHz I2C Current TRL: 2, Estimated final TRL: 6

PLL 10GHz / 312.5MHz
Reference 32
Clock

Figure 2. A block diagram of the ASIC.

The chip is assembled in an LTCC BGA chip package (Fig. 3). An
evaluation board (Fig. 4) will be supplied to selected customers.
Applications
• Remote sensing instruments
TBD TBD TBD • Radio astronomy
• Planet and Sun exploration missions
• Distributed spacecraft missions
Figure 3. The ASIC chip (left), BGA (center), and packaged • Communication and navigation satellites
part (right). • Synthetic aperture radars and radiometers

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