Digital Design using FPGA
VHDL
Reem Ibrahim, PHD.
Outline
• Evolution of Programmable Devices?
• Why use FPGAs?
• FPGA Challenges
• FPGA Generic Design Flow
• Hardware Description Languages
• FPGA Applications
• FPGA Markets
• Design issues (Combinational ,Sequential)
• FPGA Course outline - Projects
Evolution of Programmable
Devices
Digital Logic
Digital Logic Function
3 Inputs
Transistor Switches
Programmable Read Only Memories (PROMs)
– Memory programmed by user to contain a specific pattern
(a microprocessor program, a simple algorithm, or a state
machine)
– Some PROMs can be programmed once only.
– EPROMs or EEPROMs can be erased and programmed
multiple times.
– Used for implementing combinatorial logic with a limited
number of inputs and outputs
– PROMs tend to be extremely slow
Programmable Logic Arrays (PLAs)
• Solution to the speed and
input limitations of
PROMs.
• The first programmable
chips were PLAs : two
level structures of AND
and OR gates with user
programmable
connections.
Programmable AND Logic (PALs)
• Programmable AND plane Fixed OR
plane.
• Basic logic devices: Muxs, XORs &
latches are added to the inputs and
outputs.
• Clocked flip-flops, included.
• implement a large number of logic
functions , clocked sequential logic
need for state machines.
• PALs are also extremely fast.
• PLD (Programmable Logic Devices)
Programmable Logic Devices
(PLDs)
• Simple PLDs could only handle up to
10–20 logic equations couldn't fit
very large logic designs into just one
of them need set of PLDs.
– time-consuming
– interconnect the PLDs with wires new
circuit board
Solutions
Building larger programmable chips
complex programmable logic devices (CPLDs)
&
field-programmable gate arrays (FPGAs).
CPLD
• A CPLD contains sets of PLD blocks whose inputs and outputs
are connected together by a global interconnection matrix
• Two levels of programmability:
– each PLD block can be programmed
– the interconnections between the PLDs can be programmed.
FB
FB FB
FB
CPLD Architecture
CPLD
• A CPLD contains sets of PLD blocks whose inputs and outputs
are connected together by a global interconnection matrix
• Two levels of programmability:
– each PLD block can be programmed
– the interconnections between the PLDs can be programmed.
Function Block (FB)
Application Specific Integrated Circuit
(ASIC)
material (e.g., silicon), insulators (e.g., oxides)
Gate array is done with metal mask design and processing.
Field Programmable Gate Arrays FPGA
Prefabricated Custom Fabricated
Programmed Design from Scratch
Limited Complexity Large Complex Functions . Millions of Gates
Thousands of Gates Customised for Extremes of Speed, Low Power, Radiation
Hard
(Very) Expensive (in small quantities) > $1 Million mask set
Cheap (Very) Hard to Design.
Easy to Design Long Design cycles.
Reprogrammable. NOT Reprogrammable. High Risk
Field Programmable Gate Arrays FPGA
FPGA
Inexpensive
Easy to Design Large Complex Functions
Reprogrammable.
Field Programmable Gate Arrays FPGA
• Field Programmable Gate Array
– Programmable Logic Blocks
– Massive of Programmable Interconnects
Large Number of Logic
Block ‘Islands’
1,000 … 100,000+
in ‘Sea’ of Interconnects
Interconnection between cells:
– Using SRAM based switches.
– Using antifuse elements.
FPGA Architecture
Logic Blocks
• Logic Functions implemented in Lookup Table LUTs
• Multiplexers (select 1 of N inputs)
• Flip-Flops. Registers. Clocked Storage elements.
16-bit SR
16x1 RAM
a 4-input
LUT
b
y
c
mux
d flip-flop
q
e
clock
clock enable
set/reset
FPGA Logic Block
Why use FPGAs?
• Increasing speed.
• Increased I/O pin count and bandwidth
• Lower power
• Integration of hard IP (e.g. multipliers, PowerPC
cores).
FPGA Challenges
1. Will FPGAs sustain their performance lead
over microprocessor technology?
250
200
150
100
50
0
Computation Memory Bandwidth IO Bandwidth
(GOPS) (GB/sec) (Gbps)
Pentium Virtex-4
www.openfpga.org
2. Why FPGAs for DSP?
FPGAs handle high computational workloads.
2. Why FPGAs for DSP?
FPGAs handle high computational workloads.
FPGA Generic Design Flow
Specifications
RST Output
CLK
Enable_out
Input_data AES
KEY_IN
SYSTEM
LD_KEY
Enc_dec
Signal I/O Width(bits) Description
Input_data I 128 Plaintext/Ciphertext data address.
KEY_IN I 128 Encryption key data
LD_KEY I 1 Load encryption key
CLK I 1 Clock signal
Enc/Dec I 1 mode select 1: Encryption, 0: Decryption
RST I 1 Asynchronous reset
Enable_out O 1 Indicating the Plaintext/Ciphertext word output is valid
Output O 128 Plaintext / Ciphertext data
FPGA Generic Design Flow
HDL Entry
Hardware description language (Verilog, VHDL)
Library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity AES_core is
port(
clock, rst, enc_dec: in std_logic;
input_data_: in std_logic_vector(31 downto 0);
output: out std_logic_vector(31 downto 0);
enable_out: out std_logic;
key_in: in std_logic_vector(31 downto 0);
ld_key: in std_logic;
);
end AES_core;
FPGA Generic Design Flow
Synthesis
Produce synthesized circuit netlist in a standard EDIF format
FPGA Generic Design Flow
Place
choose which specific logic blocks to use in the FPGA.
FPGA Generic Design Flow
Route
Route the logic blocks.
FPGA
FPGA Generic Design Flow
Bit File Generation
Download to FPGA
Bit File
Download
Board Test
FPGA Generic Design Flow
CAD Tools Design Stage Tools
VHDL Design Text Editor
FPGAadv
Simulation ISIM Simulator
Modelsim SE
Synthesis Xilinx ISE – XST
Leonardo
Pyhsical Design & Xilinx ISE
Implementation Xilinx Impact
Hardware Description Languages
• Two Widely Used Languages
– Verilog HDL
• C-language like syntax, easy to learn
– VHDL
• VHSIC Hardware Description Language
• VHSIC - Very High Speed Integrated Circuits
• Follows the structure of ADA programming Language
• Originally intended as a Simulation Language for very large
systems
• Verilog and VHDL each have about 50% share of the
commercial user base.
FPGA Applications
• What is a good application for FPGAs?
– High speed needed
– Computation can be parallelized
– Arithmetic operations
– Reconfigurability important
• Small to medium sized production quantities
– No strict power constraints
• FPGAs increasingly replacing ASICs
– Cost efficiency
FPGA Markets
• FPGA manufacturers
– Xilinx
– Altera
– Actel
– Atmel, Cypress, Lattice,…
Course Objectives
• Mastering VHDL.
• Design flows for FPGA.
• Learning about computer-aided design tools
for FPGAs (FPGAadv – XilinX)
• Designing complete digital systems.
Course Objectives
Lec Contents
(1) Introduction to FPGA Design Flow
(2) Top-Down Design Methodology (Model types: Structural model,
Behavioral model).
(3) VHDL Basics – Data Types
VHDL Examples
(4) Combinational Logic Concepts and examples
(5) Sequential Logic Concepts (Clock, Reset, Met-stability) examples.
Writing synthesizable VHDL codes
(6) Memory Design (RAM, ROM)
Functions , Procedures
(7) Dealing with Xilinx ISE Design Suite - Schematic
(8) Digital Design using IP Cores
(9) (10) Complete FPGA Design Flow - Practicing Xilinx ISE Place & route tool.
Course Examples/ Projects Implementation
Demo Board
