Ade Mod2@Azdocuments - in
Ade Mod2@Azdocuments - in
18CS33
MODULE – 2
THE COMBINATIONAL LOGIC CIRCUITS
THE BASIC GATES
PREREQUISITES:
Electronic circuits and systems can be divided into two broad categories – analog and digital. Analog
circuits are designed for use with small signals and are used in a linear fashion. Digital circuits are
generally used with large signals and are considered nonlinear. Any quantity that changes with time can
be represented as an analog signal or it can be treated as digital signal.
Digital electronics involves circuits that have exactly two possible states. A system having only
two states is said to be binary. The binary number system is widely used in digital electronics.
Hexa-Decimal Decimal Binary Hexa-Decimal Decimal Binary
0 0 0000 8 8 1000
1 1 0001 9 9 1001
2 2 0010 A 10 1010
3 3 0011 B 11 1011
4 4 0100 C 12 1100
5 5 0101 D 13 1101
6 6 0110 E 14 1110
7 7 0111 F 15 1111
The operation of electronic circuits can be described in terms of its voltage levels – high (H) level and low
(L) level. This could be related to the binary number system by assigning L = 0 = F (false) and H = 1 = T
(true).
1
ANALOG AND DIGITAL ELECTRONICS
18CS33
REVIEW OF LOGIC GATES:
Truth Table
Circuit Symbol VHDL IC Details
A B X
NOT Gate: 0 - 1
X = ~A
X <= not A;
1 - 0
𝑋𝑋 = 𝐴𝐴̅
OR Gate: 0 0 0
0 1 1 X=A|B
1 0 1 X <= A or B;
𝑋𝑋 = 𝐴𝐴 + 𝐵𝐵 1 1 1
AND Gate: 0 0 0
0 1 0 X=A&B
1 0 0 X <= A and B;
𝑋𝑋 = 𝐴𝐴. 𝐵𝐵 1 1 1
NOR Gate: 0 0 1
0 1 0 X = ~(A | B)
1 0 0 X <= A nor B;
𝑋𝑋 = 𝐴𝐴̅. 𝐵𝐵� 1 1 0
NAND Gate: 0 0 1
0 1 1 X = ~(A & B)
1 0 1 X <= A nand B;
𝑋𝑋 = 𝐴𝐴̅ + 𝐵𝐵� 1 1 0
XOR Gate: 0 0 0
0 1 1 X=A^B
1 0 1 X <= A xor B;
𝑋𝑋 = 𝐴𝐴⨁𝐵𝐵
1 1 0
= 𝐴𝐴̅𝐵𝐵 + 𝐴𝐴𝐵𝐵�
XNOR Gate: 0 0 1
0 1 0
X = ~(A ^ B)
1 0 0
X <= A xnor B;
𝑋𝑋 = 𝐴𝐴⨀𝐵𝐵
1 1 1
= 𝐴𝐴̅𝐵𝐵� + 𝐴𝐴𝐴𝐴
2
ANALOG AND DIGITAL ELECTRONICS
18CS33
Universality of NOR Gate:
3
ANALOG AND DIGITAL ELECTRONICS
18CS33
Proof:
A B A+B ��������
𝐴𝐴 + 𝐵𝐵 𝐴𝐴̅ 𝐵𝐵� 𝐴𝐴̅. 𝐵𝐵�
0 0 0 1 1 1 1
0 1 1 0 1 0 0
1 0 1 0 0 1 0
1 1 1 0 0 0 0
NOR Gate Bubbled AND Gate
Bubbled OR Gate:
Duality Theorem: Starting with a Boolean relation, you can derive another Boolean relation by –
1. Changing each OR sign to an AND sign
2. Changing each AND sign to an OR sign
3. Complementing any 0 or 1appearing in the expression.
Example: 1. We say that, A+0 = A; the dual is, A.1 = A
2. Consider, A(B+C) = AB + AC
By changing the OR and AND operation, we get the dual relation:
A + BC = (A+B)(A+C)
4
ANALOG AND DIGITAL ELECTRONICS
18CS33
Note that, if A is a variable, then either A = 0 or A = 1. Also, when A = 0, A ≠ 1;
and when A = 1, A ≠ 0.
1) Commutative Law:-
A+B=B+A and A.B=B.A
2) Associative Law:-
A + (B + C) = (A + B) + C and A . (BC) = (AB) . C
3) Distributive Law:-
A(B + C) = AB + AC
5
ANALOG AND DIGITAL ELECTRONICS
18CS33
Simplification of Boolean Expressions:-
The following hints are found to be of use, in reducing complex Boolean expressions –
1. If there are parentheses present in the given expression, they are removed first; since,
multiplication should precede addition.
E.g.:- AB + C (A + B) = AB + AC + BC
2. If there are several identical terms, all except one can be removed.
E.g.:- A + B + C + A . 1 = A + B + C + A = A + B + C
3. If a variable repeats in a term, only one variable may be retained.
E.g.:- A . A = A
B .B . C = BC
4. If in any term, both a variable & its complement are present, that term may be removed; since,
AA’ = 0.
E.g.:- XX’Y = 0 . Y = 0
5. Identify pairs of terms which contains same variables. If in a pair, a variable is absent in one term,
it can be removed.
E.g.:- ABCD + ABC = ABC (D + 1)
= ABC . 1 since, 1 + D =1
= ABC
6. If, in a pair of terms, several variables are common, and another variable is present in one term &
its complement is present in another term, this variable & its complement can be removed.
E.g.:- ABC + A’BC = BC (A’ + A)
= BC . 1 since, A’ + A = 1
= BC
KARNAUGH MAPS
MINIMUM FORMS OF SWITCHING FUNCTIONS:
When a function is realized using AND and OR gates, the cost of realizing the function is directly related
to the number of gates and gate inputs used. The Karnaugh map techniques developed, lead directly to
minimum cost two-level circuits composed of AND and OR gates. An expression consisting of a sum-of-
product terms corresponds directly to a two-level circuit composed of a group of AND gates feeding a
single OR gate (see the following Figure). Similarly, a product-of-sums expression corresponds to a two-
level circuit composed of OR gates feeding a single AND gate.
Therefore, to find minimum cost two-level AND-OR gate circuits, we must find minimum expressions in
sum-of-products or product-of-sums form.
6
ANALOG AND DIGITAL ELECTRONICS
18CS33
A minimum sum-of-products expression for a function is defined as a sum of product terms which
a) has a minimum number of terms and
b) of all those expressions which have the same minimum number of terms, has a minimum number
of literals.
The minimum sum of products corresponds directly to a minimum two-level gate circuit which has
a) a minimum number of gates and
b) a minimum number of gate inputs.
Unlike the minterm expansion for a function, the minimum sum of products is not necessarily unique; that
is, a given function may have two different minimum sum-of-products forms, each with the same number
of terms and the same number of literals.
Given a minterm expansion, the minimum sum-of products form can often be obtained by the following
procedure:
1. Combine terms by using 𝑋𝑋𝑌𝑌 ′ + 𝑋𝑋𝑋𝑋 = 𝑋𝑋(𝑌𝑌 ′ + 𝑌𝑌) = 𝑋𝑋. Do this repeatedly to eliminate as many
literals as possible. A given term may be used more than once because X+X=X.
2. Eliminate redundant terms by using the theorems of Boolean Algebra.
A minimum product-of-sums expression for a function is defined as a product of sum terms which
a) has a minimum number of factors, and
b) of all those expressions which have the same number of factors, has a minimum number of
literals.
Unlike the maxterm expansion, the minimum product-of-sums form of a function is not necessarily
unique. Given a maxterm expansion, the minimum product of sums can often be obtained by a procedure
similar to that used in the minimum sum-of-products case, except that the theorem (𝑋𝑋 + 𝑌𝑌 ′ )(𝑋𝑋 + 𝑌𝑌) = 𝑋𝑋
is used to combine terms.
7
ANALOG AND DIGITAL ELECTRONICS
18CS33
Y – Fundamental Min-
A B C A B C Y – Fundamental Sum Max-term
Product term
0 0 0 0 m0 0 0 0 0–A+B+C M0
0 0 1 0 m1 0 0 1 0 – A + B + 𝐶𝐶̅ M1
0 1 0 0 m2 0 1 0 0 – A + 𝐵𝐵� + C M2
0 1 1 1 – 𝐴𝐴̅𝐵𝐵𝐵𝐵 m3 0 1 1 1 M3
1 0 0 0 m4 1 0 0 0 – 𝐴𝐴̅ + B + C M4
1 0 1 1 – 𝐴𝐴𝐵𝐵�𝐶𝐶 m5 1 0 1 1 M5
1 1 0 1 – 𝐴𝐴𝐴𝐴𝐶𝐶̅ ̇ m6 1 1 0 1 M6
1 1 1 1 – 𝐴𝐴𝐴𝐴𝐴𝐴 m7 1 1 1 1 M7
YSOP = 𝐴𝐴̅𝐵𝐵𝐵𝐵 + 𝐴𝐴𝐵𝐵�𝐶𝐶 + 𝐴𝐴𝐴𝐴𝐶𝐶̅ + 𝐴𝐴𝐴𝐴𝐴𝐴 YPOS = (A + B + C) (𝐴𝐴 + 𝐵𝐵 + 𝐶𝐶̅ ) (𝐴𝐴 + 𝐵𝐵� + 𝐶𝐶) (𝐴𝐴̅ + 𝐵𝐵 + 𝐶𝐶)
= ∑m(1, 2, 4, 7). = ∏M(0, 1, 2, 4).
8
ANALOG AND DIGITAL ELECTRONICS
18CS33
Example: Adders & Subtractors
Adder circuit is a combinational digital circuit that is used for adding two numbers. A typical adder
circuit produces a sum bit (denoted by S) and a carry bit (denoted by C) as the output. Adder circuits are
of two types: Half adder ad Full adder.
Subtractor is the one which used to subtract two binary numbers (digits) and provides Difference and
Borrow as an output.
Half Adder & Half Subtractor:
9
ANALOG AND DIGITAL ELECTRONICS
18CS33
1 0 1 0 1 1 0 1 0 0
1 1 0 0 1 1 1 0 0 0
1 1 1 1 1 1 1 1 1 1
Sum, S = ∑m (1, 2, 4, 7) = ∏M(0, 3 , 5, 6). Difference, D = ∑m (1, 2, 4, 7) = ∏M(0, 3, 5, 6).
𝑆𝑆𝑆𝑆𝑆𝑆, 𝑆𝑆 = 𝐴𝐴̅𝐵𝐵�𝐶𝐶 + 𝐴𝐴̅𝐵𝐵𝐶𝐶̅ + 𝐴𝐴𝐵𝐵�𝐶𝐶̅ + 𝐴𝐴𝐴𝐴𝐴𝐴 𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷. , 𝐷𝐷 = 𝐴𝐴̅𝐵𝐵�𝐶𝐶 + 𝐴𝐴̅𝐵𝐵𝐶𝐶̅ + 𝐴𝐴𝐵𝐵�𝐶𝐶̅ + 𝐴𝐴𝐴𝐴𝐴𝐴
����) + 𝐶𝐶(𝐴𝐴̅𝐵𝐵� + 𝐴𝐴𝐴𝐴)
𝑂𝑂𝑂𝑂, 𝑆𝑆 = 𝐶𝐶̅ (𝐴𝐴̅𝐵𝐵 + 𝐴𝐴𝐵𝐵 ���)� + 𝐶𝐶(𝐴𝐴̅𝐵𝐵� + 𝐴𝐴𝐴𝐴)
𝑂𝑂𝑂𝑂, 𝐷𝐷 = 𝐶𝐶̅ (𝐴𝐴̅𝐵𝐵 + 𝐴𝐴𝐵𝐵
𝑂𝑂𝑂𝑂, 𝑆𝑆 = 𝐶𝐶̅ (𝐴𝐴⨁𝐵𝐵) + 𝐶𝐶(𝐴𝐴 ⊙ 𝐵𝐵) 𝑂𝑂𝑂𝑂, 𝐷𝐷 = 𝐶𝐶̅ (𝐴𝐴⨁𝐵𝐵) + 𝐶𝐶(𝐴𝐴 ⊙ 𝐵𝐵)
����������
𝑂𝑂𝑂𝑂, 𝑆𝑆 = 𝐶𝐶̅ (𝐴𝐴⨁𝐵𝐵) + 𝐶𝐶(𝐴𝐴 ⊕ 𝐵𝐵) ����������
𝑂𝑂𝑂𝑂, 𝐷𝐷 = 𝐶𝐶̅ (𝐴𝐴⨁𝐵𝐵) + 𝐶𝐶(𝐴𝐴 ⊕ 𝐵𝐵)
𝑇𝑇ℎ𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒, 𝑺𝑺 = 𝑨𝑨 ⊕ 𝑩𝑩 ⊕ 𝑪𝑪 𝑇𝑇ℎ𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒, 𝑫𝑫 = 𝑨𝑨 ⊕ 𝑩𝑩 ⊕ 𝑪𝑪
10
ANALOG AND DIGITAL ELECTRONICS
18CS33
The following Figure shows a three-variable truth table and the corresponding Karnaugh map:
Example: Write the Karnaugh Map for – (a) f = ∑m (1, 3, 5) (b) 𝑓𝑓(𝑎𝑎, 𝑏𝑏, 𝑐𝑐) = 𝑎𝑎𝑎𝑎𝑐𝑐 ′ + 𝑏𝑏 ′ 𝑐𝑐 + 𝑎𝑎′
(c) F = ∑m (0, 1, 2, 5, 6, 7)
Solution: (a) f = ∑m (1, 3, 5) (b) 𝑓𝑓(𝑎𝑎, 𝑏𝑏, 𝑐𝑐) = 𝑎𝑎𝑎𝑎𝑐𝑐 ′ + 𝑏𝑏 ′ 𝑐𝑐 + 𝑎𝑎′ (c) F = ∑m (0, 1, 2, 5, 6, 7)
11
ANALOG AND DIGITAL ELECTRONICS
18CS33
Example: Find two different minimum sum-of-products expressions for the function G = ∑m (0, 2, 3, 4, 5,
7).
Solution: Given, G = ∑m (0, 2, 3, 4, 5, 7);
𝑐𝑐̅𝑑𝑑̅ 0 4 12 8
00
1 5 13 9
𝑐𝑐̅d 01
3 7 15 11
𝑐𝑐𝑐𝑐 11
2 6 14 10
𝑐𝑐𝑑𝑑̅ 10
f (a, b, c, d) =
12
ANALOG AND DIGITAL ELECTRONICS
18CS33
Solution:
𝑤𝑤
�𝑥𝑥̅ 𝑤𝑤
�𝑥𝑥 wx 𝑤𝑤𝑥𝑥̅ 0 1
f Y
𝑦𝑦�𝑧𝑧̅ 00
𝑦𝑦�𝑧𝑧 01
𝑦𝑦𝑦𝑦 11
𝑦𝑦𝑧𝑧̅ 10
f (w, x, y, z) = Y (A, B, C) =
Example: Write the Karnaugh map for (a) f1 = = ∑m (3, 4, 5, 6, 7, 9, 12, 13); (b) f2 = = ∑m (2, 3, 5, 7,
8, 10, 11, 15).
Solution: (a) Given, f1 = = ∑m (3, 4, 5, 6, 7, 9, 12, 13) & f2 = = ∑m (2, 3, 5, 7, 8, 10, 11, 15);
The following Figure shows the flowchart for determining a Minimum Sum of Products using a Karnaugh
Map with an Example.
13
ANALOG AND DIGITAL ELECTRONICS
18CS33
14
ANALOG AND DIGITAL ELECTRONICS
18CS33
PAIRS, QUADS, AND OCTETS:
Pairs: The following K-map contains a pair of 1s that are horizontally adjacent. Two adjacent 1s, such as
these are called a pair. A pair eliminates one variable and its complement.
Quad: A quad is a group of four 1s that are horizontally or vertically adjacent. A quad eliminates two
variables and their complements.
Y
𝐴𝐴̅𝐵𝐵� 𝐴𝐴̅𝐵𝐵 AB A𝐵𝐵�
0 0 1 0 The sum-of-product equation is:
𝐶𝐶̅ 𝐷𝐷
� 𝑌𝑌 = 𝐴𝐴𝐴𝐴𝐴𝐴′ + 𝐴𝐴𝐴𝐴𝐴𝐴 = 𝐴𝐴𝐴𝐴(𝐶𝐶 + 𝐶𝐶 ′ ) = 𝐴𝐴𝐴𝐴
0 0 1 0
𝐶𝐶̅ D
0 0 1 0
𝐶𝐶𝐶𝐶 0 0 1 0
�
𝐶𝐶𝐷𝐷
The Octet: The octet is a group of eight 1s, as shown in the following Fig. An octet eliminates three
variables and their complements.
15
ANALOG AND DIGITAL ELECTRONICS
18CS33
KARNAUGH SIMPLIFICATIONS:
A pair eliminates one variable and its complement. A quad eliminates two variables and their
complements. An octet eliminates three variables and their complements. Because of this, after drawing
the K-map, first encircle the octets, then the quads, and finally the pairs, to get highest simplification.
Example: Using K-map, simplify; Y = ∑m (1, 2, 3, 6, 8, 9, 10, 12, 13, 14).
Solution:
Y 𝐴𝐴̅𝐵𝐵� 𝐴𝐴̅𝐵𝐵 AB A𝐵𝐵�
𝐶𝐶̅ 𝐷𝐷
� 0 0 1 1
1 0 1 1
𝐶𝐶̅ D
1 0 0 0
𝐶𝐶𝐶𝐶
1 1 1 1 𝑌𝑌 = 𝐴𝐴𝐶𝐶 ′ + 𝐶𝐶𝐷𝐷 ′ + 𝐴𝐴′𝐵𝐵′𝐷𝐷
�
𝐶𝐶𝐷𝐷
𝐶𝐶̅ 𝐷𝐷
� 0 0 0 0
𝐶𝐶̅ 𝐷𝐷
� 0 0 0 0
0 1 0 0
𝐶𝐶̅ D 𝐶𝐶̅ D
0 1 0 0
1 1 1 1 1 1 1 1
𝐶𝐶𝐶𝐶 𝐶𝐶𝐶𝐶
1 1 1 1 1 1 1 1
�
𝐶𝐶𝐷𝐷 �
𝐶𝐶𝐷𝐷
Y1 = Y2 =
Rolling the Map:
𝐶𝐶̅ 𝐷𝐷
� 0 0 0 0 𝐶𝐶̅ 𝐷𝐷
� 0 0 0 0
1 0 0 1 1 0 0 1
𝐶𝐶̅ D 𝐶𝐶̅ D
1 0 0 1 1 0 0 1
𝐶𝐶𝐶𝐶 𝐶𝐶𝐶𝐶
0 0 0 0 0 0 0 0
�
𝐶𝐶𝐷𝐷 �
𝐶𝐶𝐷𝐷
Y3 = Y4 =
16
ANALOG AND DIGITAL ELECTRONICS
18CS33
Rolling and Overlapping:
1 1 0 1 1 1 0 1
𝐶𝐶̅ D 𝐶𝐶̅ D
1 1 0 1 1 1 0 1
𝐶𝐶𝐶𝐶 𝐶𝐶𝐶𝐶
1 1 0 0 1 1 0 0
� �
𝐶𝐶𝐷𝐷
𝐶𝐶𝐷𝐷
Y1 = Y2 =
1 1 0 1 1 1 0 1 1 1 0 1
𝐶𝐶̅ D 𝐶𝐶̅ D 𝐶𝐶̅ D
1 1 0 0 1 1 0 0 1 1 0 0
𝐶𝐶𝐶𝐶 𝐶𝐶𝐶𝐶 𝐶𝐶𝐶𝐶
1 1 0 1 1 1 0 1 1 1 0 1
�
𝐶𝐶𝐷𝐷 �
𝐶𝐶𝐷𝐷 �
𝐶𝐶𝐷𝐷
Y3 = Y4 = Y5 =
Eliminating Redundant Groups: After encircling groups, eliminate any redundant groups. This is a
group whose 1s are already used by other groups.
1 1 1 0 1 1 1 0 1 1 1 0
𝐶𝐶̅ D 𝐶𝐶̅ D 𝐶𝐶̅ D
0 1 1 1 0 1 1 1 0 1 1 1
𝐶𝐶𝐶𝐶 𝐶𝐶𝐶𝐶 𝐶𝐶𝐶𝐶
0 1 0 0 0 1 0 0 0 1 0 0
�
𝐶𝐶𝐷𝐷 �
𝐶𝐶𝐷𝐷 �
𝐶𝐶𝐷𝐷
17
ANALOG AND DIGITAL ELECTRONICS
18CS33
Homework:
1] Determine the minimum sum-of-products for –
a) f1 (a, b, c) = ∑(1, 3, 4, 5, 6, 7)
b) f2 (a, b, c) = Π (2, 4, 7)
c) f3 (a, b, c, d) = 𝑏𝑏 ′ 𝑐𝑐 ′ 𝑑𝑑′ + 𝑏𝑏𝑏𝑏𝑏𝑏 + 𝑎𝑎𝑎𝑎𝑑𝑑 ′ + 𝑎𝑎′ 𝑏𝑏 ′ 𝑐𝑐 + 𝑎𝑎′𝑏𝑏𝑏𝑏′𝑑𝑑
2] Determine the minimum product-of-sums for –
a) f1 (a, b, c) = ∑ (0, 1, 2,3, 4, 6, 7)
b) f2 (a, b, c) = Π (1, 4, 5)
c) f3 (a, b, c, d) = 𝑏𝑏 ′ 𝑐𝑐 ′ 𝑑𝑑′ + 𝑏𝑏𝑏𝑏𝑏𝑏 + 𝑎𝑎𝑎𝑎𝑑𝑑 ′ + 𝑎𝑎′ 𝑏𝑏 ′ 𝑐𝑐 + 𝑎𝑎′𝑏𝑏𝑏𝑏′𝑑𝑑
3] Solve for the simplified Boolean expression using K-Map:
a) 𝑓𝑓1 (𝑎𝑎, 𝑏𝑏, 𝑐𝑐, 𝑑𝑑) = 𝑎𝑎�𝑐𝑐̅𝑑𝑑 + 𝑎𝑎�𝑐𝑐𝑐𝑐 + 𝑏𝑏�𝑐𝑐̅𝑑𝑑̅ + 𝑎𝑎𝑏𝑏�𝑐𝑐 + 𝑎𝑎�𝑏𝑏�𝑐𝑐𝑑𝑑̅
b) 𝑓𝑓2 (𝑎𝑎, 𝑏𝑏, 𝑐𝑐, 𝑑𝑑) = �𝑎𝑎 + 𝑏𝑏 + 𝑑𝑑̅��𝑎𝑎� + 𝑏𝑏 + 𝑑𝑑̅��𝑎𝑎 + 𝑏𝑏� + 𝑐𝑐̅ + 𝑑𝑑��𝑎𝑎� + 𝑏𝑏� + 𝑐𝑐̅ + 𝑑𝑑̅�(𝑎𝑎� + 𝑏𝑏� + 𝑐𝑐̅ +
𝑑𝑑)
4] Find the minimum sum-of-products for –
(a) f1 (a, b, c) = m0 + m2 + m5 + m6 (b) f2 (d, e, f) = ∑m (0, 1, 2, 4)
(c) f3 (r, s, t) = 𝑟𝑟𝑡𝑡 ′ + 𝑟𝑟 ′ 𝑠𝑠 ′ + 𝑟𝑟′𝑠𝑠) (d) f4 (x, y, z) = M0 . M5
5] Design a 3-input, 1-output, minimal two-level gate combinational circuit; which has an output equal to
1 when majority of its inputs are at logic 1, and has output 0 when majority of inputs are at logic 0.
6] Design a minimal sum and minimal product combinational gate circuit to generate the odd parity bit
for an 8421 BCD code.
18
ANALOG AND DIGITAL ELECTRONICS
18CS33
Two minterms will combine if they differ in exactly one variable. The examples given below
show both the binary notation and its algebraic equivalent.
In order to find all of the prime implicants, all possible pairs of minterms should be compared and
combined whenever possible. To reduce the required number of comparisons, the binary
minterms are sorted into groups according to the number of 1’s in each term.
Now, function; f(a, b, c, d) = ∑m (0, 1, 2, 5, 6, 7, 8, 9, 10, 14) can be represented by following list of
minterms:
In this list, the term in group 0 has zero 1’s, the terms in
group 1 have one 1, those in group 2 have two 1’s, and
those in group 3 have three 1’s.
Two terms can be combined if they differ in exactly one
variable. Only terms in adjacent groups must be compared.
First, we will compare the term in group 0 with all of the
terms in group 1.Terms 0000 and 0001 can be combined to
eliminate the fourth variable, which yields 000– (𝑎𝑎′𝑏𝑏′𝑐𝑐′).
Similarly, 0 and 2 combine to form 00–0 (𝑎𝑎′𝑏𝑏′𝑑𝑑′), and 0 and 8 combine to form –000 (𝑏𝑏′𝑐𝑐′𝑑𝑑′).
The resulting terms are listed in Column II of the following Table.
Whenever two terms combine, the corresponding decimal numbers differ by a power of 2 (1, 2, 4,
8, etc.).
Since the comparison of group 0 with groups 2 and 3 is unnecessary, we proceed to compare
terms in groups 1 and 2. Comparing term 1 with all terms in group 2, we find that it combines
with 5 and 9 but not with 6 or 10. Similarly, term 2 combines only with 6 and 10, and term 8 only
with 9 and 10. The resulting terms are listed in Column 2.
Each time a term is combined with another term, it is checked off. Also note that, a term may be
used more than once. Even though two terms have already been combined with other terms, they
still must be compared and combined if possible.
At this stage, we may generate redundant terms, but these redundant terms will be eliminated
later.
19
ANALOG AND DIGITAL ELECTRONICS
18CS33
We finish with Column 1 by comparing terms in groups 2 and 3. New terms are formed by
combining terms 5 and 7, 6 and 7, 6 and 14, and 10 and 14.
a b c d f Column 1 Column 2 Column 3
0 0 0 0 1 abcd abcd abcd
0 0 0 1 1
0 0 1 0 1
0 0 1 1 0
0 1 0 0 0
0 1 0 1 1
0 1 1 0 1
0 1 1 1 1
1 0 0 0 1
1 0 0 1 1
1 0 1 0 1
1 0 1 1 0
1 1 0 0 0
1 1 0 1 0
1 1 1 0 1
1 1 1 1 0
Note that the terms in Column 2 have been divided into groups. In order to combine two terms,
the terms must have the same variables, and the terms must differ in exactly one of these
variables. Thus, it is necessary only to compare terms which have dashes (missing variables) in
corresponding places and which differ by exactly one in the number of 1’s.
Terms in the first group in Column 2 need only be compared with terms in the second group
which have dashes in the same places. Term 000– (0, 1) combines only with term 100– (8, 9) to
yield –00– (𝑏𝑏′𝑐𝑐′).
The resulting term is listed in Column 3 along with the designation 0, 1, 8, 9 to indicate that it
was formed by combining minterms 0, 1, 8, and 9.
Term (0, 2) combines only with (8, 10), and term (0, 8) combines with both (1, 9) and (2, 10).
Again, the terms which have been combined are checked off. Comparing terms from the second
and third groups in Column 2, we find that (2,6) combines with (10, 14), and (2, 10) combines
with (6,14).
Note that there are three pairs of duplicate terms in Column 3. These duplicate terms were formed
in each case by combining the same set of four minterms in a different order.
20
ANALOG AND DIGITAL ELECTRONICS
18CS33
After deleting the duplicate terms, we compare terms from the two groups in Column 3. Because
no further combination is possible, the process terminates.
In general, we would keep comparing terms and forming new groups of terms and new columns
until no more terms could be combined. The terms which have not been checked off because they
cannot be combined with other terms are called prime implicants. Because every minterm has
been included in at least one of the prime implicants, the function is equal to the sum of its prime
implicants. In this example we have;
Definition:
Given a function F of n variables, a product term P is an implicant of F iff for every combination
of values of the n variables for which P = 1, F is also equal to 1.
A prime implicant of a function F is a product term implicant which is no longer an implicant if
any literal is deleted from it.
Consider an Example:
o In the above function, the implicant 𝑎𝑎′𝑏𝑏′𝑐𝑐′ is not a prime implicant because a can be eliminated,
and the resulting term 𝑏𝑏′𝑐𝑐′ is still an implicant of F. The implicants 𝑏𝑏 ′ 𝑐𝑐 ′ and 𝑎𝑎𝑎𝑎 are prime
implicants because if we delete a literal from either term, the term will no longer be an implicant
of F.
The Quine-McCluskey method, as previously illustrated, finds all of the product term implicants of a
function. The implicants which are nonprime are checked off in the process of combining terms, so that
the remaining terms are prime implicants. Any nonprime term in a sum-of-products expression can thus
be replaced with a prime implicant, which reduces the number of literals and simplifies the expression.
21
ANALOG AND DIGITAL ELECTRONICS
18CS33
following Table shows the prime implicant. All of the prime implicants (terms which have not
been checked off in the above Table) are listed on the left.
- 0 1 2 5 6 7 8 9 10 14
(0, 1, 8, 9) (𝑏𝑏 ′ 𝑐𝑐 ′ )
(0, 2, 8, 10) (𝑏𝑏′𝑑𝑑′)
(2, 6, 10, 14) (𝑐𝑐𝑐𝑐′)
(1, 5) (𝑎𝑎′𝑐𝑐′𝑑𝑑)
(5, 7) (𝑎𝑎′ 𝑏𝑏𝑏𝑏)
(6, 7) (𝑎𝑎′𝑏𝑏𝑏𝑏)
In the first row, X’s are placed in columns 0, 1, 8, and 9, because prime implicant 𝑏𝑏′𝑐𝑐′ was formed
from the sum of minterms 0, 1, 8, and 9. Similarly, the all other X’s are placed.
If a minterm is covered by only one prime implicant, then that prime implicant is called an
essential prime implicant and must be included in the minimum sum of products. Essential prime
implicants are easy to find using the prime implicant chart. If a given column contains only one
X, then the corresponding row is an essential prime implicant. In the above Table, columns 9 and
14 each contain one X, so prime implicants 𝑏𝑏′𝑐𝑐′ and 𝑐𝑐𝑐𝑐′ are essential.
Each time a prime implicant is selected for inclusion in the minimum sum, the corresponding row
should be crossed out. After doing this, the columns which correspond to all minterms covered by
that prime implicant should also be crossed out.
A minimum set of prime implicants must now be chosen to cover the remaining columns. In this
example, the resulting minimum sum of products is –
22
ANALOG AND DIGITAL ELECTRONICS
18CS33
The following Table shows the resulting prime implicants chart:
- 0 1 2 5 6 7
Therefore, F =
NOTE: A prime implicant chart which has two or more X’s in every column is called a cyclic prime
implicant chart.
Example: Solve, using Quine Mc-Cluskey method & K-Map method: F = ∑m (0, 1, 2, 8, 10, 11, 14, 15).
Solution:
Quine Mc-Clusky method:
A B C D F Stage 1 Stage 2 Stage 3
0 0 0 0 ABCD ABCD ABCD
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
23
ANALOG AND DIGITAL ELECTRONICS
18CS33
-
- 0 1 2 8 10 11 14 15
(0, 1) (𝐴𝐴′𝐵𝐵′𝐶𝐶′)
(0, 2, 8, 10) (𝐵𝐵′𝐷𝐷′)
(10, 11, 14, 15) (𝐴𝐴𝐴𝐴)
Therefore, F = 𝐴𝐴𝐴𝐴 + 𝐵𝐵′𝐷𝐷 + 𝐴𝐴′ 𝐵𝐵′ 𝐶𝐶′ ′
K-Map Method:
𝐶𝐶̅ 𝐷𝐷
�
𝐶𝐶̅ D
𝐶𝐶𝐶𝐶
F= 𝐴𝐴𝐴𝐴 + 𝐵𝐵′𝐷𝐷 ′ + 𝐴𝐴′ 𝐵𝐵′ 𝐶𝐶′
�
𝐶𝐶𝐷𝐷
PATRICK’S METHOD:
Petrick’s method is a technique for determining all minimum sum-of-products solutions from a
prime implicant chart. The example discussed above has two minimum solutions. As the number
of variables increases, the number of prime implicants and the complexity of the prime implicant
chart may increase significantly. In such cases, a large amount of trial and error may be required
to find the minimum solution(s).
Petrick’s method is a more systematic way of finding all minimum solutions from a prime
implicant chart than the method used previously. Before applying Petrick’s method, all essential
prime implicants and the minterms they cover should be removed from the chart.
24
ANALOG AND DIGITAL ELECTRONICS
18CS33
First, we will label the rows of the table P1, P2, P3, etc. We will form a logic function, P, which
is true when all of the minterms in the chart have been covered. Let P1 be a logic variable which
is true when the prime implicant in row P1 is included in the solution, P2 be a logic variable
which is true when the prime implicant in row P2 is included in the solution, etc.
Since, column 0 has X’s in rows P1 and P2, we must choose row P1 or P2 in order to cover
minterm 0. Therefore, the expression (P1+P2) must be true.
In order to cover minterm 1, we must choose row P1 or P3; therefore, (P2+P3) must be true. In
order to cover minterm 2, (P2+P4) must be true.
Similarly, in order to cover minterms 5, 6, and 7, the expressions (P3+P5), (P4+P6) and (P5+P6)
must be true.
Since we must cover all of the minterms, the following function must be true:
The next step is to reduce P to a minimum sum-of-products. This is easy because there are no
complements. First, we multiply out, using (𝑋𝑋 + 𝑌𝑌)(𝑋𝑋 + 𝑍𝑍) = 𝑋𝑋 + 𝑌𝑌𝑌𝑌 and the ordinary
distributive law:
Because P must be true (P = 1) in order to cover all of the minterms, we can translate the equation
back into words as follows. In order to cover all of the minterms, we must choose rows P1 and P4
and P5, or rows P1 and P2 and P5 and P6, or . . . or rows P2 and P3 and P6.
Although there are five possible solutions, only two of these have the minimum number of rows.
Thus, the two solutions with the minimum number of prime implicants are obtained by choosing
rows P1, P4, and P5 or rows P2, P3, and P6.
Thus; 𝐹𝐹 = 𝑎𝑎′ 𝑏𝑏 ′ + 𝑏𝑏𝑐𝑐 ′ + 𝑎𝑎𝑎𝑎 𝑜𝑜r F = a'c' + b'c + ab are two minimum solutions.
ANALOG AND DIGITAL ELECTRONICS
18CS33
SIMPLIFICATION OF INCOMPLETELY SPECIFIED FUNCTIONS:
In some digital systems, certain input conditions never occur during normal operation; therefore, the
corresponding output never appears. Since the output never appears, it is indicated by an X in the truth
table. The X is called a don’t-care condition.
Remember these points about don’t-care conditions:
1. Given the truth table, draw the K-map and transfer 0s, 1s, and don’t-care terms.
2. Encircle the actual 1s on the K-map in the largest groups you can find treating don’t cares as 1s.
3. After the actual1s have been included in the groups, disregard the remaining don’t cares by
visualizing them as 0s.
Example: Consider the following truth table with don’t care conditions for all the inputs from 1010 to
1111.
A B C D Y A B C D Y Y 𝐴𝐴̅𝐵𝐵� 𝐴𝐴̅𝐵𝐵 AB A𝐵𝐵�
0 0 0 0 0 1 0 0 0 0
𝐶𝐶̅ 𝐷𝐷
�
0 0 0 1 0 1 0 0 1 1
0 0 1 0 0 1 0 1 0 X 𝐶𝐶̅ D
0 0 1 1 0 1 0 1 1 X
0 1 0 0 0 1 1 0 0 X 𝐶𝐶𝐶𝐶
0 1 0 1 0 1 1 0 1 X �
𝐶𝐶𝐷𝐷
0 1 1 0 0 1 1 1 0 X Y=
0 1 1 1 0 1 1 1 1 X
𝐶𝐶̅ 𝐷𝐷
� Therefore, Y1 = 𝐵𝐵′𝐶𝐶′𝐷𝐷′
𝐶𝐶̅ D
𝐶𝐶𝐶𝐶
�
𝐶𝐶𝐷𝐷
26
ANALOG AND DIGITAL ELECTRONICS
18CS33
(b)
𝐴𝐴̅𝐵𝐵� 𝐴𝐴̅𝐵𝐵 AB A𝐵𝐵�
Y2
Therefore, Y2 = 𝐴𝐴′𝐵𝐵′𝐶𝐶′𝐷𝐷′ 𝐶𝐶̅ 𝐷𝐷
�
𝐶𝐶̅ D
𝐶𝐶𝐶𝐶
(c)
Y3 𝐴𝐴̅𝐵𝐵� �
𝐶𝐶𝐷𝐷
𝐴𝐴̅𝐵𝐵 AB A𝐵𝐵�
𝐶𝐶̅ 𝐷𝐷
�
𝐶𝐶𝐶𝐶
�
𝐶𝐶𝐷𝐷
Homework: Using Quine-McCluskey method (same questions can be asked to solve by using Patrick’s
method also), simplify;
a) f (a, b, c, d) = ∑m (3, 4, 5, 7, 10, 12, 14, 15) + ∑d (2)
b) f (a, b, c, d) = ∑m (1, 5, 7, 9, 11, 12, 14, 15)
c) f (a, b, c, d) = ∑m (0, 1,0 3, 5, 6, 7, 8, 10, 14, 15)
d) f (a, b, c, d) = ∑m (1, 3, 4, 5, 6, 7, 10, 12, 13) + ∑d (2, 9, 5)
e) f(a, b, c, d) = ∑m (9, 12, 13, 15) + ∑d (1, 4, 5, 7, 81 11, 14).
Example: Solve using QM method: F (A, B, C, D) = ∑m (2, 3, 7, 9, 11, 13) + ∑d (1, 10, 15).
Solution: The don’t-care terms are treated like required minterms when finding the prime implicants:
27
ANALOG AND DIGITAL ELECTRONICS
18CS33
A B C D F Column 1 Column 2 Column 3
0 0 0 0 ABCD ABCD ABCD
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
The don’t-care columns are omitted when forming the prime implicant chart:
- 2 3 7 9 11 13
Therefore, F =
28
ANALOG AND DIGITAL ELECTRONICS
18CS33
When E appears in a square, this means that if E = 1, the corresponding minterm is present in the function
G, and if E = 0, the minterm is absent. Thus, the map represents the six-variable function;
Example: Simplify Y (A, B, C) = ∑m (2, 6, 7) by using entered variable map method by taking –
a) “C” as map entered variable
b) “A as map entered variables.
Solution: Let Y = ∑m (2, 6, 7)
A B C Y A B YC B C YA
0 0 0 0 0 0 0 0
0 0 1 0 0 1 0 1
0 1 0 1 1 0 1 0 (c) A’ A
0 1 1 0 1 1 1 1 B’ 0 C
1 0 0 0 B C’ 1
1 0 1 0 (a) A’ A (b) B’ B
1 1 0 1 Y = AB + BC’
B’ 0 0 C’ 0 1
1 1 1 1 B C’ 1 C 0 A
YC = BC’ + AB YA = AB + BC’
Simplification is similar to K-map method. In Fig (a), C’ is grouped with 1 to get a larger group as 1 can
be written ac 1 = 1 + C’. Similarly, A is grouped with 1 in Fig (b).
Now, the product term representing each group is obtained by including map entered variable (MEV) in
the group as an additional ANDed term.
Hence, for Fig (a): 𝑌𝑌 = 𝐵𝐵𝐶𝐶̅ + 𝐴𝐴𝐴𝐴. For Fig (b): 𝑌𝑌 = 𝐵𝐵𝐶𝐶̅ + 𝐴𝐴𝐴𝐴.
Consider the EBM shown in Fig (c). This has only two product terms; and doesn’t need a separate
coverage for 1. This is because, one can write 1 = C + C’, and C is included in one group and C’ is
included in other group.
29
ANALOG AND DIGITAL ELECTRONICS
18CS33
Example: Simplify Y (A, B, C) = ∑m (1, 2, 3, 4, 8, 9, 10, 13, 14) by using entered variable map method by
taking – a) “D” as map entered variable
b) “C and D” as map entered variables.
Solution:
Example: Solve by using (a) K-Map method & (b) MEV method taking “D” as map entered variable:
𝐹𝐹(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = 𝐴𝐴′ 𝐵𝐵′ 𝐶𝐶 + 𝐴𝐴′ 𝐵𝐵𝐵𝐵 + 𝐴𝐴′ 𝐵𝐵𝐶𝐶 ′ 𝐷𝐷 + 𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴 + (𝐴𝐴𝐵𝐵′ 𝐶𝐶); where 𝐴𝐴𝐴𝐴′𝐶𝐶 is a don’t-care term.
Solution: Given 𝐹𝐹(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = 𝐴𝐴′ 𝐵𝐵′ 𝐶𝐶 + 𝐴𝐴′ 𝐵𝐵𝐵𝐵 + 𝐴𝐴′ 𝐵𝐵𝐶𝐶 ′ 𝐷𝐷 + 𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴 + (𝐴𝐴𝐵𝐵′ 𝐶𝐶)
i.e., 𝐹𝐹 = 𝐴𝐴′ 𝐵𝐵′ 𝐶𝐶(𝐷𝐷 + 𝐷𝐷 ′ ) + 𝐴𝐴′ 𝐵𝐵𝐵𝐵(𝐷𝐷 + 𝐷𝐷 ′ ) + 𝐴𝐴′ 𝐵𝐵𝐶𝐶 ′ 𝐷𝐷 + 𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴 + [𝐴𝐴𝐵𝐵′ 𝐶𝐶(𝐷𝐷 + 𝐷𝐷 ′ )]
or 𝐹𝐹 = 𝐴𝐴′ 𝐵𝐵′ 𝐶𝐶 ′ 𝐷𝐷 ′ + 𝐴𝐴′ 𝐵𝐵′ 𝐶𝐶 ′ 𝐷𝐷 + 𝐴𝐴′ 𝐵𝐵𝐵𝐵𝐷𝐷 ′ + 𝐴𝐴′ 𝐵𝐵𝐵𝐵𝐵𝐵 + 𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴 + (𝐴𝐴𝐵𝐵′ 𝐶𝐶𝐷𝐷 ′ + 𝐴𝐴𝐵𝐵′ 𝐶𝐶𝐶𝐶)
i.e., F = ∑m (0, 1, 6, 7, 15) + ∑d (10, 11).
𝐶𝐶̅ 𝐷𝐷
�
𝐶𝐶̅ D
𝐶𝐶𝐶𝐶
�
𝐶𝐶𝐷𝐷
30
ANALOG AND DIGITAL ELECTRONICS
18CS33
MEV method taking “D” as map entered variable:
A B C D Y YD
0 0 0 0 1
1
0 0 0 1 1
0 0 1 0 0
0
0 0 1 1 0 Y A A’
0 1 0 0 0
0 𝐵𝐵′𝐶𝐶′
0 1 0 1 0
0 1 1 0 1 𝐵𝐵′𝐶𝐶
1
0 1 1 1 1
BC
1 0 0 0 0
0
1 0 0 1 0 𝐵𝐵𝐵𝐵′
1 0 1 0 X
X Y (A, B, C) =
1 0 1 1 X
1 1 0 0 0
0
1 1 0 1 0
1 1 1 0 0
D
1 1 1 1 1
Exercise:
a) Design (a) Binary-to-Gray Code Converter, and (b) Gray-to-Binary Code Converter
b) A switching circuit has two control inputs (C1 and C2), two data inputs (X1 and X2), and one
output (Z). The circuit performs one of the logic operations AND, OR, EQU (equivalence), or
XOR (exclusive OR) on the two data inputs. The function performed depends on the control
inputs:
31
ANALOG AND DIGITAL ELECTRONICS
18CS33
d is an odd-parity bit; that is, the value of d is such that a, b, c, and d always contains an odd
number of 1’s. (For example, the digit 1 is represented by abc = 001 and d = 0, and the digit 3 is
represented by abcd = 0111.) The function f has value 1 if the input digit is a prime number. (A
number is prime if it is divisible only by itself and 1; 1 is considered to be prime, and 0 is not.)
a. Draw a Karnaugh map for f
b. Find all prime implicants of f
c. Find all minimum sum of products for f
d. Find all prime implicants of f’
e. Find all minimum product of sums for f.
32