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Unit 1 - 18EC61

The document discusses CMOS VLSI design and provides information on various topics related to MOS transistors and CMOS fabrication. It begins with an overview of MOS transistor operation and the enhancement and depletion modes. It then covers the CMOS fabrication process and discusses topics like the P-well process, N-well process, and twin tub process. The document also summarizes second order effects in MOS transistors, static CMOS inverter characteristics, noise margins, and scaling of MOS circuits. It provides scaling factors for device parameters and discusses the limitations of scaling at smaller dimensions.

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0% found this document useful (0 votes)

85 views93 pages

Unit 1 - 18EC61

Uploaded by

Pritam Sarkar

We take content rights seriously. If you suspect this is your content, claim it here.

Available Formats

Download as PDF, TXT or read online on Scribd

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Faculty:

Subject: CMOS VLSI Design Swamy T N

Assistant Professor
Code: 18EC61 ECE Department
Dr. AIT
Semester: VI , ‘B’ section Email: [email protected]
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Contents

• Enhancement and Depletion mode operation MOS transistors (p & n type),

• MOS fabrication (p & n type),
• CMOS fabrication.
• MOS device design equations,
• Second order effects of MOS,
• Static CMOS Inverter DC Characteristics,
• Beta Ratio Effect, Noise Margin, Pass Transistor, Transmission Gate, Tristate Inverter.
• Scaling of MOS Circuits: Scaling models and scaling factors,
• Scaling factors for device parameters,
• Limitation of Scaling (Points).

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Integrated Circuit Era:

• Transistor was first invented by William.B.Shockley, Walter Brattain

and John Bardeen of Bell laboratories.
• In 1961, first IC was introduced.

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Levels of Integration:
Levels Number of Transistors Examples
Small Scale Integration(SSI) 10-100 Planar devices, Logic Gates. Flip-Flops

Medium Scale Integration (MSI) 100-1000 Counters, Multiplexers, Adders

Large Scale Integration (LSI) 1000-20,000 8 bit Microprocessors, ROM, RAM

Very Large Scale Integration (VLSI) 20,000-1,000,000 16 and 32 bit microprocessors, DRAM

Ultra Large Scale Integration (ULSI) 1,000,000-10,000,000 Special Processors, Virtual Reality
Machines, Smart Sensors

Giant Scale Integration (GSI) >10,000,000

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Moore’s Law:
The number of transistors embedded on the chip doubles after every one and a half years.
The number of transistors is taken on the y-axis and the years in taken on the x-axis. The diagram also shows the
speed in MHz.

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Various Technologies:

Gallium arsenide (GaAs)

Emitter-Coupled Logic (ECL)
Bipolar Complementary Metal Oxide Semiconductor(BiCMOS)
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MOS (METAL OXIDE SEMICONDUCTOR)

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Basic MOS Transistors
• nMOS(Enhancement and depletion)
• pMOS (Enhancement and depletion)

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Basic MOS Transistors

nMOS Enhancement nMOS Depletion

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Basic MOS Transistors

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Enhancement Mode Transistor Action

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nMOS Fabrication
• Thermal Oxidation,
• Diffusion,
• Rapid Thermal Processing,
• Ion implantation,
• chemical vapor deposition,
• photolithography,
• Etching,
• Metallization.
• Integrated Circuits: Evolution of ICs: CMOS Process Integration, Integration
of Other Circuit Elements.
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Fabrication Process(nmos)

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CMOS Fabrication
• The P-well Process
• The N-well Process

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The P-well Process

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The P-well Process

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N-WELL Process

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N well process

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The Berkeley n-well process

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The Twin-Tub Process

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Second Order Effects
• Threshold voltage – Body Effect
• Subthreshold Region
• Channel-Length Modulation
• Mobility Variation
• Drain Punch-through
• Impact Ionization – Hot Electrons

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Threshold Voltage-Body Effect
The Threshold Voltage Vt is not constant with respect to the
voltage difference between the substrate and the source of the
MOS transistor. This is know as Substrate-bias effect or body
effect.

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Numerical (to find gamma, bulk potential, Vt at
Vsb = 2.5V)

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The CMOS Inverter-DC characteristics

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βn/βp Ratio β(MOS transistor Gain Factor)

βn/βp = 1

It is desirable since it allows a

capacitive load to
charge and discharge in equal times

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Noise Margin:
-----defined as allowable noise voltage at the input of
a gate so that output is not affected.

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Pass Transistors

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Pass transistor Working

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Transmission Gate(TG)

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Transmission Gate

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Tristate Inverter

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Scaling of MOS circuits
• The process of reducing vertical and horizontal dimensions of
MOSFET is called scaling.
• Scaling factors
• W, L, tox, junction depth,

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Benefits of scaling
• Increased component density
• Increased speed
• Reduction in power consumption
• Less cost per chip

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Types of scaling
• Constant voltage scaling
• Constant field scaling

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Constant Field Scaling
• Here MOSFET dimensions as well as supply voltages are scaled by the
same factor S(greater than 1)
• Full scaling: Scaling of supply voltages and terminal voltages
maintains the same electric field, hence the name.
• Benefits of constant field scaling
• Increased component density
• Increased speed
• Decreased cost

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Constant Voltage Scaling
• Here geometrical dimension of the MOSFET are scaled by scaling
factor S while the supply and terminal voltage remain constant.
• Also called as Partial scaling
• Advantages of constant voltage scaling
• Less delay
• Decreased cost
• More reliable

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Scaling factors for device Parameters