Microprocessors Chapter 4 : Microprocessor System

Address decoding:

Microprocessor is connected with memory and I/O devices via common address
and data bus. Only one device can send data at a time and other devices can only receive
that data. If more than one device sends data at the same time, the data gets garbled. In
order to avoid this situation, ensuring that the proper device gets addressed at proper
time, the technique called address decoding is used.

In address decoding method, all devices like memory blocks, I/O units etc. are
assigned with a specific address. The address of the device is determined from the way in
which the address lines are used to derive a special device selection signal k/a chip select
(CS). If the microprocessor has to write or to read from a device, the CS signal to that
block should be enabled and the address decoding circuit must ensure that CS signal to
other devices are not activated.
Depending upon the no. of address lines used to generate chip select signal for the
device, the address decoding is classified as:

1. I/O mapped I/O

In this method, a device is identified with an 8 bit address and operated by I/O related
functions IN and OUT for that IO/M =1. Since only 8bit address is used, at most 256
bytes can be identified uniquely. Generally low order address bits A0-A7 are used and
upper bits A8-A15 are considered don’t care. Usually I/O mapped I/O is used to map
devices like 8255A, 8251A etc.

2. Memory mapped I/O

In this method , a device is identified with 16 bit address and enabled memory related
functions such as STA , LDA for which IO/M =0, here chip select signal of each
device is derived from 16 bit address lines thus total addressing capability is 64K
bytes . Usually memory mapped I/O is used to map memories like RAM, ROM etc.

Depending on the address that are allocated to the device the address decoding are
categorized in the following two groups.

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Microprocessors Chapter 4 : Microprocessor System

1. Unique Address Decoding:

If all the address lines on that mapping mode are used for address decoding then that
decoding is called unique address decoding. It means all 8-lines in I/O mapped I/O and
all 16 lines in memory mapped I/O are used to derive signal. It is expensive and
complicated but fault proof in all cases.

 If A0 is high and A1- A7 are low and if IOW becomes low, the latch gets enabled.
 The data to the LED can be transferred in only one case and hence the device has unique
address of 01H.
Eight I/P switch interfacing at 53H. (01010011)

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Microprocessors Chapter 4 : Microprocessor System

Non Unique Address decoding:

If all the address lines available on that mode are not used in address decoding then that
decoding is called non unique address decoding. Though it is cheaper there may be a chance of
address conflict.

- If A0 is low and is low. Then latch gets enabled.

- Here A1-A7 is neglected that is any even address can enable the latch.

Q) Design an address decoding circuit for two RAM chips each of 256 bytes at address
5300H.
- 256 bytes requires 8 address lines.
2x=256, x=8
So to address one of 256 bytes in each RAM requires 8 address lines A0-A7

Block Address A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

1 Start 5300H 0 1 0 1 0 0 1 1 0 0 0 0 0 0 0 0
End 53FFH 0 1 0 1 0 0 1 1 1 1 1 1 1 1 1 1
2 Start 5400H 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0
End 54FFH 0 1 0 1 0 0 1 1 1 1 1 1 1 1 1 1

Address Decoding Circuit:

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Microprocessors Chapter 4 : Microprocessor System

Q. Draw a circuit diagram to interface two 256 Byte memory chips at address starting at
2050H and 3050H.
Q. Two 4 KB ROM at starting address 0000H
4 KB= 4X1KB = 22 X 210 =212 therefore we need 12 address lines

Address Decoding with 8086 Microprocessor

The 8086 microprocessor provides a 20 bit memory address that allows up to 1 MB main
memory. Out of these several address lines are unused, but these extra lines determine the range
of addresses the memory interface occupies. Address decoder circuit determines these extra
address lines and enables the memory for a specific range of addresses. Depending up on number
of lines used for decoder, we get
Full Decoding (Absolute Decoding): All the unused lines (zero lines) are used.
Partial Decoding (Linear Decoding): All the unused lines (zero lines) are not used.
Block Decoding: Same as full decoding except that in this case blocks of memory is
enabled using the unused lines.

Important Points to be considered for Memory Interfacing

 After reset CS contains FFFFH and IP contains 0000H. Therefore, the physical address is
FFFF0H. Here instruction execution starts from FFFF0H which is normally a jump from
some other location where a longer program resides. This program always resides in a
ROM. For example, we want to interface 4 chips of 2K memory that means 8K bytes of

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memory requires 13 address lines A0 to A12. So, 8K means 01FFFH bytes, therefore
EPROM address starts from FFFFFH – 01FFFH = FE000H.
 Since ROMs and EPROMs are read-only devices, A0 and BHE’ are not required to be
part of the chip enable/select decoding. The 8086 address lines must be connected to the
ROM/EPROM chip starting with A1 and higher to all the address lines of the
ROM/EPROM chips. The 8086 unused address lines can be used as chip enable/select
decoding.
 Since static RAMs are read/write memories, both A0 and BHE’ must be included in the
chip select/enable decoding of the devices and write timing must be considered in the
compatibility analysis.

EPROM Interfacing with 8086

Whenever the 8086 CPU is reset, its value is set to FFFFH and IP value is set to 0000H that
corresponds to physical address FFFF0H which is always a part of ROM. This means FFFF0H to
FFFFFH should be always included in the ROM.

Let us take an example to address 16 KB of EPROM to 8086 microprocessor, 16 KB means

3FFFH bytes. Hence the EPROM memory should start from FFFFFH – 03FFFH = FC000H.
To address 16 KB, we require 14 address lines. Of the 16 KB, 8 KB will be at even addresses
and 8 KB will be at odd addresses. Hence, we use 2 EPROM chips, each of 8 KB capacity one
for storing bytes at even address and another for storing bytes for odd address.

A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A09 A08 A07 A06 A05 A04 A03 A02 A01 A00

Start: 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0

End: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Used for Chip Select Address within the 16KB

The EPROM address ranges from FC000H to FFFFFH

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A0 and BHE’ is not used for interfacing of EPROM. Both the 8 KB EPROM chips are selected
whenever any address in the range FC000H – FFFFFH comes on the address bus.

Static RAM Interfacing with 8086

The general procedure of static memory interfacing with 8086 is briefly described as follows.

 Arrange the available memory chips so as to obtain 16 bits data bus with the upper 8 bit
bank is called “Odd address memory bank” and the lower 8 bit bank is called “Even
address memory bank”.
 Connect available memory address lines of memory chips with those of the
microprocessor and also connect the memory RD’ and WR’ inputs to the corresponding
processor control signals. Connect the 16 bit data bus of the memory bank was that of
microprocessor 8086.
 The remaining address lines of the microprocessor, BHE’ and A0 are used for loading the
required chip select signals for the odd and even memory banks. The CS’ of the memory
is derived from the O/P of the decoding.

Let us take an example to address 16 KB of RAM to 8086 microprocessor. We will split 16 KB

into two blocks each of 8 KB one of even addressed and another of odd addressed. Depending
upon the bit on A0, either the even or odd bank will be selected. If A0 = 0, the even bank is
selected. Now the BHE’ signal will be 0 whenever a byte or a word is being accessed at odd
address. Also for an even addressed word, both the banks will have to be enabled at the same
time. Hence, A0 has to be given to CS’ of even bank and BHE’ has to be given to CS’ of odd
bank.

 If only A0 is low, memory location from even bank is accessed.

 If only BHE’ is low, memory location from odd bank is accessed.
 If both are low, 2 memory locations are accessed from each bank.

To address 16 KB, we require 14 address lines. Of the 16 KB, 8 KB will be at even addresses
and 8 KB will be at odd addresses. Hence, we use 2 RAM chips, each of 8 KB capacity one for
storing bytes at even address and another for storing bytes for odd address. We will start the
RAM address from 80000H.

A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A09 A08 A07 A06 A05 A04 A03 A02 A01 A00

Start: 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

End: 1 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Block A

Start: 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0

End: 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Block B

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As a good and efficient interfacing practice, the address map of the system should be continuous
as far as possible i.e. these should be no windows and no feedback space should be allowed. A
memory location should have a single address corresponding to it i.e. absolute decoding should
be preferred.

Q) Interface two 4K X 8 EPROMs and two 4K X 8 RAM chips with 8086, select suitable
maps.
We know that, after reset, the IP and CS are initiated to from address FFFF0H. Hence this
address must lie in the EPROM. The address of RAM may be selected anywhere in the 1MB
space of 8086, but we will select the RAM address such that the address map of the system is
continuous as shown in table below.

Address A A A A A A A A A A A A A A A A A A A A
19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FFFFFH 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
EPROM 8K X 8
FE000H 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0

FDFFFH 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1
RAM 8K X 8
FC000H 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Total 8K of EPROM need 13 address lines A0-A13 (Since 213 = 8K). Address lines A13-A19 are
used for decoding to generate the chip select. The BHE’ signal goes low when a transfer is at odd
address or higher byte of data is to be accessed, let us assume that the latched address, BHE’ and
de-multiplexed data lines are readily available for interfacing.

The two 4K X 8 chips of RAM and EPROM are arranged in parallel to obtain 16-bit data bus
width. If A0 is 0 i.e. the address is even and is in RAM, then the lower RAM chip is selected

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Microprocessors Chapter 4 : Microprocessor System

indicating 8-bit transfer at even address. If A0 is 1 i.e. the address is odd and is in RAM, the
BHE’ goes low, the upper RAM chip is selected further indicating that the 8 bit transfer is at an
odd address. If the selected addresses are in ROM, the respective ROM chips are selected. If at a
time A0 and BHE’ both are zero, both the RAM or ROM chips are selected i.e. the data transfer
is of 16 bits. The selection of chips takes place as shown in table below.

Decoder I/P A2 A1 A0 Selection /

Address / BHE’ A13 A0 BHE’ Comment
Word transfer on 0 0 0 Even and Odd
D0-D15 address in RAM
Byte transfer on 0 0 1 Only even
D0-D7 address in RAM
Byte transfer on 0 1 0 Only odd address
D8-D15 in RAM
Word transfer on 1 0 0 Even and Odd
D0-D15 address in ROM
Byte transfer on 1 0 1 Only even
D0-D7 address in ROM
Byte transfer on 1 1 0 Only odd address
D8-D15 in ROM

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Microprocessors Chapter 4 : Microprocessor System

Input/ Output Devices

Input / Output devices are the means through which the microcomputer unit communicates with
the outside world. The link between the I/O devices and the microprocessor is maintained by a
circuitry known as I/O module. This circuitry includes the specific interfaces needed for I/O
devices as well as control functions that implement the I/O transfers within the computer. I/O
devices usually are appeared as passive devices which take action only when instructed to do.
The CPU monitors the status of the I/O devices and selects them according to availability and
need.
 Consider the keyboard as input device and the steps when the key is
pressed are
 Microprocessor detects the key change in status of keyboard i.e. the key
is pressed.
 It receives the encoded information corresponding to pressed key.
 It checks the validity of required signal.

 Consider the printer as output device

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