9th International Symposium on Quality Electronic Design

Printed Circuit Board Assembly Test Process and Design for Testability
Thao Nguyen and Navid Rezvani
Network Appliance, Inc.
NPI Test Process Development
Contact: Thao Nguyen [email protected]
Navid Rezvani [email protected]

Abstract 1.0 Introduction

The trend in Printed Circuit Board Assembly technology is This paper serves as a guideline in terms of test process
towards higher complexity, many boards have significantly development and benefits of design for testability at
more components and solder joints today than just a few years board level, its main purpose is to make sure that the
ago. In addition, board assembly process variations may lead board is designed not only to be testable, but also the
to board failures due to the change of process parameters. The test coverage will be achieved at the highest level. In
sooner process and electrical defects are caught, the lower the the high volume manufacturing of printed circuit board
total cost of ownership will be. Defect finding and analysis at assemblies (PCBAs), it is critically important to
early manufacturing stages are critical to lower cycle time and automate every step in the process in order to meet the
cost for high-volume production. Therefore, a key challenge desired overall production quality level. This includes
facing electronics manufacturers of high complexity boards is completely automated inspection of the product;
the issue of board test strategy. An effective board test strategy automated optical inspection (AOI) that delivers
can be critical in determining a company’s ability to succeed comprehensive inspection of a complex PCBA,
in an environment of extreme cost and time to market automated X-ray (AXI) inspection of a complex PCBA
pressures, and requirement to faster volume ramp with higher that has BGA package(s) at the full run rate of the
yield and quality. Design for testability is a key to lower life production line.
cycle cost of the product from design, manufacturing, and Product manufacturing is comprised of different test
field support. Poor design for testability makes product testing operations. Case studies have shown that
difficult and with low test coverage. More and more failures manufacturing stages can be optimized for speed and
escape to the field and would create a larger bone-pile of cost if the manufacturing stages are taken into
boards that need to be debugged and repaired. In order to consideration during the design phase. This is called
improve quality, a special attention should be given to design an early manufacturing involvement from new
for testability at early design stages while defining good test product introduction engineers to work with layout
process strategy for the high-volume production. and design engineers in DFT and product test
strategy.
Today, in order to remain competitive, manufacturers
1.1 Board Test Process must keep costs low and quality high, design for
testability now gains wide acceptance.
1.1.1 Automated Optical Inspection
Automated optical inspection technology has many benefits:
• Automated systems are orders of magnitude faster
than human inspectors.
• AOI systems are more accurate and objective than
human inspectors.
• AOI systems make repeatable and stable judgment.
The current generations of AOI systems have fairly well
defined set of fault detection capabilities. The commonly
employed fault detection types that today’s AOI systems can
deliver include:

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 • Placement faults (missing, tombstone, billboarded, 1.1.2 Automated X-ray Inspection
etc.) There are three commonly used X-Ray Techniques:
• Solder faults (no, low, excess, bridging) 2D, Laminography and Off-Center
• Other (lifted lead, wrong component, etc.) Tomosynthersys.
The techniques that are employed to achieve these inspections 2D provides the best resolution, solder
depend on having visual access to the areas of interest, and measurement information as the whole joint
they also depend on certain visual attributes to make good vs. information is available in the image. Test
bad judgments. If visual access is blocked, or if the visual engineering department has been always looking
attributes of the PCBA are not consistent with the for an AXI machine with fastest, most joint
requirements of the AOI techniques, fault coverage is information, high resolution, high reliability, and
degraded. low false call rates.
There are cases where solder joints are buried under a device Laminography uses a mechanical rotating
and not visible to AOI. For example, the shift from Pb solders averaging technique to create a focal plane. Items
to lead free or for the boards with large number of Area Array outside the focal plane are blurred and their effect
devices such as LGA, QFN, BGA, CSP, 0201, etc, test minimized in the resultant image. Slow machine,
development team should be looking at another equipment low resolution, blurred images, and high false call
type to cover the gaps. rates.

Off-Center Tomosynthersys uses a computed

tomographic technique with no moving parts to
1.1.3 JTAG Test generate 3D slices, no artifacts in final images,
During prototype bring up, JTAG (Joint Test Action high reliability, slow, low resolution, and low false
Group, Boundary Scan 1149.1 and 1149.6) is a good tool call rates.
for testing board, quickly finding process defects and
saving time for designers to focus on their design instead AXI 3D X-ray inspection is designed for in line or
of spending time looking for manufacturing process off line automated process testing solder
defects. connections on printed circuit board assembly
(PCBA), this is a leading process defect coverage
In recent years, many in the electronics test industry have for higher yields and lower repair costs.
begun to realize that the value of boundary scan test
technology can be leveraged across the various phases in a The current generations of AXI systems have a
product’s life cycle. In particular, boundary scan can well defined set of fault detection capabilities. The
provide a link between design test and manufacturing test, commonly employed fault detection types that can
boundary scan provides many advantages for achieving deliver include:
high quality products and reducing time to market. There • Insufficient, Poor wetting, marginal joints,
are many benefits to re-using tests from design and Voids, Billboard, Misalignment,
prototype testing in production and field repair. Faster time Tombstone, Missing, Shorts, Opens,
to market, lower test costs and higher quality are some of Missing ball(BGA)
the critical benefits. Supporting all component types: BGA, CGA, chip
resistor, capacitor, flip chip, Leadless Chip Carrier
In order to achieve the benefits of re-using tests, ASICs, (LCC), SMT device, PTH connector, SMT
ICs, memory devices, boards, and systems must be connector, Press fit connector
designed correctly to support JTAG. In addition, there are
a number of best practices that have been identified to aid
the transition from design, prototype testing into
production. Some results from case studies will be
presented in this paper to indicate how well the theory can
be put into practice. Leveraged tests could be shared
among the following test and repair operations: Prototype
test, Design Verification, In Circuit Test, Functional test
and repair, Field re-programming and repair.

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 2.0 Production board test coverage matrix 1.1. 4 In-Circuit Test (ICT)
process There are many versions of ICT that should be
A comprehensive test process on the printed circuit board considered:
assembly is to have AOI, AXI, and ICT prior to board 1. MDA Manufacturing Defect Analyzer –
functional test. This is the best and overall cost effective analog only tests
possible method to cover board test process after board SMT 2. MDA+ Analog only tests, Boundary Scan,
completion. The earlier defects are found, the most cost Powerless
effective the process is. 3. ICT, All of the above + digital testing < 5000
Coverage AOI AXI ICT nodes
Placement • Extra • Extra • Missing 4. Full ICT, All of the above + low voltage, +
Parts Parts • Tombstone Functional, up to 5000 nodes.
• Missing • Missing • Inverted 5. Best in class, all of the above and up to 8000
• Tombstone • Tombston • Polarity nodes.
• Billboard e
• Misalign • Billboard Depending on product quality requirements
ment • Misalignme and complexity, the use of each type of
• Orientation nt equipment can have different affects on quality
• Missing • Bypass and costs.
Non-Elec. Caps, L’s
• Bypass In Circuit Testers use a complex bed of nails to
Caps, L’s structurally test printed circuit board after SMT
• Inverted process. ICT can identify shorts, opens, wrong
components, incorrectly installed components,
• Polarity
missing components, malfunctioning digital
components, voltage/current measurements are
Solder
• Shorts • Shorts made across individual components to check
correct values on non power up boards, guarding
• Opens • Opens techniques are used to eliminate the effect of
• Insufficient
parallel components by biasing so that no current
flows through them, digital logic can be tested on
• Poor power up boards by inputting a series of test
wetting vectors and verifying output. A component’s
logic input states are forced high or low by back
• Marginal driving the component(s) that normally supplies
Joints the input. ICT system also can check and verify
• Voids color and brightness of LEDs, measure frequency
of crystal oscillators.
• Solder balls
3.0 Approaches to Test
Electrical
• Wrong Part • Wrong Part • Wrong Part Board assembly (PCBA):
• Dead/Bad Part Placement, solder, AOI/AXI inspection

• Cold Solder • Build product right or test product right

• PCB
• AOI or Xray can reduce the need for test
Can it be eliminated?
Short/Open
• Continuity Board Test:
Structural test – Process
• Part Board functional test, diagnostic test
Functionality
• Values/Tolerances
• Structural – Is product built right? Find
• Bent Leads manufacturing defects. ICT/BSCAN
• Functional – Does the board work? Board
diagnostic test.

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 ICT:
Passives,
Programmables,
Actives, JTAG
Boundary Scan

4.0 Board design DFT – Design for Testability

4.1 Overview of Design for Testability 4.2 DFT requirements

Design for Testability refers to a class of design methods that put • All test points located on bottom side of board
constraints on the design process to make test vectors generation and • Minimum of one test point per Net
diagnosis simpler and easier, thereby optimizing test related product • As close as possible to signal source
costs. Testability is the property of a circuit which allows a test • Do not tie control lines (reset, clear, or enable)
engineer to easily derive a procedure to determine accurately the directly to ground or VCC; this is especially
functionality of a circuit. It can also be defined as the controllability important on Output Enable lines on devices
of a circuit to determine defects. whose outputs drive other devices or buses.
Using pull up or pull down resistor instead to
Design for Testability is covering for both area physically (AOI and allow the ICT to test down stream devices.
AXI) and electrically (ICT, JTAG, board functional testing). Product • Resistors used for pull-up/down should have a
Development, New Product Introduction test process development value of 1K Ω.
team shall work together at the early development stage in order to • TAP inputs (TDI, TMS, TCK,
have a solid working product releasing to production with no issues. TRST*(optional)) must be properly terminated
Figure 1 below shows a product that has production problem after with a pull up/down resistor. A typical resistor
accepting it from engineering. (1) value is 1K Ω
• Chain all JTAG devices together to gain a
better coverage
• On each JTAG device, provide a test point on
TDI, TDO, TCLK, TMS pin
• Tie multiple boundary scan devices to a single
scan chain with common TMS, TCLK, TRST
(optional) and connect TDO to the next TDI.
• Use bypass 0 ohm resistor (No populate) on
JTAG scan chain where it’s necessary for
debugging purposes.
• The function of the JTAG pins (TDI, TDO,
TMS and TCLK) must be independent of any
normal chip function such as a system reset.
Do not incorporate a system reset condition to
initialize the TAP controller.
• All device outputs must be tri-state. If IEEE
Figure 1: Product development without DFT – Design for Testability 1149.1 compliant, the JTAG signal TDO is the
only output pin that should remain active when
tri-state pin is enabled.
• Some systems require only one boundary scan
chain.

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 Physical design for testability
Board labeling
Board part number, revision and serial number
clearly marked on top-side
Barcode label on top-side and consistent

Future DFT
Most DFT rules will remain the same, but in the
next few years there will be higher densities,
requiring more accurate probing, there should be
more tools available for boundary scan testing and
also there are more limitations due to lead free
process, so the future DFT may have some
challenges to meet DFT rules.

5.0 Application
Some results from case studies will be presented in
this paper to indicate how well the board test
process covers to achieve maximum
Figure 2: DFT review in product development phase coverage and cost effective using combination
or all of these tests AOI, AXI, Bench top JTAG,
Above process (Figure 2) is a successful product launch with and ICT.
involvement from operations engineering NPI team in the area of
design for testability, review, feedback, build, and fixing issues.

6.0 DFT Guidelines of ASIC for Board 7.0 Economic model - Case study (3)
Case study from Teradyne with cost to repair per defect at each
Test test operation, the sooner process defects and electrical defects
are caught, the lower the total cost for the product, and high
To date, design for testability are required to incorporate in all quality. Table and Graph 1 below are summary of cost model
phases of the design from embedded blocks, chip level, to and quality level of different test process applied to the product.
board and system level in order to meet the aggressive design
to volume production. There is cost overhead for DFT, but the
cost of not using DFT in complex designs is much more and
expensive due to larger bone-pile production boards which Tables and Bar charts below:
will take too much time to repair or un-repairable. Use of
JTAG DFT technique simplifies manufacturing tester
requirements. A fully testable device, system increases
productivity of design and manufacturing groups; lowers
manufacturing test and debug costs; lowers costs of system
and board rework; enhances product time to volume; and
increases product confidence in the end user (2) . Using
BSDL file available from the ASIC, In Circuit Test can
perform JTAG testing for all scanable devices on board, and
also it is very beneficial for checking all the nets associated
with high speed signals where not allowed to have test points.

8.0 New recommended board test process

There are some duplicated tests from one operation to
another; this adds cost to your product. Depending on
complexity of the printed circuit board assembly, test
process differs from a small board to a larger board

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 which based on the number of components and
component types on board:
• All passive components, ICs, no BGA
package, on a not high density, not complex
board shall have AOI and ICT after SMT
process (such as riser card, mezzanine
board, back plane)

• A high density board, over 200 components

with BGA packages on board should have
AOI, 5DX, and ICT for board testing after
SMT process then FVT and ESS

• After 90 days in production, if the yield of

5DX is 100%, test engineer could consider
sampling 5DX (10-20% of any lot build) for
cost reduction and inspection cycle time
improvement. Going through process of
AOI, 5DX, and ICT would allow for a high
yield at board function test FVT and ESS

9.0 Reference
1) Teradyne white paper - Michael Smith
2) ASIC DFT techniques and benefits –
IEEE Butt, H.H Vertex Semiconductor,
San Jose CA
3) Teradyne Economic model paper –
Paul Groom/Michael Smith

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