I1 ,

IEEE TRANSACTIONS O N CIRCUITS AND SYSTEMS, V o l . 37. NO. 11, NOVEMBER 1990 1375

Limits of Low Noise Performance of

Detector Readout Front Ends
in CMOS Technology

Abstract -The limits of the noise performance of detector readout

HV
front ends in CMOS technology have been studied. A theoretical mini-
mal number of equivalent noise charge (ENC) that can be achieved by a ,t
I1

CMOS technology is derived, taking both the thermal noise and 1/f II Cf
noise into account. Design criteria and techniques of CMOS readout
front ends are presedted so as to fully exploit the maximal capability of
a CMOS technology. The optimal input transistor dimensions and bias
conditions of charge sensitive amplifiers (CSA) are analytically deter-
mined. For readout front ends using semi-Gaussian pulse shapers, the
optimal number of integrators and the optimal peaking time are deter-
Fig. 1. Principal block diagram of a detector readout system.
mined as well from the point of view of achieving the best detector
resolution.
In order to verify the theoretical analyses, a charge sensitive amplifier
and a fourth-order semi-Gaussian pulse shaper with 1-ps peaking time system to store the informations for serial readout. For
have been designed in a standard 3-pm CMOS technology. Calculations resolution analyses, the detail of the circuits in the pro-
and computer simulations show that by optimal design of input CSA cessing unit is of no concern and only the CSA and the
and semi-Gaussian pulse shaper, a detector resolution as low as 600
pulse shaper will be considered.
equivalent noise electrons can be obtained for a 40-pF detector capaci-
tance. In most modern semiconductor detector systems,
printed circuit and hybrid electronics are still the main
approaches to the readout front ends. Discrete junction
I. INTRODUCTION field effect transistors (JFET’s) are used universally as

I N ELEMENTARY-particle physics, the energies of input amplifying elements mainly due to their high input
radiation particles are measured by means of a semi- impedance and low noise characteristics. As the number
conductor detector readout system. A principal schema of of identical readout channels is continually increasing, the
such a detection system is depicted in Fig. 1. An inverse requirements of low power consumption, low noise, and
biased diode (Si or Oe) detects radiation events by gener- small size of the readout electronics become more severe.
ating electron-hole pairs proportional to the absorbed For example, a silicon microstrip detector used in high
energies. A low-noise charge sensitive amplifier (CSA) is energy and collider experiments can contain up to 1000
widely used at the front end due to its low noise configu- strips with a readout pitch of only several 10 p m [11-[31.
ration and insensitivity of the gain to the detector capaci- To read out such a large number of channels, the printed
tance variations. The generated charge Q is integrated circuits and hybrid electronics currently available are
onto a small feedback capacitance C,, which gives rise to clearly inadequate and monolithic integration seems to be
a step voltage signal at the output of the CSA with an the only approach to the design of the readout system.
amplitude equal to Q/C,. The step signal is fed to a Recently, continuing efforts have been made to imple-
main amplifier, often called a pulse shaper, where pulse ment multichannel readout systems in a monolithic form
shaping is performed primarily to optimize the S/N ratio [4]-[7]. CMOS technologies have been chosen for integra-
of the system. In all cases, the resulting output signal is a tion due to the high integration density, low power con-
rather narrow pulser suitable for further processing. De- sumption, and capability of combining both digital and
pending on applications, the pulse processing unit can be analog circuits on the same chip. As the CMOS approach
simply a multichannel analyzer (MCA), a series of dis- is just in the beginning phase, no comprehensive study has
criminators, or sample-hold circuits in a multichannel been published so far on the maximal capability of CMOS
technology for the implementation of detector readout
Manuscript received July 13, 1989: revised June 18, 1990. This paper
systems.
was recommended by Associate Editor R. K. H a t e r . It is the aim of this paper to determine the upper limit
The authors are with the Katholieke Universiteit Leuven, B-3030 of the detector resolution that can be achieved by using a
Heverlee, Belgium.
IEEE Log Number 9038545. CMOS approach, and to show design criteria and tech-

0098-4094/90/1100-1375$01.00 01990 IEEE

 1 1 I I

1376 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, VOL. 37, NO. 11, NOVEMBER 1990

niques of readout front ends in order to fully exploit the

capability of CMOS technology. In the next section, the r I
resolution of a detector readout system implemented in a ...............................................................................
: 2
CMOS technology is calculated, taking both the thermal
and l/f noise into account. It is the first time that a
generalized analysis is performed for a CMOS detector n integrators
readout system using a semi-Gaussian pulse shaper of an ...............................................................................
Semi-Gaussian shaper
arbitrary order. In Section 111, the optimal design of
Fig. 2. Noise sources in a detector readout system.
charge sensitive amplifiers, which are the key building
blocks of detector readout front ends, is performed. The
theoretical maximal resolution and optimal input transis- The noise of a detector readout front end can always be
tor dimensions and bias conditions will be derived. A represented by an equivalent input voltage noise genera-
CMOS CSA matching a 40-pF detector capacitance is tor and an equivalent input current noise generator, as
designed to check the theoretical analyses. Section IV is shown in Fig, 2. c d represents the detector capacitance.
devoted to the optimal design of CMOS pulse shapers With the generally accepted assumption that the total
where the optimal order and the optimal peaking time are system noise is dominated by the input device of the CSA,
determined from the point of view of achieving the best the two equivalent input noise sources are given by
detector resolution. A design example will be given to
illustrate the theoretical analyses. It is shown that by
optimal design of the CSA and the pulse shaper detector
resolution as low as 600 equivalent noise electrons can be '.e2q i = [S(CGS+CGD)]2rc?qi
(2)
achieved for a detector with 40-pF capacitance. This is
more than a factor of two better than the best results where g m is the transconductance, C,, is the gate-source
recently published [41, [51, [71. capacitance, and C,, is the gate-drain capacitance of
the input MOS transistor. The first term in (1) repre-
sents the channel thermal noise and the second term
11. EQUIVALENT
NOISECHARGES represents the l / f noise of the input MOS transistor
In the detector world, the noise performance of a where K , is the l / f noise coefficient of the CMOS
detector readout system is generally expressed as the process used [12], [13]. In addition to the amplifier noise,
equivalent noise charge (ENC). The equivalent noise the detector leakage current and its associated bias net-
charge ENC is defined as the ratio of the total integrated work give rise to another noise component, which is the
rrns noise at the output of the pulse shaper to the signal shot noise. It is generally expressed as
amplitude due to one electron charge q. Clearly, the ENC :i = 2q1, (3)
depends on the characteristics of both the charge sensi-
tive amplifier and the pulse shaper. Many studies have where I, is the sum of the detector leakage current and
been performed on the pulse shapers in terms of the S/N the equivalent noise current of the bias network.
performance and counting-rate behavior [81, [9]. It has From the expressions (11, (21, and (3), the total noise
been concluded that the optimum choice of pulse shaper power spectrum at the output of the charge sensitive
depends strongly on applications, and for a given applica- amplifier is calculated to be
tion one must assess the trade-offs among different design
parameters. In this paper all analyses will be carried out
for semi-Gaussian shapers, which are the most common
pulse shapers employed in readout systems [41, [81.
In principle, either the time-domain or frequency- The first term is due to the amplifier noise and the
domain approach can be used to calculate the ENC of a second is the contribution of the detector leakage current
detector readout system [9]-[ll]. While the analysis in the and its associated bias network. In order to calculate the
frequency domain is more straightforward and familiar to ENC the total integrated rms noise at the output of the
most scientists, the time-domain approach is more conve- pulse shaper must be calculated. The transfer function of
nient for making comparison of the S/N performances a semi-Gaussian pulse shaper consisting of one RC differ-
between different pulse shapers. The reason is that it entiator and n integrators (see Fig. 2) is given by
gives an intuitive picture of the effect of the different
pulse shaper parameters on the S/N performance. How-
ever, the time-domain approach has thus far been limited
H(s)= -
1 [
1+As7,]n ::J [ ~
(5)

to the treatment of the thermal and shot noise. The l/f where T, is the time constant of the differentiator and
noise can not be dealt with by this method. As CMOS integrators, and A is the dc gain of the integrators. The
technologies have inherently much higher l/f noise, the number n of integrators is called the order of the semi-
frequency domain analysis must be adopted in order to Gaussian shaper. The noise power spectrum at the output
investigate the effect of l/f noise. of CSA is weighted by the transfer function ( 5 ) of the
SANSEN AND CHANG: DETECTOR READOUT FRONT ENDS 1377

shaper. The total integrated rms noise is then given by

2 3 4 5 6 7

In order to calculate the ENC of the detector system, the B,:( n -f) 1.57 0.39 0.20 0.12 0.086 0.063 0.051
signal amplitude at the pulse shaper output due to one
B ( i , n + l ) 1.57 1.17 0.98 0.86 0.77 0.71 0.66
electron charge must be determined as well. 2 2

A. Signal Amplitude Due to One Electron Charge n!2e2n,n2n 7.39 13.64 19.92 26.20 32.48 38.76 45.04

The signal due to one electron charge delivered by the

detector can be represented as a Dirac current impulse, integrated rms thermal noise becomes explicitly as given
the integral of which is equal to q corresponding to one
by
electron charge. It can be shown that the output signal of
the CSA is an exponentially rising step function with a
time constant T , proportional to the detector capacitance
and inversely proportional to the GBW of the core ampli-
fier. The steady state amplitude of the step signal is equal where C , = C, + C, + C, +
CGD.In general, the above
to q/Cf. In practice, the value of T~ can be made as low integral cannot be solved under a closed form. Fortu-
as several nanoseconds so that the output signal can be nately, for all practical cases where n is an integer, it can
approximated as an ideal step signal with an amplitude of be shown that the solution of the above integral is given
q / C f . In the frequency domain, the signal at the output by the following equation:
of the pulse shaper is simply given by the product of the
transfer function H ( s ) of the pulse shaper and the Laplace
transform of the step signal that is equal to q / s C C f .By
\--,
taking the inverse Laplace transform of the product, the
output signal in the time domain is obtained:
where B ( x , y ) is the beta-function. Dividing the above
expression to the signal amplitude due to one electron
(7) charge, the ENC, due to the channel thermal noise is
obtained:
where T,, called peaking time of the shaper, is defined by
T$ = n ~ , .Equation (7) has a semi-Gaussian pulse shape in
the time domain. It can be easily verified by taking the
derivative of (7) with respect to time t that the signal
VOut(t>reaches the peak amplitude at the peaking time 7,. This is a general expression for the ENC, due to the
The peak amplitude of the signal pulse is calculated by
channel thermal noise and is valid for all detector systems
evaluating (7) at peaking time T , and is given by
using semi-Gaussian pulse shapers of an arbitrary order.
qAnnn For the simplest RC - RC semi-Gaussian pulse shaper,
V,"tnl,X = ___.
C, n !e" (11) reduces to the classical expression for ENC, [81.
From (11) the effect of the pulse shaper characteristics on
The peak amplitude is thus proportional to the generated the detector resolution can be evaluated. Obviously, the
charge q. Therefore, by measuring the peak amplitude use of pulse shapers with large peaking time T , always has
the energy of radiation particles can be determined. Note the effect of limiting the thermal noise. Evaluation of the
that for n = 1 the above expression is reduced to the effects of the order n on the ENC, is clearly more
classical expression for the simplest first order RC - RC complicated. For clearness, the values of B ( 3 / 2 , n - 1/2)
pulse shapers [81. and last product term are listed in Table I. With the help
The ENC of the detector system is calculated as the of Table I the value of the ENC, can be calculated from
ratio of the total integrated rms noise in (6) to the peak (1 1). For example, for a detector readout front end having
amplitude of the output signal given in (8). As the total C, = 60 pF, gm = 10 mS, n = 4, and T , = 1 ps, the ENC,
noise power spectrum u,(s) in (4) or (6) contains three is calculated from (11) to be 390 noise electrons.
independent noise components, which are the channel
thermal noise, l/f noise, and the shot noise, it is better C. ENC Due to 1 / f Noise: ENCf
to deal with each component separately. In the design of detector readout systems using discrete
JFET transistors the effect of l/fnoise has been gener-
B. ENC Due to Channel Thermal Noise: ENC, ally neglected. However, as a CMOS process has much
The thermal noise source associated with the channel higher l / f noise, its effect on the detector resolution
resistance of the input MOS transistor is given by the first must be examined as well. The l/f noise source of the
term in (1). Filling in the general expression (61, the total input MOS transistor is given by the second term in (1).
 I1 1

1378 I F F F TRANSACTIONS O N CIRCUITS AND SYSTEMS, VOL. 37, NO. 11, NOVEMBER 1990

Evaluation of the integral (6) for the l/f noise yields as 111. OPTIMAL
DESIGN
OF CHARGE
the total rms output l/f noise: SENSITIVE
AMPLIFIERS
In the previous section, the ENC's of the detector
system using a semi-Gaussian shaper have been analyti-
cally derived. The design parameters of the CSA that
affect the ENC's are the input MOS transistor dimen-
The ENCf is calculated as the ratio of (12) to (8). It is
given by sions and dc bias conditions. A careful examination of the
three ENC's given by (111, (131, and (15) reveals that the
optimization of each ENC separately is equivalent to
minimizing the equivalent input noise current in parallel
with the signal source due to each noise source. This
An important conclusion drawn from (13) is that the allows optimizing the noise performance of the CSA
ENC, due to the l / f noise is totally independent of the separately without any reference to the characteristics of
time constant T , of the pulse shaper and only slightly the pulse shaper, which makes the calculations easier.
depends on the number of the integrators in the pulse However, to optimize the total ENC,, the shaper charac-
shaper. It strongly depends on the process parameters teristic must be taken into account as well, which will
K,, CO,, and the input MOS transistor dimensions. If an result in analyses that are too complicated. To avoid
MOS input transistor with WL = 30 000 p m 2 is used and elaborate calculations and the loss of insight into the
the CMOS process used has Kf = 6.1OP3' C2/cm2 and optimization procedures, each ENC is optimized individu-
C,x = 0.8 fF/pm2 [12], [13], then for the same example ally at first. Once the effects of the input transistor
above, the ENCf is calculated to be 380 noise electrons, dimensions and dc bias conditions on each ENC are
which is comparably as important as the channel thermal well-determined, the optimization of the total ENC, can
noise. be obtained numerically.
In order to determine the effect of the input transistor
D. ENC Due to 241, Noise: ENC, dimensions and dc bias conditions on the ENC's, the
For the noise component 2q10, due to the detector input capacitance and transconductance of the input MOS
leakage current and the associated bias circuit, the inte- transistor must be explicitly expressed in terms of these
gral (6) is calculated to be parameters as given by

2
C,, = -CO, WL and C,, = C,,WL, ( 17)
3

The corresponding ENC, is given by

Combining (17) and (18) with the expression (11) for the
ENC, due to the channel thermal noise, it can be easily
In contrast to the ENC,, due to the channel thermal
seen that in order to minimize the ENC,, the minimal
noise, ENC, is proportional to the peaking time 7, of the
transistor gatelength L and the maximal dc bias level ,Z
pulse shaper. Furthermore, it depends only on the shaper
must be chosen. The transistor gatewidth W has a double
characteristics and is totally independent of the character-
effect. On the one hand, the increase in the gatewidth
istics of the CSA. The value of the function B ( 1 / 2 ,
reduces the transistor channel thermal noise due to the
n + 1/2) is given in Table I. For the same example above
increase in the transistor transconductance g,. On the
and assuming a total leakage current I, = 10 nA, from
other hand, the increase in the gatewidth impairs the
(15) the ENC, is calculated to be 230 noise electrons.
S/N performance due to the increase in the input capaci-
The total equivalent noise charge ENC, is simply given
tance. As a result, an optimal gatewidth must exist for
by the sum of the ENC's due to three individual noise
which the ENC, is minimal. It is calculated by solving the
sources given in (111, (131, and (15):
equation of the derivative of (11) with respect to the
ENC, = dENC: + ENC; + ENC; . (16)
gatewidth W. It is given by

In the following sections the effect of the design param-

eters of CSA and pulse shaper on the ENC's will be
investigated in more detail. The optimal input transistor
characteristics of the CSA and the optimal peaking time
and order n of the pulse shaper will be determined in where a is defined as C U =L L +3L,, which is very close
order to obtain the minimal total ENC,. to unity for long channel devices. Filling the optimal WO,,

7- 7
SANSEN AND CHANG: DETECTOR R E A D O U T FRONT ENDS 1379

due to the channel thermal noise and requirements re-

lated to the GBW and the response speed, etc., a minimal
transistor gatelength should be chosen. The correspond-
ing minimal ENCfmi, is obtained by filling (21) in (13) as
given by

ENC& =

This theoretical minimal ENCfminis totally independent

of any design parameters of the CSA and depends only
on the process parameters for a given detector capaci-
tance. Furthermore, it depends only slightly on the order
-50 5 0 l o o 150 2oo 250 300 350 400 450 500 of the pulse shaper as will be shown in the next section.
Fig. 3. Theoretical minimal ENC's versus detector capacitance for
semi-Gaussian shaper n = 4, = 1 ps. NMOS input: L = 3 p m ,
The fact that for a given capacitive source ENC,,, only
IDS = 0.5 mA, K , = 6.'10-" C2,,?cm2. depends on the basic process parameters K , and CO,
means that it sets the lowest limit of ENC that can be
in (11) yields the minimal ENC,, which is given by achieved by using a specific CMOS technology. In Fig. 3 ,
the ENCfmi, is plotted as a function of detector capaci-
128 (C, + C,)' L 6 tances together with the ENCdmi,. For small detector
ENC;,~, = ?kz-
J ~ ~ o s (+
c, c,> capacitance the effect of ENCfmi, is very important,
while for a large detector capacitance ENC,,, plays the
most significant role. It should be emphasized that it is
always possible to lower the ENC,,, curve by increasing
. (20) dc bias current or peaking time, but the curve ENC,,,,,
on the other hand, cannot be changed without process
improvement. It gives the maximal capability of a CMOS
This is the theoretical minimal ENC, due to the channel technology. For example, using a CMOS technology with
thermal noise of the input MOS transistor of the CSA. In Kf = 6.10-31 C2,cm2 and cox = o.8 fF/Pm2 [12~, it
order to minimize this minimum, a transistor with a is not possible to design a CMOS readout system for a
minimal channel L must be chosen and a high DC bias detector of 40 pF with a total ENC, lower than 340
current must be used. Also, the parasitic capacitances and electrons.
feedback capacitance should be kept at minimum, in spite As mentioned in the previous section, in contrast to
of the fact that they are noiseless components. For de- ENC, and ENC,, ENCo depends only on the detector
signers engaged in the detector design it is interesting to and shaper characteristics and is totally independent of
the ENCdmin as a function Of the detec- characteristics of the CSA, so that for the design of the
tor capacitance C,. Fig. 3 shows the minimal ENCdmi, as CSA, ENCo is not significant.
a function of the detector capacitance C, in the case of The final goal is to minimize the total equivalent noise
using a fourth-order ( n = 4) semi-Gaussian shaper with charges ENC, given by expression (16) rather than in&
1%~ peaking time. As expected, the minimal ENC,min vidual ENC, and ENC,. Since the optimal input transis-
increases with the detector capacitance C,. For example, tor gatewidths for ENC, and ENCf are different, it is not
if a detector with 40-pF capacitance is to be read Out possible to derive optimal input transistor dimensions for
using an nMoS input transistor with = 3pm, /1. = 6oo
ENC, analytically so that a numerical approach based on
cm2/V's, and IDS = 0.5 mA, then from (20) the the results for ENC, and ENC, must be used. Fig. 4
ENC,,, is calculated to be 345 noise electrons. shows schematically the effects of the transistor gatewidth
While for ENC, an optimal transistor gatewidth exists, on the ENC,, ENCf, and the sum of both ENC7s. It is
for an Optima' gate area is found for which readily recognized that the optimal gatewidth for the total
is minimal. It is derived by solving the equation of the ENC differs from the optimal for ENC, and ENC,
derivative Of (I3) with respect to gate area wL and is and lies between both. Clearly, for each specific applica-
given by tion where the detector capacitance is given it is always
3(c,+ C f > possible to find the optimal gate W based on the numeri-
WLOPt = 2aC0x '
(21) cal approach. As a rule of thumb one can approximate
the optimal gatewidth simply as the average of both
The existence of the optimal gate area rather than optima.
gatewidth stems from the fact that the l/f noise source To verify the theoretical analyses, a CMOS CSA has
depends on WL and is independent of W / L ratio [12], been designed and integrated in a standard 3-pm CMOS
[131. It means that as far as ENC, is concerned, either W technology with 1-pF feedback capacitance for 40-pF de-
or L may be chosen freely to meet the noise matching tector capacitance. The circuit schematic is shown in Fig.
condition (21). However, taking into account the ENC, 5 . The core amplifier is basically a folded cascode ampli-
 I 1 I

1380 IEEE TRASSACTIONS ov CIRC-UITSANI) SYSTEMS. VOL. 37, NO. 11. NOVEMBER 1990

700
1o3
ENC's

400

300

t
+ ENcd
+ END
- ENCd+f
200
w Iml 100
I"
0 2 4 6 8 10 12 14 16 18 20 22 24
1o3 1o4 1o5
Fig. 4. Effect of input transistor gatewidth W on ENC's. Parameters Fig. 6. Effect of order n of shaper on ENC's of a readout system with
T, = 1 ps.
are the same as in Fig. 3.

+ ENcd
+ ENCf
+- ENCs
- ENa
1 o3

102

ts [ps] n=4
GND
[e Rf
I I L

Fig. 5. Circuit schematic of designed low noise CMOS CSA.

integrators, the dc gain A of integrators, and the number

fier. It can be shown that the impedances at the node 2 is of integrators. As shown in the Section 11, the three
low ( = l / g m 2 ) for frequencies higher than go, /27rC, ENC's are completely independent of the dc gain of
where go, is the output conductance of the cascode integrators so that only 7, and n should be optimized
transistor M2. Since the frequency go, / 2 x C , is very low, from the point of view of achieving minimal number of
the Miller effect can be generally neglected. total ENC,. Mathematically, the optimal 7, and n must
In order to achieve the best noise performance the be found by solving the following set of equations simulta-
optimal input transistor dimensions are determined ac- neously:
cording to the above analyses. A bias current of 0.5 mA is
d ENC,
chosen for the input transistor considering the noise and =O
response speed requirements. As shown in (20) the higher a7,
the dc bias current the lower the thermal noise contribu- a ENC,
tion will be. The maximal dc bias current is mainly limited -- - 0.
by the available power supply V,, and dc bias voltages of dn
MOS transistors. Once the input transistor noise is opti- Unfortunately, the above set of equations can not be
mized the noise of other transistors must be minimized as solved analytically. To obtain insight into the effects of T~
well. This can be easily carried out because the input and n on the noise performance of the detector system,
transistor provides a large power gain. Hand calculations numerical methods must be adopted. In Fig. 6 the effect
and computer simulations show that the input MOS tran- of order n on the three ENC's and total ENC, is plotted
sistor contributes more than 90% to the total amplifier for a given peaking time 7, of 1 ps, while in Fig. 7 the
noise. effect of peaking time 7, is illustrated for n = 4. From
Fig. 6 it is clear that when the peaking time T , is given,
IV. OPTIMAL
DESIGN SHAPERS
OF PULSE
both E N C , and ENC, decrease with the order n. An
The transfer function of a semi-Gaussian pulse shaper inverse effect is observed for ENC, for n > 2. These
given in ( 5 ) is fully characterized by the following three combined effects lead to the important conclusion that
parameters: the time constant 7 , of the differentiator and for a given peaking time 7, an optimal order n of the

T
SANSEN AND CHANG: DETECTOR READOUT FRONT ENDS 1381

shaper exists for which the total ENC, is minimum. At

first sight, the existence of the optimal order n or the
increase in ENC, with n is not feasible. In fact, it is the
direct result of the constraint T , = T , / n required to en-
sure the output pulse to reach the top value at the
peaking time 7,. This constraint means that if the peaking
time T~ is given, then the time constant T , of the differen-
tiator and integrators must be varied in inverse propor-
tion to the order n of the shaper. The higher the order n ,
the smaller the T~ must be and the wider the frequency
range that is covered by the transfer characteristic of the
shaper.
Fig. 7 shows the effect of T , on the S/N performance
of a shaper. As has been widely observed [SI, for a given
order n of the shaper, ENC, is inversely proportional to Fig. 8. Circuit schematic of a second-order integrator using one OTA.
T,, ENC, is proportional to it, and ENCf is independent
of it. This results in an optimum peaking time from the where g, is the transconductance of the OTA and T~ =
point of view of the S/N performance. It can be shown
C , / g r n 3 and T * = ( R I + R2)C,. Equation (26) represents
that the optimum T , corresponds with the time at which the transfer function of a second-order integrator with the
the contributions of ENC, and ENC, are equal. It is time constant T , = 2 ~ / ( T~ ~+ 77,). ~It is important to
interesting to note that for a given order n of the shaper, note that as long as g,R, >> 1, the condition (25) depends
the optimum T , can be directly solved from the equation only on the ratios of gm's, R's, and C's that can be
(23a), which is given by precisely controlled in an IC process. Also, in this case
the gain of integrator is given by A = 1+ R , / R I , and the
integrator time constant is T~ = 2 ~ ~ .
It should be noted that although the noise performance
It is worthwhile comparing the optimum T , of shapers in a of the shaper is much less important compared to that of
CMOS technology with the shapers employing discrete the CSA, care must be taken to limit the 1/ f noise of the
JFET input devices. For a CMOS technology, the opti- shaper. Because in the frequency range lower than
mum T~ is always larger due to the negligible shot noise of 1/27r~,, the noise of the CSA is attenuated by the
the MOS transistor. Furthermore, the high l/f noise in a differentiator so that the I/f noise of the pulse shaper
CMOS technology makes the curve around the optimum turns out to be significant.
T$ more flat so that the choice of T , is less critical than in The total readout front end composed of the CSA of
the case of using JFET. In practice, other constraints such Fig. 5 and pulse shaper designed in this section has been
as high counting rate requirement and pile-up problem [8] simulated with SPICE. The output pulse and noise spec-
may force one to choose a peaking time T~ shorter than tral density are shown in Fig. 9(a) and (b). The simulated
the optimum one. value of the peak amplitude is exactly same as the theo-
The above noise analyses and discussions enable circuit retically calculated one. A slight delay in the peaking time
designers to determine the optimal pulse shaper charac- is due to the finite rise time of the step signal at the
teristics for a given detector capacitance in terms of S/N output of the CSA and parasitic poles within the pulse
performance. As an example, a fourth-order semi- shaper. In the passband of the shaper, the noise of the
Gaussian shaper ( n = 4) with the corresponding optimal input transistor contributes more than 70%. At low fre-
peaking time ~ , = 1ps has been designed in a CMOS quency the l / f noise of the shaper and the noise of
technology. In order to limit the number of active and resistances in the differentiator and integrators have sig-
passive components and power consumptions, which are nificant contributions, while at high frequency the reduc-
very important for multichannel systems, the fourth-order tion of the contribution of the input transistor is due to
integrator is realized as a cascade of two second-order the high frequency rolloff of the CSA. The total ENC,
integrators. Each of them is designed using only one due to both the CSA and pulse shaper is about 600
active gain block as shown in Fig. 8. It can be shown that electrons for a 40-pF detector capacitance. This value can
under the following condition: only be reduced by increasing the input transistor bias
current and the use of large capacitances in the integra-
grn3(R1+ Rz)', tors and differentiator.
=1 (25)
4(1+ grn',)C,
the transfer function of the circuit in Fig. 8 is given by V. CONCLUSIONS
The maximal capability of a CMOS technology for
implementing an integrated semiconductor detector read-
out system has been analyzed in terms of the detector
1382 IEEE TRANSACTIONS O N CIRCUITS AND SYSTEMS,
VOL.37, NO. 11, NOVEMBER 1990

3.75 ogy. Calculations and computer simulations show that a

Vout (t) [VI
detector resolution as low as 600 noise electrons can be
3.50
obtained, which is the best result among all recently
3.25 published ones. A further reduction of this value is only
possible by increasing the bias currents of the CSA and
3.00
integrated capacitances in the pulse shaper.
2.75
ACKNOWLEDGMENT
2.50 The authors would like to thank Canberra Semiconduc-
tor N.V, Olen, Belgium for their encouragement and
2.25
support.
2.00
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 REFERENCES
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of achieving the best detector resolution. The important
effect of l / f noise is studied and it is concluded that l / f m
noise in a CMOS process sets the lowest limit of the
detector resolution, especially for detectors with small
capacitances. For instance, for a detector having 40-pF Willy M. C. Sansen (S’66-M’72-SM’86), for a biography and photo
capacitance the best resolution obtainable by using a please see page 1084 of the September 1990 issue of this TRANSACTIONS.
CMOS technology is about 340 noise electrons.
In contrast to the optimal design of CSA’s, the optimal
design of semi-Gaussian pulse shapers depends not only m
on the noise in MOS transistors, but also on the noise of
the detector and its associated bias network. For a given
detector it is shown that when a peaking time is given, an Zhong Yuan Chang (S’88) received the engi-
optimal order of shaper can be determined. On the other neering degree in electronics from the
hand, if the order of the shaper is given, the optimal Katholieke Universiteit Leuven, Heverlee, Bel-
peaking time can be found as well. gium in 1985, where he is currently a research
assistant working towards the Ph.D. degree.
To verify the theoretical analyses, a charge sensitive His research interests are in the design and
amplifier matching a 40-pF detector capacitance and a implementation of low noise analog CMOS and
fourth-order semi-Gaussian pulse shaper with 1-ps peak- BJT integrated circuits for HiFi, biomedical,
and particle detector readout applications.
ing time are designed in a standard 3-bm CMOS technol-