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Digital Logic Design HW4 Solution

The document describes the solutions to a homework assignment on standard interconnect module designs including decoders, encoders, and multiplexers. It provides implementations of Boolean functions using minimal networks of these basic components. Students are asked to complete circuits with decoders, encoders, and multiplexers of different sizes to minimize the overall network.

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Ahmad Mirza Ahmad
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221 views11 pages

Digital Logic Design HW4 Solution

The document describes the solutions to a homework assignment on standard interconnect module designs including decoders, encoders, and multiplexers. It provides implementations of Boolean functions using minimal networks of these basic components. Students are asked to complete circuits with decoders, encoders, and multiplexers of different sizes to minimize the overall network.

Uploaded by

Ahmad Mirza Ahmad
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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CSE140 - HW #4 - Solution

Due Monday May 28, 11:59PM

We practice the standard interconnect module designs and applications.

1. (Decoders) Given four four-input Boolean functions (35 Points)


P P
f1 (a, b, c, d) = m(0, 1, 4, 7) + d(2, 3, 5),
P P
f2 (a, b, c, d) = m(1, 4, 11) + d(3, 14),
P P
f3 (a, b, c, d) = m(0, 8, 10, 11) + d(9, 12, 15).
P P
f4 (a, b, c, d) = m(2, 12) + d(8, 11, 14).
1.1. Implement the functions using a minimal network of 4:16 decoders and OR gates. (5
Points: Completion)

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1.2. Implement the functions using a minimal network of 3:8 decoders and OR gates. (25
Points: Correctness)

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1.3. Implement the functions using a minimal network of 2:4 decoders and OR gates. (5
Points: Completion)

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2. (Encoders) A high bit priority encoder inputs 2n bits from 2n devices and outputs n bit
as the index of the asserted input line with the highest priority (largest in binary code) as
shown in page 25 of lecture 11. Implement a high bit 16:4 priority encoder using 4:2 high
bit priority encoders and minimal networks of NAND gates.(15 Points: Completion)

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3. (Multiplexers) Assume a dual-railed system, where you have access to any variable
and its complement. Implement the following four-input Boolean function as indicated in
each of the following subproblems. (15 Points)
P P
f (a, b, c, d) = m(1, 2, 3, 5, 8, 13) + d(0, 7, 10, 14).
3.1. Implement the function using a minimal network of 8:1 multiplexers. (5 Points:
Completion)

a b c d=0 d=1 D(d)


0 0 0 X 1 1
0 0 1 1 1 1
0 1 0 0 1 d
0 1 1 0 X 0
1 0 0 1 0 d0
1 0 1 X 0 0
1 1 0 0 1 d
1 1 1 X 0 0

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3.2. Implement the function using a minimal network of 4:1 multiplexers. (5 Points:
Completion)

a b cd = 00 cd = 01 cd = 10 cd = 11 D(c, d)
0 0 X 1 1 1 1
0 1 0 1 0 X d
1 0 1 0 X 0 d0
1 1 0 1 X 0 c0 d

For the case of ab = 11:

c d D
0 0 0
0 1 1
1 0 0
1 1 0

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3.3. Implement the function using a minimal network of 2:1 multiplexers. (5 Points:
Completion)

a b cd = 00 cd = 01 cd = 10 cd = 11 D(c, d)
0 0 X 1 1 1 1
0 1 0 1 0 X d
1 0 1 0 X 0 d0
1 1 0 1 X 0 c0 d

For the case of ab = 11:

c d=0 d=1 D(d)


0 0 1 d
1 X 0 0

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4. Assume a dual-railed system, where you have access to any variable and its complement.
Given a four-input Boolean function (35 Points)
P P
f (a, b, c, d) = m(0, 3, 4, 7, 10, 12) + d(5, 11, 14).
4.1. Implement the function using a minimal network of 2:4 decoders and OR gates. (5
Points: Completion)

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4.2. Implement the function using a minimal network of 4:1 multiplexers. (25 Points:
Correctness)

a b cd = 00 cd = 01 cd = 10 cd = 11 D(c, d)
0 0 1 0 0 1 c0 d0 + cd
0 1 1 X 0 1 c0 d0 + cd
1 0 0 0 1 X c
1 1 1 0 X 0 d0

Note that for the case of ab = 01, we could use the don’t-care for cd = 01 (by letting
X = 1) to simplify D(c, d) to c0 + d, but letting X = 0 makes the overall network minimal
because we can reuse the multiplexer of the ab = 00 case. That said, either of the following
answers would be acceptable as well:

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4.3. Implement the function using a minimal network of 2:1 multiplexers. (5 Points:
Completion)

bcd
a 000 001 010 011 100 101 110 111 D(b, c, d)
0 1 0 0 1 1 X 0 1 D0
1 0 0 1 X 1 0 X 0 D1

Here is the K-map for D0 , which gives D0 = c0 d0 + cd:


cd
00 01 11 10

0 1 0 1 0
b
1 1 X 1 0

Here is the K-map for D1 , which gives D1 = bd0 + cd0 or D1 = bd0 + b0 c:


cd
00 01 11 10

0 0 0 X 1
b
1 1 0 0 X

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To get the minimal circuit, we choose D1 = bd0 + b0 c:

Choosing D1 = bd0 + cd0 results in an extra multiplexer.

b cd = 00 cd = 01 cd = 10 cd = 11 D(c, d)
0 0 0 1 0 cd0
1 1 0 1 0 d0

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