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ECE 270: Embedded Logic Design: Dr. Sumit J Darak Algorithms To Architectures Lab Associate Professor, ECE, IIIT Delhi

ECE 270 is a course on embedded logic design that covers block RAM in FPGA devices. Block RAM can be configured as single-port or dual-port and in sizes from 36Kb down to 18Kb blocks. It has features like cascading to create larger memory blocks, independent read and write ports, and configurable write modes for the data output.

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246 views29 pages

ECE 270: Embedded Logic Design: Dr. Sumit J Darak Algorithms To Architectures Lab Associate Professor, ECE, IIIT Delhi

ECE 270 is a course on embedded logic design that covers block RAM in FPGA devices. Block RAM can be configured as single-port or dual-port and in sizes from 36Kb down to 18Kb blocks. It has features like cascading to create larger memory blocks, independent read and write ports, and configurable write modes for the data output.

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Math Calculator
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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ECE 270: Embedded Logic Design

Dr. Sumit J Darak


Algorithms to Architectures Lab
Associate Professor, ECE, IIIT Delhi
http://faculty.iiitd.ac.in/~sumit/
ECE270: Embedded Logic Design
(ELD)

▪ The material for this presentation is taken from various books, courses and
Xilinx XUP resources. The instructor does not claim ownership of the material
presented in this class.
Block RAM
Block RAM
• All members of the 7-series families have dual-
port 36 Kb block RAM with port widths of up to 72
• Fully synchronous operation
• Multiple configuration options: True dual port,
simple dual port, single port
Block RAM
Each block RAM block can be used
• Each BRAM can be segmented as: as

• 36 Kb BRAM 18 Kb
BRAM
• 36 Kb FIFO 36 Kb
BRAM / or
• Independent 18 Kb BRAMs FIFO 18 Kb
BRAM /
• 18 Kb FIFO and 18 Kb BRAM FIFO

(1) 36 Kb BRAM (2) independent 18 Kb block RAMs


OR OR
(1) 36 Kb or FIFO (1) 18 Kb FIFO + (1) 18 Kb block RAM
Block RAM
• Each BRAM can be segmented as:
• 36 Kb BRAM
• 36 Kb FIFO
• Independent 18 Kb BRAMs
• 18 Kb FIFO and 18 Kb BRAM
• Dedicated hardware to convert BRAM in to FIFO
• Integrated cascade logic to build larger memories
• Integrated error correction logic to fix bit errors*
Dual-Port Block RAM
Dual-Port Block RAM
• Two separate read/write ports
• Each port has separate clock, address, data in, data out,
write enable…
• Clocks can be asynchronous to each other
• The two ports can have different widths
• The two ports can have different write modes
• Each block RAM can be divided into two completely
independent 18 Kb block RAMs
Dual-Port
Block RAM
Configurations
32K x 1
16K x 2
8K x 4
4K x 8(or 9)
2K x 16(or 18)
1K x 32(or 36)
512 x 64(or 72)
Block RAM Cascading
• Built-in cascade logic for 64Kx1
• Cascade two vertically adjacent 32Kx1 block RAMs
without using external CLB logic or compromising
performance
Block RAM Cascading
Block RAM Cascading
• Built-in cascade logic for 64Kx1
• Cascade two vertically adjacent 32Kx1 block RAMs
without using external CLB logic or compromising
performance
• Saves resources and improves speed of larger
memories
• Cascade option for larger arrays
• 128Kb, 256Kb, 512Kb, 1 Mb, …
• Using external CLB logic for depth expansion
• Not quite as fast as cascaded block RAMs
• Width expansion uses parallel block RAMs
Single-Port Block RAM
• Single read/write port
• Clock: CLKA, Address: ADDRA, Write enable: WEA
• Write data: DIA, Read data: DOA
• 36-kbit configurations
• 32k x 1, 16k x 2, 8k x 4, 4k x 9, 2k x 18, 1k x 36
• 18-kbit configurations*: 16k x 1, 8k x 2, 4k x 4, 2k x 9, 1k x 18
• The parity bits are only available for the x9, x18, and x36 port
widths. The parity bits should not be used when the read width is x1, x2, or x4
Simple Dual Port Block RAM 72
8
WRADDR
DI
WE
Port A

WRCLK

36 Kb
• Simple dual-port mode is defined as having one read- Memory
Array
only port and one write-only port with independent RDADDR
72
clocks. DO

• Each 36Kb block RAM can be set to simple dual-port RDCLK


Port B
(SDP) mode, doubling data width of the block RAM to
72 bits.
Configurations
• The 18Kb block RAM can also be set to simple dual-port
32K x 1
mode, doubling data width to 36 bits.
16K x 2
8K x 4
4K x 8(or 9)
2K x 16(or 18)
1K x 32(or 36)
512 x 64(or 72)
Simple Dual-Port Block RAM
Simple Dual-Port Block RAM
• In simple dual-port mode, independent
Read and Write operations can occur
simultaneously, where port A is designated
as the Read port and port B as the Write
port.
Block RAM
• Fully synchronous operation (Nothing happens without a clock)
• Each memory access, read or write, is controlled by the clock.
• All inputs, data, address, clock enables, and write enables are registered.
• The input address is always clocked, retaining data until the next operation.
• An optional output data pipeline register allows higher clock rates at the
cost of an extra cycle of latency.
Dual-Port Block RAM
Simple Dual-Port Block RAM
Block RAM: Ports
• Two ports (A and B) are symmetrical and totally independent, sharing only
the stored data
• Each port can be configured in one of the available widths, independent of
the other port.
• In addition, the read port width can be different from the write port width
for each port.
• The memory content can be initialized or cleared by the configuration
bitstream.
Block RAM (Configuration Modes)
• During a write operation, the data output can reflect either the previously stored
data, the newly written data, or can remain unchanged.
• Configurable write mode
• WRITE_FIRST: Data written on DIA is available on DOA
• READ_FIRST: Old contents of RAM at ADDRA is presented on DOA
• NO_CHANGE: The DOA holds its previous value (saves power)
These waveforms correspond to latch mode when the optional output pipeline register is not used.

Block RAM: WRITE_FIRST


Block RAM: READ_FIRST
Block RAM: NO_CHANGE Most power efficient

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