“​ Jacinto 6 Plus”

Automotive Processors

Introduction
Device Overview
The DRA74xP, DRA75xP, DRA76xP, and DRA77xP automotive applications
TI’s new “Jacinto 6 Plus” processors
are an extension of the current processors are built to meet the intense processing needs of the modern digital
“Jacinto 6” family of devices with cockpit automobile experiences.
improved performance and additional
features. Using the same common
core platform and heterogeneous Device Features o Real-time clock (RTCsubsystem
architecture as the existing • The device is composed of the o Debug subsystem
“Jacinto 6” family enables software
following subsystems:
platforming, allowing for maximum
reuse of investments and reduced
Package
o Two ARM® Cortex®-A15
time to market. microprocessor units (MPUs) • The “Jacinto 6 Plus” devices are
offered in two packages:
• “Jacinto 6 Plus” – Improved o Two digital signal processors
performance in the main (DSP C66x subsystem) • DRA74xP and DRA75xP are available
processing units (MPUs), in a 760-ball, 23x23mm, 0.8mm pitch
TMS320C66x digital signal o Imaging Subsystem (ISS), ball grid array (BGA) package,
processor (DSP), graphics including an image signal allowing for pin-to-pin compatibility
processing unit (GPU), and processor (ISP) with existing “Jacinto 6” devices.
memory speed allows for
concurrencies of infotainment o Image and video accelerator • DRA76xP and DRA77xP are available
and digital cluster features, high definition (IVA-HD) in a 784-ball, 23x23mm, 0.8mm pitch
emerging analytics and image subsystem ball grid array (BGA) package to
manipulation, as well as multi- take full advantage of Jacinto 6 Plus
OS capabilities. The integration o Two ARM Cortex-M4
of an image signal processor processing subsystems, capability and performance.
(ISP), CSI-2 ports, and CAN-FD1 each including two ARM 1: CSI-2 and CAN-FD available on DRA76xP
enable an optimized system Cortex-M4 microprocessors and DRA77xP only
bill-of-materials (BOM) while
supporting innovation. o Vision AccelerationPac 2: Vision AccelerationPac for Jacinto
including two embedded 6 Ex Plus only
• “Jacinto 6 EP Plus” - Adds a vision engines (EVEs)2
second TMS320C66x digital
signal processor (DSP) core for o Display subsystem (DSS)
image manipulation technologies
such as dynamically stitching o Video Processing High-Speed Interconnect
multiple cameras into a single, subsystem (VPE)
surround view; additional multi- o MIPI® CSI-2 camera
Graphics Processor
SGX544-MP2
radio tuner configurations; ARM * +
serial interface1
complex post processing Cortex << – Imaging Subsystem (ISS)
algorithms for audio and speech A15 C66x DSP with ISP
o Video Input
processing and a variety of other Capture (VIP) Capture Subsystem
differentiated technologies like ARM
Cortex
ARM
Cortex
Video Input Ports & CS1-2
driver monitoring system (DMS). o Dual-core M4 M4
IVA HD 1080p Video
POWERVR™ Co-Processors
• “Jacinto 6 Ex Plus” - Further SGX544-MPx 2x 32b DDR2/3
Shared RAM w/
extends performance and ECC Vision AccelerationPaC
3D GPU including two Embedded
integration possibilities from the On Chip Memory Controller Vision Engines2
“Jacinto 6 EP” by offering the TI o 2D-graphics Display Subsystem
Vision AccelerationPac including accelerator (BB2D)
System Services

two embedded vision engines subsystem, including

Security Timers, PLLs, GPIO PWM/CAP/QEP Radio Co-Processors
(EVEs) enabling simultaneous
Vivante™ GC320 core Connectivity and I/O
informational advanced driver PCIe DCAN NAND/
QSPI McSPI MMC/SD DMM
assistance systems (ADAS) o Three pulsewidth Gen 2 MLB CAN-FD NOR

and infotainment functionalities modulation (PWM) USB 2.0 USB 3.0 McASP MLB I2C UART Gigabit EMAC AVB
without compromising the subsystem
performance of either system.

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