Microprocessors and Microcontrollers

Unit I
8086 Architecture
B.Tech, ETM,
II Year, II Semester

N. Ramakrishna
Assistant Professor
Dept. of Electronics and Telematics
GNITS, Hyderabad

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 Syllabus
Unit I
8086 Architecture:
• Introduction to 8085 Microprocessor
• 8086 Architecture:
– Architecture of 8086
– Signal descriptions of 8086
– Common function signals
– Minimum and Maximum mode signals
– Timing diagrams
– Interrupts of 8086.
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 8086 Features
8086 Main Features:
• 16-bit processor
• 16-bit data bus, can also process 8 bit data
• 20 bit address bus, 1 MB memory
• 6 - 10 MHz frequency
• Fixed point arithmetic
• Two modes – Minimum, Maximum
• Multiprocessor environment
• Pre-fetch up to Six instructions
• +5V power supply, 40-pin DIP
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 8086 Architecture

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 8086 Architecture

8086 CPU – Two blocks

1. Bus interface Unit (BIU)
2. Execution unit (EU)
Bus Interface Unit
– Sends out addresses
– Fetches instructions from memory
– Reads data from ports and memory
– Writes data to ports and memory
(Handles all transfers of data and addresses
on the buses for execution unit)
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 Bus Interface Unit (BIU)

• Queue
– While EU is decoding an instruction or executing
an instruction that does not require use of buses,
BIU fetches up to 6 bytes for following instructions
– Stores in FIFO (first-in first-out) register called queue
– EU reads next instruction from queue
– Much faster than fetching from memory
– Fetching next instruction from memory
while current instruction executes is called pipelining

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 8086 Architecture

8086 CPU – Two blocks

Execution Unit
– Tells BIU where to fetch instructions or data from
– Decodes instructions
– Executes instructions

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 8086 Architecture

Execution unit (EU)

Control circuitry
– Directs internal operations
Decoder
– Decodes the instructions fetched from memory
into a series of actions which the EU carries out
ALU
– 16 bit
– add, subtract, AND, OR, XOR, increment, decrement,
complement, shift binary numbers
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 8086 internal registers
(register organization of 8086)

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 8086 internal registers

General purpose
Registers

Pointer and Index

Registers

Status and control

Register
Segment
Registers

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 8086 internal registers

• Registers
– Registers 16-bit, 14 Nos. are in the CPU and
are referred to by specific names
– Data registers (general purpose/scratch pad)
• Hold data for an operation to be performed
• There are 4 data registers (AX, BX, CX, DX)
– Address registers
• Hold the address of an instruction or data element
• Segment registers (CS, DS, ES, SS)
• Pointer registers (SP, BP, IP)
• Index registers (SI, DI)
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 8086 internal registers

Registers
– Status register
• Keeps the current status of the processor
• status register is called the FLAGS register

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 8086 internal registers
16 bits (2 bytes each)
Registers
• Instructions execute faster if the data is in a register
• AX, BX, CX, DX are the data registers
• Low and High bytes of the data registers
can be accessed separately
– AH, BH, CH, DH are the high bytes
– AL, BL, CL, and DL are the low bytes
• Data Registers are general purpose registers
but they also perform special functions

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 8086 internal registers

General-purpose Registers
• 8 General-purpose registers
• Similar to 8080 and 8085
• Temporary storage of data
• Located in CPU
• Data can be accessed very quickly
• AH, AL = AX BH, BL = BX
CH, CL = CX DH, DL = DX
• AL (AX) – accumulator

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 8086 internal registers
• AX
– Accumulator Register
– Preferred register to use in arithmetic, logic and
data transfer instructions because it generates
the shortest Machine Language Code
– Must be used in multiplication and division operations
– Must also be used in I/O operations
• BX
– Base Register
– Also serves as an address register
– Used in array operations
– Used in Table Lookup operations (XLAT)
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 8086 internal registers

• CX
– Count register
– Used as a loop counter
– Used in shift and rotate operations
• DX
– Data register
– Used in multiplication and division
– Also used in I/O operations

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 Pointer and Index Registers

• Contain the offset addresses of memory locations

• Can also be used in arithmetic and other operations
• SP: Stack pointer
– Points to the top of stack
– Used with SS to access the stack segment
• BP: Base Pointer
– Primarily used to access data on the stack
– Can be used to access data in other segments
• IP: Instruction Pointer
– Holds the offset of the next code byte
– Used with code segment
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 Pointer and Index Registers

• SI: Source Index register

– Required for some string operations
– When string operations are performed,
the SI register points to memory locations
in the data segment which is addressed
by the DS register.
Thus, SI is associated with the DS in string operations.

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 Pointer and Index Registers

• DI: Destination Index register

– Also required for some string operations.
– When string operations are performed,
the DI register points to memory locations
in the data segment which is addressed
by the ES register.
Thus, DI is associated with the ES in string operations.
• The SI and the DI registers may also be used
to access data stored in arrays

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 8086 Architecture

Flag Register
FlagH FlagL

Carry flag
Overflow flag
Direction Parity flag
flag
Interrupt enable Auxiliary flag
flag
Trap Zero flag
flag
Sign flag 6 status flags
3 control flags

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 8086 Architecture

Flag Register
• Flag : Flip-flop that indicates some condition produced
by the execution of an instruction or
control certain operations of EU
• 16-bit register, contains 9 flags
• 6 flags indicate condition produced by instruction
• Carry flag (CF), parity flag (PF), Auxiliary carry flag (AF),
zero flag (ZF), sign flag (SF), overflow flag (OF)
• 3 flags are control flags
• Set or reset by EU
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 8086 Architecture
Flags
C or Carry Flag
• If an operation causes overflow from MSB
(bit D7 or bit D15),
Carry flag C = 1 (set), else C = 0 (reset)
Z or Zero Flag
• If result of arithmetic or logic operation = 0
flag ZF= 1 (set), else ZF = 0 (reset)
S or Sign Flag
• If MSB (bit D7 or bit D15) of result = 1,
Sign flag S = 1 (set), else S = 0 (reset)

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 8086 Architecture
Flags
P or Parity Flag
• If result has even parity for lower byte (8 bits),
Parity flag P = 1 (set), else P = 0 (reset)
• Even for 16 bit operation, only lower 8 bits checked
AC or Auxiliary Carry Flag
• If an operation causes a carry from D3 to D4,
Auxiliary Carry flag AC = 1 (set), else AC = 0 (reset)
• Use for BCD operations
• No branching instructions based on this flag

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 8086 Architecture
OF or Overflow Flag
• Set under two conditions
1. Overflow into MSB (D7 or D15) from bit of
lower significance (D6 or D14),
but no carry from MSB
2. Carry from MSB, but no carry into MSB
Indicates that result of signed number of operation is
too large, modifying the sign bit.

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 8086 Architecture

Flag Register
• 3 flags to control operations,
deliberately set or reset by instructions
• Trap flag (TF)
Set to perform single step execution for debug.
• Interrupt flag (IF)
Set to enable the interrupts
• Direction flag (DF)
Used with string instructions
Indicates left or right for moving or
comparing string data
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 Memory organization

Memory Segmentation
F0000
E0000 8000:FFFF
D0000
C0000
B0000
A0000
90000
one segment
80000
70000
60000
8000:0250
50000
0250
40000
30000 8000:0000
20000
10000
seg ofs
00000

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 Memory Segmentation

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 Memory Segmentation

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 Memory organization

Memory Segmentation
Calculation of Physical address
from base address in segment + offset

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 Memory organization

Memory Segmentation
Segments and Corresponding Registers
Used for Specifying Offsets

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 Memory organization

Memory Organization
– Each byte in memory has a 20 bit address
starting with 0 to 220-1 or 1 Meg of addressable memory
– Addresses are expressed
as 5 hex digits from 00000 - FFFFF
Problem: But 20 bit addresses are
TOO BIG to fit in 16-bit registers!

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 Memory organization

Solution: Memory Segmentation

• Block of 64K (65,536) consecutive memory bytes
• A segment number is a 16 bit number
• Segment numbers range from 0000 to FFFF
• Within a segment, a particular memory location
is specified with an offset
• An offset also ranges from 0000 to FFFF
• Segmented memory addressing:
absolute (linear) address is a combination of
a 16-bit segment value added to a 16-bit offset

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 Memory organization
Segment registers
• A segment addresses 64 KB of memory
• Segment register contains
the address of starting location of segment
• Absolute location of segment obtained by appending 0H
• An offset is the distance from the beginning of
the segment to the location of instruction or data
• Code segment (CS) register
Stack segment (SS) register
Extra segment (ES) register
Data segment (DS) register
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 Memory organization

Stack and Physical address of top of the stack

Example: SS = 4466H  44660H

SP = 0122H  0122H
Physical address 44782H
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 Memory organization

Segment registers
• Stack
A section of the memory set aside to store addresses
and data while a subprogram executes
• Stack segment register
Used to hold the upper 16 bits of the starting address
for the program stack
• Extra segment register, data segment register
Used to hold upper 16 bits of starting addresses of
two memory segments that are used for data

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 Memory organization

Stack Segment Register and Stack Pointer Register

• Stack segment (SS) register
Holds the upper 16 bits of the starting address
for the stack
• Stack pointer register in EU
Holds 16-bit offset from start of the segment to
the memory location where a word was most recently
stored (known as top of the stack)
• 20-bit Physical address = SS:SP
Example: SS = 4466H  44660H
SP = 0122H  0122H
Physical address 44782H
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 Memory organization

Instruction Pointer

Addition of IP to CS
to produce
physical address of
the code byte
Example:
CS = 348AH  348A0H
IP = 4214H  4214H
Physical address 38AB4H
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 Memory organization

Instruction Pointer
• Code segment (CS) register
Holds the upper 16 bits of the starting address
for the instruction
• Instruction pointer register
Holds 16-bit offset of next code byte within CS
• 20-bit Physical address = CS + IP
• 20-bit Physical address = CS:IP
Example: CS = 348AH  348A0H
IP = 4214H  4214H
Physical address 38AB4H
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 8086 Pin diagram

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 Minimum/Maximum Mode

• Affects functions of pins 24-31

• Minimum Mode
 8086 is the only processor
 Pin 33 MN/MX = High
 Pins 24-31 are memory and I/O control signals
 Control signals generated internally

• Maximum Mode
 8086 and 8087 math coprocessor used
 Pin 33 MN/MX = Low
 Some control signals generated externally (e.g. 8288)
 Some pins used for new features
 These pins must be used when using an 8087
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 8086 Minimum Mode Pin Functions
Min/Max mode
Minimum Mode: +5V (High)
Maximum Mode: 0V (Low)

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 8086 Minimum Mode Pin Functions

Ground Power Supply

5V  10%

Reset
Registers, segment
registers, flags

Clock CS: FFFFH, IP: 0000H

Duty cycle: 33% If high for minimum 4 clks

First instruction after reset
at FFFF0H
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 8086 Minimum Mode Pin Functions

Address/Data Bus:
Contains address bits
A15-A0 when ALE is 1 &
data bits D15 - D0
Address Latch Enable:
when ALE is 0.
When high, multiplexed
address/data bus contains
address information.

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 8086 Minimum Mode Pin Functions

INTERRUPT

Non-maskable interrupt

Interrupt acknowledge
Interrupt request

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 8086 Minimum Mode Pin Functions

Direct Memory Access

DMA

Hold

Hold acknowledge

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 8086 Minimum Mode Pin Functions

S6: Logic 0.

S5: Indicates
condition of IF flag
bits.
Address/Status Bus
Address bits A19 - A16 &
S4-S3: Indicate Status bits S6 - S3
which segment is
accessed during
current bus cycle:

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 8086 Minimum Mode Pin Functions

BHE, A0: Bus High Enable/S7

0, 0: Whole word During T1, Enables
(16-bits) most significant data bits
D15 – D8 during read or
0,1: High byte to/from write operation.
odd address S7: available
during T2, T3, T4
1,0: Low byte to/from
even address

1,1: No selection

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 Physical Memory Organization
• In an 8086 based system, the 1Mbyte memory is physically
organized as odd bank and even bank, each of 512kbytes,
addressed in parallel by the processor.
BHE Ao Description

0 0 Whole word

0 1 Higher byte
to/from odd
address
(D15-D8)
1 0 Low byte
to/from even
address
(D7-D0)
1 1 No Selection

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28 March 2022 MPMC-N.Ramakrishna Unit I Session 1 49
 Physical Memory Organization
•Byte data with even address is transferred on D7-D0 and byte
data with odd address is transferred on D8-D15.
•The processor provides two enable signals, and for selecting of
either even or odd or both the banks.

BHE Ao Description

0 0 Whole word
0 1 High byte to/from
odd address
1 0 Low byte to/from
even address
1 1 No Selection

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 8086 Minimum Mode Pin Functions

Min/Max mode
Minimum Mode: +5V (High)
Maximum Mode: 0V (Low)

Min mode pins

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 8086 Minimum Mode Pin Functions

Wait

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 Minimum/Maximum Mode

• READY:
The acknowledgement
from the addressed memory or
I/O device that it will complete the data transfer.

• TEST:
Input is examined by the “WAIT” instruction.
If the TEST input is LOW execution continues,
otherwise the processor waits
in an ``Idle'‘ state.

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 8086 Minimum Mode Pin Functions

Read Signal

Write Signal

Memory or I/O

Data
Transmit/Receive

Used by external data bus buffers Data Bus Enable

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 8086 Maximum Mode Pin Functions

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 8086 Maximum Mode Pin Functions

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 8086 Maximum Mode Pin Functions

S2 S1 S0
000: INTA
001: read I/O port
010: write I/O port
011: halt
Status Signal
100: code access
Inputs to 8288
101: read memory
to generate
110: write memory
eliminated signals
111: none -passive
due to max mode.

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 Maximum Mode

RQ0/GT0 30-31 Used by the other local bus masters to force

RQ1/GT1 the processor to release the local bus
at the end of the processor’s current bus cycle

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 Maximum Mode

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 8086 Maximum Mode Pin Functions

DMA
Request/Grant

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 8086 Maximum Mode Pin Functions

Lock Output
Used to lock
peripherals off Lock Output
the system
Activated by using
the LOCK: prefix
on any instruction

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 8086 Maximum Mode Pin Functions

QS1 QS0
00: Queue is idle
01: First byte
of opcode Queue Status
10: Empty the Queue Used by numeric
11: Subsequent byte coprocessor (8087)
of opcode

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 The Queue operation

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 8086 Timing Diagram
Simplified 8086 Write Bus Cycle

http://www.ece.unm.edu/~jimp/310/slides/8086_chipset.html
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 8086 Timing Diagram
Simplified 8086 Read Bus Cycle

http://www.ece.unm.edu/~jimp/310/slides/8086_chipset.html
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 8086 Timing Diagram
8086 Write, Read Bus Cycle
Writing:
• Dump address on address bus.
• Dump data on data bus.
• Issue a write ( WR ) and set M/ IO to 1.

Reading:
• Dump address on address bus.
• Issue a read ( RD ) and set M/ IO to 1.
• Wait for memory access cycle.

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 Minimum mode 8086 System

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 Minimum mode 8086 System

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 Minimum mode 8086 System

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 Minimum mode 8086 System

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 Minimum mode 8086 System

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 Read Cycle Timing diagram –Minimum
mode

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 Read Cycle Timing diagram –Minimum
mode

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 Write Cycle Timing diagram –Minimum
mode

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 Write Cycle Timing diagram –Minimum
mode

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 Minimum mode-8086

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 Maximum mode 8086 System

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 Read Cycle Timing diagram –
Maximum mode

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 Write Cycle Timing diagram –
Maximum mode

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 8086 Timing Diagram
Bus Timing for Read Operation

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 I/O addressing Capability of
8086

The 8086 processor can address up to 64K I/O byte register, i.e 216 64Kbyte I/O
devices may be accessed by 8086

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 Text Books
TEXT BOOKS:
1. Advanced Microprocessors and Peripherals – A. K.
Ray and K.M. Bhurchandi, Tata-McGraw Hill, 2nd
edition 2006.
2. Microprocessors and Microcontrollers, Lyla B.Das,
Pearson, 2012

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 References
REFERENCES:
1. The 8051 Microcontrollers, Architecture and programming and
Applications -K.Uma Rao, Andhe Pallavi, , Pearson, 2009.
2. The 8051 Microcontoller and Embedded Systems Using
Assembly and C, Second Edition, Muhammad Ali Mazidi, Janice
Gillispie Mazidi, Rolin D. McKinlay, Prentice Hall
3. Micro Computer System 8086/8088 Family Architecture,
Programming and Design - Liu and GA Gibson,
Prentice Hall India, 2nd Ed.
4. Microcontrollers and application, Ajay. V. Deshmukh,
Tata-McGraw Hill, 2005
5. The 8085 Microprocessor: Architecture, programming and
Interfacing – K. Uday Kumar, B.S. Umashankar, 2008, Pearson

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