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Vlsi Assignment No. (2) : Name: Walaa Khalil Wagan Berima Computer and Networks

Here are the key steps to plot Ids vs. Vds for the given nMOS transistor: 1) Given: W/L = 4/2 λ = 1.2/0.6 μm 2) Cox = εo/Tox = 8.85×10^-14 F/cm^2 / 100×10^-8 cm = 8.85×10^-15 F/cm^2 3) K = W×Cox = 1.2×8.85×10^-15 = 1.062×10^-14 F 4) μn = 350 cm^2/V·s 5) Vth = 0.7 V 6) Use the n

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85 views

Vlsi Assignment No. (2) : Name: Walaa Khalil Wagan Berima Computer and Networks

Here are the key steps to plot Ids vs. Vds for the given nMOS transistor: 1) Given: W/L = 4/2 λ = 1.2/0.6 μm 2) Cox = εo/Tox = 8.85×10^-14 F/cm^2 / 100×10^-8 cm = 8.85×10^-15 F/cm^2 3) K = W×Cox = 1.2×8.85×10^-15 = 1.062×10^-14 F 4) μn = 350 cm^2/V·s 5) Vth = 0.7 V 6) Use the n

Uploaded by

Wilo Khalil
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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VLSI

Assignment no. ( 2)

Name : Walaa Khalil Wagan Berima

Computer and networks

Question One: What the difference between pass transistor and


transmission gate?

Transmission-Gate | Pass-Transistor-Logic Transmission Gate Logic : The transmission gate logic is used
to solve the voltage drop problem of the pass transistor logic. This technique uses the complementary
properties of NMOS and PMOS transistors. i.e. NMOS devices passes a strong '0' but a weak ' 1' while
PMOS transistors pass a strong '1' but a weak '0'. The transmission gate combines the best of the two
devices by placing an NMOS transistor in parallel with a PMOS transistor as shown in Figure below . The
control signals to the transmission gate C and ––C are complementary to each other . The transmission gate
is mainly a bi-directional switch enabled by the gate signal 'C'.When C = 1 both MOSFETs are ON and the
signal pass through the gate i.e. A = B if C = 1.
Whereas C = 0 makes the MOSFETs cut off creating an open circuit between nodes A and B.

When the gate of a transistor is ON (or has a value 1) then electricity flows from the source to the sink and
the transistor is said to be ON.

Otherwise when the gate of a transistor is OFF (or has a value 0) then electricity does not flow from the
source to the sink and the transistor is said to be OFF.
Question Two : Explain, by illustration the noise margin's in COMS
noise margin of a logic gate:

Noise margin is the amount of noise that a CMOS circuit could withstand without compromising the
operation of circuit. Noise margin does makes sure that any signal which is logic ‘1’ with finite noise
added to it, is still recognized as logic ‘1’ and not logic ‘0’. It is basically the difference between signal
value and the noise value. Refer to the diagram below.:

Consider the following output characteristics of a CMOS inverter.


Ideally, when input voltage is logic ‘0’, output voltage is supposed to logic
‘1’. Hence Vil (V input low) is ‘0’V and Voh (V output high) is ‘Vdd’V.

Vil = 0Voh = Vdd


Ideally, when input voltage is logic ‘1’, output voltage is supposed to be at
logic ‘0’. Hence, Vih (V input high) is ‘Vdd’, and Vol (V output low) is ‘0’V.

Vih = Vdd, Vol = 0 Noise Margins could be defined as Follows:


NMl (NOISE MARGIN low) = Vil – Vol = 0 – 0 = 0

NMh (NOISE MARGIN high) = Voh – Vih = Vdd – Vdd = 0


But due to voltage droop and ground bounce, Vih is usually slightly less than
Vdd i.e. Vdd’, whereas Vil is slightly higher that Vss i.e. Vss’.

Hence Noise margins for a practical circuit is defined as follows :


NMl (NOISE MARGIN low) = Vil – Vol = Vss’ – 0 = Vss’
NMh (NOISE MARGIN high) = Voh – Vih = Vdd – Vdd’

Hence, if input voltage (Vin) lies somewhere between Vol and Vil, it would be detected as logic ‘0’, and would
result in an output which is acceptable.

Similarly, if input voltage (Vin) lies between Vih and Voh, it would be detected as logic ‘1’ and would result in
an output which is acceptable.

Fixed noise margin:

Luckily, there are some things you can do to improve the SNR margin:

 Buy a router that is good enough to manage low SNR margin figures.
 Install a good quality ADSL filter to your router and to each phone device installed on the same
line.
 Try to change the ADSL provider, as some providers are less crowded than others
Question Three:- Consider an nMOS transistor in a 0.6 µm process
with W/L = 4/2 λ (i.e., 1.2/0.6 µm). In this process, the gate oxide
thickness is 100 Ǻ and the mobility of electrons is 350 cm2/V·s. The
threshold voltage is 0.7 V. Plot Ids vs. Vds for Vgs = 0, 1, 2, 3, 4, and 5
V. 𝐾𝑜𝑥 = 3.9, 𝜀𝑜 = 8.85 × 10−14𝐹/ 𝑐
Solution :-

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