Example 1: Simplify the following Boolean expression.

Using Boolean algebra postulates and

& DE Morgan’s low.
 X + XY = X·1 + XY = X(1+Y) = X·1 = X
 XY+XY’ = X(Y + Y’) = X·1 = X
 X+X’Y = (X+X’)(X+Y) = 1· (X+Y) = X+Y
 X· (X+Y)=X·X+X·Y= X+XY=X(1+Y)=X·1=X
 (X+Y) ·(X+Y’)=XX+XY’+XY+YY’= X+XY’+XY+0=X(1+Y’+Y)=X·1=X
 X(X’+Y) = XX’+XY = 0 + XY = XY
 (A+B)(A’+C) = AA’ + AC + A’B + BC = AC + A’B + BC= AC + A’B

Example 2: Find the complement of the following Boolean function

F=X’YZ’+X’Y’Z

Example 3: Simplify the following Boolean expression. Using Boolean algebra postulates and
& DE Morgan’s low. Draw its logic diagram before and after the simplification.

 F = X’YZ + X’YZ’ + XZ
 Reduces to F = X’Y + XZ

Before
After
Example 4: Simplify the following Boolean expression. Using Karnaugh Maps.
(A) F(A,B,C,D)=∑ m(0,2,8,9,10,11,14,15)

F(A,B,C,D)= A.B’+A.C+B’.D’

(B) f1(x, y, z) = ∑ m(2,3,5,7) = f1(x, y, z) = x’y + xz

(C) f2(x, y, z) = ∑ m (0,1,2,3,6) =f2(x, y, z) = x’+yz’

- - - - - - - - - - - - - - - - - - - - - - - - -
Example 5: Simplify the following Boolean function:
g (A,B,C,D) = ∑m(0,1,2,4,5,7,8,9,10,12,13).
First put the function g( ) into the map, and then group as many 1s as possible.

ab
cd

1 1 1 1 1 1

1 1 1 1 1 1

1 1 1 1

1 1 1 1 1 1

g(A,B,C,D) = c’+b’d’+a’bd
 Example 6: Simplify the function f(a,b ,c,d) whose K-map is shown in the following figure

cd
ab 00 01 11 10
00
01

11
10

0 1 0 1 0 1 0 1

1 1 0 1 1 1 0 1

0 0 x x 0 0 x x

1 1 x x 1 1 x x

f = a’c’d+ab’+cd’+a’bd’ Or… f = a’c’d+ab’+cd’+a’bc’

Example 7: Recall full adder equations, and let X, Y, and Z be the inputs:
S(X,Y,Z) = X+Y+Z = m(1,2,4,7)
C (X,Y,Z) = m(3, 5, 6, 7).
Represent S and C using 3- to 8 line decoder.

Since there are 3 inputs and

a total of 8 minterms, we need a 3-to-8 decoder

Example 8: Use NAND gates and NOT gates to implement Z=E’F(AB+C’+D’)+GH

Step 1: AB
Step 2: AB+C’+D’
Step 3: E’F(AB+C’+D’)
Step 4: E’F(AB+C’+D’)+GH
Example 9:
Implement the following set of parity functions using decoder
P1 (w,x,y,z)= Sm(1,2,5,6,8,11,12,15)
P2 (w,x,y,z)= Sm(1,3,4,6,8,10,13,15)
P4 (w,x,y,z)= Sm(2,3,4,5,8,9,14,15)

w 0 P1
1
x 2
y 3
4
z 5 P2
6
7
8
9
10
11 P4
12
13
14
15

Example 10:
Use the universal property of NAND gate to draw the logic diagram corresponding to the
following Boolean function:
̅̅̅̅̅̅̅
̅̅̅̅̅ ) + 𝑥𝑧̅] + 𝑤𝑥𝑧 + 𝑦̅𝑧̅.
𝑓(𝑤, 𝑥, 𝑦, 𝑧) = 𝑤𝑦̅[(𝑤𝑦

Example 11:
Simplify the following Boolean function
- F(A, B, C) = Σm(1, 2, 5, 7) + Σdc(0, 4, 6)
- F(A, B, C) = Σm(0, 1, 6, 7) + Σdc(3, 4, 5)
- F(A, B, C, D) = Σm(0, 2, 8, 10, 14) + Σd(5, 15)
- F(A, B, C, D) = Σm(3, 4, 5, 7, 9, 13, 14, 15)
- F(W, X, Y, Z) = Σm(1, 3, 4, 6, 9, 11, 12, 14)
Example 12:
Write a Boolean expression for the following logic diagram:

Example 13:
Simplify the following minterm canonical formula using Boolean algebra & Demorgan’s low
𝑓(𝑥, 𝑦, 𝑧) = ∑ 𝑚(0,1,2,4,5,6)

Example 14:
Simplify the following Boolean function, which is given as true table using Karnaugh Map.
After the simplification, draw the function logic diagram after.
Input Output
W X Y Z F
0 0 0 0 X
0 0 0 1 0
0 0 1 0 1
0 0 1 1 0
0 1 0 0 X
0 1 0 1 1
0 1 1 0 X
0 1 1 1 0
1 0 0 0 1
1 0 0 1 1
1 0 1 0 X
1 0 1 1 0
1 1 0 0 0
1 1 0 1 1
1 1 1 0 0
1 1 1 1 1
Example 15:
Perform the addition operation of the two octal numbers (76) and (67), and then use the
Binary Full Adders to design the suitable logic circuit to execute the operation .

Example 16:
Perform the following additional operation in binary and then draw its corresponding logic
circuit. W=X+Y. Please note that X=101 and Y=111.
Example 17:
Use the universal property of NAND gate to draw the logic diagram corresponding to the
following Boolean function:
̅̅̅̅̅̅̅
̅̅̅̅̅ ) + 𝑥𝑧̅] + 𝑤𝑥𝑧 + 𝑦̅𝑧̅.
𝑓(𝑤, 𝑥, 𝑦, 𝑧) = 𝑤𝑦̅[(𝑤𝑦

Example 18:
What is the difference between:
- Decoder Vs Encoder
- Multiplexer Vs DE-multiplexer
- SR Flip-Flop Vs D Flip-Flop

Example 19:
Implement a full adder with two 4 x 1 multiplexers.

Example 20:
Design 16 x 4 line Encoder, create the truth table, extract the output equations and then create
the logic circuit accordingly.

Example 21:
Create 1 X 8 De-multiplexer, that has an input I, and outputs (𝑌0 𝑡𝑜 𝑌7 ), using one 1 X 2 De-
multiplexer and two 1 x 4 De-multiplexer. Create the truth table and then use the block
diagrams to implement the logic circuit.

Example 22:
Execute the following Boolean function with a multiplexer
f  A, B, C , D    m0,1,2,3,4,8,9, A, B, D, F 
f  A, B, C , D    m0,1,3,4,5,9,10,11
f  A, B, C    m0,1,2,3,5,7 
f  A, B, C , D    m2,4,5,6,7 

Example 23:
An 8 X 1 multiplexer has input A,B and C connected to select lines 𝑆2 , 𝑆1 𝑎𝑛𝑑 𝑆0 respectively.
The data input 𝐼0 through 𝐼7 are as following:
𝐼1 = 𝐼2 = 0 𝐼3 = 𝐼5 = 1 𝐼0 = 𝐼4 = 𝐷′ 𝐼6 = 𝐼7 = 𝐷
Example 24:
What is the difference between Normal Encoder and priority Encoder?

Example 25:
What is the difference between SR-Flip Flop and JK Flip Flop?

Example 26:
What is the difference between SR-Flip Flop and JK Flip Flop?

Example 27: (‫(مثال محلول‬

Assume that the following signals are applied to SR Flip-Flop and its initial condition is zero.
Identify outputs ( 𝑄 , 𝑄̅) timing diagram.

Example 28: (‫(مثال محلول‬

Assume that the following signals are applied to JK Flip-Flop and its initial condition is zero.
Identify outputs ( 𝑄 , 𝑄̅) timing diagram.
Example 29: (‫(مثال محلول‬
Assume that the following signals are applied to D Flip-Flop and its initial condition is zero.
Identify outputs ( 𝑄 , 𝑄̅) timing diagram.

Example 30:
Assume that the following signals are applied to JK Flip-Flop and its initial condition is zero.
Identify outputs ( 𝑄 , 𝑄̅) timing diagram.

CLK

Example 31:
Assume that the following signals are applied to JK Flip-Flop and its initial condition is zero.
Identify outputs ( 𝑄 , 𝑄̅) timing diagram.

CLK
J

K
Example 32:
Assume that the following signals are applied to D Flip-Flop and its initial condition is zero.
Identify outputs ( 𝑄 , 𝑄̅) timing diagram.

Example 33:
Assume that the following signals are applied to SR Flip-Flop and its initial condition is zero.
Identify outputs ( 𝑄 , 𝑄̅) timing diagram.

CLK