UART

Programming in
AVR
LECTURE# 16
MICROPROCESSOR SYSTEMS AND INTERFACING

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Last Lecture
Keypad Interfacing
Serial Communication
◦ Simplex, Half Duplex and Full Duplex
◦ Synchronous and Asynchronous
◦ UART
◦ RS232

AVR Serial Port Programming

◦ Introduction

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Quiz 2

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Quiz 2 -

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 Vector Program
Source Interrupt Definition
No. Address

Quiz 2 – Timer 8
9
10
0x000E
0x0010
0x0012
TIMER2_COMPA
TIMER2_COMPB
TIMER2_OVF
Timer/Counter2 Compare Match A
Timer/Counter2 Compare Match B
Timer/Counter2 Overflow

Programming using Interrupts

Q1. How many timers are available in AVR ATmega328?
Q2. What is the different between Normal and CTC mode?
◦ Write 2 - 3 lines each

Q3. Write steps (or C or assembly), register values and ISR to

◦ Configure timer 2 in CTC mode
◦ 𝐹𝑂𝑆𝐶 = 16 MHz, 𝐹𝑡𝑖𝑚𝑒𝑟2 = 2 MHz
◦ Using OCR2A register
◦ To toggle pin PC.3
◦ every (2 x reg#) clock cycles
◦ Using interrupts

Other registers are TCNT2, OCR2A, OCR2B

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Serial Communication
Offers communication over less number of wires
◦ Imagine LCD interfacing with 3 wires

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Simplex, Half and Full Duplex
UART offers Full Duplex
◦ Two simplex lines

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Synchronous and Asynchronous
Serial Communication
The sender and receiver should agree to a few rules
◦ Called protocol
In Synchronous communication
◦ the clock is shared between sender and receiver
In Asynchronous communication there is no shared clock
◦ Both sender and receiver have their own clock sources
◦ But should have same frequency (called baud rate)
◦ Also, extra bits are added to ensure reliable transfer
UART (Universal Asynchronous Receiver/Transmitter)
◦ is an asynchronous means of serial communication
Baud rate is signal changes per second
◦ Unlike bit rate which is number of bits sent per second

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UART Frame
In UART, communication is done, frame by frame
◦ Each frame contains 5-9 data bits, usually
Each character transmitted is placed between start and stop bit(s)
◦ This is called framing
There is always one start bit
◦ Start bit is logic low
Stop bit(s) can be one or two bits
◦ Stop bit(s) is always high
A UART frame is shown for sending 8 data bits 0b01000001

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RS232
A standard for defining signals
◦ Voltage levels, pinouts, connectors
◦ Like COM ports on a PC

While UART define timings and bits

◦ RS232 defines physical signals

Unlike TTL, RS232

◦ Logic Low is +3 to +25 V
◦ Logic High is -3 to -25 V
◦ Undefined -3 to +3 V

A converter is needed
◦ MAX232

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ATMEGA328p and RS232
Connection of ATmega328p with PC using RS232 is shown below
◦ MAX232 IC translates logic levels between TTL (µC side) and RS232 (PC side)
Vcc Nowadays, USB-to-UART (TTL)
C3 converter is used instead, such
16 +
+ 2 as CH340 or CP2102 ICs.
C1 1 MAX232 ATmega328p To connect PC with µC.
3 6
+ C4 MAX232
4
C2 5 +
T1IN T1OUT (PD1)TXD 3 11
14 2
5
11 14
R1OUT R1IN
12 13 13 3
(PD0)RXD 2 12
T2IN T2OUT
10 7
R2OUT R2IN DB-9
9 8

TTL side 15 RS232 side 40-Pin DIP Package ATmega32

Corrected version of
Figure 11-7 (a) Inside MAX232 and (b) Its connection to ATmega328p*

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AVR Serial port programming
Baud rate calculation

→
For 8 MHz oscillator:

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AVR Registers
UBRR0
◦ URSEL = 0

UDR0
◦ Tx and Rx Register

UCSR0A, UCSR0B & UCSR0C

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AVR Registers
UCSR0A RXC0 TXC0 UDRE0 FE0 DOR0 UPE0 U2X0 MPCM0

RXC (Bit 7): USART Receive Complete

This flag bit is set when there are new data in the receive buffer that are not read yet. It is cleared when the receive buffer is
empty. It also can be used to generate a receive complete interrupt.
TXC (Bit 6): USART Transmit Complete
This flag bit is set when the entire frame in the transmit shift register has been transmitted and there are no new data available in
the transmit data buffer register (TXB). It can be cleared by writing a one to its bit location. Also, it is automatically cleared when
a transmit complete interrupt is executed. It can be used to generate a transmit complete interrupt.
jab yeh bit UCSR0A mein empty ho ga tou it will get ready to receive the new data jo k us ko print
UDRE (Bit 5): USART Data Register Empty karw a ga if we want to print something udre0a should be empty in register UCSR0A
This flag is set when the transmit data buffer is empty and it is ready to receive new data. If this bit is cleared, you should not
write to UDR because it overrides your las tdata. The UDRE flag can generate a data register empty interrupt.
FE (Bit 4): Frame Error
This bit is set if a frame error has occurred in receiving the next character in the receive buffer. A frame error is detected when the
first stop bit of the next character in the receive buffer is zero.
DOR (Bit 3): Data OverRun
This bit is set if a data overrun is detected. A data overrun occurs when the receive data buffer and receive shift register are full,
and a new start bit is detected.
PE (Bit 2): Parity Error
This bit is set if parity checking was enabled (UPM1 = 1) and the next character in the receive buffer had a parity error when
received.
U2X (Bit 1): Double the USART Transmission Speed
Setting this bit will double the transfer rate for asynchronous communication.
MPCM (Bit 0): Multi-processor Communication Mode
This bit enables the multi-processor communication mode. The MPCM feature is not discussed in this text.
Notice that FE, DOR, and PE are valid until the receive buffer (UDR) is read. Always

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 Enable transmitter

AVR Registers Enable receiver

UCSR0B RXCIE0 TXCIE0 UDRIE0 RXEN0 TXEN0 UCSZ02 RXB80 TXB80

RXCIE (Bit 7): Receive Complete Interrupt Enable

To enable the interrupt on the RXC flag in UCSRA you should set this bit to one. UCSR0B=0b10000000

TXCIE (Bit 6): Transmit Complete Interrupt Enable

To enable the interrupt on the TXC flag in UCSRA you should set this bit to one. UCSR0B=0b01000000

UDRIE (Bit 5): USART Data Register Empty Interrupt Enable

To enable the interrupt on the UDRE flag in UCSRA you should set this bit to one. UCSR0B=0b00100000

RXEN (Bit 4): Receive Enable

To enable the USART receiver you should set this bit to one.
UCSR0B=0b00011000
TXEN (Bit 3): Transmit Enable
To enable the USART transmitter you should set this bit to one.

UCSZ2 (Bit 2): Character Size

This bit combined with the UCSZ1:0 bits in UCSRC sets the number of data bits (character size) in a frame.

RXB8 (Bit 1): Receive data bit 8

This is the ninth data bit of the received character when using serial frames with nine

TXB8 (Bit 0): Transmit data bit 8

This is the ninth data bit of the transmitted character when using serial frames with nine data bits. This bit is not used in this text.

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 AVR Registers
UCSR0C
UMSEL01 UMSEL00 UPM01 UPM00 USBS0 UCSZ01 UCSZ00 UCPOL0

USBS0 Stop Bit Select

0 1-bit
1 2-bit

UPM[1:0] Parity Mode UCSZ0[2:0] Character Size

00 Disabled 000 5-bit
01 (Reserved 001 6-bit
10 Even Parity 010 7-bit
11 Odd Parity 011 8-bit
100 (Reserved)
UMSEL01 UMSEL00 Mode 101 (Reserved)
0 0 Asynchronous USART 110 (Reserved)
0 1 Synchronous USART 111 9-bit

1 0 (Reserved)
1 1 Master SPI (MSPIM) UCPOL Used in Synchronous Mode

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 AVR Registers Summary
and Interrupt Vectors
UMSEL01 UMSEL00 UPM01 UPM00 USBS0 UCSZ01 UCSZ00 UCPOL0

UCSR0A RXC0 TXC0 UDRE0 FE0 DOR0 UPE0 U2X0 MPCM0 UCSZ0[2:0] Character Size
UCSR0B RXCIE0 TXCIE0 UDRIE0 RXEN0 TXEN0 UCSZ02 RXB80 TXB80 000 5
UCSR0C UMSEL01 UMSEL00 UPM01 UPM00 USBS0 UCSZ01 UCSZ00 UCPOL0 001 6
010 7
UBRR0H - - - - UBBR[11:8] 011 8
UBRR0L UBRR[7:0] 111 9
UDR0 (Read) RXB0[7:0] Number of
UDR0 (Write) TXB0[7:0] USBS0
Stop bits
0 1
1 2

Address Source Interrupt Definition

$024 USART_RX USART, Rx Complete
$026 USART_UDRE USART Data Register Empty
$028 USART_TX USART, Tx Complete End of lecture

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