Digital Logic Design Lab 02 Report

Experiment: VHDL-Quartus II /ModelSim & Implementation of 4 bit full adder, BCD adder,

4 bit adder/subtractor using Structural VHDL.

Instructor Name:
 1

Lab 2 Objectives:
 Understanding the basics of VHDL descriptions
 Use Quartus IDE
 Use ModelSim Simulator

Software Used:
a. Quartus II
b. ModelSim
c. MultiSim

Introduction
VHSIC Hardware Description Language (VHDL) is a programming language used to describe
hardware. Unlike other programming languages such C or Java which are sequential
languages, VHDL is concurrent (parallel) language. VHDL statements run at the same time
A fundamental motivation to use VHDL (or its competitor, Verilog) is that VHDL is a standard,
technology/vendor independent language, and is therefore portable and reusable. The two main
immediate applications of VHDL are in the field of Programmable Logic Devices (including CPLDs and
FPGAs) and ASICs. A final note regarding VHDL is that contrary to regular computer programs which
are sequential, its statements are inherently concurrent (parallel). In VHDL, only statements placed inside
a Process, Function or Procedure are executed sequentially.

In the previous laboratory session, the basics of behavioral VHDL were revised.
The current lab session revises the basics of structural VHDL to build a hardware system in
bottom-up fashion
Circuit Diagram

Figure 1 Diagram for 4-bit full adder

 2

Figure 2: Diagram for 4-bit BCD adder

Figure 3: Diagram for 4-bit adder/Subtract.

 3

Experiment Details
Task 3.1
Commonly reused entities

Figure 1: VHDL File Code for “XOR gate” In Behavioral Model(task3.1).

Figure .2: VHDL File Code for “AND gate” In Behavioral Model(task3.1).
 4

Figure 3: VHDL File Code for “OR gate” In Behavioral Model(task3.1).

Figure 4: VHDL File Code for “HALF ADDER” In Behavioral Model(task3.1).

Figure 5: VHDL File Code for “1 BIT FULL ADDER” In Behavioral Model(task3.1).
 5

Figure 3.1: VHDL File Code for “4-bit FULL ADDER” In Behavioral Model(task3.1).
Task 3.2

Figure 3.2: VHDL File Code for “BCD ADDER” In Behavioral Model(task3.2).
 6

Task 3.3

Figure 3.3: VHDL File Code for “4 bit ADDER/SUBTRACTOR” In Behavioral

Model(task3.3).

Outputs

Figure 3.1.1: Output Result of “4 bit full adder” behavioral Model.

 7

Figure 3.1.1(2): Output Result of “4 bit full adder” in generic form of Behavioral Model.

Figure 3.2.1: Output Result of “BCD ADDER” in Behavioral Model.

 8

Figure 3.3.1: Output Result of “4 bit ADDER/SUBTRACTOR” Behavioral Model.

Truth Tables

INPUT A INPUT B CARRY in OUTPUT (SUM) CARRY out

A3 A2 A1 A0 B3 B2 B1 B0 Cin S3 S2 S1 S0 Cout
0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1 0 0 0 1 0 0
0 0 1 0 0 0 1 0 0 0 1 0 0 0
0 0 1 1 0 0 1 1 0 0 1 1 0 0
0 1 0 0 0 1 0 0 0 1 0 0 0 0
0 1 0 1 0 1 0 1 0 1 0 1 0 0
0 1 1 0 0 1 1 0 0 1 1 0 0 0
0 1 1 1 0 1 1 1 0 1 1 1 0 0
1 0 0 0 1 0 0 0 0 0 0 0 0 1
1 0 0 1 1 0 0 1 0 0 0 1 0 1
1 0 1 0 1 0 1 0 0 0 1 0 0 1
1 0 1 1 1 0 1 1 0 0 1 1 0 1
1 1 0 0 1 1 0 0 0 1 0 0 0 1
1 1 0 1 1 1 0 1 0 1 0 1 0 1
1 1 1 0 1 1 1 0 0 1 1 0 0 1
1 1 1 1 1 1 1 1 1 1 1 1 0 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1
Table Figure 3.1: Truth table for “4- bit ADDER” (a).
 9

Decimal BCD INPUT 1 BCE INPUT 2 CARRY CARRY OUTPUT

value (BCD SUM)
A3 A2 A1 AO B 3 B2 B1 B0 C¿ C OUT S3 S2 S1 S0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
2 0 0 0 1 0 0 0 1 0 0 0 0 1 0
4 0 0 1 0 0 0 1 0 0 0 0 1 0 0
6 0 0 1 1 0 0 1 1 0 0 0 1 1 0
8 0 1 0 0 0 1 0 0 0 0 1 0 0 0
10 0 1 0 1 0 1 0 1 0 1 1 0 1 0
12 0 1 1 0 0 1 1 0 0 1 0 0 1 0
14 0 1 1 1 0 1 1 1 0 1 0 1 0 0
16 1 0 0 0 1 0 0 0 0 1 0 1 1 0
18 1 0 0 1 1 0 0 1 0 1 0 0 1 0
And so on ….
Table Figure 3.3: Truth table for BCD Adder(b).

Selectio INPUT A INPUT B CAR OUTPUT (SUM) CARR

n line RY in Y out
0/1 A3 A2 A1 AO B3 B2 B1 B0 C¿ C OUT S3 S2 / S1 S0 / D0
/ / D2 /
Borrow D3 D1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 1 0 0 0 1 0 0 0 1 0 0
0 0 0 1 0 0 0 1 0 0 0 1 0 0 0
0 0 0 1 1 0 0 1 1 0 0 1 1 0 0
0 0 1 0 0 0 1 0 0 0 1 0 0 0 0
0 0 1 0 1 0 1 0 1 0 1 0 1 0 0
0 0 1 1 0 0 1 1 0 0 1 1 0 0 0
0 0 1 1 1 0 1 1 1 0 1 1 1 0 0
0 1 0 0 0 1 0 0 0 0 0 0 0 0 0
0 1 0 0 1 1 0 0 1 0 0 0 1 0 0
0 1 0 1 0 1 0 1 0 0 0 1 0 0 0
0 1 0 1 1 1 0 1 1 0 0 1 1 0 0
0 1 1 0 0 1 1 0 0 0 1 0 0 0 0
1 1 1 0 1 1 1 0 1 0 0 0 0 0 0
1 1 1 1 0 1 1 1 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1 1 1 0 0 0 0 1
1 1 1 1 1 1 1 1 1 1 0 0 0 0 1

Table Figure 3.3: Truth table for 4 bit Adder/Subtractor (c).

 10

Discussion

 In Task 1, Four-bit adder is designed, and result is verified as, when 0111 is added with
0111 then output I got is 1110 meaning 7+7 = 15. So, this correct. Other outputs also
obtained are correct. I also attached the result obtained when 4-bit inputs are added as a
array with second input and output also shown in array. That is figure 3.1(2).
 In 2nd task, BCD adder is implemented. I verified its results when input is 0010 (2decimal )
on both inputs then output is 0100(4 decimal ). So, this is also correct.
 In task 3, 4 bit adder/subtractor is designed, again I used same technique to verify my
result, I applied input 0111(7 decimal) on both inputs and got result 1110(14 decimal) when
selection line is 0 that is Cin is this case, that is 14 in decimal which is result of 7 plus 7
in decimal. But when selection line is 1 then output is 0 at all but Borrow is 1 that is
Cout in this case. For some other verifications I also added other inputs and their results
are also according to truth table.
 Note: I added ADDER/SUBTRACTOR truth table results in same table by differing
results with selection line.

Conclusion
All the results obtained are correct and exact according to the truth table.
 All the tasks performed, and their results or outputs are attached with their respective
section with proper labels. I did not attach the same entities of task 1 like OR gate, ANG
gate, XOR gate, HALF adder and FULL ADDER that reused again in task 2 and 3. These
entities are labeled as ‘commonly reused entities’ in top of tasks.
 All the tasks are implemented with structural VHDL technique.
 This method of programming enhances our code reusability and decrease the effort of
writing code again and again.
 In 4-bit adder, first half adder is implemented using entities, XOR gate and, AND GATE.
Then by using two half adders, I designed 1-bit full adder. After this, by joining four, 1-
bit adders, one 4-bit full adder is designed. This full adder is then reused in task 1,2 and
3.
 The truth table of task 2 is added shortly up to decimal value 18, as our concern and
objective is to design BCD adder and verify results from truth table.
 Truth table values and software stimulated results are exactly same.
 11

 All relevant material is attached above in report.