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Verilog HDL - Samir Palnitkar

This document is a guide to digital design and synthesis using Verilog HDL. It is authored by Samir Palnitkar and published by SunSoft Press in 1996. The document covers basic and advanced topics of Verilog HDL over three parts, including modeling concepts, gate-level modeling, behavioral modeling, and logic synthesis with Verilog HDL. It also includes appendices with additional reference material.

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Krisumraj Purkait
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348 views

Verilog HDL - Samir Palnitkar

This document is a guide to digital design and synthesis using Verilog HDL. It is authored by Samir Palnitkar and published by SunSoft Press in 1996. The document covers basic and advanced topics of Verilog HDL over three parts, including modeling concepts, gate-level modeling, behavioral modeling, and logic synthesis with Verilog HDL. It also includes appendices with additional reference material.

Uploaded by

Krisumraj Purkait
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Verilog HDL

A guide to Digital Design


and Synthesis

Samir Palnitkar

SunSoft Press
1996
PART 1 BASIC VERILOG TOPICS 1
1 Overview of Digital Design with Verilog HDL 3
2 Hierarchical Modeling Concepts 11
3 Basic Concepts 27
4 Modules and Ports 47
5 Gate-Level Modeling 61
6 Dataflow Modeling 85
7 Behavioral Modeling 115
8 Tasks and Functions 157
9 Useful Modeling Techniques 169
PART 2 Advance Verilog Topics 191
10 Timing and Delays 193
11 Switch- Level Modeling 213
12 User-Defined Primitives 229
13 Programming Language Interface 249
14 Logic Synthesis with Verilog HDL 275
PART3 APPENDICES 319
A Strength Modeling and Advanced Net Definitions 321
B List of PLI Rountines 327
C List of Keywords, System Tasks, and Compiler Directives 343
D Formal Syntax Definition 345
E Verilog Tidbits 363
F Verilog Examples 367
Verilog HDL
A guide to Digital Design
and Synthesis

Samir Palnitkar

SunSoft Press
1996
PART 1 BASIC VERILOG TOPICS 1
1 Overview of Digital Design with Verilog HDL 3
2 Hierarchical Modeling Concepts 11
3 Basic Concepts 27
4 Modules and Ports 47
5 Gate-Level Modeling 61
6 Dataflow Modeling 85
7 Behavioral Modeling 115
8 Tasks and Functions 157
9 Useful Modeling Techniques 169
PART 2 Advance Verilog Topics 191
10 Timing and Delays 193
11 Switch- Level Modeling 213
12 User-Defined Primitives 229
13 Programming Language Interface 249
14 Logic Synthesis with Verilog HDL 275
PART3 APPENDICES 319
A Strength Modeling and Advanced Net Definitions 321
B List of PLI Rountines 327
C List of Keywords, System Tasks, and Compiler Directives 343
D Formal Syntax Definition 345
E Verilog Tidbits 363
F Verilog Examples 367
Verilog HDL
A guide to Digital Design
and Synthesis

Samir Palnitkar

SunSoft Press
1996
PART 1 BASIC VERILOG TOPICS 1
1 Overview of Digital Design with Verilog HDL 3
2 Hierarchical Modeling Concepts 11
3 Basic Concepts 27
4 Modules and Ports 47
5 Gate-Level Modeling 61
6 Dataflow Modeling 85
7 Behavioral Modeling 115
8 Tasks and Functions 157
9 Useful Modeling Techniques 169
PART 2 Advance Verilog Topics 191
10 Timing and Delays 193
11 Switch- Level Modeling 213
12 User-Defined Primitives 229
13 Programming Language Interface 249
14 Logic Synthesis with Verilog HDL 275
PART3 APPENDICES 319
A Strength Modeling and Advanced Net Definitions 321
B List of PLI Rountines 327
C List of Keywords, System Tasks, and Compiler Directives 343
D Formal Syntax Definition 345
E Verilog Tidbits 363
F Verilog Examples 367

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