International Journal of Engineering, Management & Sciences (IJEMS)

ISSN-2348 3733, Volume-2, Issue-5, May 2015

Power Analysis of Si MOSFET and CNFET based

Logic Gates
Rishika Sethi, Gaurav Soni
 This leads to a lack of control over static leakage, short
Abstract- With the continuous trend of reducing feature size, channel effects and drain voltage induced barrier lowering
and employing continuously smaller components on [9]. In order to sustain Moore s law and to ensure further
integrated circuits, new challenges arises on the way of improvements in performance of field effect transistors and
silicon CMOS circuits and devices. Emerging nanodevices
promise the possibility of increased integration density and
interconnects, it is necessary to look for an alternative of
reduced power consumption. The emerging devices, partially MOSFETs and Copper interconnects. CNTs are considered
due to their extremely small dimensions, show large variations as most promising candidate for future CMOS circuits and
in their behavior. The variation shown by these devices affects interconnect because of their superior performance and size
their reliability and the performance of circuits made from advantage [6].
them. After aggressive scaling, the bulk Complementary Metal
Oxide Semiconductor (CMOS) technology is facing numerous
challenges which have motivated the researchers to concentrate
II. STRUCTURE OF NANOTUBES
for other promising devices. Carbon Nanotubes with their
superior properties, high thermal conductivities and high A. Carbon nanotube
current drivability has emerged out as a potential alternative
device to the bulk CMOS technology. Initially we have analyzed CNTs are considered as most promising candidate for
the key performance of a Carbon Nanotube Field Effect future CMOS circuits and interconnect because of their
Transistor (CNFET) based inverter and NAND Gate and superior performance and size advantage. A CNT is a hollow
compared it with the CMOS for 32nm technology node. Both
the inverters and NAND Gate are simulated in HSPICE
cylinder constructed by rolling up a sheet of graphene.
platform and the results show improved performance of CNFET Graphene is a single atomic layer of graphite which in turn is
inverter and NAND gate in terms of power in comparison to a crystalline form of carbon [6].
CMOS inverter and NAND Gate.
B. Chirality
Index Terms : CNFET, nanodevices, CMOS
The term chirality is used to classify the physical and
I. INTRODUCTION electronic structure of carbon nanotubes. Chirality is used to
describe the reflection symmetry between an object and its
Silicon device scaling in future faces limitations. As the
mirror image. A chiral object is an object that is not
silicon industry moves into the 45nm node and beyond,
superimposable on its mirror image. CNTs that are
increasing technology challenges will be imposed by silicon
superimposable on their mirror images are classified as A
CMOS device scaling. Among the most important obstacles
chiral CNTs. Achiral CNTs are further classified as:[6]
against further device scaling is the performance variation
introduced by increased process variations as feature sizes
1. Armchair CNTs (n=m)
shrink and the standby power dissipation Signal Transmission
2. Zigzag CNTs (n=0 or m=0)
in Interconnect. Increased device density and device
parametric variation, rising sub-threshold leakage current and CNTs that are not superimposable on their mirror images are
gate tunnelling current and higher device temperatures all classified a Chiral CNTs. The circumferential edge shape of
contribute to the power problem. As CMOS approaches the different types of CNTs is shown in the fig.1
25nm node, stochastic threshold variation caused by dopant
implant position in ultra-small inversion regions will give rise
to more than 100mV of threshold variation. The timing
behaviour of devices is also greatly affected by spatial and
temporal process parameter tolerance and voltage and
temperature variation. Continued channel length reduction is
prevented by the limitation to reduce gate insulator thickness.

Manuscript received February 20, 2015.

Rishika Sethi, Department of Electronics & Communication, Poornima Figure 1: Carbon Nanotube types: A-Armchair; B-Zig-Zag; C-Chiral [6].
University, Jaipur, India, (e-mail: [email protected]).
Gaurav Soni, Department of Electronics & Communication, Poornima
University, Jaipur, India, (e-mail: [email protected]).

40 www.alliedjournals.com
 Power Analysis of Si MOSFET and CNFET based Logic Gates

 We can again make use of the established CMOS

C. Single walled and Multiwalled Nanotubes design infrastructure and CMOS fabrication
process.
Carbon nanotubes can be single walled or multi walled  CNFETs have the excellent experimentally
depending upon the number of shells forming the tubular demonstrated device current carrying ability
structure. Single walled carbon nanotubes consist of single
grapheme cylinder which can be either metallic To explore the role of CNTFETs in future integrated circuits
semiconducting in nature. Multiwalled nanotubes (MWNTs) (ICs), their performance should be evaluated and compared it
consist of concentric CNT cylinders which are held together with the metal oxide semiconductor field-effect transistor
by Vander Waals forces. They contain both metallic and (MOSFET). Stanford University have developed a compact
semiconducting cylinders. Presence of metallic tubes negates model that can be used to investigate the performances of
the semiconducting properties of the shells and hence carbon nanotube field-effect transistors (CNTFETs). This
MWNTs are usually avoided in electronics industry. model accounts for practical issues such as scattering in the
Elimination of the outermost shells is possible by passing channel, electron-electron interactions, effects of
huge amount of current down the outershells causing the source/drain extension regions, and charge screening.
breakdown of the shells. The Multi-Wall Carbon Nanotubes
(MWCNTs) or Single Wall Carbon Nanotubes (SWCNTs) as
shown in fig III. ADVANTAGES OF CNFETS OVER TRADITIONAL
2 [31]. MOSFETS

The advantages of CNFETs making them ideal for nanoscale

applications now can be easily recognized.

 One-dimensional carbon nanotube acting as

channel reduces the scattering probability and
offers ballistic transport resulting in high-speed
devices.
 The nanotube conducts essentially on its surface
Figure 2: Structure of SWCNT (A) and MWCNT (B) [31] where no dangling bonds forming interface states
are present. Hence, there is no need for
D. Carbon nanotube field effect transistor careful passivation of the interface between the
nanotube channel and the gate dielectric.
CNTFET is the only field effect transistor that is projected to  CNFET consumes less power than an equivalent Si
outperform the 11nm node ITRS target. CNTFETs intrinsic device.
delay (CV/I) is very low. They show higher electron mobility  It has an ability to carry large current. CNTs can
compared to bulk silicon and provide better power-delay carry current density of the order 10 µA/nm
product. They possess excellent electrical properties such as  Current levels in CNFET donot depend on channel
high speed, compatibility with high-k dielectric layer, reduced length. Hence no channel length minimization
short channel effects (SCEs). Moreover CMOS circuit blocks probl
em.
can be realized using CNTFETs since their operation
 NCNFETs and PCNFETs are symmetrical which is
principle is similar. The schematic of CNFET is shown in fig
ideal for CMOS structures [31]
3 [31].
All these unique properties suggest that CNFETs have
potential to be a successful replacement of MOSFETS in
nanoscale devices [31].

IV. PARAMETERS REQUIRED

A. Chirality

The chirality of carbon nanotube is defined using the

Figure 3: CNFET cross section [9] vector C (the roll-up direction). The vector C is a
combination of lattice vectors a1 and a2. It connects any
Carbon nanotube field effect transistor (CNTFET) is the best two primitive lattice points of grapheme such that when
promising technology to replace the existing silicon folded into a nanotube the two points are
technology due to following reasons: indistinguishable [6] .

 The operation principle and structure of devices

are similar to CMOS devices.  Where (n, m) are pair of integers known as the chiral

41 www.alliedjournals.com
 International Journal of Engineering, Management & Sciences (IJEMS)
ISSN-2348 3733, Volume-2, Issue-5, May 2015

indices. the vector C is given as [6]: and read port with 8 transistors. From HSPICE simulation, the
authors have found the proposed technique saves dynamic
C=3 +3 = (3, 3) power by reducing discharging frequency during write
operation. Compared to 6T SRAM structure, the proposed 8T
 Chiral a n g l e ( ) d e s c r i b e s t h e t i l t a n g l e o f SRAM saves power up to 48% and obtains 56% wider SNM
the hexagons with respect to the tubular axis. It is the during read operation at the minimal cost of 2% leakage
angle between the chiral vector C and the primitive power and 3% delay increase. Finally authors have concluded
lattice vector a1 [6]. that 3~7 times less dynamic power consumption, 11~17 times
less leakage power consumption, 5~6 times faster read and
write operations, and 1.6 wider SNM than the conventional
designs[39].
 Translational vector (T) defines the periodicity of the
lattice along the tubular axis. It is the smallest graphene [Sheng Lin,et-al, 2010] proposed a highly stable and
lattice vector perpendicular to C. It can be computed low-power 6T static RAM (SRAM) cell using carbon
from the othogonality condition [6]. nanotube FETs that utilizes different threshold voltages for
best performance. In the proposed SRAM cell, n-type and p-
C.T=0 type transistors have different chiralities, that means a dual-
B. Diameter of CNT which is best to replace silicon in nanoscaled transistors. They
presented the design of the concept addressing the realistic
Depending o n their band gap, the CNTs are either
design challenges and issues such as performance, static noise
metallic or semiconducting. The band-gap of a carbon
margin (SNM), power consumption, and tolerance to process,
nanotube is inversely proportional to its diameter. The
power supply voltage, and temperature (PVT) variations. The
diameter of the CNT is determined by the chiral indices
results obtained From H-Spice Simulations that the SPR of
(n, m) as [6]:
the CNTFET 6T SRAM cell is four times higher than its
CMOS counterpart, hence attaining low power, high stability,
and low delay within the comprehensive metric provided by
= the SPR under write conditions. Finally authors have
concluded that the proposed dual-diameter CNTFET SRAM
cell has a better SPR under write operation than its CMOS
Here, a is lattice constant of grapheme (0.246 nm) counterpart cell and has significant lower sensitivity to PVT
variations [34].
C. Threshold Voltage of CNT
[Anuj Pushkama, et-al, 2010] has presented the MOSFET
In CNTFETs, the threshold voltage of the transistor like CNTFET based 6T SRAM design. The authors have
is established by the diameter of the CNT. Therefore a studied about both Si MOSFET and CNTFET, they have
multiple threshold design can be achieved by employing found that Carbon Nano Tubes(CNTs) have immense
CNTs with different diameters in the CNTFET. The potential in dictating the future VLSI devices due to their
threshold voltage of CNTFET is determined by the great electrical, thermal properties, high mechanical
CNT diameter as [6]: stability, current carrying capacity and later's
electromigration concerns at high temperature. The SRAM
design uses the smallest transistors possible and is also
susceptible to reliability issues and process variation, making
Here V is carbon to bond energy (3.033 e V), it an ideal benchmark circuit to compare the two technologies.
DCNT is diameter of CNT, q is electronic Authors have used HSPICE to simulate the structure of the
charge SRAM designs implemented by using 16nm CMOS
technology nodes and Stanford University CNTFET. The
results showed that there is a 52.7% increase in SNM of the
V.CNFET CIRCUITS USED BY THE RESEARCHERS memory cell. Meanwhile, the cell becomes 5% faster. Finally
authors have concluded that NTFET is more suitable for
[Young Bok Kim, et-al, 2008] has proposed a new 8T circuit design rather than MOSFETs [29]
SRAM based on CNFET and also compared the performance
of CMOS, FinFET and CNT based 6T and 8T SRAM. The [N.Somorjit Singh, et-al, 2013] has presented the
authors have reviewed many research papers on CMOS, MOSFET like CNTFET based 3T and 4T based DRAM
FinFET and CNFET, then they have observed that Carbon design. After study Si MOSFET and CNTFET, authors have
nanotube have superior properties, high thermal found that Carbon Nano Tubes(CNTs) have better potential in
conductivities, and high current handling capacities, which dictating the future VLSI devices due to their great electrical,
proved it to be a promising alternative device to the thermal properties, high mechanical stability, current carrying
conventional CMOS. The new SRAM cell cuts off the capacity and later's electromigration concerns at high
feedback connection between the two back-to-back inverters temperature. The operation of the three-transistor DRAM cell
in the SRAM cell when data is written and separates the write and its peripheral circuitry is based on a two-phase

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 Power Analysis of Si MOSFET and CNFET based Logic Gates

nonoverlapping clock scheme. All "data read" and "data

write" operations are performed during the active 2 phase,
i.e., when PC is low. Authors have used HSPICE to
simulate the structure of the DRAM designs implemented
by using Berkely- 32nm PTM technology nodes and
Circuit Parameters Results
CNTFET Parameter by Stanford University. The results Table 1: Circuits, and parameters used by the researcher
showed that the power dissipation, leakages power is better
Channel length =32nm  3-7 times less dynamic
performance in 3T DRAM CNTFET than 4T DRAM, but
delay has comparatively less delay time in 4T DRAM [27]. Chirality-(19,0), power Consumption
Pitch =10nm  11-17 times less
[Shimaa I. Sayed, et-al, 2013] have compared the leakage power
performance of basic logic gates using CMOS and pure VFbn, VFbp=0.0ev Consumption,
CNFET with hybrid configurations. Authors have reviewed MFP =200nm  5-6 times faster read
many research papers and observed that Carbon nanotube and Write Operation
Power supply =0.9
(CNT) based technology has significant potential to replace than CMOS design
silicon technology. Single-walled carbon nanotubes sensing
circuits due to their superior transport properties and CMOS room temperature
(complementary metal oxide semiconductor) technology is Channel length  It becomes 5% faster
CNFET
better in switching speed specially for NMOS. So the authors based 6T
=32nm
technology node= than Si MOSFET.
have take advantage of the high mobility transport in p-type SRAM 16nm CMOS % INCREASE
CNTFETs and combine them with high-performance Cell Pitch =4 nm OF SNM in the
conventional n-type MOSFETs, and achieved the best overall [39],[29], memory cell.
[34] VFbn, VFbp=0.0ev
performance in a hybrid configuration. From HSPICE 
Simulation results shown that the performance of the hybrid MFP =200nm
PCNFET-NMOS configuration is better than that of the pure Power supply =0.9
CMOS in terms of noise margin (32.8% higher) and power Dcnt= 1.2 to 1.8nm
consumption (60% lower) and therefore (2.5% lower )in PDP. work function cnt=
The performance of PCNFET-NMOS is the same of pure 4.5ev
CNFET for noise margin, 65% lower in power consumption Channel length =32nm
and 2% lower in PDP. Finally authors have concluded that the Chirality-(16, 19, 0)  Significant
proposed Hybrid1 has the best overall performance in Vth= 289mv improvement in power
designing logic circuits [35]. consumption and area
SNM=206.3mv
.
[Priyanka Saha, et-al, 2014] has have presented a Power supply =0.9
comparative circuit level analysis between conventional C room temperature
MOS, fully depleted SOI/SON and CNFET devices. The Vdd= 0.9V
authors have reviewed several research papers and found that Vth= 0.293 volt
due to scaling theory, bulk silicon device technology faced the
power explosion of chips so the authors have used future Diameter= 1.487V  It consumes less power
devices like SOI/SON/CNFET, for developing a power Chirality=(19.0) than CMOS.
efficient, high performance 4x4 1T DRAM cell array. In the Channel length =
4x4 1T DRAM cell array memory organizations have CNFET 32nm
memory cell arrays with sense amplifiers and column/row based N=10, S= 20 nm
decoders are present. Any data can be read from or written Inverter, Vdd= 0.9V
into the cell array by proper selection of row and column NAND
Vth= 0.293 volt
gate, XOR
address. The word line (WL) acts as the horizontal select line gate [7][35] Diameter= 1.487V
that enables single row of cells depending upon the row Chirality=(19,0)  It shows reduction in
decoder input whereas the bitline is used to connect the cells dynamic power
Channel length =
in a single column to I/O circuit. From HSPICE Simulation 32nm Consumption and
results, the analysis shows an improvement of 41% for SOI, better PDP
N=10, S= 20 nm
49.9% for SON and 54.9% for CNFET circuits in terms of PMOS:NMOS=2:1
average power consumption. From concerning average delay (W/L ratio)
the result gives an effective improvement of 43.9% for SOI, technology node 32nm
55.35% for SON and 70.16% for CNFET circuits compared
to MOSFET circuits. Finally authors have concluded that Chirality=(19.0)
CNFET based 1T DRAM cell array is the much better Vth= 0.293 volt
option and the most advantageous in terms of performance Diameter= 1.487V
parameters [33].
Channel length =
VI. CNFET CIRCUITS, PARAMETERS AND RESULTS 32nm

The table 1 shows the description of CNFET based Circuits,

parameters used by the various researchers respeectively with
their results.

43 www.alliedjournals.com
 International Journal of Engineering, Management & Sciences (IJEMS)
ISSN-2348 3733, Volume-2, Issue-5, May 2015

Chirality=(19,0) An experiment of Si MOSFETbased Inverter is performed by

using HSPICE. The input / output characteristics obtained is
Pitch=30nm
 Power Dissipation, shown in Figure. 4. The supply voltages considered for the
(Tox) = 4.0nm Leakages Power Is experimentation are 0.9V for 32nm technology. The input is
Less In 3t Dram taken in the form of a pulse and output of the Si MOSFET
(Vfbn) = 0.0ev Cntfet Than 4t based inverter circuit is shown in figure above. The output
Dram. waveform is simulated under the process of transient analysis
(Lceff) = 200.0nm  But Delay Time Is at 32nm technology
Less
Mfp In P+/N+ Doped
CNFET In 4t Dram.
Cnt = 15.0nm
Based 3t Cnt Work Function =
And 4t 4.5ev.
Dram
Vdd= 0.9v  The Average
[27],[33]
Chirality=(19.0) Delay Is
Vth= 0.293 Volt Improvement Of
43.9% For Soi,M
Diameter= 1.487v
55.35% For Son And
Channel Length = N 70.16% For Cnfet
32nm Circuits Compared To
Mosfet Circuits.

Figure 4: Transient Response of Si MOSFET based Inverter

VII. SIMULATION AND RESULTS An experiment of CNFET Tbased Inverter is performed by

using HSPICE. The input / output characteristics obtained
The below Table 2 shows that CNFET and Si MOSFET is shown in Figure. 5. The supply voltages considered for
Parameters which was used in the HSPICE simulation of the experimentation are 0.9V for 32nm technology. The
nverter and NAND Gate. This parameters was extracted from input is taken in the form of a pulse and output of the
ITRS [13] and M.tech. Thes is [6]. CNFET based inverter circuit is shown in figure above. The
output waveform is simulated under the process of transient
Table 2: CNFET & Si MOSFET Circuit s parameter analysis at 32nm technology

Si
S. CNFET
MOSFET Value Value
No parameter
parameter

Technology Channel
1 32nm 32nm
node Length

2 Vdd 0.9V Vdd 0.9V

W&L L=32nm
3 (n1,n2) (19,0)
(NMOS) W= 64nm

W&L L=32nm
4 DCNT 1.487nm
(PMOS) W= 192nm Figure 5: Transient Response of CNFET based Inverter
Average power obtained is shown in below
Load Table:
5 20fF Vth 0.293V
capacitance Average Power
S. Technology from=
6 Pitch 20nm Device
No node 0.0000E+00 to=
1.2000E-08
No. of
7 3 Si MOSFET
Tubes 1 32nm 8.5964E-07 Watt
Note: All the values are taken from M.tech Thesis and ITRS [ Inverter
13]. CNFET
2 32nm 8.0742E-09 Watt
Inverter

 Si MOSFETand CNFET based Inverter

 Si MOSFETand CNFET based NAND Gate

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 Power Analysis of Si MOSFET and CNFET based Logic Gates

Average power obtained is shown in below Table :

An experiment of Si MOSFET based NAND Gate is
performed by using HSPICE. The input / output Average Power
characteristics obtained is shown in Figure. 6. The supply Technology from=
voltages considered for the experimentation are 0.9V for Device
node 0.0000E+00 to=
32nm technology. The input is taken in the form of a 1.2000E-08
pulse and output of the Si MOSFET based NAND Gate
circuit is shown in figure above. The output waveform is Si MOSFET
32nm
simulated under the process of transient analysis at 32nm NAND Gate 2.9983E-07 Watt
technology. CNFET
32nm 1.1003E-08 Watt
NAND Gate

VIII. CONCLUSION

This Paper investigated the performance of the CNTFET

technology based Inverter and NAND Gate and compared it
with the existing silicon MOSFET technology using
HSPICE. Simulation results have shown that CNT
technology offer low power performance. Thus the
performance analysis of CNFETs and its comparative
studies show that it can obviously be a viable option
for future and superior technology for applications to
circuit designs. Thus a replacement of traditional MOSFET
technology as they are emerging as excellent candidates for
building highly energy- efficient future electronic systems.

ACKNOWLEDGMENT

I would like to express my deep gratitude and thanks to Prof.

Figure.6: Transient Response of Si MOSFET based NAND Mahesh Bundele (Coordinator, Research), Poornima
Gate University for giving me an opportunity to work under his
guidance for review of research papers and his consistent
An experiment of CNFET based NAND Gate is performed motivation & direction in this regard. I would also express my
by using HSPICE. The input / output characteristics sincere thanks to Mr. Gaurav Soni (Asst.Professor, ECE),
obtained is shown in Figure.7. The supply voltages Poornima University for their guidance and support
considered for the experimentation are 0.6V for 32nm
technology. The input is taken in the form of a pulse and REFERENCES
output of the CNFET based NAND Gate circuit is shown in [1]. Aswatha, A.R., Basavaraju, T. (2008). "Faster delay modeling and
figure below. The output waveform is simulated under the power optimization for on-chip global interconnects",
Semiconductor Electronics, ICSE 2008. IEEE International
process of transient analysis at 32nm technology.
Conference on , 82-86.
[2] Coulibaly, L.M., Kadim, H.J. (2004). "Analytical ramp delay model
for distributed on-chip RLC interconnects", Circuits and Systems.
MWSCAS '04. The 47th Midwest Symposium on , 1, 457-460.
[3] Das, D., Rahaman, H.(2011). "Analysis of Crosstalk in Single- and
Multiwall Carbon Nanotube Interconnects and Its Impact on Gate
Oxide Reliability", Nanotechnology, IEEE Transactions on , 10 (6),
1362-1370.
[4] Datta, M., Sahoo, S., Kar, R.(2011). "Bandwidth Modeling for
Distributed On - Chip RLCG Interconnect Considering Coupling
Effects", Devices and Communications International Conference on
, 1-5.
[5] Feng Shi, Xuebin Wu, Zhiyuan Yan (2014). "Improved Analytical
Delay Models for RC-Coupled Interconnects", Very Large Scale
Integration Systems, IEEE Transactions on , 22(7), 1639-1644.
[6] Gaurav Soni (2013). Performance evaluation of Carbon Nanotube
based devices and circuits for VLSI design , M.Tech. Thesis,
Department of Electronics and Communication Engineering,
Malaviya National Institute of Technology Jaipur.
[7] Geunho Cho, Yong-Bin Kim, Lombardi, F., Minsu Choi (2009).
"Performance evaluation of CNFET-based logic gates",
Instrumentation and Measurement Technology Conference
I2MTC '09. IEEE, 909-912.
[8] Halder, A., Maheshwari, V., Goyal, A., Kar, R.; Mandal, D.,
Figure 7: Transient Response of CNFET based NAND Gate Bhattacharjee, A.K.(2012). "Moment based delay modelling for
on-chip RC global VLSI interconnect for unit ramp input",
Computer Science and Software Engineering (JCSSE)
International Joint Conference on , 164-167.
[9] Hamed Shahidipour(2012). A Study on the Effects Of Variability
On Performance Of CNFET Based Digital Circuits , Ph.D. thesis,
School of Electronics and Computer Science, University Of

45 www.alliedjournals.com
 International Journal of Engineering, Management & Sciences (IJEMS)
ISSN-2348 3733, Volume-2, Issue-5, May 2015

Southampton.
[10] Hong Li, Wen-Yan Yin, Banerjee, K., Jun-Fa Mao (2008). "Circuit
Modeling and Performance Analysis of Multi-Walled Carbon
Nanotube Interconnects," Electron Devices, IEEE Transactions on,
55(6), 1328- 1337.
[11] https://nano.stanford.edu/stanford-cnfet-model
[12] http://www.sr.bham.ac.uk/yr4pasr/project06/GT/CNT.html.
[13] Jie Deng (2007). Device Modeling and circuit performance
evaluation for nanoscale devices: Silicon technology beyond 45nm
node and carbon nanotube field effect transistors , Ph.D. thesis,
Department of Electrical Engineering, Stanford University, Stanford.
[14] Jun Yong Shin, Dutt, N., Kurdahi, F. (2013). "Vision-inspired
global routing for enhanced performance and reliability"
Quality Electronic Design (ISQED), 2013 14th International
Symposium on, 239-244.
[15] Kar, R., Maheshwari, V., Agarwal, V., Choudhary, A., Singh, A.
Mai, A.K., Bhattacharjee, A.K. (2010). "Accurate estimation of
on-chip global RLC interconnect delay for step input", Computer
and Communication Technology (ICCCT), International
Conference on , .673-677.
[16] Kar, R., Maheshwari, V., Choudhary, A., Singh, A. (2010). "Modeling
of on-chip global RLCG interconnect delay for step input",
Computer and Communication Technology (ICCCT), 2010
International Conference on , 318-,323.
[17] Kavicharan, M., Murthy, N.S., Rao, N.B. (2013). "An efficient delay
estimation model for high speed VLSI interconnects", Advances
in Computing, Communications and Informatics (ICACCI), 2013
International Conference on , 1358-1362.
[18] Majumder, M.K. , Pandya, N.D. Kaushik, B.K., Manhas, S.K.
(2012). "Analysis of MWCNT and Bundled SWCNT Interconnects:
Impact on Crosstalk and Area", Electron Device Letters, IEEE,
33(8), 1180- 1182.

Rishika Sethi, received the bachelor degree in Electronics and

Communication Engineering from Govt. Engineering College, Jhalawar
(Rajasthan). She is currently working as Research scholar at Poornima
University. Her area of interest is Carbon Nanotube.
Gaurav Soni, Presently working as Head of Department- Department of
Electronics & Communication Engineering and Department of Electrical
Engineering at Poornima University, Jaipur. He is having an experience of
seven years. His area of interest includes Electromagnetic field theory,
Electronic devices and circuits, Network on Chip (NOC), Nanoelectronics
and Bioelectronics. He has authored a book titled Radar & TV Engineering

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