COMPUTER ORGANIZATION AND ARCHITECTURE 18EC35

MODULE 3: INPUT/OUTPUT ORGANIZATION

INTRODUCTION

Input/output architecture is a interface to the outside world that provide systematic means of
controlling interaction with outside world. Input device such as keyboard, scanner, digital camera, etc.
Output devices such as display, printer etc.Input/output devices cannot directly connect to the system bus
because Data transfer rate of input/output devices is slower than (memory & processor) and verse versa.
Input/output devices are used different data format and word length.

3.1 ACCESSING I/O-DEVICE

• A single bus-structure can be used for connecting I/O-devices to a computer (Figure7.1).

• Each I/O device is assigned a unique set ofaddress.
• Bus consists of 3 sets of lines to carry address, data & controlsignals.
• Each IO devices is assigned with unique set of addresses
• When processor places an address on address-lines, the intended-device responds to thecommand
using control signal line.
• The processor requests either a read orwrite-operation.
• The requested-data are transferred over thedata-lines.

• There are 2 ways to deal with I/O-devices: 1) Memory-mapped I/O & 2) I/O-mappedI/O.
1) Memory-MappedI/O
 Memory and I/O-devices share a commonaddress-space.
 Any data-transfer instruction (like Move, Load) can be used to exchangeinformation.
 Forexample,
Move DATAIN, R0; This instruction sends the contents of location DATAIN to register R0.
Here, DATAIN address of the input-buffer of the keyboard.
2) I/O-MappedI/O
 Memory and I/0 address-spaces aredifferent.
 A special instructions named IN and OUT are used fordata-transfer.
Ex: Processor in Intel family.
 Advantage of separate I/O space: I/O-devices deal with feweraddress-lines.
I/O Interface for an Input Device
1) Address Decoder: enables the device to recognize its address when this address
appears on the address-lines (Figure7.2).
2) Status Register: contains information relevant to operation ofI/O-device.
3) Data Register: holds data being transferred to or from processor. There are 2types:
i) DATAIN Input-buffer associated withkeyboard.
ii) DATAOUT Output data buffer of adisplay/printer.
 Both data and status register are connected to the data bus and assigned unique address.
 The address decoder, the data and status register and the control circuitry required to coordinate
I/O transfers constitute the device’s interface circuit.

Dept. of ECE, ATMECE, Mysuru Page 1

 COMPUTER ORGANIZATION AND ARCHITECTURE 18EC35

MECHANISMS USED FOR INTERFACING I/O-DEVICES

1) Program ControlledI/O
• Processor repeatedly checks status-flag to achieve required synchronization b/w processor & I/O
device. (We say that the processor polls thedevice).
• Maindrawback:
The processor wastes time in checking status of device before actual data-transfer takes place.
2) InterruptI/O
• I/O-device initiates the action instead of theprocessor.
• I/O-device sends an INTR signal over bus whenever it is ready for a data-transferoperation.
• Like this, required synchronization is done between processor & I/Odevice.
3) Direct Memory Access(DMA)
• Device-interface transfer data directly to/from the memory w/o continuous involvement by the
processor.
• DMA is a technique used for high speedI/O-device.

3.2 INTERRUPTS
• There are many situations where other tasks can be performed while waiting for an I/O device to
becomeready.
• A hardware signal called an Interrupt will alert the processor when an I/O device becomesready.
• Interrupt-signal is sent on the interrupt-requestline.
• The processor can be performing its own task without the need to continuously check theI/O-device.
• The routine executed in response to an interrupt-request is calledISR.
• The processor must inform the device that its request has been recognized by sending INTA
signal. (INTR Interrupt Request, INTA Interrupt Acknowledge, ISR Interrupt
ServiceRoutine)
• For example, consider COMPUTE and PRINT routines (Figure3.6).

Dept. of ECE, ATMECE, Mysuru Page 2

 COMPUTER ORGANIZATION AND ARCHITECTURE 18EC35

Assume that an interrupt request arrives during execution of instruction i in Fig 3.6
• The processor first completes the execution of instructioni.
• Then, processor loads the PC with the address of the first instruction of theISR (interrupt service
routine).
• After the execution of ISR, the processor has to come back to instructioni+1.
• Therefore, when an interrupt occurs, the current content of PC is put in temporary storagelocation.
• A return at the end of ISR reloads the PC from that temporary storagelocation.
• This causes the execution to resume at instructioni+1.
• When processor is handling interrupts, it must inform device that its request has beenrecognized.
• This may be accomplished by special control signal on bus. An interrupt-acknowledge signal is used
• The task of saving and restoring the information can be done automatically by theprocessor or by
program instruction.
• Saving and restoring registers involves memory transfers:
• Increases the total execution time.
• Increases the delay between the time an interrupt request is received, and the start of execution of
the interrupt-service routine. This delay is called interrupt latency.
• In order to reduce the interrupt latency, most processors save only the minimal amount of
information:
• This minimal amount of information includes Program Counter and processor status registers.
• Any additional information that must be saved, must be saved explicitly by the program instructions
at the beginning of the interrupt service routine.

• Interrupt Latency is a delaybetween

→ time an interrupt-request is received and
→ start of the execution of the ISR.

Difference between Subroutine & ISR

Subroutine ISR
A subroutine performs a function required by the ISR may not have anything in common with
program from which it is called. program being executed at time INTR is received
Subroutine is just a linkage of 2 or more function Interrupt is a mechanism for coordinating I/O
related to each other. transfers.

3.2.1 INTERRUPT HARDWARE

• Most computers have several I/O devices that can request aninterrupt.
• A single interrupt-request (IR) line may be used to serve n devices (Figure4.6).
• All devices are connected to IR line via switches toground.
• To request an interrupt, a device closes its associatedswitch.
• Thus, if all IR signals are inactive, the voltage on the IR line will be equal toV dd.
• When a device requests an interrupt, the voltage on the line drops to0.
• This causes the INTR received by the processor to go to1.
• The value of INTR is the logical OR of the requests from individualdevices.
INTR=INTR1+ INTR2+ . . . . . +INTRn
• A special gates known as open-collector or open-drain are used to drive the INTRline.
• The Output of the open collector control is equal to a switch to the ground thatis
→ open when gates input is in ”0‟ state and
→ closed when the gates input is in “1‟ state.
• Resistor R is called a Pull-up Resistorbecause
it pulls the line voltage up to the high-voltage state when the switches are open.

Dept. of ECE, ATMECE, Mysuru Page 3

 COMPUTER ORGANIZATION AND ARCHITECTURE 18EC35

3.2.2 ENABLING & DISABLING INTERRUPTS

All computers fundamentally should be able to enable and disable interruptions asdesired.
 Processors generally provide the ability to enable and disable such interruptions as desired.
The problem of infinite loop occurs due to successive interruptions of active INTRsignals.
There are 3 mechanisms to solve problem of infiniteloop:

1) Processor should ignore the interrupts until execution of first instruction of theISR by the
processor hardware.
 By using an Interrupt-disable instruction as the first instruction in the interrupt-service
routine, the programmer can ensure that no further interruptions will occur until an
Interrupt-enable instruction is executed. Typically, the Interrupt-enable instruction will
be the last instruction in the interrupt-service routine before the Returnfrom-interrupt
instruction.

2) Processor should automatically disable interrupts before starting the execution of theISR.
 The second option, which is suitable for a simple processor with only one interrupt-
request line, is to have the processor automatically disable interrupts before starting
the execution of the interrupt-service routine. After saving the contents of the PC Dept
of CSE,SJBIT Page 64 INTR , to name the interrupt-request COMPUTER ORGANIZATION
10CS46 and the processor status register (PS) on the stack, the processor performs the
equivalent of executing an Interrupt-disable instruction. It is often the case that one bit
in the PS register, called Interrupt-enable, indicates whether interrupts are enabled.

3) In the third option, the processor has a special interrupt-request line for which the interrupt-
handling circuit responds only to the leading edge of the signal. Such a line is said to be edge-
triggered.

Sequence of events involved in handling aninterrupt-request:

1) The device raises aninterrupt-request.
2) The processor interrupts the program currently beingexecuted.
3) Interrupts are disabled by changing the control bits in the processor status register(PS).
4) The device is informed that its request has beenrecognized.
In response, the device deactivates the interrupt-request signal.
5) The action requested by the interrupt is performed by the interrupt-serviceroutine.
6) Interrupts are enabled and execution of the interrupted program is resumed.

Dept. of ECE, ATMECE, Mysuru Page 4

 COMPUTER ORGANIZATION AND ARCHITECTURE 18EC35

3.2.3 HANDLING MULTIPLE DEVICES

• While handling multiple devices, the issues concernedare:
1) How can the processor recognize the device requesting aninterrupt?
2) How can the processor obtain the starting address of the appropriateISR?
3) Should a device be allowed to interrupt the processor while another interrupt is being
serviced?
4) How should 2 or more simultaneous interrupt-requests behandled?
When a request is received over the common interrupt-request line, additional information is needed to
identify the particular device that activated the line.
The information needed to determine whether a device is requesting an interrupt is available in its
status register. When a device raises an interrupt request, it sets to 1 one of the bits in its status register,
which we will call the IRQ bit.
2 methods to handle multiple devices are:
1. Polling
2. Vectored Interrupts
POLLING
• Information needed to determine whether device is requesting interrupt is available instatus-register
• Following condition-codes areused:
 DIRQ Interrupt-request fordisplay.
 KIRQ Interrupt-request forkeyboard.
 KEN keyboardenable.
 DEN DisplayEnable.
 SIN, SOUT statusflags.
• For an input device, SIN status flag inused.
SIN = 1 when a character is entered at the keyboard.
SIN = 0 when the character is read by processor.
IRQ=1 when a device raises an interrupt-requests (Figure 4.3).
• Simplest way to identify interrupting-device is to have ISR poll all devices connected tobus.
• The first device encountered with its IRQ bit set isserviced.
• After servicing first device, next requests may beserviced.
• Advantage: Simple & easy toimplement.
Disadvantage: More time spent polling IRQ bits of all devices.

Dept. of ECE, ATMECE, Mysuru Page 5

 COMPUTER ORGANIZATION AND ARCHITECTURE 18EC35

VECTORED INTERRUPTS
• A device requesting an interrupt identifies itself by sending a special-code to processor overbus.
• Then, the processor starts executing theISR.
• The special-code indicates starting-address ofISR.
• The special-code length ranges from 4 to 8bits.
• The location pointed to by the interrupting-device is used to store the staring address toISR.
• The staring address to ISR is called the interruptvector.
• Processor
→ loads interrupt-vector into PC &
→ executes appropriate ISR.
• When processor is ready to receive interrupt-vector code, it activates INTAline.
• Then, I/O-device responds by sending its interrupt-vector code & turning off the INTRsignal.
• The interrupt vector also includes a new value for the Processor StatusRegister.

INTERRUPT NESTING
Interrupts should be disabled during the execution of an interrupt-service routine, to ensure that a
request from one device will not cause more than one interruption. The same arrangement is often
used when several devices are involved, in which case execution of a given interrupt-service routine,
once started, always continues to completion before the processor accepts an interrupt request from a
second device. Interrupt-service routines are typically short, and the delay they may cause is
acceptable for most simple devices
• A multiple-priority scheme is implemented by using separate INTR & INTA lines for eachdevice
• Each INTR line is assigned a different priority-level (Figure4.7).
• Priority-level of processor is the priority of program that is currently beingexecuted.
• Processor accepts interrupts only from devices that have higher-priority than itsown.
• At the time of execution of ISR for some device, priority of processor is raised to that of thedevice.
• Thus, interrupts from devices at the same level of priority or lower aredisabled.
Privileged Instruction
• Processor's priority is encoded in a few bits of PS word. (PS Processor-Status).
• Encoded-bits can be changed by Privileged Instructions that write intoPS.
• Privileged-instructions can be executed only while processor is running in SupervisorMode.
• Processor is in supervisor-mode only when executing operating-systemroutines.
Privileged Exception
• User programcannot
→ accidently or intentionally change the priority of the processor &
→ disrupt the system-operation.
• An attempt to execute a privileged-instruction while in user-mode leads to a PrivilegedException.

Dept. of ECE, ATMECE, Mysuru Page 6

 COMPUTER ORGANIZATION AND ARCHITECTURE 18EC35

SIMULTANEOUS REQUESTS
• The processor must have some mechanisms to decide which request to service when simultaneous
requestsarrive.
A widely used scheme is to connect the devices to form a daisy chain, as shown in fig. 4.8a
• INTR line is common to all devices (Figure4.8a).
• The interrupt-acknowledge line, INTA, is connected in a daisy-chain fashion, such that the INTA signal
propagates serially through the devices.
• INTA signal propagates serially throughdevices.
• When several devices raise an interrupt-request, INTR line isactivated.
• Processor responds by setting INTA line to 1. This signal is received by device1.
• Device-1 passes signal on to device 2 only if it does not require anyservice.
• If device-1 has a pending-request for interrupt, thedevice-1
→ blocks INTA signal &
→ proceeds to put its identifying-code on data-lines.
• Device that is electrically closest to processor has highestpriority.
• Advantage: It requires fewer wires than the individualconnections.
Arrangement of Priority Groups
• Here, the devices are organized in groups & each group is connected at a different prioritylevel.
• Within a group, devices are connected in a daisy chain. (Figure4.8b).

Dept. of ECE, ATMECE, Mysuru Page 7

COMPUTER ORGANIZATION AND ARCHITECTURE 18EC35
3.2.4 CONTROLLING DEVICE REQUESTS:
Until now, we have assumed that an I/O device interface generates an interrupt
request whenever it is ready for an I/O transfer, for example whenever the SIN flag
is 1. It is important to ensure that interrupt requests are generated only by those I/O
devices that are being used by a given program. Idle devices must not be allowed to
generate interrupt requests, even though they may be ready to participate in I/O
transfer operations. Hence, we need a mechanism in the interface circuits of
individual devices to control whether a device is allowed to generate an interrupt
request.
The control needed is usually provided in the form of an interrupt-enable bit in
the device’s interface circuit. The keyboard interrupt-enable, KEN, and display
interrupt enable, DEN, flags in register CONTROL perform this function. If either of
these flags is set, the interface circuit generates an interrupt request whenever the
corresponding status flag in register STATUS is set. At the same time, the interface
circuit sets bit KIRQ or DIRQ to indicate that the keyboard or display unit,
respectively, is requesting an interrupt. If an interrupt-enable bit is equal to 0, the
interface circuit will not generate an interrupt request, regardless of the state of the
status flag.

3.3 DIRECT MEMORY ACCESS (DMA)

• The transfer of a block of data directly b/w an external device & main-memory w/o
continuous involvement by processor is calledDMA.
• DMAcontroller
→ is a control circuit that performs DMA transfers (Figure 8.13).
→ is a part of the I/O device interface.
→ performs the functions that would normally be carried out by
processor.
• While a DMA transfer is taking place, the processor can be used to execute
anotherprogram.

• DMA interface has three registers (Figure8.12):

1) First register is used for storingstarting-address.
2) Second register is used for storingword-count.
3) Third register contains status- &control-flags.

• The R/W bit determines direction oftransfer.

If R/W=1, controller performs a read-operation (i.e. it transfers data from
memory to I/O), Otherwise, controller performs a write-operation (i.e. it
transfers data from I/O to memory).
• If Done=1, the controller
→ has completed transferring a block of data and
→ is ready to receive another command. (IE Interrupt Enable).
• If IE=1, controller raises an interrupt after it has completed transferring a block of
data.

Dept. of ECE, ATMECE, Mysuru Page 8

COMPUTER ORGANIZATION AND ARCHITECTURE 18EC35

• If IRQ=1, controller requests aninterrupt.

• Requests by DMA devices for using the bus are always given higher priority than
processorrequests.
• There are 2 ways in which the DMA operation can be carriedout:
1) Processor originates most memory-accesscycles.
 DMA controller is said to "steal" memory cycles fromprocessor.
 Hence, this technique is usually called CycleStealing.
2) DMA controller is given exclusive access to main-memory to transfer a
block of data without any interruption. This is known as Block Mode (or
burstmode).

Dept. of ECE, ATMECE, Mysuru Page 9