Data Converter Testing

ESE 568: Mixed Signal Design and

!  Measuring DNL & INL
Modeling "  Servo-loop
"  Code density testing (histogram testing)
Lec 21: November 27, 2017 !  Dynamic tests
Data Converter Testing "  Spectral testing # Reveals ADC errors associated with
dynamic behavior i.e. ADC performance as a function of
frequency
"  Direct Discrete Fourier Transform (DFT) based measurements utilizing
sinusoidal signals
"  DFT measurements including windowing
"  Relationship between: DNL & SNR, INL & SFDR
"  Effective number of bits (ENOB)
Penn ESE 568 Fall 2017 - Khanna adapted from Murmann Penn ESE 568 Fall 2017 - Khanna adapted from Murmann
EE315B, Stanford EE315B, Stanford 2

ADC DNL/INL (endpoint) How to Measure DNL/INL

!  DAC: 
!  1. Endpoints connected 
"  Simply apply digital codes and use a good voltmeter
to measure corresponding analog output 
!  2. Ideal characteristics derived
eliminating offset & full-scale !  ADC 
error (same as for DNL) 
"  Not as simple as DAC # need to find "decision levels",
i.e. input voltages at all code boundaries 
!  3. DNL # deviation of code
width from D (1LSB)  "  One way: Adjust voltage source to find exact code
trip points "code boundary servo” 
!  4. INL # deviation of "  More versatile: Histogram testing # Apply a signal with
code transition from ideal known amplitude distribution and analyze digital code
distribution at ADC output

Penn ESE 568 Fall 2017 - Khanna adapted from Murmann Penn ESE 568 Fall 2017 - Khanna adapted from Murmann
EE315B, Stanford 3 EE315B, Stanford 4

Code Boundary Servo Code Boundary Servo

!  i1 and i2 are small, and C1 is
large (ΔV=it/C1), so
the ADC analog input moves
a small fraction of an
LSB (e.g. 0.1LSB)
each sampling period 
!  For a code input of 101, the
ADC analog input settles to
the code boundary shown

Penn ESE 568 Fall 2017 - Khanna adapted from Murmann Penn ESE 568 Fall 2017 - Khanna adapted from Murmann
EE315B, Stanford 5 EE315B, Stanford 6

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 Code Boundary Servo Code Boundary Servo
!  A very good digital voltmeter (DVM) measures the
analog input voltage corresponding to the desired
code boundary 
!  DVMs have some interesting properties 
"  They can have very high resolutions (8½ decimal digit
meters are inexpensive) 
"  To achieve stable readings, DVMs average voltage
measurements over multiple 60Hz ac line cycles to filter
out pickup in the measurement loop

Penn ESE 568 Fall 2017 - Khanna adapted from Murmann Penn ESE 568 Fall 2017 - Khanna adapted from Murmann
EE315B, Stanford 7 EE315B, Stanford 8

Code Boundary Servo Code Boundary Servo

!  ADCs of all kinds are notorious !  Just before the input is

for kicking back high- sampled and conversion
frequency, signal- starts, the analog input is
dependent glitches to their pretty quiet 
analog inputs  !  As the converter begins to
!  A magnified view of an analog quantize the signal, it kicks
input glitch follows … back charge

Penn ESE 568 Fall 2017 - Khanna adapted from Murmann Penn ESE 568 Fall 2017 - Khanna adapted from Murmann
EE315B, Stanford 9 EE315B, Stanford 10

Code Boundary Servo Code Boundary Servo

!  The difference between

what the ADC measures
and what the DVM !  A large C2 reduces the effect
measures is not ADC INL, of kick-back 
it’s error in the INL !  At the expense of longer
measurement  measurement time
!  How do we control
this error?

Penn ESE 568 Fall 2017 - Khanna adapted from Murmann Penn ESE 568 Fall 2017 - Khanna adapted from Murmann
EE315B, Stanford 11 EE315B, Stanford 12

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 Histogram Testing Histogram Test Setup
!  Code boundary measurements are slow 
"  Long testing time 
!  Histogram testing 
"  Apply input with known pdf (e.g. ramp or sinusoid) &
quantize 
"  Measure output pdf 
"  Derive INL and DNL from deviation of measured pdf
from expected result !  Slow (relative to conversion time) linear ramp applied to
ADC 
!  DNL derived directly from total number of occurrences of
each code @ the output of the ADC

Penn ESE 568 Fall 2017 - Khanna adapted from Murmann Penn ESE 568 Fall 2017 - Khanna adapted from Murmann
EE315B, Stanford 13 EE315B, Stanford 14

A/D Histogram Test Using Ramp Signal A/D Histogram Test Using Ramp Signal
!  Example:  !  Example: 
"  ADC sampling "  ADC sampling
rate: fs=100kHz # rate: fs=100kHz #
Ts=10us  Ts=10us 
"  1LSB =10mV  "  1LSB =10mV 
"  For 0.01LSB "  For 0.01LSB
measurement resolution:  measurement resolution: 
"  # n=100 samples/code  "  # n=100 samples/code 
"  # Ramp duration per "  # Ramp duration per
code=100x10us=1ms  code=100x10us=1ms 
"  # Ramp slope: 10mV/ms "  # Ramp slope: 10mV/ms

Penn ESE 568 Fall 2017 - Khanna adapted from Murmann Penn ESE 568 Fall 2017 - Khanna adapted from Murmann
EE315B, Stanford 15 EE315B, Stanford 16

Ramp Histogram Example: Ideal 3-bit ADC Ramp Histogram Example: Real 3-bit ADC

Penn ESE 568 Fall 2017 - Khanna adapted from Murmann Penn ESE 568 Fall 2017 - Khanna adapted from Murmann
EE315B, Stanford 17 EE315B, Stanford 18

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 DNL from Histogram DNL from Histogram

!  3- Normalize: 
"  Divide histogram by average
!  1- Remove “Over-range count/bin 
bins” (0 and full-scale)  "  # ideal bins have exactly
the average count, which,
!  2- Compute average count/ after normalization, would be 1 
bin (600/6=100 in this case) "  # Non-ideal bins would
have a normalized value greater
or smaller than 1

Penn ESE 568 Fall 2017 - Khanna adapted from Murmann Penn ESE 568 Fall 2017 - Khanna adapted from Murmann
EE315B, Stanford 19 EE315B, Stanford 20

DNL from Histogram DNL and INL from Histogram

!  DNL histogram # used
to reconstruct the exact
converter characteristic
(having measured only the
!  4- Subtract ‘1’ from
histogram) 
the normalized code count 5-
!  Width of all codes derived
!  Result # DNL (+-0.4LSB in
from measured DNL (Code
this case)
width=DNL + 1LSB) 
!  INL # (deviation from a
straight line through the end
points) is found

Penn ESE 568 Fall 2017 - Khanna adapted from Murmann Penn ESE 568 Fall 2017 - Khanna adapted from Murmann
EE315B, Stanford 21 EE315B, Stanford 22

DNL and INL from Histogram Measuring DNL

!  Ramp speed is adjusted to provide large number of output/
code - e.g. an average of 100 outputs of each ADC code (for
1/100 LSB resolution) 

!  Ramp test can be quite slow for high resolution ADCs 

!  Example: 16bit ADC & 100 conversions/code @
100kHz sampling rate:

Penn ESE 568 Fall 2017 - Khanna adapted from Murmann Penn ESE 568 Fall 2017 - Khanna adapted from Murmann
EE315B, Stanford 23 EE315B, Stanford 24

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 Histogram Testing: Sinusoidal Input ADC Histogram Test Using Sinusoidal Signals
!  Ramp signal generators
linear to only 8 to10bits &
thus only good for testing
ADCs <10bit res
"  #Need to find input
signal with better purity for
testing higher res. ADCs 
!  Solution: Use sinusoidal test
signal (may need to filter
out harmonics) 
"  Problem: Ideal
ADC histogram not flat but has
“bath-tub shape”

Penn ESE 568 Fall 2017 - Khanna adapted from Murmann Penn ESE 568 Fall 2017 - Khanna adapted from Murmann
EE315B, Stanford 25 EE315B, Stanford 26

DNL/INL Extraction Matlab Program Example Sinusoid Histogram

Penn ESE 568 Fall 2017 - Khanna adapted from Murmann Penn ESE 568 Fall 2017 - Khanna adapted from Murmann
EE315B, Stanford 27 EE315B, Stanford 28

Eample: DNL/INL Code Test Histogram Testing Limitations

!  The histogram (as any ADC test, of course) characterizes one particular
converter. Test many devices to get valid statistics. 
!  Histogram testing assumes monotonicity 
E.g. “code flips” will not be detected. 

!  Dynamic sparkle codes produce only minor DNL/INL errors E.g. 123,

123, …, 123, 0, 124, 124, … # look at ADC output to detect 
!  Noise not detected & averaged out E.g. 9, 9, 9, 10, 9, 9, 9, 10, 9, 10, 10,
10, … 
!  Ref: B. Ginetti and P. Jespers, “Reliability of Code Density Test for High
Resolution ADCs,” Electron. Lett., vol. 27, pp. 2231-3, Nov. 1991.

Penn ESE 568 Fall 2017 - Khanna adapted from Murmann Penn ESE 568 Fall 2017 - Khanna adapted from Murmann
EE315B, Stanford 29 EE315B, Stanford 30

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 Why Additional Tests/Metrics?  DAC Spectral Test or Simulation
!  Static testing does not tell the full story 
"  E.g. no info about "noise“ or high frequency effects 
!  Frequency dependence (fs and fin) ? 
"  In principle we can vary fs and fin when
performing histogram tests 
"  Result of such sweeps is usually not very useful 
"  Hard to separate error sources, ambiguity 
"  Typically we use fs=fsNOM and fin << fs/2 for histogram
!  Input sinusoid # Need to have significantly better purity compared
tests (Static metrics) to DAC linearity 
!  For additional info regarding higher !  Spectrum analyzer need to have better linearity than DUT 
frequency operation # Spectral testing !  Typically, test performed at several different input signal frequencies

Penn ESE 568 Fall 2017 - Khanna adapted from Murmann Penn ESE 568 Fall 2017 - Khanna adapted from Murmann
EE315B, Stanford 31 EE315B, Stanford 32

Direct ADC Spectral Test via DAC Direct ADC-DAC Test

!  Need DAC with much better performance compared to ADC under test  !  Issues to beware of: 
!  Beware of DAC output sinx/x frequency shaping  "  Linearity of the signal generator output has to be much better than ADC linearity 
"  Spectrum analyzer nonlinearities 
!  Good way to "get started"... "  #May need to build/purchase filters to address one or both above problems 
"  Clock generator signal jitter

Penn ESE 568 Fall 2017 - Khanna adapted from Murmann Penn ESE 568 Fall 2017 - Khanna adapted from Murmann
EE315B, Stanford 33 EE315B, Stanford 34

Filtering ADC Input Signal ADC Spectral Test via Data Acquisition System

Penn ESE 568 Fall 2017 - Khanna adapted from Murmann Penn ESE 568 Fall 2017 - Khanna adapted from Murmann
EE315B, Stanford 35 EE315B, Stanford 36

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 Analyzing ADC Outputs via DFT DFT Properties
!  DFT of N samples spaced Ts=1/fs seconds: 
"  N frequency bins from DC to fs 
"  Num of bins # N & each bin has width= fs/N 
"  Bin # m represents frequencies at m * fs/N [Hz] 
!  DFT frequency resolution: 
"  Proportional to fs/N in [Hz/bin] 
!  Sinusoidal waveform has all its power at one single frequency  "  DFT with N = 2k (k is an integer) can be found using
!  An ideal, infinite resolution ADC would preserve ideal, single a computationally more efficient algorithm named: 
tone spectrum  "  FFT # Fast Fourier Transform
!  DFT (Discrete Fourier Transform) used as a vehicle to reveal
ADC deviations from ideality

Penn ESE 568 Fall 2017 - Khanna adapted from Murmann Penn ESE 568 Fall 2017 - Khanna adapted from Murmann
EE315B, Stanford 37 EE315B, Stanford 38

DFT Magnitude Plots Matlab Example: Normalized DFT

!  Because magnitudes of DFT bins (Am) are symmetric around
fS/2, it is redundant to plot ⏐Am⏐’s for m >N/2 

!  Usually magnitudes are plotted on a log scale normalized so

that a full scale sinusoidal waveform with rms value aFS yields
a peak bin of 0dBFS:

Penn ESE 568 Fall 2017 - Khanna adapted from Murmann Penn ESE 568 Fall 2017 - Khanna adapted from Murmann
EE315B, Stanford 39 EE315B, Stanford 40

DFT Noise DFT Periodicity

!  The DFT implicitly assumes that time
sample blocks repeat every N samples 
!  With a non-integer number of signal
periods within the observation window,
the input yields significant amplitude/
phase discontinuity at the block
boundary
!  This energy spreads into other frequency
bins as “spectral leakage” 
!  Spectral leakage can be eliminated by
either 
"  1. Choice of integer number of sinusoids
in each block 
"  2. Windowing

Penn ESE 568 Fall 2017 - Khanna adapted from Murmann Penn ESE 568 Fall 2017 - Khanna adapted from Murmann
EE315B, Stanford 41 EE315B, Stanford 42

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 Frequency Spectrum Choice of Number of Cycles & Samples

!  To overcome frequency
spectrum leakage problem: 
"  Number of Cycles # integer 
"  N/cycles = fs/fx # non-
integer (choose prime # of
cycles) otherwise quant. Noise
# periodic and non-random 
"  Preferable to have N: # power
of 2 (FFT instead of DFT)

Penn ESE 568 Fall 2017 - Khanna adapted from Murmann Penn ESE 568 Fall 2017 - Khanna adapted from Murmann
EE315B, Stanford 43 EE315B, Stanford 44

Example: Integer Number of Cycles Example: Integer Number of Cycles

Penn ESE 568 Fall 2017 - Khanna adapted from Murmann Penn ESE 568 Fall 2017 - Khanna adapted from Murmann
EE315B, Stanford 45 EE315B, Stanford 46

Windowing Example: Nuttall Window

!  Spectral leakage can be attenuated by
“windowing” time samples prior to the DFT 
"  Windows taper smoothly down to zero at the beginning
and the end of the observation window 
"  Time samples are multiplied by window coefficients on
a sample-by-sample basis # Convolution in frequency
domain 
!  Large number choices of various windows 
"  Tradeoff: attenuation versus fundamental signal spreading !  Time samples are multiplied by window coefficients on a
to number of adjacent bins  sample-by-sample basis
!  Window examples: Nuttall versus Hann !  Multiplication in the time domain # convolution in the
frequency domain
Penn ESE 568 Fall 2017 - Khanna adapted from Murmann Penn ESE 568 Fall 2017 - Khanna adapted from Murmann
EE315B, Stanford 47 EE315B, Stanford 48

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 Windowed Data Nuttall Window DFT
!  Only first 20 bins shown
!  Signal before windowing !  Response attenuated by
-120dB for bins > 5
!  Time samples are multiplied !  Lots of windows to choose
by window coefficients on a from (go by name of
sample-by-sample basis inventor Blackman, Harris,
Nutall…)
!  Signal after windowing !  Various window trade-off
"  Windowing removes the attenuation versus width
discontinuity at block (smearing of sinusoids)
boundaries

Penn ESE 568 Fall 2017 - Khanna adapted from Murmann Penn ESE 568 Fall 2017 - Khanna adapted from Murmann
EE315B, Stanford 49 EE315B, Stanford 50

DFT of Windowed Signal Nuttall vs. Hann

Penn ESE 568 Fall 2017 - Khanna adapted from Murmann Penn ESE 568 Fall 2017 - Khanna adapted from Murmann
EE315B, Stanford 51 EE315B, Stanford 52

Integer Cycles Vs. Windowing Example: ADC Spectral Testing

!  Integer number of cycles  !  ADC with B=10 bits
"  Signal energy for a single sinusoid falls into single DFT bin 
!  Full scale input level = 2V
"  Requires careful choice of fx 
"  Ideal for simulations 
B = 10;
"  Measurements # need to lock fx to fs (PLL)- not always possible 
delta = 2/2^B;
!  Windowing  %sampled sinusoid, N Samples
"  No restrictions on fx # no need to have the signal locked to fs #
y = cos(2*pi*fx/fs*[0:N-1]);
Good for measurements w/o having the capability to lock fx to fs
or cases where input is not periodic  %quantize samples to delta=1LSB
"  Signal energy and its harmonics distributed over several DFT bins –  y=round(y/delta)*delta;
handle smeared-out harmonics with care!  s = abs(fft(y/N*2);
"  Requires more samples for a given accuracy  f = (0:length(s)-1)/N;

Penn ESE 568 Fall 2017 - Khanna adapted from Murmann Penn ESE 568 Fall 2017 - Khanna adapted from Murmann
EE315B, Stanford 53 EE315B, Stanford 54

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 ADC Output Spectrum ADC Output Spectrum
!  Noise bins: all except signal bin

!  Input signal bin: bx = N*fx/fs + 1;

"  Bx @ bin # (N * fx/fs + 1) As = 20*log10(s(bx))
(Matlab arrays start at 1) %set signal bin to 0
"  Asignal = 0dBFS s(bx) = 0;
An = 10*log10(sum(s.^2))
SNR = As - An
"  What is the SNR?
!  Matlab#SNR = 62dB (10 bits)
!  Computed SQNR =
6.02xN+1.76dB=61.96dB

Penn ESE 568 Fall 2017 - Khanna adapted from Murmann Penn ESE 568 Fall 2017 - Khanna adapted from Murmann
EE315B, Stanford 55 EE315B, Stanford 56

Why is Noise Floor Not @ -62dB? DFT Plot Annotation

!  DFT bins act like an analog !  Need to annotate DFT plot such that actual noise
spectrum analyzer with floor can be readily computed by one of these 3
bandwidth per bin of fs/N
ways:
!  Assuming noise is uniformly
"  1. Specify how many DFT points (N) are used
distributed, noise per bin:
"  (Total noise)/(N/2) "  2. Shift DFT noise floor by 10log10(N/2) [dB]
!  # The DFT noise floor wrt "  3. Normalize to "noise power in 1Hz bandwidth“ then
total noise: noise is in the form of power spectral density
"  -10log10(N/2) [dB] below the actual
noise floor
!  For N=2048:
"  -10log10(N/2) =-30 [dB]

Penn ESE 568 Fall 2017 - Khanna adapted from Murmann Penn ESE 568 Fall 2017 - Khanna adapted from Murmann
EE315B, Stanford 57 EE315B, Stanford 58

Example:10Bit ADC FFT Example:10Bit ADC FFT

!  Increasing N, the number
of samples (at the cost of
measurement or
!  For a real 10bit ADC spectral
simulation time)
test results:
distributes the noise over
!  SNR=55.9dB larger # of bins
!  A 3rd harmonic is barely !  Larger # of bins # less
visible noise power per bin (total
!  Is better view of distortion noise stays constant)
component possible? !  Note the 3rd harmonic is
clearly visible when N is
increased

Penn ESE 568 Fall 2017 - Khanna adapted from Murmann Penn ESE 568 Fall 2017 - Khanna adapted from Murmann
EE315B, Stanford 59 EE315B, Stanford 60

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 Spectral Performance Metrics Spectral Performance Metrics
!  Signal S !  Signal S
!  DC !  DC
!  Distortion D !  Distortion D
!  Noise N !  Noise N

!  Ideal ADC adds: !  Signal-to-noise ratio

"  Quantization noise "  SNR = 10log[(Signal Power)/
(Noise Power)]
!  In Matlab: Noise power
!  Real ADC typically adds: includes power associated with
"  Thermal and flicker noise all bins except:
"  Harmonic distortion associated "  DC
with circuit nonlinearities "  Signal
"  Signal harmonics

Penn ESE 568 Fall 2017 - Khanna adapted from Murmann Penn ESE 568 Fall 2017 - Khanna adapted from Murmann
EE315B, Stanford 61 EE315B, Stanford 62

ADC Spectral Performance Metrics Harmonic Components

!  At multiples of fx
!  Aliasing:
!  SDR & SNDR & SFDR "  fsignal = fx = 0.18 fs
"  SDR#Signal-to-distortion ratio "  f2 = 2f0 = 0.36 fs
"  10log[(Signal Power)/(Total "  f3 = 3f0 = 0.54 fs
Distortion Power)] "  # 0.46 fs
"  SNDR#Signal-to-(noise+distortion) "  f4 = 4f0= 0.72 fs
"  10log[S/(N+D)] "  # 0.28 fs
"  SFDR#Spurious-free dynamic range "  f5 = 5f0 = 0.90 fs
"  10log[(Signal)/(Largest Harmonic)] "  # 0.10 fs
"  f6 = 6f0 = 1.08 fs
"  # 0.08 fs

Penn ESE 568 Fall 2017 - Khanna adapted from Murmann Penn ESE 568 Fall 2017 - Khanna adapted from Murmann
EE315B, Stanford 63 EE315B, Stanford 64

Relationship INL & SFDR/SNDR Frequency Spectrum vs. INL/DNL

Penn ESE 568 Fall 2017 - Khanna adapted from Murmann Penn ESE 568 Fall 2017 - Khanna adapted from Murmann
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 Relationship INL & SFDR/SNDR SNR Degradation due to DNL
!  Nature of harmonics depend on "shape" of INL
curve
!  Rule of Thumb: SFDR ≅ 20log(2B/INL)
"  E.g. 1LSB INL, 10b # SFDR ≅ 60dB
!  Beware, this is of course only true under the same
conditions at which the INL was taken, i.e. typically
low input signal frequency
!  Uniform quantization error pdf was assumed for ideal
quantizer over the range of: +/- Δ/2
!  Let's now add uniform DNL over +/- Δ/2 and repeat
math...
"  Joint pdf for two uniform pdfs # Triangular shape
Penn ESE 568 Fall 2017 - Khanna adapted from Murmann Penn ESE 568 Fall 2017 - Khanna adapted from Murmann
EE315B, Stanford 67 EE315B, Stanford 68

Quantization Error Statistics SNR Degradation due to DNL

!  Crude assumption: eq(x) has uniform probability !  To find total noise # Integrate triangular pdf:
density
!  This approximation holds reasonably well in
practice when
"  Signal spans large number of quantization steps
!  Compare to ideal quantizer:
"  Signal is "sufficiently active”
"  Quantizer does not overload

#Error associated with DNL reduces overall SNR

Penn ESE 568 Fall 2017 - Khanna adapted from Murmann Penn ESE 568 Fall 2017 - Khanna adapted from Murmann
EE315B, Stanford 69 EE315B, Stanford 70

SNR Degradation due to DNL SNR Degradation due to DNL

!  More general case: !  Degradation in dB:
"  Uniform quantization error (ideal) ±0.5Δ
"  Uniform DNL error ± DNL [LSB]
"  Convolution yields trapezoid shaped joint pdf
"  SQNR becomes:

Penn ESE 568 Fall 2017 - Khanna adapted from Murmann Penn ESE 568 Fall 2017 - Khanna adapted from Murmann
EE315B, Stanford 71 EE315B, Stanford 72

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 Summary Effective Number of Bits (ENOB)
!  Is a 12-Bit converter with 68dB SNDR really a 12-Bit
converter?
!  Effective Number of Bits (ENOB)## of bit of an ideal
ADC with the same SQNR as the SNDR of the nonideal
ADC

!  #Above ADC is a 12bit ADC with ENOB=11bits

Penn ESE 568 Fall 2017 - Khanna adapted from Murmann Penn ESE 568 Fall 2017 - Khanna adapted from Murmann
EE315B, Stanford 73 EE315B, Stanford 74

ENOB ENOB Survey

!  At best, we get "ideal" ENOB only for negligible
thermal noise, DNL, INL
!  Low noise design is costly # 4x penalty in power
per (ENOB-) bit or 6dB extra SNDR
!  Rule of thumb for good performance/power
tradeoff: ENOB < N-1

Penn ESE 568 Fall 2017 - Khanna adapted from Murmann Penn ESE 568 Fall 2017 - Khanna adapted from Murmann
EE315B, Stanford 75 EE315B, Stanford 76

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