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Chapter 5

The document describes exercises for modeling gates and circuits in Verilog. It includes tasks to create basic logic gates from NAND gates, build an XOR gate, implement a 1-bit full adder using sum of products, model an RS latch with delay, and design a 2-to-1 multiplexer using bufif0 and bufif1 gates with specified delay ranges. For each exercise, it provides the logic function or diagram and asks the student to write the Verilog description and testbench.

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shubham
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113 views8 pages

Chapter 5

The document describes exercises for modeling gates and circuits in Verilog. It includes tasks to create basic logic gates from NAND gates, build an XOR gate, implement a 1-bit full adder using sum of products, model an RS latch with delay, and design a 2-to-1 multiplexer using bufif0 and bufif1 gates with specified delay ranges. For each exercise, it provides the logic function or diagram and asks the student to write the Verilog description and testbench.

Uploaded by

shubham
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Chapter 5:

Chapter 5. Gate-level Modeling


5.4 Exercises
1. Create your own 2-input Verilog gates called my_or, my_and and my_not
from 2-input Nand gates. Check the functionality of these gates with a
stimulus module.
My answer:

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2. A 2-input xor gate can be built from my_and, my_or and my_not gates.
Construct an xor module in Verilog that realizes the logic function, z=xy’+x’y.
Inputs are x and y, and z is the output. Write a stimulus module that
exercises all four combinations of x and y inputs.
My answer:

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3. The 1-bit full adder described in the chapter can be expressed in a sum of
products form.
sum=a.b.c_in+a’.b.c_in’+a’.b’.c_in+a.b’c_in’
c_out=a.b+b.c_in+a.c_in
Assuming a,b,c_in are the inputs and sum and c_out are the outputs, design a
logic circuit to implement the 1-bit full adder, using only and, not ,and or
gates. Write the Verilog description for the circuit. You may use up to 4-input
Verilog primitive and and or gates. Write the stimulus for the full adder and
check the functionality for all input combinations.
my answer:

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4. The logic diagram for an RS latch with delay is shown below.

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Write the Verilog description for the RS latch. Include delays of 1 unit when
instantiating the nor gates. Write the stimulus module for the RS latch, using
the following table, and verify the outputs.

My answer:

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5. Design a 2-to-1 multiplexer using bufif0 and bufif1 gates as shown below.

The delay specification for gates b1 and b2 are as follows:

Min Typ Max


Rise 1 2 3
Fall 3 4 5
Turnoff 5 6 7

Apply stimulus and test the output values.


My answer:

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