Breaking NES Book

6502 Core
andkorzh, HardWareMan, org

A book on how the MOS 6502 processor works, but basically just a copy of the
wiki from the GitHub.

Translated with www.DeepL.com/Translator (free version)

Rev. A6
Foreword
This book would probably be the best choice for reading on long winter evenings, in front of a
warm fireplace with wood crackling and a snowstorm blowing outside the window at the same
time.

2
Contents
Overview…………………………………………………………………………………………………….. ……………………………..4
Pinout…………………………………………………………………………………………………………. ……………………………14
Clock…………………………………………………………………………………………………………... ……………………………18

Top Part
Instruction Register……………………………………………………………………………………. ……………………………..24
Extended Cycle Counter…………………………………………………………………………….. ……………………………..27
Decoder……………………………………………………………………………………………………… ……………………………..30
Pre-decode………………………………………………………………………………………………… ……………………………..41
Interrupt Processing…………………………………………………………………………………… ……………………………..45
Random Logic……………………………………………………………………………………………. ……………………………..51
Registers Control……………………………………………………………………………….. ……………………………..55
ALU Control……………………………………………………………………………………….. ……………………………..60
Program Counter Control………………………………………………………………….. ……………………………..67
Bus Control………………………………………………………………………………………… ……………………………..71
Dispatcher………………………………………………………………………………………….. ……………………………..80
Flags Control……………………………………………………………………………………… ……………………………..88
Flags…………………………………………………………………………………………………… ……………………………..93
Branch Logic………………………………………………………………………………………. ……………………………..99
Control Commands……………………………………………………………………………………. …………………………...102

Bottom Part
Address Bus………………………………………………………………………………………………. ……………………………107
Data Bus……………………………………………………………………………………………………. ……………………………111
Registers……………………………………………………………………………………………………. ……………………………114
ALU……………………………………………………………………………………………………………. ……………………………117
Program Counter………………………………………………………………………………………. ……………………………130

3
This page is needed so that the schematics on the spreads start on even pages.

4
6502 Overview
The 6502 processor was developed by MOS. It was based on the architecture of the Motorola
6800 processor:

6502 6800

In both cases the top part is occupied by the decoder and random logic, and the whole bottom
part of the processor is occupied by the context and the ALU.

Architecture
The processor is divided into two parts: the upper part and the lower part.

The upper part contains the control logic, which issues a number of control lines ("commands")
to the lower part. The lower part contains the context of the processor: internal buses and regis-
ters, with one exception - the flags register (P) is in the upper part in a "spread out" form.

Also in the lower part is the ALU.

The processor is clocked by the PHI0 clock pulse, both half-cycles are used. During the first half-
cycle (PHI1) the processor is in "talking" mode. At this time the processor is outputting data to
the outside. During the second half-cycle (PHI2) the processor is in "listening" mode, during this
half-cycle external devices can put data on the data bus for the processor to process it.

5
6
7
Registers

• PD: current operation code for precoding

• IR: instruction register (stores the current operation code)
• X, Y: index registers
• S: Stack pointer
• AI, BI: input values for ALU
• ADD: Intermediate result of an ALU operation
• AC: accumulator
• PCH/PCL: program counter in two halves
• PCHS/PCLS: program counter auxiliary registers (S stands for "set" (?))
• ABH/ABL: registers for output to the external address bus
• DL: data latch, stores the last read value of the external data bus
• DOR: data output register, holds the value which will be written to the data bus
• P: flag register, actually consists of a set of latches scattered around the circuit

The following registers are directly available to the programmer: A (accumulator), X, Y, S, P, PC.

External Buses
There are only two external buses: a 16-bit address bus (ADDR) and an 8-bit data bus (DATA).
The address bus is one-way - only the processor can write to it. The data bus is bidirectional.

Internal Buses

• ADH/ADL: address bus

• SB: side(?) bus, register exchange bus
• DB: Internal data bus

During the second half-step (PHI2) all internal buses are precharged and have a value of 0xff.
This is done because it is faster to "discharge" the transistor at the right moment than to
"charge" it (the change of 1=>0 is faster than the change of 0=>1).

8
Register-Bus Connections

By connecting buses and registers in series, the processor executes a variety of instructions. The
variety of connections provides a variety of processor instructions, and the division of instruc-
tions into clock cycles allows complex actions to be performed. In addition, the ALU is controlled
(addition, logical operations, etc.).

Software Model

Addressing Modes

Addressing modes are described here because they should be kept in mind when analyzing
circuits.

Addressing is a way to get the operand to (or load it from) the desired memory location. The
developers of the 6502 were very generous and added as many as two X and Y index registers to
the context.

"Indexed" means that an offset is added to the memory address in a certain way to get a new
address. This is usually needed to access arrays. In this case the beginning of the array will be a
fixed address and the value in the index register will be the array index (offset).

9
List of addressing modes:

• Immediate (immediate operand). In this case the operand is stored in the instruction itself
(usually the second byte, after the operation code). Example LDA #$1C: A = 0x1C
• Absolute (absolute addressing). The instruction specifies the full 16-bit address from which
to get the operand. For example LDA $1234: A = [$1234]
• Zero Page Absolute: Developers have made an optimized version of absolute addressing by
adding the ability to address only page zero (pages are 256 bytes in size). Example LDA
$56: In this case the processor itself makes the highest 8 bits of the address equal to 0x00,
while the lowest 8 bits are taken from the instruction. The final address is 0x0056. A =
[0x0056]. This is done to save instruction size (one byte is saved).
• Indexed: In this addressing mode an offset from the X or Y register is added to the constant
address value. For example LDA $1234, X: A = [$1234 + X]
• Zero Page Indexed: Similar to Indexed but only the X register can be used. Example LDA
$33, X: A = [$0033 + X]

And then the special magic begins:

• Pre-indexed Indirect: The value of the operand which is the address in page zero is added
to the value of register X and the indirect address is obtained. The address the indirect
address refers to is then used to get the value of the operand. Example LDA ($34, X): A
= [[$0034 + X]]. Important: When you add an address and a value in the X register, it
"wraps" around 256 bytes. That is, it does not wrap to the higher half of the address. (0xFF
+ 0x02 will be 0x0001, not 0x0101). Indirect means "take address by address".
• Post-indexed Indirect: Different from the previous one in that the indirect address from
page zero is selected first, and then the index register Y value is added to it. Example LDA
($2A), Y: A = [[$002A] + Y].

10
Instruction Set

The 6502 has all the necessary instructions and also includes such rather handy instructions as
bit rotation (ROL/ROR) and bit testing (BIT). Not all processors of the time contained such in-
structions.

The instruction type and address mode are fully contained in the operation code, to simplify
decoding, but the bus width (8 bits) does not allow all instructions to be executed in a single
clock cycle. Also, the decoder is somewhat unoptimized, so the minimum instruction execution
time is 2 clock cycles, with the first clock cycle always taken by sampling the operation code (the
first byte of the instruction).

Summary of instructions:

Instruction Description Instruction Description

ADC Add Memory to Accumulator with Carry ROL Rotate One Bit Left (Memory or Accumulator)

AND "AND" Memory with Accumulator ROR Rotate One Bit Right (Memory or Accumulator)

ASL Shift Left One Bit (Memory or Accumulator) RTI Return from Interrupt

BCC Branch on Carry Clear RTS Return from Subroutine

BCS Branch on Carry Set SBC Subtract Memory from Accumulator with

BEQ Branch on Result Zero SEC Set Carry Flag

BIT Test Bits in Memory with Accumulator SED Set Decimal Mode

BMI Branch on Result Minus SEI Set Interrupt Disable Status

BNE Branch on Result not Zero STA Store Accumulator in Memory

BPL Branch on Result Plus STX Store Index X in Memory

BRK Force Break STY Store Index Y in Memory

BVC Branch on Overflow Clear TAX Transfer Accumulator to Index X

BVS Branch on Overflow Set TAY Transfer Accumulator to Index Y

CLC Clear Carry Flag TSX Transfer Stack Pointer to Index X

CLD Clear Decimal Mode TXA Transfer Index X to Accumulator

CLI Clear interrupt Disable Bit TXS Transfer Index X to Stack Pointer

CLV Clear Overflow Flag TYA Transfer Index Y to Accumulator

CMP Compare Memory and Accumulator

CPX Compare Memory and Index X

CPY Compare Memory and Index Y

DEC Decrement Memory by One

DEX Decrement Index X by One

DEY Decrement Index Y by One

EOR "Exclusive-Or" Memory with Accumulator

INC Increment Memory by One

INX Increment Index X by One

INY Increment Index Y by One

JMP Jump to New Location

JSR Jump to New Location Saving Return Address

LDA Load Accumulator with Memory

LDX Load Index X with Memory

LDY Load Index Y with Memory

LSR Shift Right One Bit (Memory or Accumulator)

NOP No Operation

ORA "OR" Memory with Accumulator

PHA Push Accumulator on Stack

PHP Push Processor Status on Stack

PLA Pull Accumulator from Stack

PLP Pull Processor Status from Stack

11
The developers chose the encoding so that it would be easier to process by decoder and random
logic.

Table of 6502 opcodes (for reference):

You can find a description of the instructions in any Reference Manual for 6502.

Interrupts

6502 interrupts:

• IRQ: hardware interrupt. Can be disabled with flag I (interrupt disable), if flag I=1 the inter-
rupt is "disabled" and does not go to the CPU.
• NMI: non-maskable interrupt. It has higher priority than IRQ, triggered on falling edge.
• RES: hardware reset. After powering up the 6502 it is necessary to set the /RES pin to 0 for a
few cycles so that the processor "comes to its senses".
• BRK: software interrupt. It is initiated by the BRK instruction.

12
Note on Transistor Circuits
The transistor circuits of each component are chopped into component parts so that they don't
take up too much space.

To keep you from getting lost, each section includes a special "locator" at the beginning that
marks the approximate location of the component being studied on the large 6502 "family por-
trait" (https://github.com/emu-russia/breaks/blob/master/Docs/6502/6502.jpg)

Example locator:

Note on Logic Circuits

The logic circuits are mostly made in the Logisim program. The following element is used to
denote DLatch:

DLatch (transistor circuit) DLatch (logic equivalent)

For convenience, the logical variant of DLatch has two outputs (out and /out), since the current
value of DLatch (out) is often used as an input of a NOR operation.

13
Pinout
The study of any integrated circuit begins with the pinout.

Name Direction Description

VCC => 6502 Power +5 V

VSS 6502 => Ground

/NMI => 6502 Non-maskable interrupt signal, active low

/IRQ => 6502 Maskable interrupt signal, active low

/RES => 6502 Reset signal, active low

PHI0 => 6502 Reference clock signal

PHI1 6502 => First half-cycle, processor in writing mode

PHI2 6502 => Second half-cycle, processor in read mode

RDY => 6502 Processor Ready (1: ready)

SO => 6502 Forced setting of the overflow flag (V)

R/W 6502 => Data bus direction (R/W=1: processor reads data, R/W=0: processor writes)

SYNC 6502 => The processor is on cycle T1 (opcode fetch)

A0-A15 6502 => Address bus

D0-D7 6502 <=> Data bus (bidirectional)

N.C. -- Not connected

14
Vcc/Vss
From the official datasheet we know that the operating range of Vcc = +5.0 volts +/- 5%.

Clock Generator
The clock signals are described in a separate section (see clock generator).

/NMI, /IRQ, /RES

Each contact contains a FF where the interrupt arrival event is stored. The FF value corresponds
to the control signals /NMIP, /IRQP and RESP (the value from FF for contact /RES is output as
direct value). The "P" in the name of the control signals stands for "Pad" (contact).

RDY

The RDY pin goes to the internal RDY signal and also through the DLATCH delay chain as the /
PRDY ("Previous Ready") signal. /PRDY goes to the decoder input Branch T0.

The RDY pin can be used to temporarily suspend the processor, e.g. while an external device
performs a DMA.

15
SYNC

The SYNC signal comes from the internal T1 signal (opcode fetch).

SO

The internal signal SO is fed to the flag V input to process the control signal 1/V.

R/W

The WR signal comes from dispatcher and defines the operating mode of the processor (WR:1 -
processor writes data, WR:0 - processor reads data).

Address Bus
See Address Bus.

Data Bus
See Data Bus.

16
Notes in the margins for future revisions of the book.

17
Clock Generator
The 6502 includes two clock reference circuits: an external and an internal one.

The processor inputs one clock signal, PHI0, and outputs two clock signals, PHI1 and PHI2.

This principle is based on the fact that each clock cycle of the processor consists of two
"modes" (or "states"): write mode and read mode.

During write mode the PHI1 signal is high. During this time, external devices can use the ad-
dress set on the external address bus of the processor.

During read mode the signal PHI2 is high. During this time external devices can write data to
the processor's data bus so that the processor can use it for its own purposes.

The signals PHI1 and PHI2 are called half-cycles and are derived from the original clock sig-
nal PHI0 as follows:

• When PHI0 is low - the processor is in write mode and the PHI1 signal is high
• When PHI0 is high - the processor is in read mode and the PHI2 signal is also high

PHI0 PHI1 PHI2

0 1 0

1 0 1

Internal Clock

18
The circuit is quite complicated, because it is not quite "digital". The numerous transistors that
act as inverters slightly delay the PHI0 signal, so the PHI1 and PHI2 signals going inside the pro-
cessor are a bit "laggy". Here is the logical representation of the circuit:

Logical analysis:

The layout of the clock signals should be about the following:

• PHI1/PHI2 are slightly lagging relative to PHI0

• The lower level of PHI1/PHI2 is slightly longer than the upper level, so that both signals are
guaranteed not to have a high level

The simulation in Altera Quartus shows "lag", but does not show the elongated lower level (it is
hand-drawn in the picture above).

19
BigEd from the 6502.org forum suggested that he ran a simulation on the 6502 FPGA netlist and
got the following sweeps:

The signal designations are as follows: clk0 = PHI0, cp1 = PHI1, cclk = PHI2 (according to the
netlist with Visual6502)

The schematic on which his simulation was based corresponds to the one in Balasz's documenta-
tion:

http://forum.6502.org/viewtopic.php?f=8&t=2208&start=195

It turns out that because of the asymmetrical inverter stage the rising edge is delayed, so the
lower level is as if "delayed".

20
The official documentation gives the following diagram:

External Clock

The PHI1/PHI2 reference signals are also output to the outside for consumers.

The logic circuit of the external wiring of the clock signals does not differ from the internal wiring
circuit, except that the outputs of PHI1/PHI2 go to the same contacts through the "comb" of
powerful transistors.

Why PHI
In the official 6502 datasheet the half-cycles are called "phases", respectively the name of these
signals is Φ1 and Φ2. For unification we use the designations PHI1 and PHI2.

21
Notes in the margins for future revisions of the book.

22
23
Instruction Register

The Instruction Register (IR) stores the current operation code, for processing on decoder. The
operation code is loaded into the IR from predecode logic.

Transistor Circuit

The outputs in the schematic are on the left because the decoder is topologically located on the
left side.

• IR0 and IR1 are combined into one common line IR01 to save lines
• IR0 is used only for the 128th decoder line (IMPL) (this operation with IR0 is part of the
random logic)
• /IR5 goes additionally to flags and is used in set/clear flags instructions (SEI/CLI, SED/CLD,
SEC/CLC)

24
Logic

• During PHI1 the IR value is overloaded from the Predecode (PD) latch, but only if
the FETCH command is active
• During PHI2 the IR is "refreshed" (this is not shown in logic circuit)

It should be noted that an inverted operation code (PD) value is fed to the IR input and is also
stored on the latch in an inverted form.

25
Notes in the margins for future revisions of the book.

26
Extended Cycle Counter

The 6502 has 3 cycle counters:

• The base counter, used for short instructions (Counts T0-T1 cycles)
• Extended counter (which we will talk about here) used for long instructions (Counts cycles
T2-T5)
• Counter for very long instructions (Counts cycles T5-T6)

One cycle (T) refers to two consecutive half-cycles (PHI1 + PHI2) of the processor.

Transistor Circuit

The whole circuit is a shift register, with a control sig-

nal T1 as its input. While the shift register is running, the
value of T1 is shifted and goes to the output of /T2, then
to /T3 and so on. The /T2-/T5 outputs are in inverse logic.

The shift register is used as a counter for easy transfer of

the current cycle (/T2-/T5) to the decoder input.

The register is reset by the TRES2 command and is done

after the instruction has been processed.

The circuit includes multiplexers on the /ready signal.

This is done so that when the processor is not ready
(ready=0) - shift register remains in the current state.

27
Logic

28
Notes in the margins for future revisions of the book.

29
Decoder
The decoder is an ordinary demultiplexer, but a very large one. The formula for the demultiplex-
er is 21-to-130. Sometimes the 6502 instruction decoder is also called a PLA.

Topologically, the decoder is divided by ground lines into several groups, so we'll stick to the
same division, for convenience.

The input signals are:

• /T0, /T1X: current cycle for short (2 clock) instructions. These signals are output
from dispatch logic.
• /T2, /T3, /T4, /T5: current cycle for long instructions. Signals are output from extended cycle
counter.
• /IR0, /IR1, IR01: the lower bits of the operation code from instruction register. To reduce the
number of lines 0 and 1 bits are combined into one control line IR01.
• IR2-IR7, /IR2-/IR7: direct and inverse values of the remaining bits. The direct and inverse
forms are needed to check the bit for 0 and 1.

The decoder logic is based on the exclusion principle. Schematically, each output is a multi-input
NOR element, which means that if at least one of the inputs has a 1, the whole line will NOT
work.

That is, the decoder outputs are not in inverse logic (as is usual), but in direct logic.

30
Special Lines
Additional logical operations are applied to some decoder outputs, which although territorially
are in the decoder area, are actually part of random logic. Most likely this logic got into the de-
coder simply because it was more convenient to split the connections that way.

List:

• Internal Push/Pull line: a special (129th) line that does not extend beyond the decoder. It is
used to "cut off" Push/pull instructions when selecting instructions. It is used in three lines:
83, 90, and 128. Appears on the schematic in duplicate, for different parts of the decoder.
• /PRDY: this line goes to decoder line 73 (Branch T0)
• IR0: normally the common signal IR01 is used to check the two lowest bits of the operation
code, but exclusively for the 128th line (IMPL), IR0 is used (IR0 is not included in the mask
for the table below).

31
PLA Contents

Cy
Grou Decoded
N Mask value (Raw bits) cle Comments Where to use
p mask value
(T)

A01 0 000101100000100100000 100XX100 TX STY Register control

A02 1 000000010110001000100 XXX100X1 T3 OP ind, Y Register control

A03 2 000000011010001001000 XXX110X1 T2 OP abs, Y Register control

A04 3 010100011001100100000 1X001000 T0 DEY INY Register control

A05 4 010101011010100100000 10011000 T0 TYA Register control

A06 5 010110000001100100000 1100XX00 T0 CPY INY Register control

B01 6 000000100010000001000 XXX1X1XX T2 OP zpg, X/Y & OP abs, X/Y Register control

B02 7 000001000000100010000 10XXXX1X TX LDX STX A<->X S<->X Register control

B03 8 000000010101001001000 XXX000X1 T2 OP ind, X Register control

B04 9 010101011001100010000 1000101X T0 TXA Register control

B05 10 010110011001100010000 1100101X T0 DEX Register control

B06 11 011010000001100100000 1110XX00 T0 CPX INX Register control

B07 12 000101000000100010000 100XXX1X TX STX TXA TXS Register control

B08 13 010101011010100010000 1001101X T0 TXS Register control

B09 14 011001000000100010000 101XXX1X T0 LDX TAX TSX Register control

B10 15 100110011001100010000 1100101X T1 DEX Register control

B11 16 101010011001100100000 11101000 T1 INX Register control

B12 17 011001011010100010000 1011101X T0 TSX Register control

B13 18 100100011001100100000 1X001000 T1 DEY INY Register control

B14 19 011001100000100100000 101XX100 T0 LDY Register control

B15 20 011001000001100100000 1010XX00 T0 LDY TAY Register control

32
C

C01 21 011001010101010100000 00100000 T0 JSR Register control

C02 22 000101010101010100001 00000000 T5 BRK Register control; Auxiliary signal BRK5

C03 23 010100011001010100000 0X001000 T0 Push Register control

C04 24 001010010101010100010 01100000 T4 RTS Register control

C05 25 001000011001010100100 0X101000 T3 Pull Register control

C06 26 000110010101010100001 01000000 T5 RTI Register control; Auxiliary signal RTI/5

C07 27 001010000000010010000 011XXX1X TX ROR To obtain an auxiliary /ROR signal for

C08 28 000000000000000001000 XXXXXXXX T2 T2 ANY Auxiliary signal T2 (processor is in cycle

C09 29 010110000000011000000 010XXXX1 T0 EOR ALU Control

C10 30 000010101001010100000 01X01100 TX JMP (excluder for ALU Control

C11 31 000000101001000001000 XXX011XX T2 ALU absolute ALU Control

C12 32 010101000000011000000 000XXXX1 T0 ORA ALU Control

The entire "left" half

C13 33 000000000100000001000 XXXX0XXX T2 of the opcode table ALU Control
(values X0-X7)

C14 34 010000000000000000000 XXXXXXXX T0 T0 ANY ALU Control

BRK JSR RTI RTS Regs Control, ALU Control; Auxiliary

C15 35 000000010001010101000 0XX0X000 T2
Push/pull - stack signal STK2

C16 36 000000000001010100100 0XX0XX00 T3 BRK JSR RTI RTS ALU Control

33
D

D01 37 000001010101010100010 00X00000 T4 BRK JSR ALU Control

D02 38 000110010101010100010 01000000 T4 RTI ALU Control

D03 39 000000010101001000100 XXX000X1 T3 OP X, ind ALU Control

D04 40 000000010110001000010 XXX100X1 T4 OP ind, Y ALU Control

D05 41 000000010110001001000 XXX100X1 T2 OP ind, Y ALU Control

D06 42 000000001010000000100 XXX11XXX T3 RIGHT ODD ALU Control

D07 43 001000011001010100000 0X101000 TX Pull ALU Control

D08 44 001010000000100010000 111XXX1X TX INC NOP ALU Control

D09 45 000000010101001000010 XXX000X1 T4 OP X, ind ALU Control; Bus Control (DL/DB)

D10 46 000000010110001000100 XXX100X1 T3 OP ind, Y Bus Control (DL/DB)

D11 47 000010010101010100000 01X00000 TX RTI RTS Bus Control (DL/DB); Auxiliary

D12 48 001001010101010101000 00100000 T2 JSR Auxiliary signal JSR2

D13 49 010010000001100100000 11X0XX00 T0 CPY CPX INY INX ALU Control

D14 50 010110000000101000000 110XXXX1 T0 CMP ALU Control

D15 51 011010000000101000000 111XXXX1 T0 SBC ALU Control; Auxiliary signal SBC0

D16 52 011010000000001000000 X11XXXX1 T0 ADC SBC ALU Control

D17 53 001001000000010010000 001XXX1X TX ROL ALU Control

34
E

E01 54 000010101001010100100 01X01100 T3 JMP ind ALU Control

E02 55 000001000000010010000 00XXXX1X TX ASL ROL Bus Control

E03 56 001001010101010100001 00100000 T5 JSR Auxiliary signal JSR/5

BRK JSR RTI RTS Push/

E04 57 000000010001010101000 0XX0X000 T2 Bus Control
pull

E05 58 010101011010100100000 10011000 T0 TYA Bus Control

E06 59 100000000000011000000 0XXXXXX1 T1 UPPER ODD Bus Control

E07 60 101010000000001000000 X11XXXX1 T1 ADC SBC Bus Control

E08 61 100000011001010010000 0XX0101X T1 ASL ROL LSR ROR Bus Control

E09 62 010101011001100010000 1000101X T0 TXA Bus Control

E10 63 011010011001010100000 01101000 T0 PLA Bus Control

E11 64 011001000000101000000 101XXXX1 T0 LDA Bus Control

E12 65 010000000000001000000 XXXXXXX1 T0 ALL ODD Bus Control

E13 66 011001011001100100000 10101000 T0 TAY Bus Control

E14 67 010000011001010010000 0XX0101X T0 ASL ROL LSR ROR Bus Control

E15 68 011001011001100010000 1010101X T0 TAX Bus Control

E16 69 011001100001010100000 0010X100 T0 BIT0 ALU Control (AND)

E17 70 011001000000011000000 001XXXX1 T0 AND0 ALU Control (AND)

E18 71 000000001010000000010 XXX11XXX T4 OP abs,XY Bus Control (ADL/ABL)

E19 72 000000010110001000001 XXX100X1 T5 OP ind,Y Bus Control (ADL/ABL)

35
F

<- Branch, additionally affected by the /

F01 73 010000010110000100000 XXX10000 T0 Auxiliary signal BR0
PRDY line (from the RDY contact),

F02 74 000110011001010101000 01001000 T2 PHA Bus Control (AC/DB)

F03 75 010010011001010010000 01X0101X T0 LSR ROR ALU Control (SR)

F04 76 000010000000010010000 01XXXX1X TX LSR ROR ALU Control (SR)

F05 77 000101010101010101000 00000000 T2 BRK PC Control

F06 78 001001010101010100100 00100000 T3 JSR PC Control

F07 79 000101000000101000000 100XXXX1 TX STA Auxiliary signal STA

F08 80 000000010110000101000 XXX10000 T2 BR2 (Branch T2) Схема управления PC и

F09 81 000000100100000001000 XXXX01XX T2 zero page Bus Control (DL/ADL)

F10 82 000000010100001001000 XXXX00X1 T2 ALU indirect Bus Control (DL/ADL)

The entire "right" half of the opcode

F11 83 000000001000000001000 XXXX1XXX T2 table (X8-XF values). The Push/Pull Auxiliary signal ABS/2
opcode exclusion operation is additional-

F12 84 001010010101010100001 01100000 T5 RTS Auxiliary signal RTS/5

F13 85 000000000000000000010 XXXXXXXX T4 T4 ANY Bus Control (NOADL)

F14 86 000000000000000000100 XXXXXXXX T3 T3 ANY Bus Control (NOADL)

F15 87 010100010101010100000 0X000000 T0 BRK RTI Bus Control (NOADL)

F16 88 010010101001010100000 01X01100 T0 JMP Bus Control (NOADL)

F17 89 000000010101001000001 XXX000X1 T5 OP X, ind Bus Control (NOADL,

The entire "right" half of the opcode

F18 90 000000001000000000100 XXXX1XXX T3 table (X8-XF values). The Push/Pull Bus Control (IND)
opcode exclusion operation is additional-

36
G

G01 91 000000010110001000010 XXX100X1 T4 OP ind, Y Cycle Counter Reset, Bus

G02 92 000000001010000000100 XXX11XXX T3 RIGHT ODD Cycle Counter Reset

G03 93 000000010110000100100 XXX10000 T3 BR3 (Branch T3) PC control circuit and PC

G04 94 000100010101010100000 0X000000 TX BRK RTI PC Control (JB)

G05 95 001001010101010100000 00100000 TX JSR PC Control (JB)

G06 96 000010101001010100000 01X01100 TX JMP PC Control (JB), ENDX (Long

P/P 129 000000011001010100000 0XX01000 TX <- Push/pull opcodes, used as an

For RW Control and to

G07 97 000101000000100000000 100XXXXX TX STORE
obtain an auxiliary STOR

G08 98 000101010101010100010 00000000 T4 BRK RW Control, !POUT (flags

G09 99 000101011001010101000 00001000 T2 PHP !POUT (flags control)

G10 100 000100011001010101000 0X001000 T2 Push RW Control, ENDX (Long

ENDX, Bus Control; Auxiliary

G11 101 000010101001010100010 01X01100 T4 JMP ind
signal JMP/4

G12 102 000010010101010100001 01X00000 T5 RTI RTS ENDX (Long instruction

G13 103 001001010101010100001 00100000 T5 JSR ENDX (Long instruction

37
H

ENDX (Long instruction

H01 104 000110101001010101000 01001100 T2 JMP abs
completion)

ENDX (Long instruction

H02 105 001000011001010100100 0X101000 T3 Pull
completion)

LSR ROR DEC INC DEX NOP (4x4

H03 106 000010000000000010000 X1XXXX1X TX Cycle Counter 5-6
bottom right)

Cycle Counter 5-6, flags

H04 107 000001000000010010000 00XXXX1X TX ASL ROL
control

H05 108 010010011010010100000 01X11000 T0 CLI SEI flags control

H06 109 101001100001010100000 0010X100 T1 BIT flags control

H07 110 010001011010010100000 00X11000 T0 CLC SEC flags control

H08 111 000000100110000000100 XXX101XX T3 Memory zero page X/Y MemOP

H09 112 101010000000001000000 X11XXXX1 T1 ADC SBC flags control

H10 113 011001100001010100000 0010X100 T0 BIT flags control

H11 114 011001011001010100000 00101000 T0 PLP flags control

H12 115 000110010101010100010 01000000 T4 RTI flags control

H13 116 100110000000101000000 110XXXX1 T1 CMP flags control

H14 117 100010101001100100000 11X01100 T1 CPY CPX abs flags control

H15 118 100001011001010010000 00X0101X T1 ASL ROL flags control

H16 119 100010000101100100000 11X00X00 T1 CPY CPX zpg/immed flags control

P/P 129 000000011001010100000 0XX01000 TX <- Push/pull opcodes, used as an

K01 120 010010011010100100000 11X11000 T0 CLD SED flags control

K02 121 000001000000000000000 X0XXXXXX TX /IR6 Branch Logic

K03 122 000000101001000000100 XXX011XX T3 Memory absolute MemOP

K04 123 000000100101000001000 XXX001XX T2 Memory zero page MemOP

K05 124 000000010100001000001 XXXX00X1 T5 Memory indirect MemOP

K06 125 000000001010000000010 XXX11XXX T4 Memory absolute X/Y MemOP

K07 126 000000000000010000000 0XXXXXXX TX /IR7 Branch Logic

K08 127 001001011010100100000 10111000 TX CLV flags control

IMPL. The Push/Pull opcode exclusion

operation is additionally applied to this
K09 128 000000011000000000000 XXXX10X0 TX line, right on the spot. Also, the mask for Bus Control (DL/DB)
this line does not take into account the
& ~IR0 operation

38
What Raw bits mean
If you think of a decoder as a 21x130 ROM, where each bit repre-
sents a transistor, then the Raw bits value will represent one line
of the decoder. This is why it is called the mask value.

For example, the picture shows the 5th line of the decoder. The bit
counting starts from bottom to top. 0 means no transistor, 1 means
present.

Online Decoder
You can use an online decoder to highlight opcodes: http://
breaknes.com/files/6502/decoder.htm (You can also find it
here: https://github.com/emu-russia/breaks/blob/master/
Docs/6502/decoder.htm)

In the Raw bits field you can insert the mask value from the table
above and when you press the Make IR Mask button you will get
the decoded mask value (e.g. 11X00X00). The decoded mask value
can be inserted into the IR field and when the Decode button is
pressed, the opcodes that correspond to the specified IR mask will
be highlighted in the table.

Branch T0 Skip
From pin RDY a special line /PRDY comes through the delay line. If the processor was not ready
when the previous instruction finished, then if the next instruction is a conditional branch, its
cycle 0 (T0) is skipped. The meaning of this operation is not known yet.

Why the decoder is so big and scary

Actually, there is nothing scary about it.

The decoder was compiled according to the requirements of random logic. Random logic is
divided into several parts (domains) and each part corresponds to its own zone in the decoder,
which was specially chosen so that the necessary opcodes were processed.

In other words - it is not random logic that adjusts to decoder, but vice versa. The impression
that the decoder is "more important" is formed simply because it is above random logic.

39
Notes in the margins for future revisions of the book.

40
Predecode

The circuit is designed to define the "class" of an instruction:

• A short instruction which is executed in 2 clock cycles (TWOCYCLE)

• An instruction of type IMPLIED which has no operands (takes 1 byte in memory)

41
The operation code received from the external data bus (D0...D7) is stored on the PREDECODE
latch (PD) during PHI2 (in inverted form), after which the precoding logic immediately deter-
mines the instruction class (the circuit is combinatorial).

The output /TWOCYCLE is used by a short cycle counter. The output /IMPLIED is used by the
PC increment logic.

The PD latch value is fed to the instruction register input in inverted form.

Also the control line 0/IR is fed to the Predecode logic input which "injects" the BRK operation
into the instruction stream. This occurs during interrupt processing, to initialize the BRK se-
quence (all interrupts simply mimic the BRK instruction, with slight modifications).

The pre-decode circuit works closely with the dispatcher, all control signals go there.

Logic
The corresponding gates are marked on the transistor schematic:

42
The predecoding logic is self-descriptive:

• 2-cycle instructions are: Direct operand instructions OR all single-byte instructions EXCEPT
push/pull instructions (specified by mask XXX010X1 + 1XX000X0 + XXXX10X0 - 0XX0XX0X)
• Single-byte instructions are set by mask XXXX10X0

TWOCYCLE instructions:

IMPLIED instructions:

43
Notes in the margins for future revisions of the book.

44
Interrupt Processing

Interrupt processing includes the following circuits:

• NMI edge detection

• Cycle counter 6-7 for interrupt handling
• Setting the low-order bits of the interrupt vector address (ADL0-3)
• Circuit for issuing internal signal DORES.
• B Flag

Three signals /NMIP, /IRQP and RESP come to the input of the circuits from the corresponding
input pads.

NMI Processing
Transistor circuit (includes cycle counter 6-7 and NMI edge detector):

45
Interrupt vector address and Reset FF
Transistor circuit:

The circuit for getting the control signal DORES ("Do Reset") (which is binned to all other inter-
nals) is combined here with the interrupt vector setting circuit to save space.

46
B Flag
Transistor circuit:

47
Logic
Interrupt handling schematic:

48
To handle interrupts an additional circuit is required to generate cycles 6 and 7 (because they do
not come from the decoder) (control signals BRK6E and BRK7). And the control signal BRK6E
("Break Cycle 6 End") starts during PHI2 of cycle 6 and ends during PHI1 of cycle 7. This is done
to determine the edge of the /NMI signal.

The detection of the /NMI edge is done by a classic edge detection circuit based on two RS trig-
gers.

The /RES signal is additionally stored on RESET FLIP/FLOP, because it is required for other ran-
dom logic circuits (particularly for special control of the R/W pin).

The arrival of any interrupt is reflected on flag B, the output of which (B_OUT) forces the proces-
sor to execute a BRK instruction (operation code 0x00). This way the developers have unified the
handling of all interrupts.

The last small circuit forms the address (or vector) of the interrupts (control signals 0/ADL0, 0/
ADL1 and 0/ADL2), which control the lowest 3 bits of the address bus.

Schematic for setting the address of the interrupt handler:

49
Notes in the margins for future revisions of the book.

50
Random Logic

The name has nothing to do with random numbers, it simply reflects the essence of randomly
scattered circuits here and there.

This logic is the thinking organ of the processor and completely determines its behavior when
processing and executing instructions.

From the hardware point of view, the random logic is a "handmade" product of MOS engineers,
which is a mess of transistors and wires. Therefore, it would be more correct to use the name
"chaotic logic" instead of random logic.

There is no need to give a full-size transistor circuit here, because it will be easier to master it by
component parts.

Below you can see all the function blocks of the random logic:

• Register control
• ALU control
• Program counter (PC) control
• Bus control
• Execution logic (dispatch)
• Flags control logic
• Flags
• Conditional branch logic

51
Principle of Operation
In general, the operation of the logic is quite complex (did you think I would say simple
again? :smiley:):

• The execution logic (dispatch) conducts the work of the entire processor. It determines
when to terminate an instruction and also controls the PC increment and the cycle counter.
Additionally it includes a processor readiness circuit (RDY) which is controlled by the RDY
pin.
• After the execution logic has started executing the next instruction - the code of that in-
struction as well as the current cycle is fed to the decoder
• Depending on the results of decoding the control circuitry of registers, ALU, PC and buses
give outward to the lower part special control commands
• Additionally, the behavior of the processor is affected by its flags as well as interrupt han-
dling logic. And flags are also affected by executable instructions.

All this is closely coupled to control the lower part of the processor, where its context (registers),
ALU and communication with the outside world via buses are located.

52
Notes in the margins for future revisions of the book.

53
Auxiliary Signals
This section contains a table of auxiliary signals exchanged between all parts of the random logic (for reference):

Name From To Description

ACRL1 Dispatch Dispatch One of the ACR Latch outputs

ACRL2 Dispatch Bus Control One of the ACR Latch outputs

AND ALU Control Bus Control Used when forming an ALU ANDS command

BR2 Decoder PC Control, PC Increment Branch T2

BR3 Decoder PC Control, PC Increment Branch T3

Branch Logic, ALU

BRFW PC Control Branch forward (whenever taken)
Control

BRK5 Decoder Interrupts, Regs Control Used to obtain the STKOP signal and also goes into the interrupt handling circuit

BRK6E Interrupts ALU Control, Bus Control BRK6 (cycle 6 of the interrupt sequence), during the half-step PHI2

/BRTAKEN Branch Logic PC Control Branch taken

C_OUT Flags ALU Control Flag C value

/C_OUT Flags ALU Control Flag C value (inverted)

DL/PCH PC Control Bus Control Intermediate signal

D_OUT Flags ALU Control Flag D value

Regs Control, ALU Control, Bus

JSR2 Decoder To obtain the JSXY signal and other bus control circuits
Control

/JSR2 Bus Control Regs Control Intermediate signal, JSR2 inversion

IMPL Decoder ALU Control Decoder X128. Additionally modified with Push/Pull (X129) and IR0 signals.

INC_SB ALU Control Bus Control Intermediate signal ("Increment SB")

NOADL Bus Control ALU Control Intermediate signal ("No ADL")

PC/DB PC Control Dispatch Auxiliary output signal for the RW Control circuit that is part of the dispatcher

PGX Bus Control ALU Control Intermediate signal ("Page X")

/ready Dispatch All Global internal processor readiness signal

RTI/5 Decoder Regs Control, ALU Control Used to obtain STKOP and NOADL signals

SBXY Regs Control Bus Control Intermediate signal ("SB Bus X,Y")

STK2 Decoder Regs Control, ALU Control Auxiliary signal from decoder (X35)

STKOP Regs Control ALU Control Intermediate signal ("Stack Operation")

Regs Control, ALU Control, RW

STOR Dispatcher Intermediate signal
Control

STXY Regs Control Bus Control Intermediate signal ("Store X,Y")

T0 Short Cycle Counter All Processor in the T0 instruction execution cycle

T1 PC Control All Processor in the T1 cycle

T2 Decoder All Processor in the T2 cycle

T5 Long Cycle Counter All Processor in the T5 cycle

T6 Long Cycle Counter All Processor in the T6 cycle

ZTST Bus Control Flags Control Intermediate signal ("Z Test")

54
Registers Control

Most likely this control circuit will be observed first, so I will write here: be prepared to see a
large number of intermediate signals in the control circuits, which can come sometimes from all
other parts of the random logic. A summary table of all the intermediate signals can be found in
the main section with the random logic overview.

The register control circuit is responsible for generating control commands to exchange registers
with the internal buses.

55
Inputs:

Signal Description

X0-X26 Outputs from the decoder

/JSR2 Intermediate signal from the bus control circuit

STK2 Just an auxiliary signal from another part of the decoder (X35)

STOR Auxiliary signal from the dispatcher circuit

/ready Global processor readiness signal

Outputs:

Signal Description

SBXY Intermediate signal for bus control circuitry

STXY Intermediate signal for bus control circuitry

STKOP Intermediate signal ("Stack Operation") for the ALU control circuit

#Y/SB Intermediate signal to latch, to obtain a Y/SB command

#X/SB Intermediate signal to latch, to obtain a X/SB command

#SB/X Intermediate signal to latch, to obtain a SB/X command

#SB/Y Intermediate signal to latch, to obtain a SB/Y command

#S/SB Intermediate signal to latch, to obtain a S/SB command

#S/ADL Intermediate signal to latch, to obtain a S/ADL command

#SB/S Intermediate signal to latch, to obtain a SB/S command

BRK5 Output X22 from decoder. Used to obtain the STKOP signal and also goes to the interrupt circuitry

RTI/5 Output X26 from decoder. Used to obtain STKOP and NOADL signals

The TXS (X13) signal is used within this circuit and does not go outside.

56
The intermediate signals from the register control circuitry go to the input of the control com-
mand latches:

Register control commands:

Command Description

X/SB Place the value of register X on the SB bus

Y/SB Place the value of register Y on the SB bus

SB/X Place the SB bus value on the X register

SB/Y Place the SB bus value on the Y register

S/SB Place the value of register S on the SB bus

S/ADL Place the value of register S on the ADL bus

SB/S Place the SB bus value on the S register

S/S Refresh the value of the S register. The S/S control command is obtained by a complement of the SB/S signal

57
Logic

58
Notes in the margins for future revisions of the book.

59
ALU Control

The ALU control is designed to generate ALU control commands.

Intermediate Signals
/ROR SR AND CSET

60
Table of auxiliary and intermediate signals, which are found further in the schematics:

Signal Description

/ROR Intermediate signal, used in the ADD/SB7 circuit

SR Intermediate signal

AND Intermediate signal

T0 Comes from the cycle counter of short instructions

T5 Comes from the cycle counter of long instructions

/C_OUT Flag C value (inverted value)

CSET Intermediate signal ("Carry Set"), used in the main ALU control circuit

STK2 Decoder X35

RET Decoder X47

SBC0 Decoder X51

JSR2 Decoder X48

/BR3 Decoder X93 (inverted value). The inversion circuit was lost somewhere in the optimization process.

BRK6E Comes from the interrupts processing circuit

STKOP Comes from register control circuitry

/ready Global internal processor readiness signal

INC_SB Intermediate signal ("Increment SB"), used in the main control circuitry as well as in the bus control circuitry

JSR/5 Decoder X56

PGX Comes from the bus control circuitry

NOADL Comes from the bus control circuitry

BRFW Comes from the conditional branch logic

T1 Comes from the PC increment circuit (see dispatcher)

T6 Comes from the cycle counter of long instructions

D_OUT Flag D value

C_OUT Flag C value

61
ALU Сontrol (Main Part)
The circuit is a mess of gates and 4 latches to generate the input carry for the ALU (control sig-
nal /ACIN).

62
BCD Correction Control
BCD correction is applied in the following cases:

• If the BCD mode is enabled with flag D and the current instruction SBC (control signal
DSATemp)
• If the BCD mode is enabled with flag D and the current instruction ADC (control signal
DAATemp)

ADD/SB7
The attentive reader will notice that the processor has support for bit rotation instructions (ROL/
ROR). The additional processing associated with these instructions is just handled by this circuit.

63
ALU Control Commands

Command Description

Setting the ALU input values

NDB/ADD Load inverse value from DB bus to the BI latch

DB/ADD Load direct value from DB bus to the BI latch

0/ADD Write 0 to the AI latch

SB/ADD Load a value from the SB bus to the AI latch

ADL/ADD Load a value from the ADL bus to the BI latch

ALU operation commands

ANDS Logical AND operation (AI & BI)

EORS Logical XOR operation (AI ^ BI)

ORS Logical OR operation (AI | BI)

SRS Shift Right

SUMS Summation (AI + BI)

Control commands of the intermediate ALU result

ADD/SB06 Place the value of the ADD latch on the SB bus (bits 0-6)

ADD/SB7 Place the value of the ADD latch on the SB bus (bit 7)

ADD/ADL Place the ADD latch value on the ADL bus

Additional signals

/ACIN Input carry

/DAA Perform correction after addition

/DSA Perform correction after subtraction

64
Logic

65
Notes in the margins for future revisions of the book.

66
Program Counter Control

The program counter (PC) control circuitry is designed to generate control commands to ex-
change the PC value and the internal buses ADL, ADH and DB.
Nearby is the PC increment circuit, which is discussed in another section on dispatcher.

Transistor circuit for obtaining intermediate signals:

67
Output latches and control commands:

Inputs:
Signal Description

BR0 Decoder X73. Additionally modified with the /PRDY signal

BR2 Decoder X80

BR3 Decoder X93

T0 Comes from the cycle counter of short instructions

T1 Comes from the PC increment circuit (see dispatcher)

ABS/2 Decoder X83. Additionally modified with Push/Pull signal (X129)

RTS/5 Decoder X84

JSR/5 Decoder X56

/ready Global internal processor readiness signal

Outputs:
Signal Description

DL/PCH Auxiliary output signal for DL/ADH bus control circuitry

PC/DB Auxiliary output signal for the RW Control circuit that is part of the dispatcher

Control commands:
Command Description

ADH/PCH Load ADH bus value into the PCHS latch

PCH/PCH If ADH/PCH is not running, this command is executed (refresh PCH)

PCH/ADH Write the PCH register value to the ADH bus

PCH/DB Write the PCH register value to the DB bus

ADL/PCL Load the ADL bus value into the PCLS latch

PCL/PCL If ADL/PCL is not running, this command is executed (refresh PCL)

PCL/ADL Write the PCL register value to the ADL bus

PCL/DB Write the PCL register value to the DB bus

68
Logic

69
Notes in the margins for future revisions of the book.

70
Bus Control

Bus control is most of all "scattered" around the processor surface. It is easiest to describe all the
bus control commands first, and then to look at the corresponding circuits individually.

Bus control commands:

Command Description

External address bus control

ADH/ABH Set the high 8 bits of the external address bus, in accordance with the value of the internal bus ADH

ADL/ABL Set the low-order 8 bits of the external address bus, in accordance with the value of the internal bus ADL

ALU connection to SB, DB buses

AC/DB Place the AC value on the DB bus

SB/AC Place the value from the SB bus/BCD correction circuit into the accumulator

AC/SB Place the AC value on the SB bus

Control of the SB, DB and ADH internal buses

SB/DB Connect the SB and DB buses

SB/ADH Connect SB and ADH buses

0/ADH0 Forced to clear the ADH[0] bit

0/ADH17 Forced to clear the ADH[1-7] bits

External data bus control

DL/ADL Write the DL value to the ADL bus

DL/ADH Write the DL value to the ADH bus

DL/DB Exchange the value of the DL and the internal bus DB. The direction of the exchange depends on the operating mode of

The motive of all the circuits is roughly as follows:

• The control circuits get a lot of input from the decoder and other auxiliary signals
• All circuits are mostly combinatorial (no triggers, just a mess of gates)
• The outputs from the control circuits go to the output latches of the commands to control
the lower part of the processor.

71
Auxiliary Signals
Circuits for obtaining auxiliary signals:

NOADL и IND JSXY

In the IND circuit the decoder output X90 is additionally modified by the Push/Pull signal (X129).

72
The other auxiliary and intermediate signals that can be found in the schematics in this section:

Signal Description

RTS/5 Decoder X84

RTI/5 Decoder X26

STXY Comes from register control circuitry

BR0 Decoder X73. Additionally modified with the /PRDY signal

T5 Comes from the cycle counter of long instructions

T6 Comes from the cycle counter of long instructions

PGX Output signal from ADL/ABL circuit

JSR/5 Decoder X56

T2 Decoder X28

!PCH/PCH Comes from the PC control circuitry

SBA The signal comes out of the #SB/ADH circuit, used in the #ADH/ABH circuit

/ready Global internal processor readiness signal

BR3 Decoder X93

0/ADL0 Comes from the interrupt vector setting circuit

AND Comes from the ALU control circuit

STA Decoder X79

STOR Intermediate signal from the dispatcher

SBXY Comes from a register control circuit (not to be confused with STXY)

T1 Comes from the PC increment circuit (see dispatcher)

BR2 Decoder X80

ZTST Output signal for flags control from SB/DB circuit

ACRL2 One of the ACR Latch outputs

T0 Comes from the cycle counter of short instructions

ABS/2 Decoder X83. Additionally modified with Push/Pull signal (X129)

JMP/4 Decoder X101

IMPL Decoder X128. Additionally modified with Push/Pull (X129) and IR0 signals.

JSR2 Decoder X48

/JSR Inversion of JSR2 for the register control circuit

BRK6E Comes from the interrupts processing circuit

INC_SB Comes from the ALU control circuit

DL/PCH Comes from the PC control circuitry

The signals are arranged in the order they appear in the schematics.

73
External Address Bus Control
Circuits for the generation of intermediate signals:

#ADL/ABL #ADH/ABH (1) #ADH/ABH (2)

The first piece of the #ADH/ABH circuit is to the right of flag B, the second piece is in the inter-
rupt address generation circuitry. The #ADH/ABH signal connects directly between these two
pieces.

The output latches of the ADL/ABL and ADH/ABH control commands:

74
ALU Connection to SB, DB
Circuits for the generation of intermediate signals:

#AC/DB #SB/AC, #AC/SB

AC/DB, SB/AC, AC/SB control command output latches:

75
SB, DB, ADH Control
Circuits for generating intermediate signals (for 0/ADH0 you get the control command at once):

#SB/DB (also #0/ADH17) 0/ADH0 #SB/ADH

SB/DB, SB/ADH, 0/ADH17 control command output latches:

(0/ADH0 above)

76
External Data Bus Control
Circuits for the generation of intermediate signals:
#DL/ADL #DL/DB (1) #DL/DB (2)

The first piece of #DL/DB circuitry is next to the ACR Latch, the second piece is right inside the ALU control
circuitry. The #DL/DB signal connects directly between these two pieces.

DL/ADL, DL/ADH, DL/DB control command output latches:

77
Logic

78
Notes in the margins for future revisions of the book.

79
Dispatcher

The execution logic (dispatcher) is the key mechanism of the processor that "directs" the execu-
tion of instructions.

The execution logic consists of the following circuits:

• Intermediate signals
• Processor readiness control
• R/W pad control
• Short instruction cycle counter (T0-T1)
• Cycle counter for very long instructions (T5-T6)
• Instruction completion circuit
• ACR latch
• Program counter (PC) increment circuit
• Opcode fetch circuit (Fetch)

Long instruction cycle counter (T2-T5) is discussed in the corresponding section.

Intermediate Signals
Intermediate signals are obtained from the decoder outputs without any regularity. It was very
difficult to separate them from the intermediate signals of the other control circuits, because of
the chaotic connections.

BR2 BR3, D91_92 /MemOP STORE, STOR /SHIFT

80
Processor Readiness

The /ready is the global ready signal of the processor, derived from the RDY input signal which
comes from the corresponding contact.

R/W Control

• REST: Reset cycle counters

• WR: The processor is in write mode

81
Short Cycle Counter

• T0: Internal signal (processor in T0 cycle)

• /T0, /T1X: Coming to decoder input

Very Long Cycle Counter

• T5, T6: The processor is in cycle T5/T6

82
Instruction Completion

ENDS: Complete the short instructions

ENDX: Complete long instructions

TRES2: Reset extra instruction counter

TRESX: Reset Cycle Counters

83
ACR Latch

Outputs 2 internal intermediate signals: ACRL1 and ACRL2.

84
Increment PC

The circuit contains 3 "branches" of combinatorial logic, which finally form the control command
to increment PC (#1/PC).
The circuit also generates the following signals:

• T1: Processor in cycle T1

• TRES1: Reset short instruction cycle counter

Opcode Fetch

• FETCH: Fetch opcode to instruction register

• 0/IR: Inject BRK operation code, for interrupt handling

85
Logic

86
Notes in the margins for future revisions of the book.

87
Flags Control

The flag control circuits are divided into two parts for convenience:

• Intermediate control signals from the decoder (opcode selection)

• Flag control signals

As you can guess, the purpose of the circuit is to control processor flags, depending on the cur-
rently executed instruction.

I think it makes sense to show here the relevant part of the wonderful 6502 circuit made by Don-
ald F. Hanson:

(The missing 0/V signal has been corrected in the schematic)

88
Opcode Selection

Input signals:

• /T0: Processor executes cycle T0 of the current instruction

• /T1X: Processor executes T1 cycle of the current instruction
• T6: Processor executes T6 cycle of current instruction

Output signals:

Signal Decoder outputs Dedicated instructions

!POUT 98,99 Working with flags outward (saving context after interrupt, PHP instruction)

/CSI 108 Instructions CLI, SEI

BIT1 109 Instruction BIT, cycle T1

The 110th decoder output (instructions CLC, SEC), for convenience is left in these circuits. It just goes on to the main
X110 110
flag control circuitry.

AVR/V 112 Instructions ADC, SBC. This signal is the control signal for flag V

/ARIT 107,112,116-119 Matrix of comparison (CMP, CPX, CPY) and shift instructions (ASL, ROL) where flags are used

BIT0 113 Instruction BIT, cycle T0

!PIN 114,115 Working with flags inside (context loading after RTI, instruction PLP)

/CSD 120 Instructions CLD, SED

CLV 127 Instruction CLV

All of these control signals (except AVR/V) are intermediate signals and are not used anywhere
else except for the flag control circuitry.

89
Flags Control

Input signals:

Signal Purpose

/CSI see above

X110 see above

!POUT see above

BIT1 see above

ZTST Comes from SB/DB bus control circuitry

/ARIT see above

SR Shift instruction from ALU control logic

/ready Global internal processor readiness signal

!PIN see above

BIT0 see above

/CSD see above

CLV see above

90
Output Flag control signals:
Signal Flag Purpose

IR5/C C Change the value of the flag according to the IR5 bit

ACR/C C Change the value of the flag according to the ACR value

DB/C C Change the value of the flag according to DB0 bit

DBZ/Z Z Change the value of the flag according to the /DBZ value

IR5/I I Change the value of the flag according to the IR5 bit

IR5/D D Change the value of the flag according to the IR5 bit

DB/V V Change the value of the flag according to DB6 bit

0/V V Clear flag V

DB/N N Change the value of the flag according to DB7 bit

P/DB All Place the value of the flags register P on the DB bus

DB/P All Place the DB bus value on the flag register P

The control signal 1/V is obtained by the input contact SO and is not shown here.

Logic

91
Notes in the margins for future revisions of the book.

92
Flags

The flags (bits of the P register) are in "scattered" form, as several circuits of the upper part of
the processor.

The flags are controlled by the flags control circuit.

Flag B is treated separately in the section on interrupt handling. Topologically it is also located in
another part of the processor.

C Flag

• IR5/C: Change the flag value according to the IR5 bit (applies during execution of the SEC
and CLC instructions)
• ACR/C: Change the flag value according to the ACR value
• DB/C: Change the value of the flag according to the bit DB0
• /IR5: Inverted IR5 value
• /DB0: Input value from DB bus, in inverted form
• ACR: Result of a carry from the ALU (/ACR: in inverted form for dispatcher)
• /C_OUT: Output value of flag C, in inverted form

93
D Flag

• Change the flag value according to the IR5 bit (applied during execution of SED and CLD
instructions)
• DB/P: Common control signal, place the DB bus value on the flag register P
• /IR5: IR5 bit value, in inverted form
• /DB3: Input value from the DB bus, in inverted form
• /D_OUT: Output value of flag D, in inverted form

I Flag

• IR5/I: Change the flag value according to the IR5 bit (applied during execution of SEI and
CLI instructions)
• DB/P: Common control signal, place the DB bus value on the flag register P
• /IR5: IR5 bit value, in inverted form
• /DB2: Input value from the DB bus, in inverted form
• /I_OUT: Output value of flag I, in inverted form. This signal goes to two places: to the inter-
rupt processing circuit and to the circuit for exchanging flag register values with the DB bus
(below).

94
N Flag
• DB/N: Change the flag value according to DB7
• /DB7: Input value from DB bus, in inverted form
• /N_OUT: Output value of flag N, in inverted form

V Flag

• 0/V: Clear flag V (applies during execution of CLV instructions)

• 1/V: Set flag V. Forced flag setting is done by the SO pin.
• AVR/V: Change the value of the flag according to the AVR value
• DB/V: Change the flag value according to DB6
• AVR: Overflow result from the ALU
• SO: Input value from pin SO
• /DB6: Input value from DB bus, in inverted form
• /V_OUT: Output value of flag V, in inverted form

Z Flag

• DBZ/Z: Change the flag value according to the /DBZ value

• DB/P: Common control signal, place the DB bus value on the flag P register
• /DBZ: Control signal from the flag exchange circuit with the DB bus (check that all bits of
the DB bus are 0)
• /DB1: Input value from the DB bus, in inverted form
• /Z_OUT: Output value of flag Z, in inverted form

95
Flags I/O

• C_OUT: Flag C value in direct form, used in ALU control circuit (in the circuit to form the
ADD/SB7 signal)
• D_OUT: Flag D value in direct form, used in the ALU control circuit (to form BCD correction
signals DAA/DSA)
• P/DB: Place the P flag register value on the DB bus
• /DB0-7: The value of the DB bus bits, in inverted form. It is fed to the input of the corre-
sponding bits of the P register.
• /DBZ: Check that all DB bus bits are 0 (i.e. checking the value to 0). It is used by the Z flag.
Correspondence of the bits of the DB bus and the flag register P:

DB Bit Flag

0 C

1 Z

2 I

3 D

4 B

5 -

6 V

7 N

Flag 5 is not used. The DB5 bit is not changed (not connected) when saving the register P to the
DB bus. However, the value of the DB5 bit is checked by the /DBZ control signal (to compare the
value on the DB bus with zero).

96
Logic

97
Notes in the margins for future revisions of the book.

98
Branch Logic

The logic of conditional branches determines:

• Whether the branch went forward or backward

• Whether a branch occurred at all

The branch direction is determined by the 7th bit of the branch instruction operand (relative
offset) which is stored on the internal data bus (DB). If the 7th bit is 1, it means that branch is
made "backwards" (PC = PC - offset).

The branch is checked according to the branch instruction (which differs by 6 and 7 bit of the
operation code) as well as the flags: C, V, N, Z.

Branch Forward

The BRFW trigger is updated with the value D7 during BR3.PHI1. The rest of the time the trigger
stores its current value. The value of the trigger is output as a BRFW control signal to the Pro-
gram Counter (PC) control circuit.

The BR2 is the X80 output of the decoder.

99
Branch Taken

The combinatorial logic first selects by IR6/IR7 which group the branch instruction belongs to
(i.e. which flag it checks) and the subsequent XOR selects how the branch instruction is triggered
(flag set/reset). The output of /BRTAKEN is in inverse logic, that is, if branch is triggered, then /
BRTAKEN = 0. The consumer of the /BRTAKEN signal is also the PC control circuit.

Inputs /IR6 and /IR7 are decoder outputs X121 and X126 respectively. The /IR5 input comes
directly from the instruction register.

Note: The Branch Taken logic operates continuously and the value of the /BRTAKEN control line
is updated every cycle, regardless of which instruction is being processed by the processor at the
time.

Logic

100
Notes in the margins for future revisions of the book.

101
Control Commands

"Control Commands" is the conventional name for the large number of control signals that go
from the top of the processor to the bottom and control the context (registers, buses, and ALU).

102
The control commands for the flag register are discussed in the corresponding section on flag
management, since they do not go beyond the top of the processor.

Each control signal usually contains an output latch and sometimes a special "cutoff" transistor
that turns the signal off at a certain half-cycle (usually some of the signals are turned off during
PHI2). This is because the internal buses are pre-charged during PHI2, and the registers are usu-
ally "refreshed" at that time.

Most signals have names like A/B which means that the line "connects" A to B. For example SB/X
means that the value from the internal bus SB is placed in register X.

103
List
All commands are discussed in more detail in their respective sections. The summary table is just
for reference.
Name PHI1 PHI2 Description

Register control commands

Y/SB √ Y => SB

SB/Y √ SB => Y

X/SB √ X => SB

SB/X √ SB => X

S/ADL √ √ S => ADL

S/SB √ √ S => SB

SB/S √ SB => S

The S/S command is active if the SB/S command is inactive. This command simply "refreshes" the
S/S √
current state of the S register.

ALU control commands

NDB/ADD √ ~DB => BI

DB/ADD √ DB => BI

0/ADD √ 0 => AI

SB/ADD √ SB => AI

ADL/ADD √ ADL => BI

/ACIN √ √ ALU input carry. The ALU also returns the result of carry (ACR) and overflow (AVR)

ANDS √ √ AI & BI

EORS √ √ AI ^ BI

ORS √ √ AI

SRS √ √ >>= 1

SUMS √ √ AI + BI

/DAA √ √ 0: Perform BCD correction after addition

/DSA √ √ 0: Perform BCD correction after subtraction

ADD/SB7 √ √ ADD[7] => SB[7]. Be careful, all output values are inverse latch values, except for ADD/SB7.

ADD/SB06 √ √ ADD[0-6] => SB[0-6]

ADD/ADL √ √ ADD => ADL

SB/AC √ SB => AC

AC/SB √ AC => SB

AC/DB √ AC => DB

104
 Program counter (PC) control

#1/PC √ √ 0: Increment the program counter

ADH/PCH √ ADH => PCH

PCH/PCH √ If ADH/PCH is not performed, this command is performed (refresh PCH)

PCH/ADH √ √ PCH => ADH

PCH/DB √ √ PCH => DB

ADL/PCL √ ADL => PCL

PCL/PCL √ If ADL/PCL is not performed, this command is performed (refresh PCL)

PCL/ADL √ √ PCL => ADL

PCL/DB √ √ PCL => DB

Bus control commands

ADH/ABH √ √ ADH => ABH

ADL/ABL √ √ ADL => ABL

0/ADL0, 0/ADL1, 0/ADL2 √ √ Reset some of the ADL bus bits. Used to set the interrupt vector.

0/ADH0, 0/ADH17 √ √ Reset some of the ADH bus bits

SB/DB √ √ SB <=> DB, connect the two buses

SB/ADH √ √ SB <=> ADH

DL latch control commands

DL/ADL √ √ DL => ADL

DL/ADH √ √ DL => ADH

DL/DB √ √ DL <=> DB

PHI2 Pullup
On the left side is a small circuit to pull up PHI2 (which is used by a lot of cutoff transistors, so it
must be quite powerful):

It doesn't carry any logical meaning, but it looks cool.

105
106
Address Bus

Although the 6502 communicates with the outside world on a 16-bit address bus, but because
the processor is 8-bit in nature, the address bus is internally divided into two 8-bit halves: an
upper (ADH) and a lower (ADL).

The internal ADH/ADL address bus connects to the external 16-bit bus (pins A0-A15) through
registers ABH/ABL, which contain the last written value (address that has been set).

The address bus is unidirectional. It can only be controlled by the 6502.

Transistor circuit of the lower bits of the ABL (0-2):

(The schematic is the same for ABL1 and ABL2 bits)

The remaining ABL bits (3-7):

107
ABH bits:

Control commands:

• 0/ADL0, 0/ADL1, 0/ADL2: The lower 3 bits of the ADL bus can be forced to zero by com-
mands when setting interrupts vector
• ADL/ABL: Place the value of the internal ADL bus on the ABL register
• ADH/ABH: Place the ADH internal bus value on the ABH register

108
Circuit Flow
Consider the behavior of the circuit when ADL = 0:

• The flip/flop of the ABL bit is organized on two inverters (not2 and not3) with not2 acting
simultaneously as a DLatch (whose input Enable is connected to PHI2)
• PHI2: FF is "refreshed" in this half-step.
• PHI1: In this half-step the old FF value is "cut off" by the PHI2 tristate (located to the left of
not2) and the new FF value is loaded from the ADL bus (inverted, see not1) but only if an
ADL/ABL command is active
• The output from not2 organizes the final generation of the output value for the external
address bus. This part of the circuit contains an inverter not3 to form the FF and also an
inverter not4 which controls the amplifier "comb" of the Ax contacts

Logic
On the logic circuits PHI2 is not used, and FF organized on two inverters is replaced by a regular
trigger.

109
Notes in the margins for future revisions of the book.

110
Data Bus

The circuits for working with the external data bus consist of 8 identical pieces:

(The circuit is shown for bit 0, the rest are the same)

• DOR: The DOR latch stores the output value to be placed on the D0-D7 bus pins. If RD=1
the complementary output lines with DOR are cut off, so the whole output part becomes
floating.
• DL: The DL latch stores the input value
• Next to the control signal DL/DB you can see the precharge transistor for the internal bus
DB

Control signals:

• DL/ADL: Place the DL latch value on the internal ADL bus

• DL/ADH: Place the DL latch value on the internal ADH bus
• DL/DB: In read mode (RD=1), the value from the DL latch is placed on the internal DB bus.
In write mode (RD=0) the value from the DB bus is placed on the DOR latch

The external data bus (pins D0-D7) is also directly connected to the input of the predecode cir-
cuit.

111
WR Latch
From the R/W control circuit, the latch circuit receives a control signal WR. The circuit outputs a
control signal RD which controls the direction of the external data bus.

112
Notes in the margins for future revisions of the book.

113
Registers

The X and Y registers are used for index addressing. Register S is a stack pointer and the stack is
located at addresses 0x100 ... 0x1FF (on the first page).

Schematically the X, Y and S registers consist of 8 identical chunks (bits):

(In the schematic above, replace SB0 and ADL0 with SBx and ADLx for the remaining register
bits)

Each register bit is based on a trigger, loading and unloading of values on the buses is done by
control signals:

• Y/SB: Place the value of the register Y on the SB bus

• SB/Y: Load the Y register value from the SB bus
• X/SB: Place the value of the register X on the SB bus
• SB/X: Load the X register value from the SB bus
• S/ADL: Place the value of register S on the ADL bus
• S/SB: Place the S register value onto the SB bus
• SB/S: Load the S register value from the SB bus
• S/S: Refresh S register, active when SB/S = 0

So the registers can only connect to two buses: SB and ADL.

114
Logic

• During PHI1 the X and Y registers output their value to the SB bus / are overloaded with
new values from the SB bus.
• The S register has an input latch and an output latch. During PHI1 the value from the out-
put latch is placed on the SB or ADL buses and the input latch is either loaded with a new
value from the SB bus or refreshed from the output latch (S/S).
• During PHI2 the X and Y registers "store" their old value as the control signals disconnect
them from the bus.
• The S register simply outputs its value to the S or ADL bus during PHI2. The input latch is
overridden because the exchange commands are disabled during PHI2.

The SB and ADL buses are precharged during PHI2. This is done because it takes longer to
"charge" the bus than to "discharge" it. Therefore, when the bus is not needed - it is precharged,
so that it does not have "floating" values. If the value placed on the bus is 1, then the bus is al-
ready prepared ("charged") in advance. If the value placed on the bus is 0, then the bus is
"discharged" to ground.

In modern processors the task of precharging the bus is done by dedicated standard cells called
Bus Keeper.

In the transistor schematic above you can only see the transistors to charge the SB bus (located
in the circuit for the S register bits). The transistors to precharge the ADL bus are scattered next
to the program counter (PC).

115
Notes in the margins for future revisions of the book.

116
ALU

It is not possible to show the whole ALU circuit, so let's saw it into its component parts and con-
sider each one separately.

The ALU consists of the following components:

• Input circuits for AI/BI latch loading

• The main computational part (Operations)
• A fast carry calculation circuit for the BCD
• Intermediate result (ADD latch)
• BCD correction circuit
• Accumulator (AC)

Generally speaking the ALU is a mess of transistors and wires, but its workings are not very com-
plicated, as you can see later.

117
118
119
AI/BI Latches
The input circuits consist of 8 identical chunks, which are designed to load input values on the AI
and BI latches:

Control signals:

• DB/ADD: Load direct value from DB bus to the BI latch

• NDB/ADD: Load inverse value from DB bus to the BI latch
• ADL/ADD: Load a value from the ADL bus to the BI latch
• SB/ADD: Load a value from the SB bus to the AI latch
• 0/ADD: Write 0 to the AI latch

(The picture shows the circuit for bit 0, the rest are the same)

Computational Part
The ALU uses an inverted carry chain, so the even and odd bit circuits alternate.

Bit 0 is slightly different from the other even bits because it has an input carry (/ACIN) and no
SRS input.

Schematic for bit 0:

Schematics for bits 1, 3, 5, 7:

(The circuit for bit 1 is shown, the rest are the same)

120
Schematics for bits 2, 4, 6:

(The circuit for bit 2 is shown, the rest are the same)

Anatomically, the left side deals with logical operations, the right side is the adder (Full Adder),
and in the middle is the carry chain.

Control signals for ALU operations:

• ORS: Logical OR operation (AI | BI)

• ANDS: Logical AND operation (AI & BI)
• EORS: Logical XOR operation (AI ^ BI)
• SRS: Shift Right. For this the result of the current nand operation is stored as the result of
the previous bit.
• SUMS: Summation (AI + BI)

Notations on the schematics:

• nand: intermediate result of NAND operation for the selected bit

• and: intermediate result of AND operation for the selected bit (obtained by nand inversion)
• nor: intermediate result of NOR operation for a selected bit
• xor: intermediate result of EOR operation for the selected bit
• nxor: intermediate result of an ENOR operation for the selected bit
• carry: the result of a carry operation. The carry chain is inverted every bit, but for simplicity
all carry names do not consider value inversion.
• res: the result of a logical operation or the result of an adder which is then stored on the
ADD latch. The result of an operation in inverted form.

121
To make it clearer how the intermediate results are obtained, all the main motifs are marked in
the image below:

(Bit 1 is shown, for the other bits the motif looks similar)

Logic for even bits:

122
Logic for odd bits:

Overflow calculation (control signal AVR):

123
Fast BCD Carry
This is the circuit that appears in patent US 3991307 (https://patents.google.com/patent/
US3991307A).

The schematics are "layered on the side" for easy perception.

DC3 output is connected to the carry chain as follows:

How exactly this circuit works is written in the patent, I have nothing much to add. Just a mish-
mash of logic gates - do the same and it will work.

Besides calculating the carry for BCD the circuit also generates the ACR (ALU carry for flags) and
DAAH control signals for the BCD correction circuit.

124
Logic:

Intermediate Result (ADD)

The intermediate result is stored on the ADD latch (stored in inverted form, output to the buses
in direct form). The ADD latch circuit consists of 8 identical pieces:

(The circuit is shown for bit 0, the others are the same)

• ADD/SB06: Place the value of the ADD latch on the SB bus. The control signal ADD/SB7 is
used instead of ADD/SB06 for bit 7.
• ADD/ADL: Place the ADD latch value on the ADL bus

125
BCD Correction
The BCD correction circuit is controlled by two signals: /DAA (perform correction after addition)
and /DSA (perform correction after subtraction).

The outputs of the circuit are connected to the accumulator inputs (AC) and the circuit takes into
account the ALU operation when the BCD mode is disabled.

Some of the accumulator inputs are connected directly to the SB bus and do not participate in
BCD correction (bits 0 and 4).

The circuit uses 4 auxiliary internal signals in its operation: DAAL, DAAH, DSAL and DSAH. The "L"
in the name stands for the lower part of the bits (0-3), the "H" stands for the higher part of the
bits (4-7).

Circuits for obtaining auxiliary signals:

DAAL DSAL DSAH

The DAAH circuit is in the carry circuit.

The correction circuits use a common motif:

• The input combinatorial circuits, in various combinations accounting for the 4 auxiliary sig-
nals and the bits of the intermediate result (ADD latches)
• Output xor, one of the inputs of which is a bit of the bus SB, and the second of the above
combinatorial circuits

126
Sawed schematics:

Bit 1 Bit 2 Bit 3 Bit 5 Bit 6 Bit 7

The auxiliary signals /ADDx on the BCD correction circuits are derived from the values of the
ADD latch bits as follows:

(Using /ADD5 as an example)

127
Logic:

Accumulator (AC)
The accumulator consists of eight identical pieces:

(The circuit for bit 3 is shown, the others are the same)

The accumulator inputs a value from the BCD correction circuit (bits 1-3, 5-7) or directly from the SB bus (bits 0
and 4).

In addition to directly outputting the accumulator to the SB and DB buses, other bus operations are also per-
formed at this point, so they are also discussed in this section.

• SB/AC: Place the value from the SB bus/BCD correction circuit into the accumulator
• AC/SB: Place the AC value on the SB bus
• AC/DB: Place the AC value on the DB bus
• SB/DB: Connect the SB bus to DB bus
• SB/ADH: Connect the SB bus to ADH bus
• 0/ADH17: Forced write 0 to ADH bits 1-7. The control signal 0/ADH0 is used for bit 0 instead of 0/ADH17.

128
Notes in the margins for future revisions of the book.

129
Program Counter (PC)

Because of the 8-bit nature of the processor its instruction counter is divided into two 8-bit
halves: PCL (Program Counter Low) and PCH (Program Counter High).

The PCH is also divided into two halves: the low part of the bits (0-3) and the high part (4-7).

PCL
Represents the low 8 least significant bits of PC.

PCL 0-3 PCL 4-7

130
• The circuits alternate for even and odd bits because an optimization known as an inverted
carry chain is used
• The control signal #1/PC (0: perform PC increment) comes to the PCL0 bit
• PCLC (PCL Carry): Carry from the lowest 8 bits (PC[0-7]) to the highest (PC[8-15])
• PCL connects to two buses: ADL and DB
• PCL/PCL is used when PCL is not connected to any bus (to maintain the current state)
• Each bit contains two latches (input latch PCLSx and output latch PCLx) which implement
the counter logic

PCH
Represents the top 8 most significant bits of PC.

PCH 0-3 PCH 4-7

The circuit marked as "patch" to form the PCHC is actually between the ADL/PCL and #1/PC
control outputs.

• The basic principles of PCH are the same as PCL, but PCH is divided into two halves: the
lower half (PCH0-3) and the higher half (PCH4-7)
• PCHC (PCH Carry): Carry from the lowermost to the highestermost PCH half
• The PCH connects to two buses: ADH and DB
• PCH/PCH is used when the PCH is not connected to any bus (to maintain the current state)

131
ADL/ADH Precharge
In between the PC bits you can find transistors for precharge of the ADL and ADH buses:

(The image shows the precharge transistors for ADH4 and ADL5. The others are similar)

Logic
It makes sense to show only the bit schematics (the circuitry alternates between even and odd
PCL/PCH bits).

This circuit is used, for example, in PCL0:

This circuit is used, for example, in PCL1:

For these circuits to work correctly in the simulator, FF uses a posedge trigger for the PCL/PCH
register.

132
Notes in the margins for future revisions of the book.

133
Afterword
At this point, the prepared reader is likely to ask: Where is the description of how the instructions
work?

Yes, everything on the previous pages is just the tip of the iceberg. Schematics without examples
turn into an ordinary album.

But that is exactly what the A revision book is about: setting the right direction, for further study.

In the next revision the book is planned to be expanded with a lot of examples of circuits in dif-
ferent modes and a detailed examination of the work of all the instructions.

In the meantime, the reader has a valuable material for self-preparation and checking the cor-
rectness of the circuits presented.

134
Used Materials
• Visual6502.org
• 6502.org
• US3991307A - Integrated circuit microprocessor with parallel binary adder having on-the-fly
correction to provide decimal results - Google Patents (https://patents.google.com/patent/
US3991307A)
• emu-russia/breaks: Nintendo Entertainment System (NES) / Famicom / Dendy chip revers-
ing (github.com) (https://github.com/emu-russia/breaks)
• Image of Bender © Fox Interactive

135
Author's Team:

andkorzh: Schematics for Logisim

HardWareMan: Verilog
org: Transistor circuits, simulation

Editor-in-Chief: org

Feedback: emu-russia Discord (https://discord.gg/WJcvqyCHkh), GitHub

(https://github.com/emu-russia/breaks)

© 2022, emu-russia

136
This book contains descriptions of all MOS 6502 circuits.

If you are good at digital circuitry, the 6502 processor will reveal all its secrets
to you.

The online version of the book is free, the printed version can be ordered from
various offices that print the pdf on paper.

137