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Memory Types
 Examples of memory types:

 Read only memory (ROM)

Memory Interfacing
 Flash memory (EEPROM)

 Static Random Access Memory (SRAM)

 Dynamic Random Access Memory (DRAM)

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Pin Connections Pin Connections…

 Pin connections common to all memory devices are:

 Address input

 Data output or input/outputs

 Selection input

 Control input used to select a read or write operation

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Pin Connections… Pin Connections…

 Address connections: All memory devices have address  RAM memory generally has at least one CS or S input and ROM

inputs that select a memory location within the memory at least one CE
device. Address inputs are labeled from A0 to An  If the CE , CS, S input is active the memory device perform the

 Data connections: All memory devices have a set of data read or write
outputs or input/outputs. Today many of them have bi-  If it is inactive the memory device cannot perform read or
directional common I/O pins write operation
 Selection connections: Each memory device has an input,  If more than one CS connection is present, all must be active
that selects or enables the memory device. This kind of input is to perform read or write data
most often called a chip select (CS),chip enable (CE) or simply
select (S) input

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Pin Connections… Pin Connections…

 Control connections: A ROM usually has only one control  A RAM memory device has either one or two control inputs. If
input, while a RAM often has one or two control inputs there is one control input it is often called R/W
 The control input most often found on the ROM is the output  This pin selects a read operation or a write operation only if the
enable (OE) or gate (G), this allows data to flow out of the device is selected by the selection input (CS)
output data pins of the ROM  If the RAM has two control inputs, they are usually labeled WE
 If OE and the selected input are both active, then the output is or W and OE or G
enable, if OE is inactive, the output is disabled at its high-  (WE) write enable must be active to perform a memory write
impedance state operation and OE must be active to perform a memory read
 The OE connection enables and disables a set of three-state operation
buffer located within the memory device and must be active to  When these two controls WE and OE are present, they must
read data never be active at the same time

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Memory Types Memory Types…

 ROM memory permanently stores programs and data. Data  EPROM (erasable programmable read only memory) is also

will always be present even when power is disconnected erasable if exposed to high intensity ultraviolet light for about

 It is also called as nonvolatile memory 20 minutes or less, depending upon the type of EPROM:
 We have PROM (programmable read only memory)

 RMM (read mostly memory) is also called the flash

memory
 The flash memory is also called EEPROM (electrically
erasable programmable ROM), EAROM (electrically
alterable ROM), or a NOVROM (nonvolatile ROM)

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Memory Types… 2716 EEEPROM

 These memory devices are electrically erasable in the system,  Each of these parts contains address pins, eight data
but require more time to erase than a normal RAM connections, one or more chip selection inputs (CE) and an

 EPROM contains the series of 27XXX contains the following part output enable pin (OE)

numbers :  This device contains 11 address inputs and 8 data outputs

 2704(512*8)  If both the pin connection CE and OE are at logic 0, data will

 2708(1K*8) appear on the output connection. If both the pins are not at

 2716(2K*8) logic 0, the data output connections remains at their high

 2732(4K*8)
impedance or off state

 2764(8K*8)  To read data from the EPROM Vpp pin must be placed at a logic

1
 27128(16K*8) etc

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2716 EEEPROM… 2716 EEEPROM…

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2716 EEEPROM… Static RAM

 Static RAM memory device retain data for as long as DC power
is applied
 Because no special action is required to retain stored data,
these devices are called as static memory. They are also called
volatile memory because they will not retain data without
power.
 The main difference between a ROM and RAM is that a RAM is
written under normal operation, while ROM is programmed
outside the computer and is only normally read
 The SRAM stores temporary data and is used when the size of
read/write memory is relatively small

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Static RAM… Static RAM…

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Static RAM…
 The control inputs of this RAM are slightly different from those

presented earlier

 The OE pin is labeled G , the CS pin S and the WE pin W

 This 4016 SRAM device has 11 address inputs and 8 data

Static RAM Interfacing
input/output connections

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Categories of RAM SRAM Interfacing

 The semiconductor RAM is broadly two types:  For addressing the 4K bytes of memory, 12 address lines are

 Static RAM required

 Dynamic RAM  In general to address a memory location out of N memory

 The semiconductor memories are organized as two dimensional locations, we will require at least n bits of address, i.e. n

arrays of memory locations address lines where n = Log2N

 For example 4K*8 or 4K byte memory contains 4096 locations,  Thus if the microprocessor has n address lines, then it is able

where each location contains 8-bit data and only one of the to address at the most N locations of memory, where 2n=N

4096 locations can be selected at a time

 Once a location is selected all the bits in it are accessible using

a group of conductors called Data bus

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SRAM Interfacing… Static Memory Interfacing with the 8086

 If out of N locations only P memory locations are to be  The general procedure of static memory interfacing with 8086

interfaced, then the least significant p address lines out of the is briefly described as follows:
available n lines can be directly connected from the  Arrange the available memory chip so as to obtain 16- bit data

microprocessor to the memory chip while the remaining (n-p) bus width. The upper 8-bit bank is called as odd address
higher order address lines may be used for address decoding memory bank and the lower 8-bit bank is called as even

as inputs to the chip selection logic address memory bank

 Connect available memory address lines of memory chip with
 The memory address depends upon the hardware circuit used
those of the microprocessor and also connect the memory RD
for decoding the chip select (CS). The output of the decoding
and WR inputs to the corresponding processor control signals
circuit is connected with the CS pin of the memory chip
 Connect the 16-bit data bus of the memory bank with that of
the microprocessor 8086

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Static Memory Interfacing with the 8086 Static Memory Interfacing with the 8086
 The remaining address lines of the microprocessor, BHE and A0  A memory location should have a single address corresponding

are used for decoding the required chip select signals for the to it, i.e. absolute decoding should be preferred and minimum
odd and even memory banks. The CS of memory is derived hardware should be used for decoding
from the o/p of the decoding circuit

 As a good and efficient interfacing practice, the address map of

the system should be continuous as far as possible, i.e. there

should not be no windows in the map and no fold back space
should be allowed

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DRAM
 Whenever a large capacity memory is required in a
microcomputer system, the memory subsystem is generally
designed using dynamic RAM because there are various
advantages of dynamic RAM:
 higher packing density

Dynamic RAM Interfacing  lower cost

 less power consumption

 A typical static RAM cell may require six transistors while the
dynamic RAM cell requires only a transistor along with a
capacitor. Hence it is possible to obtain higher packaging
density and hence low cost units are available

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DRAM… DRAM…
 The basic dynamic RAM cell uses a capacitor to store the  The process of refreshing the data in RAM is called as Refresh

charge as a representation of data cycle

 This capacitor is manufactured as a diode that is reverse-

biased so that the storage capacitance comes into the picture  The refresh activity is similar to reading the data from each

 This storage capacitance is utilized for storing the charge and every cell of memory, independent of the requirement of
representation of data but the reverse-biased diode has microprocessor
leakage current that tends to discharge the capacitor giving
rise to the possibility of data loss
 During this refresh period all other operations related to the
 To avoid this possible data loss, the data stored in a dynamic memory subsystem are suspended. Hence the refresh activity
RAM cell must be refreshed after a fixed time interval regularly causes loss of time, resulting in reduce system performance

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DRAM… DRAM…
 However keeping in view the advantages of dynamic RAM, like  The Refresh cycle is different from the memory read cycle in

low power consumption, high packaging density and low cost, the following aspects:
most of the advanced computing system are designed using a) The memory address is not provided by the CPU address
dynamic RAM, at the cost of operating speed bus, rather it is generated by a refresh mechanism counter
called as refresh counter

 A dedicated hardware chip called as dynamic RAM controller is

the most important part of the interfacing circuit b) Unlike memory read cycle, more than one memory chip
may be enabled at a time so as to reduce the number of
total memory refresh cycles

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DRAM… DRAM…
c) The data enable control of the selected memory chip is  Dynamic RAM is available in units of several kilobits to
deactivated, and data is not allowed to appear on the system megabits of memory
data bus during refresh, as more than one memory units are  This memory is arranged internally in a two dimensional matrix
refreshed simultaneously. This is to avoid the data from the array so that it will have n rows and m columns. The row
different chips to appear on the bus simultaneously address n and column address m are important for the
refreshing operation

d) Memory read is either a processor initiated or an external bus  For example, a typical 4K bit dynamic RAM chip has an

master initiated and carried out by the refresh mechanism internally arranged bit array of dimension 64 * 64 , i.e. 64
rows and 64 columns

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DRAM… DRAM…
 The row address and column address will require 6 bits each  The refresh signals act to control the multiplexer, i.e. when

 These 6 bits for each row address and column address will be refresh cycle is in process the refresh counter puts the row

generated by the refresh counter, during the refresh cycles address over the address bus for refreshing

 A complete row of 64 cells is refreshed at a time to minimize

the refresh time. Thus the refresh counter needs to generate  Otherwise, the address bus of the processor is connected to

only row addresses the address bus of DRAM, during normal processor initiated

 The row address are multiplexed, over lower order address activities

lines

 A timer, called refresh timer, derives a pulse for refresh action

after each refresh interval

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DRAM… DRAM…
 Refresh interval can be qualitatively defined as the time for  Let us consider 2ms as a typical refresh time interval. Hence,

which a dynamic RAM cell can hold data charge level practically the frequency of the refresh pulses will be calculated as
constant, i.e. no data loss takes place follows:

 Suppose the typical dynamic RAM chip has 64 rows, then each

row should be refreshed after each refresh interval or in other  Refresh Time ( per row ) tr = (2 * 10-3)/64
words, all the 64 rows are to refreshed in a single refresh
interval
 Refresh Frequency fr = 64/( 2 * 10-3) = 32 * 103Hz
 This refresh interval depends upon the manufacturing
technology of the dynamic RAM cell. It may range anywhere
from 1ms to 3ms

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DRAM… DRAM…
 The following block diagram explains the refreshing logic and

8086 interfacing with dynamic RAM

 Each chip is of 16K * 1-bit dynamic RAM cell array. The system

contains two 16K byte dynamic RAM units

 All the address and data lines are assumed to be available from

an 8086 microprocessor system

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DRAM… DRAM…
 The OE pin controls output data buffer of the memory chips

 The CE pins are active high chip selects of memory chips

 The refresh cycle starts, if the refresh output of the refresh

timer goes high, OE and CE also tend to go high
 The high CE enables the memory chip for refreshing, while high
OE prevents the data from appearing on the data bus, as
discussed in memory refresh cycle
 The 16K * 1-bit dynamic RAM has an internal array of 128*128
cells, requiring 7 bits for row address
 The lower order seven lines A0-A6 are multiplexed with the
refresh counter output A10-A16

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2164 DRAM 2164 DRAM…

 The pin assignment for 2164 dynamic RAM is as shown above

 The RAS and CAS are row and column address strobes and are

driven by the dynamic RAM controller outputs

 A0 –A7 lines are the row or column address lines, driven by the

OUT0 – OUT7 outputs of the controller

 The WE pin indicates memory write cycles

 The DIN and DOUT pins are data pins for write and read

operations respectively

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2164 DRAM… 2164 DRAM…

 In practical circuits, the refreshing logic is integrated inside  The A0 lines is used to select the even or odd bank

dynamic RAM controller chips like 8203, 8202, 8207 etc.  The RD and WR signals decode whether the cycle is a memory

 Intel’s 8203 is a dynamic RAM controller that support 16K or read or memory write cycle and are accepted as inputs to 8203

64K dynamic RAM chip from the microprocessor

 The WE signal specifies the memory write cycle and is not
 This selection is done using pin 16K/64K. If it is high, the 8203
output from 8203 that drives the WE input of dynamic RAM
is configured to control 16K dynamic RAM, else it controls 64K
memory chip
dynamic RAM
 The OUT0 – OUT7 set of eight pins is an 8-bit output bus that
 The address inputs of 8203 controller accepts address lines A1
carries multiplexed row and column addresses are derived from
to A16 on lines AL0-AL7 and AH0-AH7.
the address lines A1-A16 accepted by the controller on its inputs
AL0-AL7 and AH0-AH7

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2164 DRAM… 2164 DRAM…

 An external crystal may be applied between X0 and X1 pins,  The SACK output signal marks the beginning of a memory
otherwise with the OP2 pin at +12V, a clock signal may be access cycle
applied at pin CLK  If a memory request is made during a memory refresh cycle,
 The PCS pin accepts the chip select signal derived by an the SACK signal is delayed till the starring of memory read or
address decoder write cycle
 The REFREQ pin is used whenever the memory refresh cycle is  Following figure below shows the 8203 can be used to control a
to be initiated by an external signal 256K bytes memory subsystem for a maximum mode 8086
 The XACK signal indicates that data is available during a read microprocessor system
cycle or it has been written if it is a write cycle. It can be used  This design assumes that data and address busses are inverted
as a strobe for data latches or as a ready signal to the and latched, hence the inverting buffers and inverting latches
processor are used ( 8283-inverting buffer and 8287- inverting latch).

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2164 DRAM… 2164 DRAM…

 Most of the functions of 8208 and 8203 are similar but 8208

can be used to refresh the dynamic RAM using DMA approach

 The memory system is divided into even and odd banks of

256K bytes each, as required for an 8086 system

 The inverted AACK output of 8208 latches the A0 and BHE

signals required for selecting the banks

 If the latched bank select signal and the WE /PCLK output of

8208 both become low. It indicates a write operation to the

respective bank

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END

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