Multiplexer

A multiplexer is a combinational circuit that has 2n input lines and a single output line. Simply,
the multiplexer is a multi-input and single-output combinational circuit. The binary information
is received from the input lines and directed to the output line. On the basis of the values of the
selection lines, one of these data inputs will be connected to the output.

Unlike encoder and decoder, there are n selection lines and 2 n input lines. So, there is a total of
2N possible combinations of inputs. A multiplexer is also treated as Mux.

There are various types of the multiplexer which are as follows:

2×1 Multiplexer:

In 2×1 multiplexer, there are only two inputs, i.e., A 0 and A1, 1 selection line, i.e., S0 and single
outputs, i.e., Y. On the basis of the combination of inputs which are present at the selection line
S0, one of these 2 inputs will be connected to the output. The block diagram and the truth table of
the 2×1 multiplexer are given below.

Block Diagram:

Truth Table:
The logical expression of the term Y is as follows:

Y=S0'.A0+S0.A1

Logical circuit of the above expression is given below:

Y=S0'.A0+S0.A1

Logical circuit of the above expression is given below:

4×1 Multiplexer:

In the 4×1 multiplexer, there is a total of four inputs, i.e., A 0, A1, A2, and A3, 2 selection lines,
i.e., S0 and S1 and single output, i.e., Y. On the basis of the combination of inputs that are present
at the selection lines S0 and S1, one of these 4 inputs are connected to the output. The block
diagram and the truth table of the 4×1 multiplexer are given below.

Block Diagram:
Truth Table:

The logical expression of the term Y is as follows:

Y=S1' S0' A0+S1' S0 A1+S1 S0' A2+S1 S0 A3

Logical circuit of the above expression is given below:

8 to 1 Multiplexer

In the 8 to 1 multiplexer, there are total eight inputs, i.e., A0, A1, A2, A3, A4, A5, A6, and A7, 3
selection lines, i.e., S0, S1and S2 and single output, i.e., Y. On the basis of the combination of
inputs that are present at the selection lines S 0, S1, and S2, one of these 8 inputs are connected to
the output. The block diagram and the truth table of the 8×1 multiplexer are given below.
Block Diagram:

Truth Table:

The logical expression of the term Y is as follows:

Y=S0'.S1'.S2'.A0+S0.S1'.S2'.A1+S0'.S1.S2'.A2+S0.S1.S2'.A3+S0'.S1'.S2 A4+S0.S1'.S2 A5+S0'.S1.S2 .A6+S0.
S1.S3.A7

Logical circuit of the above expression is given below:

8 ×1 multiplexer using 4×1 and 2×1 multiplexer

We can implement the 8×1 multiplexer using a lower order multiplexer. To implement the 8×1
multiplexer, we need two 4×1 multiplexers and one 2×1 multiplexer. The 4×1 multiplexer has 2
selection lines, 4 inputs, and 1 output. The 2×1 multiplexer has only 1 selection line.

For getting 8 data inputs, we need two 4×1 multiplexers. The 4×1 multiplexer produces one
output. So, in order to get the final output, we need a 2×1 multiplexer. The block diagram of 8×1
multiplexer using 4×1 and 2×1 multiplexer is given below.

So, we require two 4x1 Multiplexers in first stage in order to get the 8 data inputs. Since, each
4x1 Multiplexer produces one output, we require a 2x1 Multiplexer in second stage by
considering the outputs of first stage as inputs and to produce the final output.
16 to 1 Multiplexer

In the 16 to 1 multiplexer, there are total of 16 inputs, i.e., A 0, A1, …, A16, 4 selection lines, i.e.,
S0, S1, S2, and S3 and single output, i.e., Y. On the basis of the combination of inputs that are
present at the selection lines S0, S1, and S2, one of these 16 inputs will be connected to the output.
The block diagram and the truth table of the 16×1
Block Diagram:

Truth Table:
The logical expression of the term Y is as follows:

Y=A0.S0'.S1'.S2'.S3'+A1.S0'.S1'.S2 '.S3+A2.S0'.S1'.S2.S3'+A3.S0'.S1 '.S2.S3+A4.S0'.S1.S2'.S3'+A5.S0 '.S1.S
2'.S3+A6.S1.S2.S3'+A7.S0 '.S1.S2.S3+A8.S0.S1'.S2'.S3'+A9 .S0.S1'.S2'.S3+Y10.S0.S1'.S2.S3 '+A11.S0.S1'.S2
.S3+A12 S0.S1.S2 '.S3'+A13.S0.S1.S2'.S3+A14.S0.S1 .S2.S3'+A15.S0.S1.S2'.S3

Logical circuit of the above expression is given below:

16×1 multiplexer using 8×1 and 2×1 multiplexer

We can implement the 16×1 multiplexer using a lower order multiplexer. To implement the 8×1
multiplexer, we need two 8×1 multiplexers and one 2×1 multiplexer. The 8×1 multiplexer has 3
selection lines, 4 inputs, and 1 output. The 2×1 multiplexer has only 1 selection line.

For getting 16 data inputs, we need two 8 ×1 multiplexers. The 8×1 multiplexer produces one
output. So, in order to get the final output, we need a 2×1 multiplexer. The block diagram of
16×1 multiplexer using 8×1 and 2×1 multiplexer is given below.
De-multiplexer

A De-multiplexer is a combinational circuit that has only 1 input line and 2 N output lines.
Simply, the multiplexer is a single-input and multi-output combinational circuit. The information
is received from the single input lines and directed to the output line. On the basis of the values
of the selection lines, the input will be connected to one of these outputs. De-multiplexer is
opposite to the multiplexer.

Unlike encoder and decoder, there are n selection lines and 2 n outputs. So, there is a total of
2n possible combinations of inputs. De-multiplexer is also treated as De-mux.

There are various types of De-multiplexer which are as follows:

1×2 De-multiplexer:

In the 1 to 2 De-multiplexer, there are only two outputs, i.e., Y0, and Y1, 1 selection lines, i.e., S0,
and single input, i.e., A. On the basis of the selection value, the input will be connected to one of
the outputs. The block diagram and the truth table of the 1×2 multiplexer are given below.
Block Diagram:

Truth Table:

The logical expression of the term Y is as follows:

Y0=S0'.A
Y1=S0.A

Logical circuit of the above expressions is given below:

1×4 De-multiplexer:

In 1 to 4 De-multiplexer, there are total of four outputs, i.e., Y 0, Y1, Y2, and Y3, 2 selection lines,
i.e., S0 and S1 and single input, i.e., A. On the basis of the combination of inputs which are
present at the selection lines S0 and S1, the input be connected to one of the outputs. The block
diagram and the truth table of the 1×4 multiplexer are given below.

Block Diagram:
Truth Table:

The logical expression of the term Y is as follows:

Y0=S1' S0' A
y1=S1' S0 A
y2=S1 S0' A
y3=S1 S0 A

Logical circuit of the above expressions is given below:

1×8 De-multiplexer

In 1 to 8 De-multiplexer, there are total of eight outputs, i.e., Y 0, Y1, Y2, Y3, Y4, Y5, Y6, and Y7, 3
selection lines, i.e., S0, S1and S2 and single input, i.e., A. On the basis of the combination of
inputs which are present at the selection lines S0, S1 and S2, the input will be connected to one of
these outputs. The block diagram and the truth table of the 1×8 de-multiplexer are given below.

Block Diagram:
Truth Table:

The logical expression of the term Y is as follows:

Y0=S0'.S1'.S2'.A
Y1=S0.S1'.S2'.A
Y2=S0'.S1.S2'.A
Y3=S0.S1.S2'.A
Y4=S0'.S1'.S2 A
Y5=S0.S1'.S2 A
Y6=S0'.S1.S2 A
Y7=S0.S1.S3.A

Logical circuit of the above expressions is given below:

1×8 De-multiplexer using 1×4 and 1×2 de-multiplexer

We can implement the 1×8 de-multiplexer using a lower order de-multiplexer. To implement the
1×8 de-multiplexer, we need two 1×4 de-multiplexer and one 1×2 de-multiplexer. The 1×4
multiplexer has 2 selection lines, 4 outputs, and 1 input. The 1×2 de-multiplexer has only 1
selection line.

For getting 8 data outputs, we need two 1×4 de-multiplexer. The 1×2 de-multiplexer produces
two outputs. So, in order to get the final output, we have to pass the outputs of 1×2 de-
multiplexer as an input of both the 1×4 de-multiplexer. The block diagram of 1×8 de-multiplexer
using 1×4 and 1×2 de-multiplexer is given below.
1 x 16 De-multiplexer

In 1×16 de-multiplexer, there are total of 16 outputs, i.e., Y 0, Y1, …, Y16, 4 selection lines, i.e.,
S0, S1, S2, and S3 and single input, i.e., A. On the basis of the combination of inputs which are
present at the selection lines S0, S1, and S2, the input will be connected to one of these outputs.
The block diagram and the truth table of the 1×16 de-multiplexer are given below.
Block Diagram:
Truth Table:

The logical expression of the term Y is as follows:

Y0=A.S0'.S1'.S2'.S3'
Y1=A.S0'.S1'.S2'.S3
Y2=A.S0'.S1'.S2.S3'
Y3=A.S0'.S1'.S2.S3
Y4=A.S0'.S1.S2'.S3'
Y5=A.S0'.S1.S2'.S3
Y6=A.S0'.S1.S2.S3'
Y7=A.S0'.S1.S2.S3
Y8=A.S0.S1'.S2'.S3'
Y9=A.S0.S1'.S2'.S3
Y10=A.S0.S1'.S2.S3'
Y11=A.S0.S1'.S2.S3
Y12=A.S0.S1.S2'.S3'
Y13=A.S0.S1.S2'.S3
Y14=A.S0.S1.S2.S3'
Y15=A.S0.S1.S2'.S3

Logical circuit of the above expressions is given below:

1×16 de-multiplexer using 1×8 and 1×2 de-multiplexer

We can implement the 1×16 de-multiplexer using a lower order de-multiplexer. To implement
the 1×16 de-multiplexer, we need two 1×8 de-multiplexer and one 1×2 de-multiplexer. The 1×8
multiplexer has 3 selection lines, 1 input, and 8 outputs. The 1×2 de-multiplexer has only 1
selection line.

For getting 16 data outputs, we need two 1×8 de-multiplexer. The 1×8 de-multiplexer produces
eight outputs. So, in order to get the final output, we need a 1×2 de-multiplexer to produce two
outputs from a single input. Then we pass these outputs into both the de-multiplexer as an input.
The block diagram of 1×16 de-multiplexer using 1×8 and 1×2 de-multiplexer is given below.

Key Difference Between Multiplexer and Demultiplexer

Multiplexer Demultiplexer

A multiplexer is a sort of The demultiplexer is a sort of

combinational circuit that accepts combinational circuit that takes a single
numerous data inputs but only input and distributes it to multiple
produces one output. outputs.

A digital switch is referred to as a A demultiplexer is a digital circuit that

multiplexer. demultiplexes signals.
It requires multiple inputs of data and It requires single input of data and
signals. signals.

It has single data output. It has n data output.

It is used at the transmitter end in time- It is used at the receiver end in time-
division multiplexing. division multiplexing.

To study and Verify the 4:1 Multiplexer Using IC 74L153.(MUX)

IC 74138 Pin Diagram, Truth Table, Logical Circuit, Applications

IC 74138 is a Logical Decoder IC. It also has a demultiplexing facility. The IC 74138 is
available in the market with the name of 74LS138. It is a 3 to 8 decoder IC. The internal circuit
of this IC is made of high-speed Schottky barrier diode.
Encoder :

Encoder in Digital Logic

An Encoder is a combinational circuit that performs the reverse operation of Decoder. It has
maximum of 2n input lines and ‘n’ output lines. It will produce a binary code equivalent to the
input, which is active High. Therefore, the encoder encodes 2n input lines with ‘n’ bits. It is
optional to represent the enable signal in encoders.
4 to 2 Encoder
Let 4 to 2 Encoder has four inputs Y3, Y2, Y1 & Y0 and two outputs A1 & A0. The block
diagram of 4 to 2 Encoder is shown in the following figure.

At any time, only one of these 4 inputs can be ‘1’ in order to get the respective binary code at the
output. The Truth table of 4 to 2 encoder is shown below.

Inputs Outputs

Y3 Y2 Y1 Y0 A1 A0

0 0 0 1 0 0

0 0 1 0 0 1

0 1 0 0 1 0

1 0 0 0 1 1

From Truth table, we can write the Boolean functions for each output as

A1=Y3+Y2

A0=Y3+Y1

We can implement the above two Boolean functions by using two input OR gates. The circuit
diagram of 4 to 2 encoder is shown in the following figure.
The above circuit diagram contains two OR gates. These OR gates encode the four inputs with
two bits

8 : 3 Encoder ( Octal to Binary Encoder )

Octal to binary Encoder has eight inputs, Y 7 to Y0 and three outputs A2, A1 & A0. Octal to binary
encoder is nothing but 8 to 3 encoder. The block diagram of octal to binary Encoder is shown in
the following figure.

At any time, only one of these eight inputs can be ‘1’ in order to get the respective binary code.
The Truth table of octal to binary encoder is shown below.

Inputs Outputs

Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 A2 A1 A0

0 0 0 0 0 0 0 1 0 0 0

0 0 0 0 0 0 1 0 0 0 1

0 0 0 0 0 1 0 0 0 1 0

0 0 0 0 1 0 0 0 0 1 1
 0 0 0 1 0 0 0 0 1 0 0

0 0 1 0 0 0 0 0 1 0 1

0 1 0 0 0 0 0 0 1 1 0

1 0 0 0 0 0 0 0 1 1 1

From Truth table, we can write the Boolean functions for each output as

A2=Y7+Y6+Y5+Y4

A1=Y7+Y6+Y3+Y2

A0=Y7+Y5+Y3+Y1

We can implement the above Boolean functions by using four input OR gates. The circuit
diagram of octal to binary encoder is shown in the following figure.

The above circuit diagram contains three 4-input OR gates. These OR gates encode the eight
inputs with three bits.

Decimal to BCD Encoder –

The decimal to binary encoder usually consists of 10 input lines and 4 output lines. Each input
line corresponds to the each decimal digit and 4 outputs correspond to the BCD code. This
encoder accepts the decoded decimal data as an input and encodes it to the BCD output which is
available on the output lines. The figure below shows the logic symbol of decimal to BCD
encoder :
The truth table for decimal to BCD encoder is as follows:

Logical expression for A3, A2, A1 and A0 :

A3 = Y9 + Y8
A2 = Y7 + Y6 + Y5 +Y4
A1 = Y7 + Y6 + Y3 +Y2
A0 = Y9 + Y7 +Y5 +Y3 + Y1
The above two Boolean functions can be implemented using OR gates :
Drawbacks of Encoder
Following are the drawbacks of normal encoder.
 There is an ambiguity, when all outputs of encoder are equal to zero. Because, it could be
the code corresponding to the inputs, when only least significant input is one or when all
inputs are zero.
 If more than one input is active High, then the encoder produces an output, which may not
be the correct code. For example, if both Y3 and Y6 are ‘1’, then the encoder produces
111 at the output. This is neither equivalent code corresponding to Y 3, when it is ‘1’ nor
the equivalent code corresponding to Y6, when it is ‘1’.
So, to overcome these difficulties, we should assign priorities to each input of encoder. Then, the
output of encoder will be the binarybinary code corresponding to the active High inputss, which
has higher priority. This encoder is called as priority encoder.
Priority Encoder
A 4 to 2 priority encoder has four inputs Y3, Y2, Y1 & Y0 and two outputs A1 & A0. Here, the
input, Y3 has the highest priority, whereas the input, Y0 has the lowest priority. In this case, even
if more than one input is ‘1’ at the same time, the output will be the binarybinary code
corresponding to the input, which is having higher priority.
We considered one more output, V in order to know, whether the code available at outputs is
valid or not.
 If at least one input of the encoder is ‘1’, then the code available at outputs is a valid one.
In this case, the output, V will be equal to 1.
 If all the inputs of encoder are ‘0’, then the code available at outputs is not a valid one. In
this case, the output, V will be equal to 0.
The Truth table of 4 to 2 priority encoder is shown below.

Inputs Outputs

Y3 Y2 Y1 Y0 A1 A0 V

0 0 0 0 0 0 0
 0 0 0 1 0 0 1

0 0 1 x 0 1 1

0 1 x x 1 0 1

1 x x x 1 1 1

Use 4 variable K-maps for getting simplified expressions for each output.

The simplified Boolean functions are

A1=Y3+Y2A1=Y3+Y2

A0=Y3+Y2′Y1
Similarly, we will get the Boolean function of output, V as
V=Y3+Y2+Y1+Y0

We can implement the above Boolean functions using logic gates. The circuit diagram of 4 to 2
priority encoder is shown in the following figure.

The above circuit diagram contains two 2-input OR gates, one 4-input OR gate, one 2input AND
gate & an inverter. Here AND gate & inverter combination are used for producing a valid code at
the outputs, even when multiple inputs are equal to ‘1’ at the same time. Hence, this circuit
encodes the four inputs with two bits based on the priority assigned to each input.
The above two Boolean functions can be implemented as :
Decoder

The combinational circuit that change the binary information into 2 N output lines is known
as Decoders. The binary information is passed in the form of N input lines. The output lines
define the 2N-bit code for the binary information. In simple words, the Decoder performs the
reverse operation of the Encoder. At a time, only one input line is activated for simplicity. The
produced 2N-bit output code is equivalent to the binary information.

There are various types of decoders which are as follows:

2 to 4 line decoder:

In the 2 to 4 line decoder, there is a total of three inputs, i.e., A0, and A1 and E and four outputs,
i.e., Y0, Y1, Y2, and Y3. For each combination of inputs, when the enable 'E' is set to 1, one of
these four outputs will be 1. The block diagram and the truth table of the 2 to 4 line decoder are
given below.
Block Diagram:

The logical expression of the term Y0, Y0, Y2, and Y3 is as follows:

Y3=E.A1.A0
Y2=E.A1.A0'
Y1=E.A1'.A0
Y0=E.A1'.A0'

Logical circuit of the above expressions is given below:

3 to 8 line decoder:

The 3 to 8 line decoder is also known as Binary to Octal Decoder. In a 3 to 8 line decoder, there
is a total of eight outputs, i.e., Y 0, Y1, Y2, Y3, Y4, Y5, Y6, and Y7 and three outputs, i.e., A0, A1,
and A2. This circuit has an enable input 'E'. Just like 2 to 4 line decoder, when enable 'E' is set to
1, one of these four outputs will be 1. The block diagram and the truth table of the 3 to 8 line
encoder are given below.
Block Diagram:

The logical expression of the term Y0, Y1, Y2, Y3, Y4, Y5, Y6, and Y7 is as follows:
Y0=A0'.A1'.A2'
Y1=A0.A1'.A2'
Y2=A0'.A1.A2'
Y3=A0.A1.A2'
Y4=A0'.A1'.A2
Y5=A0.A1'.A2
Y6=A0'.A1.A2
Y7=A0.A1.A2

Logical circuit of the above expressions is given below:

4 to 16 line Decoder

In the 4 to 16 line decoder, there is a total of 16 outputs, i.e., Y 0, Y1, Y2,……, Y16 and four
inputs, i.e., A0, A1, A2, and A3. The 3 to 16 line decoder can be constructed using either 2 to 4
decoder or 3 to 8 decoder. There is the following formula used to find the required number of
lower-order decoders.
Required number of lower order decoders=m2/m1

m1 = 8
m2 = 16

Required number of 3 to 8 decoders= =2

Block Diagram:
Truth Table:

The logical expression of the term A0, A1, A2,…, A15 are as follows:

Y0=A0'.A1'.A2'.A3'
Y1=A0'.A1'.A2'.A3
Y2=A0'.A1'.A2.A3'
Y3=A0'.A1'.A2.A3
Y4=A0'.A1.A2'.A3'
Y5=A0'.A1.A2'.A3
Y6=A0'.A1.A2.A3'
Y7=A0'.A1.A2.A3
Y8=A0.A1'.A2'.A3'
Y9=A0.A1'.A2'.A3
Y10=A0.A1'.A2.A3'
Y11=A0.A1'.A2.A3
Y12=A0.A1.A2'.A3'
Y13=A0.A1.A2'.A3
Y14=A0.A1.A2.A3'
Y15=A0.A1.A2'.A3

Logical circuit of the above expressions is given below:

Binary adder (IC 7483)

 IC 7483 is a 4 bit parallel adder which consists of four interconnected full adders along
with the look ahead carry circuit. The pin diagram of IC 7483 is shown above. It is a
16pin IC. The inputs to the IC are A, B and Cin0Cin0 while outputs are S
and Cout3Cout3.
 A3A2A1A0A3A2A1A0 is a 4 bit input word 'A' and B3B2B1B0B3B2B1B0 is the
second 4 bit input word 'B'. Cin0Cin0 is the input carry. The IC adds the two four bit
words along with input carry to prooduce a 4 bit sum and a one bit carry-
out. Cout3Cout3 represents the output carry. S3,S2,S1,S0S3,S2,S1,S0 represents sum
output with S3 as the MSB.
 In odrder to design an 8 bit adder, we require two IC 7483s cascaded as shown in the
figure above.
 Adder-1 is the LSB adder and it adds the four LSB bits of the two 8-bit input words
ie A3−A0A3−A0 and B3−B0B3−B0. The carry input of first adder is supposed to be 0.
Hence the carry in pin of LSB IC is connected to the ground. So the first IC adds the LSB
 bits of A and B, and produces S3–S0S3–S0 that is, LSB of sum, along with a carry
out Cout3Cout3.
 This Cout3Cout3 of adder-1 is connected to Cin0Cin0 input of Adder-2. The second
adder adds this carry and the four MSB bits of
numbers A3−A0A3−A0 and B3−B0B3−B0 to produce MSB sum S7–S4S7–S4 along
with final carry out bit Cout7Cout7.
 Thus adder-1 and adder-2 when cascaded as shown in the figure can add two 8-bit
words. Cout7Cout7 of adder-2 acts as the final output carryand the sum output is
from S7S7 though S0S0.