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Lecture 15 - Addressing Modes

The document discusses various addressing modes used in computer architecture and assembly language programming. It explains that addressing modes specify how operand addresses are interpreted or modified before being accessed. There are 10 addressing modes described: implied, immediate, register, register indirect, autoincrement/autodecrement, direct, indirect, relative, indexed, and base register. Each mode calculates effective addresses in different ways, such as using registers or explicit addresses, to provide programming flexibility and efficient memory access.

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98 views

Lecture 15 - Addressing Modes

The document discusses various addressing modes used in computer architecture and assembly language programming. It explains that addressing modes specify how operand addresses are interpreted or modified before being accessed. There are 10 addressing modes described: implied, immediate, register, register indirect, autoincrement/autodecrement, direct, indirect, relative, indexed, and base register. Each mode calculates effective addresses in different ways, such as using registers or explicit addresses, to provide programming flexibility and efficient memory access.

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Pragya Singh
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BCA: 3

BCA-S203: Computer Architecture & Assembly Language


Dr. Aditya Kumar Gupta
Associate Professor
Unit – II
Addressing Modes
The way the operands are chosen during program execution is dependent on the addressing mode
of the instruction. The addressing mode specifies a rule for interpreting or modifying the address
field of the instruction before the operand is actually referenced. Computers use addressing mode
techniques for the purpose of accommodating one or both of the following provisions:

1. To give programming versatility to the user by providing such facilities as pointers to


memory, counters for loop control, indexing of data, and program relocation.

2. To reduce the number of bits in the addressing field of the instruction.

The availability of the addressing modes gives the experienced assembly language programmer
flexibility for writing programs that are more efficient with respect to the number of instructions
and execution time. To understand the various addressing modes to be presented in this section, it
is imperative that we understand the basic operation cycle of the computer. The control unit of a
computer is designed to go through an instruction cycle that is divided into three major phases:

1. Fetch the instruction from memory.


2. Decode the instruction.
3. Execute the instruction.

There is one register in the computer called the program counter or PC that keeps track of the
instructions in the program stored in memory. PC holds the address of the instruction to be
executed next and is incremented each time an instruction is fetched from memory. The decoding
done in step 2 determines the operation to be performed, the addressing mode of the instruction,
and the location of the operands. The computer then executes the instruction and returns to step 1
to fetch the next instruction in sequence.
In some computers the addressing mode of the instruction is specified with a distinct binary code,
just like the operation code is specified. Other computers use a single binary code that designates
both the operation and the mode of the instruction. Instructions may be defined with a variety of
addressing modes, and sometimes, two or more addressing modes are combined in one instruction.
An example of an instruction format with a distinct addressing mode field is shown in Fig
Although most addressing modes modify the address field of the instruction, there are two modes
that need no address field at all. These are the implied and immediate modes.

Opcode Mode Address

BCA-S203: Computer Architecture & Assembly Language


1. Implied Mode
In this mode the operands are specified implicitly in the definition of the instruction. For example,
the instruction "complement accumulator" is an implied-mode instruction because the operand in
the accumulator register is implied in the definition of the instruction. All register reference
instructions that use an accumulator are implied-mode instructions. Zero-address instructions in a
stack-organized computer are implied-mode instructions since the operands are implied to be on
top of the stack.

2. Immediate Mode
In this mode the operand is specified in the instruction itself. In other words, an immediate-mode
instruction has an operand field rather than an address field. The operand field contains the actual
operand to be used in conjunction with the operation specified in the instruction. Immediate-mode
instructions are useful for initializing registers to a constant value.

3. Register Mode
In this mode the operands are in registers that reside within the CPU. The particular register is
selected from a register field in the instruction. A k-bit field can specify any one of 2k registers.

4. Register Indirect Mode


In this mode the instruction specifies a register in the CPU whose contents give the address of the
operand in memory. In other words, the selected register contains the address of the operand rather
than the operand itself. Before using a register indirect mode instruction, the programmer must
ensure that the memory address of the operand is placed in the processor register with a previous
instruction. The advantage of a register indirect mode instruction is that the address field of the
instruction uses fewer bits to select a register than would have been required to specify a memory
address directly.

5. Autoincrement or Autodecrement Mode


This is similar to the register indirect mode except that the register is incremented or decremented
after (or before) its value is used to access memory. When the address stored in the register refers
to a table of data in memory, it is necessary to increment or decrement the register after every
access to the table. This can be achieved by using the increment or decrement instruction.

6. Direct Address Mode


In this mode the effective address is equal to the address part of the instruction. The operand
resides in memory and its address is given directly by the address field of the instruction. In a
branch-type instruction the address field specifies the actual branch address.

BCA-S203: Computer Architecture & Assembly Language


7. Indirect Address Mode
In this mode the address field of the instruction gives the address where the effective address is
stored in memory. Control fetches the instruction from memory and uses its address part to access
memory again to read the effective address. A few addressing modes require that the address field
of the instruction be added to the content of a specific register in the CPU. The effective address in
these modes is obtained from the following computation:

Effective address = address part of instruction + content of CPU register

The CPU register used in the computation may be the program counter, an index register, or a base
register. In either case we have a different addressing mode which is used for different application.

8. Relative Address Mode


In this mode the content of the program counter is added to the address part of the instruction in
order to obtain the effective address. The address part of the instruction is usually a signed number
(in 2' s complement representation) which can be either positive or negative. When this number is
added to the content of the program counter, the result produces an effective address whose
position in memory is relative to the address of the next instruction.

To clarify with an example, assume that the program counter contains the number 825 and the
address part of the instruction contains the number 24. The instruction at location 825 is read from
memory during the fetch phase and the program counter is then incremented by one to 826. The
effective address computation for the relative address mode is 826 + 24 = 850. This is 24 memory
locations forward from the address of the next instruction.

9. Indexed Addressing Mode


In this mode the content of an index register is added to the address part of the instruction to obtain
the effective address. The index register is a special CPU register that contains an index value. The
address field of the instruction defines the beginning address of a data array in memory. The index
register can be incremented to facilitate access to consecutive operands. Note that if an index type
instruction does not include an address field in its format, the instruction converts to the register
indirect mode of operation.

10. Base Register Addressing Mode


In this mode the content of a base register is added to the address part of the instruction to obtain
the effective address. This is similar to the indexed addressing mode except that the register is now
called a base register instead of an index register. The difference between the two modes is in the
way they are used rather than in the way that they are computed. An index register is assumed to
hold an index number that is relative to the address part of the instruction. A base register is
assumed to hold a base address and the address field of the instruction gives a displacement relative
to this base address. References: Mano, M. Morris. 1984. Digital Design. Pearson

BCA-S203: Computer Architecture & Assembly Language

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