A B C D E

1 1

LCFC Confidential
S145AST M/B Schematics Document
2 2

REV:0.2
AMD FT4 Stoney SOC with DDRIV
AMD R17M-M1-70
Vinafix.com
2018-10
3 3

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2017/03/14 Deciphered Date 2017/03/14 Cover Page
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S145AST
Date: Thursday, October 25, 2018 Sheet 1 of 50
A B C D E
 A B C D E

LCFC confidential
File Name : German

AMD: R17M-M1-70
Package: S3 PCI-Express Memory BUS (DDR4)
WĂŐĞϭϱΕϭϵ PCIe Port 1~4 Single Channel B DDR4-SO-DIMM X1
Page 12
4x Gen3
1
VRAM: 256*32 1.2V DDR4 2133 MT/s 1

GDDR5*2: 2GB 1866 MT/s UP TO 8G

WĂŐĞϮϬΕϮϭ
USB3.0 x1 USB3.0 Left Conn
USB2.0 x1 USB3.0 Port0
USB2.0 Port4 WĂŐĞϮϱ
HDMI Conn. HDMI x4 Lane Port1
WĂŐĞϮϰ AMD FT4 APU
USB 2.0 1x USB2.0 Left Conn
Touch Screen Stoney 15W
USB2.0 x1 USB2.0 Port3
USB 2.0 Port WĂŐĞϮϯ WĂŐĞϮϱ

eDP x2 Lane (Integrated FCH)

eDP Conn USB3.0 Left Conn
USB3.0 x1
USB2.0 1x
Int. Camera USB2.0 x1 USB3.0 Port1
USB2.0 Port2 USB2.0 Port5 WĂŐĞϮϱ
2 2

Int. MIC Conn.

USB 2.0 1x NGFF Card
WLAN&BT
WĂŐĞϮϯ PCIe 1x Key E
PCIe Port2
WĂŐĞϯϭ USB2.0 Port1
SATA HDD SATA Gen3
WĂŐĞϯϰ SATA Port0
BGA-769
24mm*24mm SPI BUS SPI ROM
Vinafix.com
NGFF SSD
WĂŐĞϮϵ
PCI-Express 2x Gen3 8MB WĂŐĞϬϴ

TPM (Reserved)
ST33HTPH2E32AHB4
SD/MMC Conn. WĂŐĞϮϲ
Codec & C/R USB2.0 x1
3 3

SPK Conn. HD Audio Touch Pad

Realtek RTS5119
WĂŐĞϰΕϭϭ
WĂŐĞϯϲ
HP&Mic Combo Conn.
USB2.0 Port0
LPC BUS
SMBUS
IO Board EC Battery
WĂŐĞϰϯ
ITE IT8586E-LQFP
WĂŐĞϯϱ
SMBUS

Charger
WĂŐĞϰϰ
Thermistor Hall sensor
Int.KBD AH9247
WĂŐĞϯϲ WĂŐĞϯϬ WĂŐĞϯϲ
4 Thermal Sensor 4

F75303M
WĂŐĞϯϬ reserve
Security Classification LC Future Center Secret Data Title
Issued Date 2017/03/14 Deciphered Date 2017/03/14 Block Diagram
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S145AST
Date: Thursday, October 25, 2018 Sheet 2 of 50
A B C D E
 A B C D E

Voltage Rails ( O --> Means ON , X --> Means OFF )

SIGNAL
+5VS STATE SLP_S3# SLP_S5# +VALW +V +VS Clock BOARD
Config. BOARD_ID1 BOARD_ID2 reserve
+3VS
S0 (Full ON) HIGH HIGH ON ON ON ON 0: Dis 0: No KBL
+1.8VS
1: UMA 1: KBL
power +1.5VS S1 (Power On Suspend) HIGH HIGH ON ON ON LOW
plane B+ +5VALW +2.5V
(+20VSB) +1.2V +0.95VS
1 (+VSYSMEM_APU) S3 (Suspend to RAM) LOW HIGH ON ON OFF OFF BOARD 1
+3VALW +0.6VS Config. BOARD_ID0 BOARD_ID3
+3VL (+3VALW_APU)
+APU_CORE S4 (Suspend to Disk) LOW LOW ON OFF OFF OFF 14'' 0 0
+5VLP +APU_CORE_NB 15'' 0 1
+1.8VALW S5 (Soft OFF) LOW LOW ON OFF OFF OFF
+APU_GFX 17'' 1 0
+0.95VALW +VGA_CORE
State
+3VGS
+0.775VALW
+1.8VGS USB Port Table for Stoney FT4
+1.35VGS
USB 2.0 USB 3.0 Port Port device BOM Structure Table
+0.95VGS
0 Card Reader BOM Structure BTO Item
1 Blue Tooth @ Not stuff
S0 O O O O EHCI Connector
2 Camera ME@
3 LEFT USB (2.0) Debug@ For USB debug part
S3 4 LEFT USB (3.0) Lower NODebug@ For USB no debug part
O O O X EMC Part
5 LEFT USB (3.0) upper EMC@
xHCI 2 6 Touch screen EMC_NS@ EMC reserve Part
S5 S4/AC
2 O O X X 7 EMC_PX@ EMC GPU part 2

EMC_PXNS@ EMC GPU reserve part

S5 S4/ Battery only RF_NS@ RF reserve Part
O X X X PCIE PORT LIST
RF GPU reserve part
RF_PXNS@
UMA@ UMA SKU ID part
S5 S4/AC & Battery Port Device
don't exist X X X X PX@ Discrete GPU SKU part
0 EXO@ EXO GPU Part
SSD
GPP
1 TOPAZ@ TOPAZ GPU Part
2 WLAN
SMBUS Control Table
SOURCE GPU BATT IT8586E
Vinafix.com
SODIMM WLAN Thermal APU Charger PMIC Touch
3
0
1
N/A
TPM@
AOAC@
HDT@
TPM part
AOAC support part
HDT Debug part
Sensor Pad GFX DIS GPU TS@ Touch screen part
2 NOTS@ No Touch screen part
EC_SMB_CK1
3 S4GX4@ X76 SAMSUNG 2G
IT8586E
EC_SMB_DA1 X V X X X X V X X M4GX4@ X76 MICRON 2G
+3VL_EC
H4GX4@ X76 HYNIX 2G
3
EC_SMB_CK3 V S2GX4@ X76 SAMSUNG 1G 3

EC_SMB_DA3
IT8586E V X X X V
APU_SIC
APU_SID X X X M2GX4@ X76 MICRON 1G
1.8VS for AST
+3VS +3VS_VGA
H2GX4@ X76 HYNIX 1G
APU_SMB_CLK APU S2G@ SAMSUNG 2G
APU_SMB_DATA
+3VS X X X V V X X X X M2G@ MICRON 2G
H2G@ HYNIX 2G
VRAM SAMSUNG 1G
EC_SMB_CK2 S1G@
IT8586E
EC_SMB_DA2 X X X X X X X V X M1G@ MICRON 1G
+3VL_EC
H1G@ HYNIX 1G
SIVCD@ SIV COST down material
TP_I2C0_SCL_R APU
HDMI@ HDMI Logo
TP_I2C0_SDA_R
+1.8VS X X X X X X X X V
STN@ Stoney part
EC SM Bus1 address EC SM Bus2 address EC SM Bus3 address
Device Address Device Address Device Address
Battery 0X16 PMIC 0X34 Thermal Sensor 1001_100xb(reserve)
Charger 0001 0010 b GPU 0x41(default)
4 4
APU SB-TSI releate to F3x1E4[SbiAddr] or
Address Select Pins setting

APU SM Bus1 address APU SM Bus2 APU SM Bus3 address APU SM Bus4
Security Classification LC Future Center Secret Data Title
Device Address Device Address
Issued Date 2017/03/14 Deciphered Date 2017/03/14 Notes List
Touch pad 0x15 No use DDR DIMM 0xA0h No use THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.2
WLAN RSVD
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S145AST
Date: Thursday, October 25, 2018 Sheet 3 of 50
A B C D E
 5 4 3 2 1

D D

UC2B

PCIE

PCIE_CRX_DTX_P0 U4 D2 PCIE_CTX_DRX_P0 CC3 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_DRX_P0

29 PCIE_CRX_DTX_P0 PCIE_CRX_DTX_N0 U5 P_GPP_RXP0 P_GPP_TXP0 PCIE_CTX_DRX_N0 PCIE_CTX_C_DRX_N0 PCIE_CTX_C_DRX_P0 29
D1 CC4 1 2 0.22U_0201_6.3V6-K
29 PCIE_CRX_DTX_N0 P_GPP_RXN0 P_GPP_TXN0 PCIE_CTX_C_DRX_N0 29
M.2 SSD1 PCIE_CRX_DTX_P1 PCIE_CTX_DRX_P1
R8 C2 CC13 1 2 0.22U_6.3V_K_X5R_0201 PCIE_CTX_C_DRX_P1
29 PCIE_CRX_DTX_P1 PCIE_CRX_DTX_N1 P_GPP_RXP1 P_GPP_TXP1 PCIE_CTX_DRX_N1 PCIE_CTX_C_DRX_P1 29
R10 C1 CC14 1 2 0.22U_6.3V_K_X5R_0201 PCIE_CTX_C_DRX_N1
29 PCIE_CRX_DTX_N1 P_GPP_RXN1 P_GPP_TXN1 PCIE_CTX_C_DRX_N1 29
PCIE_PRX_DTX_P1 R5 B2 PCIE_PTX_DRX_P1 CC1 1 2 0.1U_0201_6.3V6-K PCIE_PTX_C_DRX_P1
31 PCIE_PRX_DTX_P1 PCIE_PRX_DTX_N1 R4 P_GPP_RXP2 P_GPP_TXP2 B1 PCIE_PTX_DRX_N1 1 2 0.1U_0201_6.3V6-K PCIE_PTX_C_DRX_N1 PCIE_PTX_C_DRX_P1 31
CC2
WLAN 31 PCIE_PRX_DTX_N1 P_GPP_RXN2 P_GPP_TXN2 PCIE_PTX_C_DRX_N1 31 WLAN
N4 A3
N5 P_GPP_RXP3 P_GPP_TXP3 B3
P_GPP_RXN3 P_GPP_TXN3
C C

PCIE_CRX_GTX_P0 L5 A4 PCIE_CTX_GRX_P0 CC5 PX@1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_P0

15 PCIE_CRX_GTX_P0 PCIE_CRX_GTX_N0 P_GFX_RXP0 P_GFX_TXP0 PCIE_CTX_GRX_N0 PCIE_CTX_C_GRX_N0 PCIE_CTX_C_GRX_P0 15
L4 B4 CC6 PX@1 2 0.22U_0201_6.3V6-K
15 PCIE_CRX_GTX_N0 P_GFX_RXN0 P_GFX_TXN0 PCIE_CTX_C_GRX_N0 15
PCIE_CRX_GTX_P1 J5 A5 PCIE_CTX_GRX_P1 CC7 PX@1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_P1
15 PCIE_CRX_GTX_P1 PCIE_CRX_GTX_N1 J4 P_GFX_RXP1 P_GFX_TXP1 B5 PCIE_CTX_GRX_N1 PCIE_CTX_C_GRX_N1 PCIE_CTX_C_GRX_P1 15
CC8 PX@1 2 0.22U_0201_6.3V6-K
15 PCIE_CRX_GTX_N1 P_GFX_RXN1 P_GFX_TXN1 PCIE_CTX_C_GRX_N1 15 GPU
GPU PCIE_CRX_GTX_P2 G5 A6 PCIE_CTX_GRX_P2 CC9 PX@1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_P2
15 PCIE_CRX_GTX_P2 PCIE_CRX_GTX_N2 G4 P_GFX_RXP2 P_GFX_TXP2 B6 PCIE_CTX_GRX_N2 PCIE_CTX_C_GRX_N2 PCIE_CTX_C_GRX_P2 15
CC10 PX@1 2 0.22U_0201_6.3V6-K
15 PCIE_CRX_GTX_N2 P_GFX_RXN2 P_GFX_TXN2 PCIE_CTX_C_GRX_N2 15
PCIE_CRX_GTX_P3 D7 A7 PCIE_CTX_GRX_P3 CC11 PX@1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_P3
15 PCIE_CRX_GTX_P3 PCIE_CRX_GTX_N3 E7 P_GFX_RXP3 P_GFX_TXP3 B7 PCIE_CTX_GRX_N3 PCIE_CTX_C_GRX_N3 PCIE_CTX_C_GRX_P3 15
CC12 PX@1 2 0.22U_0201_6.3V6-K
15 PCIE_CRX_GTX_N3 P_GFX_RXN3 P_GFX_TXN3 PCIE_CTX_C_GRX_N3 15
+0.95VS

196_0402_1%

with BOM strcture control,

1

Vinafix.com
2 STN@ RC1 P_TX_ZVDD U8
P_ZVDDP

RC1 change to 196_0402_1% for Stoney and Carrizo

FT4 REV 0.93
P_ZVSS
W8

AMD-STONEY-FT4_BGA769
P_RX_ZVDD

196_0402_1% 1 2 STN@ RC3

@
CarrizoL not support GFX4-GFX7

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2017/03/14 Deciphered Date 2017/03/14 FT4 (PCIE I/F)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S145AST
Date: Thursday, October 25, 2018 Sheet 4 of 50
5 4 3 2 1
 5 4 3 2 1

DDRB_DQS[0..7]
12 DDRB_DQS[0..7]
DDRB_DQS#[0..7]
12 DDRB_DQS#[0..7]

UC2A
MEMORY
12 DDRB_MA[13..0] DDRB_MA0 DDRB_DQ0 DDRB_DQ[63..0] 12
AG38 A34
DDRB_MA1 W35 M_ADD0 M_DATA0 B34 DDRB_DQ1
D DDRB_MA2 W38 M_ADD1 M_DATA1 A38 DDRB_DQ2 D
DDRB_MA3 W34 M_ADD2 M_DATA2 B38 DDRB_DQ3
DDRB_MA4 U38 M_ADD3 M_DATA3 A33 DDRB_DQ4
DDRB_MA5 U37 M_ADD4 M_DATA4 B33 DDRB_DQ5
DDRB_MA6 U34 M_ADD5 M_DATA5 A37 DDRB_DQ6
DDRB_MA7 R35 M_ADD6 M_DATA6 B37 DDRB_DQ7
DDRB_MA8 R38 M_ADD7 M_DATA7
DDRB_MA9 N38 M_ADD8 B41 DDRB_DQ8
DDRB_MA10 AG34 M_ADD9 M_DATA8 C40 DDRB_DQ9
DDRB_MA11 R34 M_ADD10 M_DATA9 F41 DDRB_DQ10
DDRB_MA12 N37 M_ADD11 M_DATA10 G40 DDRB_DQ11
DDRB_MA13 AN35 M_ADD12 M_DATA11 A40 DDRB_DQ12
DDRB_BG1 L38 M_ADD13 M_DATA12 B40 DDRB_DQ13
12 DDRB_BG1 DDRB_ACT# M_ADD14/M_BG1 M_DATA13 DDRB_DQ14
L35 E41
12 DDRB_ACT# M_ADD15/M_ACT_L M_DATA14 DDRB_DQ15
F40
DDRB_BA0 AJ38 M_DATA15
12 DDRB_BA0 DDRB_BA1 AG35 M_BANK0 J40 DDRB_DQ16
12 DDRB_BA1 DDRB_BG0 M_BANK1 M_DATA16 DDRB_DQ17
N34 J41
12 DDRB_BG0 M_BANK2/M_BG0 M_DATA17 N40 DDRB_DQ22 DATA16--DATA23 Byte internal swap
12 DDRB_DM[7..0] DDRB_DM0 M_DATA18 DDRB_DQ23
B35 N41
DDRB_DM1 D40 M_DM0 M_DATA19 H40 DDRB_DQ20
DDRB_DM2 K40 M_DM1 M_DATA20 H41 DDRB_DQ21
DDRB_DM3 T41 M_DM2 M_DATA21 M40 DDRB_DQ19
DDRB_DM4 AE41 M_DM3 M_DATA22 M41 DDRB_DQ18
DDRB_DM5 AL40 M_DM4 M_DATA23
DDRB_DM6 AU40 M_DM5 R40 DDRB_DQ24
DDRB_DM7 BA37 M_DM6 M_DATA24 T40 DDRB_DQ25
M_DM7 M_DATA25 W40 DDRB_DQ26
M_DATA26 Y40 DDRB_DQ27 DATA24--DATA31 Byte internal swap
DDRB_DQS0 B36 M_DATA27 P40 DDRB_DQ29
DDRB_DQS#0 A36 M_DQS_H0 M_DATA28 P41 DDRB_DQ28
DDRB_DQS1 E40 M_DQS_L0 M_DATA29 V40 DDRB_DQ30
DDRB_DQS#1 D41 M_DQS_H1 M_DATA30 V41 DDRB_DQ31
DDRB_DQS2 L40 M_DQS_L1 M_DATA31
DDRB_DQS#2 K41 M_DQS_H2 AD41 DDRB_DQ36
C DDRB_DQS3 U41 M_DQS_L2 M_DATA32 AD40 DDRB_DQ32 C
DDRB_DQS#3 U40 M_DQS_H3 M_DATA33 AH41 DDRB_DQ39 DATA32--DATA39 Byte internal swap
DDRB_DQS4 AF41 M_DQS_L3 M_DATA34 AH40 DDRB_DQ35
DDRB_DQS#4 AE40 M_DQS_H4 M_DATA35 AB40 DDRB_DQ33
DDRB_DQS5 AM40 M_DQS_L4 M_DATA36 AC40 DDRB_DQ37
DDRB_DQS#5 AM41 M_DQS_H5 M_DATA37 AF40 DDRB_DQ34
DDRB_DQS6 AV40 M_DQS_L5 M_DATA38 AG40 DDRB_DQ38
DDRB_DQS#6 AV41 M_DQS_H6 M_DATA39
DDRB_DQS7 BA36 M_DQS_L6 AK41 DDRB_DQ41
DDRB_DQS#7 AY36 M_DQS_H7 M_DATA40 AK40 DDRB_DQ44
M_DQS_L7 M_DATA41 AP41 DDRB_DQ43 DATA40--DATA47 Byte internal swap
M_DATA42 AP40 DDRB_DQ47
M_DATA43 AJ41 DDRB_DQ45
DDRB_CLK0 AC35 M_DATA44 AJ40 DDRB_DQ40
12 DDRB_CLK0 DDRB_CLK0# M_CLK_H0 M_DATA45 DDRB_DQ46
AC34 AN41
12 DDRB_CLK0# DDRB_CLK1 M_CLK_L0 M_DATA46 DDRB_DQ42
AA34 AN40
12 DDRB_CLK1 DDRB_CLK1# AA32 M_CLK_H1 M_DATA47
12 DDRB_CLK1# M_CLK_L1 DDRB_DQ54
AE38 AT40

Vinafix.com AE37 M_CLK_H2 M_DATA48 AU41 DDRB_DQ53

AA37 M_CLK_L2 M_DATA49 AY40 DDRB_DQ50 DATA48--DATA55 Byte internal swap
AA38 M_CLK_H3 M_DATA50 BA40 DDRB_DQ52
M_CLK_L3 M_DATA51 AR40 DDRB_DQ49
RC240 1 2 10_0402_5% MEM_MB_RST#_R G38 M_DATA52 AT41 DDRB_DQ48
12 MEM_MB_RST# MEM_MB_EVENT# AA41 M_RESET_L M_DATA53 DDRB_DQ51
AW40
12 MEM_MB_EVENT# M_EVENT_L M_DATA54 DDRB_DQ55
AY41
DDRB_CKE0 J38 M_DATA55
12 DDRB_CKE0 DDRB_CKE1 J34 M0_CKE0 BA38 DDRB_DQ60
12 DDRB_CKE1
L34 M0_CKE1 M_DATA56 AY37 DDRB_DQ57 DATA56--DATA63 Byte internal swap
J37 M1_CKE0 M_DATA57 BA34 DDRB_DQ58
M1_CKE1 M_DATA58 BA33 DDRB_DQ59
DDRB_ODT0 AN37 M_DATA59 AY39 DDRB_DQ61
12 DDRB_ODT0 DDRB_ODT1 AU38 M0_ODT0 M_DATA60 DDRB_DQ56
AY38
12 DDRB_ODT1 M0_ODT1 M_DATA61 DDRB_DQ63
AL34 AY35
AN34 M1_ODT0 M_DATA62 AY34 DDRB_DQ62
B
M1_ODT1 M_DATA63 B
DDRB_CS0# AL35
12 DDRB_CS0# DDRB_CS1# AR37 M0_CS_L0
12 DDRB_CS1# M0_CS_L1
AJ34
AR38 M1_CS_L0
M1_CS_L1
DDRB_MA16_RAS# AJ37
12 DDRB_MA16_RAS# DDRB_MA15_CAS# AN38 M_RAS_L/M_RAS_L_ADD16 +1.2V
12 DDRB_MA15_CAS# DDRB_MA14_WE# AL38 M_CAS_L/M_CAS_L_ADD15
12 DDRB_MA14_WE# M_WE_L/M_WE_L_ADD14
TC86 @ 1 +MEM_VREF AA40
TC70 @ 1 APU_M_VREFDQ Y41 M_VREF AB41 MB_ZVDDIO RC10 1 2 39.2_0402_1%
M_VREFDQ M_ZVDDIO_MEM_S3
FT4 REV 0.93

AMD-STONEY-FT4_BGA769
@

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2017/03/14 Deciphered Date 2017/03/14 FT4 (MEM)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S145AST
Date: Thursday, October 25, 2018 Sheet 5 of 50
5 4 3 2 1
 5 4 3 2 1

APU_SVT

APU_SVC

APU_SVD

0.01U_0201_25V6-K

0.01U_0201_25V6-K

0.01U_0201_25V6-K
1 1 1 +3VS_APU

CC1286

CC1287

CC1288
RPC18
UC2C APU_DDC_CLK 1 4
APU_DDC_DATA 2 3
+1.8VS 2 2 2 DISPLAY/SVI2/JTAG/TEST
@ @ @ RC249 1 2 0_0402_5% APU_SVT_L H27 B23 DP_ENBKL 2.2K_0404_4P2R_5%
49 APU_SVT APU_SVC_L SVT DP_BLON DP_ENVDD
RC213 1 2 22_0402_5% E27 B24
49 APU_SVC SVC DP_DIGON
1
RC215 1 2 22_0402_5% APU_SVD_L D27 A24 DP_EDP_PWM
49 APU_SVD SVD DP_VARY_BL APU_EDP_HPD
RC18 RC35 1 2 100K_0402_5%
300_0402_5% APU_SIC B30 D21 DP_150_ZVSS RC12 1 2 150_0402_1%
D SIC DP_AUX_ZVSS D
APU_SID B29 B18 DP_2K_ZVSS RC55 1 2 2K_0402_1%
ALERT# A30 SID DP_ZVSS
2

APU_RST# RC31 1 2 0_0402_5% APU_PROCHOT#_R A31 ALERT_L G15 APU_EDP_AUX +1.8VS

35,46 H_PROCHOT# PROCHOT_L DP0_AUXP APU_EDP_AUX# APU_EDP_AUX 23 RPC11
H15
PLACE CC16 CAPS CLOSE TO APU,CRB reserve 27pf APU_PWROK G25 DP0_AUXN D15 APU_EDP_HPD APU_EDP_AUX# 23 eDP ALERT# 3 2
49 APU_PWROK APU_RST# PWROK DP0_HPD APU_EDP_HPD 23 APU_PROCHOT#_R
1 D29 4 1
RESET_L G17 APU_DDC_CLK
DP1_AUXP APU_DDC_DATA APU_DDC_CLK 24
CC16 H17 1K_0404_4P2R_5%
56P_0402_50V8-J APU_SVT_L APU_TDI B25 DP1_AUXN D17 APU_HDMI_HPD APU_DDC_DATA 24 HDMI
2 APU_TDO TDI DP1_HPD APU_HDMI_HPD 24
A27
@ TDO

1
CC210 APU_TCK B27 G19
APU_PWROK 1000P_0402_25V7-K APU_TMS B26 TCK DP2_AUXP H19
@ APU_TRST# A29 TMS DP2_AUXN D19 To EDP panel

2
APU_DBRDY A26 TRST_L DP2_HPD +3VS_APU
+1.8VS APU_DBREQ# A25 DBRDY A9 APU_EDP_TX0+
1 DBREQ_L DP0_TXP0 APU_EDP_TX0+ 23
CC1276 B9 APU_EDP_TX0-
DP0_TXN0 APU_EDP_TX0- 23

1
0.01U_0201_25V6-K A10 APU_EDP_TX1+
DP0_TXP1 APU_EDP_TX1+ 23 eDP
1

EMC_NS@ B10 APU_EDP_TX1- +3VALW_APU RC70

2 DP0_TXN1 APU_EDP_TX1- 23
RC19 A11 4.7K_0402_5%
300_0402_5% DP0_TXP2 B11
DP0_TXN2

2
A12

2
DP0_TXP3 B12 RC71
2

DP0_TXN3 10K_0402_5%
APU_PWROK +3VALW_APU APU_HDMI_TX2+ PCH_EDP_PWM 23
A14
Core_type DP1_TXP0 APU_HDMI_TX2- APU_HDMI_TX2+ 24
100K_0402_5% 2 @ 1 RC239 D9 B14
APU_HDMI_TX2- 24

1
RSVD_1 DP1_TXN0

3
PLACE CC17 CAPS CLOSE TO APU,CRB reserve 27pf D11 A15 APU_HDMI_TX1+
RSVD_2 DP1_TXP1 APU_HDMI_TX1- APU_HDMI_TX1+ 24
D13 B15
1 HDMI

D2
RSVD_3 DP1_TXN1 APU_HDMI_TX0+ APU_HDMI_TX1- 24
E4 A16 5 QC8B
RSVD_4 DP1_TXP2 APU_HDMI_TX0- APU_HDMI_TX0+ 24 G2
CC17 E31 B16 PJT7838_SOT363-6
56P_0402_50V8-J RSVD_5 DP1_TXN2 APU_HDMI_CLK+ APU_HDMI_TX0- 24
H11 A17

S2
RSVD_6 DP1_TXP3 APU_HDMI_CLK+ 24

6
2 H13 B17 APU_HDMI_CLK-
@ RSVD_7 DP1_TXN3 APU_HDMI_CLK- 24
L11

D1

4
AE34 RSVD_8 A19 DP_EDP_PWM 2 QC8A
C AM15 RSVD_9 DP2_TXP0 B19 G1 PJT7838_SOT363-6 C
+1.8VS +1.8VS AM17 RSVD_10 DP2_TXN0 A20

S1
RSVD_11 DP2_TXP1

1
AM19 B20
AN8 RSVD_12 DP2_TXN1 A21 RC11

1
AP13 RSVD_13 DP2_TXP2 B21 100K_0402_5%
AP15 RSVD_14 DP2_TXN2 A22
RSVD_15 DP2_TXP3
4
3

AP17 B22

2
RPC10 AR13 RSVD_16 DP2_TXN3 RC205 1 @ 2 0_0402_5%
AR15 RSVD_17
1K_0404_4P2R_5%
RSVD_18
5

STN@ AR17 H29

AU4 RSVD_19 TEST4 G29 TEST5 1 TC14@
G2
1
2

AU13 RSVD_20 TEST5 H25 +3VS_APU

APU_SIC 4 3 EC_SMB_CK3 AU15 RSVD_21 TEST6 R32 TEST9 1 @ TC80
S2 D2 EC_SMB_CK3 16,30,35 RSVD_22 TEST9
AU17 N32 TEST10 1 @ TC81
AV7 RSVD_23 TEST10 G21 APU_TEST14_BP0 RC21 1 @ 2 1K_0402_5%
RSVD_24 TEST14

1
AV9 H21 APU_TEST15_BP1 1 @ TC18
QC6B RSVD_25 TEST15
2

AV11 D23 APU_TEST16_BP2 RC23 1 @ 2 1K_0402_5% +3VALW_APU RC74

PJT7838_SOT363-6 AV13 RSVD_26 TEST16 E23 APU_TEST17_BP3 RC24 1 @ 2 1K_0402_5% RPC14 1K_0404_4P2R_5% 4.7K_0402_5%
G1

STN@ AV15 RSVD_27 TEST17 A28 APU_TEST18_PLLTEST1 4 1 @

RSVD_28 TEST18 +1.8VS

2
APU_SID 1 6 EC_SMB_DA3 AV17 B28 APU_TEST19_PLLTEST0 3 2
EC_SMB_DA3 16,30,35

2
S1 D1 AY3 RSVD_29 TEST19 N8 APU_TEST28_H_PLLCHARZ 1 @ TC21 RC73
RSVD_30 TEST28_H APU_TEST28_L_PLLCHARZ PCH_ENVDD 23
AY7 N10 1 @ TC23 10K_0402_5%
RSVD_31 TEST28_L H31 APU_TEST31_MEM_TEST 1 @ TC25 RC28 1 2 1K_0402_5% @
QC6A TEST31

3
D25 APU_TEST36_STEREOSYNC RC27 1 2 1K_0402_5%

1
PJT7838_SOT363-6 DP_STEREOSYNC/TEST36 B31 TEST41 1 @ TC78 @

D2
STN@ TEST41 5 QC9B
D31 APU_VDDCORE_SEN_H G2 PJT7838_SOT363-6
VDDCR_CPU_SENSE APU_VDDNB_SEN_H APU_VDDCORE_SEN_H 49
E33 @

S2
VDDCR_NB_SENSE APU_VDDNB_SEN_H 49

6
D35 VDDIO_MEM_S3_SENSE 1 @
VDDIO_MEM_S3_SENSE AM21 VDD_095_FB_H 1 @ TC76

D1

4
VDDP_SENSE TC26 DP_ENVDD 2 QC9A

Vinafix.com D33 APU_VSS_SEN_L RC236 1 2 0_0402_5% G1 PJT7838_SOT363-6

VSS_SENSE_A VSS_SENSE_B APU_VDD_SEN_L 49
AM23 1 @ TC77 @

S1
VSS_SENSE_B

1
FT4 REV 0.93
B B
RC13

1
100K_0402_5%
AMD-STONEY-FT4_BGA769 @
APU_VDDNB_SEN_H 1 @ TC27
@

2
RC206 1 2 0_0402_5%
APU_VDDCORE_SEN_H 1 @ TC28 LCD Power IC can change for PCH_ENVDD for cost down
APU_VDD_SEN_L 1 @ TC29
+3VS_APU
With HDT+ Header
+1.8VS +1.8VS

2
+1.8VS JHDT1 @ RPC5 +1.8VS +1.8VS RC77
1 2 APU_TCK 8 1 +3VALW_APU 2.2K_0402_5%
1 2 7 2
APU_TMS +1.8VS @
3 4 6 3 1

1
3 4
2

2
5 4
RC7 5 6 APU_TDI CC25 RC32 RC36 RC75
5 6 0.1U_0201_6.3V6-K PCH_ENBKL 23
1K_0402_5% 1K_0804_8P4R_5% 300_0402_5% 300_0402_5% 10K_0402_5%

2
7 8 APU_TDO HDT@ 2 HDT@ HDT@ @
7 8

3
RC274
1

1
APU_TRST# RC76 1 HDT@ 2 33_0402_5% APU_TRST#_R 9 10 APU_PWROK_BUF UC6 39.2_0402_1%

D2
9 10 APU_PWROK 3 4 APU_PWROK_BUF 5 QC10B
11 12 APU_RST#_BUF 2A 2Y G2 PJT7838_SOT363-6
2

1
11 12 2 5 @

S2
GND VCC APU_TEST31_MEM_TEST @

6
CC84 13 14 APU_DBRDY
13 14 APU_RST# 1 6 APU_RST#_BUF
0.01U_6.3V_K_X7R_0201

D1

4
1A 1Y

2
1 15 16 RC273 1 HDT@ 2 33_0402_5% APU_DBREQ# DP_ENBKL 2 QC10A
15 16 HDT@ SN74LVC2G07YZPR_WCSP6 RC275 G1 PJT7838_SOT363-6
8
7
6
5

17 18 APU_TEST19_PLLTEST0 39.2_0402_1% @

S1
17 18

1
RPC17
10K_0804_8P4R_5% 19 20 APU_TEST18_PLLTEST1 RC14

1
19 20 100K_0402_5%
A HDT@ @ A
@
1
2
3
4

2
SAMTE_ASP-136446-07-B APU_DBREQ# APU_TDI RC207 1 2 0_0402_5%
Reserve follow CRB PCH_ENBKL con EC 1.8V level GPI pin cost down
2 2
CC213 CC212
HDT@ 0.01U_6.3V_K_X7R_0201 0.01U_0201_10V6K Title
1 1 @ Security Classification LC Future Center Secret Data
Issued Date 2017/03/14 Deciphered Date 2017/03/14 FT4 (DISPLAY/CLK/MISC)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S145AST
Date: Thursday, October 25, 2018 Sheet 6 of 50
5 4 3 2 1
 5 4 3 2 1

+3VALW_APU

BOARD BOARD
Config. BOARD_ID0 Config. BOARD_ID1

2
TS 1 DIS 0

2
RC39 RC40 RC41
10K_0402_5% 10K_0402_5% 10K_0402_5% RC1660 NOTS 0 UMA 1
TS@ UMA@ BD15@ 10K_0402_5%
@

1
BOARD_ID0

1
BOARD_ID1
RC38 1 2 33_0402_5% PCIE_RST#_R BOARD_ID2
15,26,29,31,35 PLT_RST# BOARD_ID3 BOARD
Config. BOARD_ID3

2
1

2
D RC43 CC19 RC47 RC48 RC49 14' 0 D
@ 100K_0402_5% 150P_25V_J_NPO_0402 2K_0402_5% 2K_0402_5% 2K_0402_5% RC1659
NOTS@ PX@ BD14@ 2K_0402_5% 15' 1 +3VS_APU
2 @

1
PCH_TP_INT# RC1655 1 2 10K_0402_5%

APU_SSD_RST# RC1671 1 2 10K_0402_5%

+1.8VALW

Connected to 10-ms RC-delay circuit on VDD_18_S5 power rail. RPC9

APU_SMB_CLK 3 2
(CRB PWR Dealy: 22K/0.1uF)

1
UC2D APU_SMB_DATA 4 1
RC247 1 2 0_0402_5% RC53 PXS_RST# change from AGPIO76 to EGPIO101
10K_0402_5% ACPI/SD/AZ/GPIO/RTC/MISC 2.2K_0404_4P2R_5%
PCIE_RST#_R AE4 BA28 EGPIO101 RC1667 1 PX@ 2 0_0402_5% RPC6
PCIE_RST_L/EGPIO26 SD_WP/EGPIO101 SD_PWR_CNTL PXS_RST# 8,15 SSD_1_CLKREQ#
DC1 AY29 1 @ TC44 8 1

2
1 2 @ RSMRST#_R RSMRST#_R AG1 SD_PWR_CTRL/AGPIO102 AY13 ODD_DETECT# 1 @ TC89 WLAN_CLKREQ# 7 2
35 EC_RSMRST# RSMRST_L SD_CD/AGPIO25 PCH_BT_OFF#
BA14 1 @ TC45 6 3
PBTN_OUT# RC191 1 2 0_0402_5% PWRBTN#_R AD2 SD_CLK/EGPIO95 AY15 1 @ TC59 PCH_WLAN_OFF# 5 4
LRB751V-40T1G_SOD323-2 1 35 PBTN_OUT# PWR_BTN_L/AGPIO0 SD_CMD/EGPIO96
1

SYS_PWRGD_R AE2 BA29 SD_LED RC1670 1 @ SSD_SATA_PCIE_DET1#

2 0_0402_5%
SYS_RESET# PWR_GOOD SD_LED/EGPIO93 SSD_SATA_PCIE_DET1# 29
RC66 CC21 AF1 10K_0804_8P4R_5%
11 SYS_RESET# PCIE_WAKE#_RA SYS_RESET_L/AGPIO1 SD_DATA0_R
@ 100K_0402_5% 0.1U_0201_6.3V6-K AE7 AY14 RC1673 1 2 0_0402_5% APU_SSD_RST#
2 WAKE_L/AGPIO2 SD_DATA0/EGPIO97 SD_DATA1_R APU_SSD_RST# 29
BA13 1 @ TC63
SD_DATA1/EGPIO98 BA16 SD_DATA2_R 1 @ TC64 add APU_SSD_RST#
2

PM_SLP_S3# RC193 1 2 0_0402_5% PM_SLP_S3#_R AC2 SD_DATA2/EGPIO99 AY16 SD_DATA3_R 1 @ TC65

35 PM_SLP_S3# PM_SLP_S5# PM_SLP_S5#_R SLP_S3_L SD_DATA3/EGPIO100 PCH_PWRBT#
RC194 1 2 0_0402_5% AG4 RC287 1 @ 2 10K_0402_5%
35 PM_SLP_S5# SLP_S5_L
AGPIO10 AB1
APU_S5_MUX_CTRL AA7 S0A3_GPIO/AGPIO10 AY33 APU_SMB_CLK
9 APU_S5_MUX_CTRL S5_MUX_CTRL/EGPIO42 SCL0/I2C2_SCL/EGPIO113 APU_SMB_DATA APU_SMB_CLK 12,31
BA32
SDA0/I2C2_SDA/EGPIO114 APU_SMB_DATA 12,31 GPU_CLKREQ#
RPC2 RC64 1 UMA@2 10K_0402_5%
with QC16,QC17, EC must set EC_RSMRST# and EC_SYS_PWRGD reversed compare to DC1 and DC2 TEST0 AF2 AC5 SCL1 1 4
TEST1 AE1 TEST0 SCL1/I2C3_SCL/AGPIO19 AC4 SDA1 2 3 GATEA20 RC276 1 2 10K_0402_5%
+3VS_APU TEST2 AC8 TEST1/TMS SDA1/I2C3_SDA/AGPIO20 @
TEST2 10K_0404_4P2R_5% PXS_RST# RC280 2 @ 1 10K_0402_5%
RC281 2 PX@ 1 10K_0402_5%
1

AC_PRESENT AH2 AJ7

C 35 AC_PRESENT AC_PRES/USB_OC4_L/IR_RX0/AGPIO23 AGPIO3 AGPIO3 11 C
RC72 BOARD_ID0 AA4 AK2
RC95 1 2 0_0402_5% 10K_0402_5% BOARD_ID1 AG8 IR_TX0/USB_OC5_L/AGPIO13 AGPIO4 AK1 AGPIO5 1 @ TC83
@ BOARD_ID3 AL5 IR_TX1/USB_OC6_L/AGPIO14 AGPIO5 AL4
add USBDEBUG
ODD_EN IR_RX1/AGPIO15 AGPIO6/LDT_RST_L PCH_TP_INT#_L USBDEBUG 25
TC90 @ 1 AE8 AJ2 RC1663 1 2 0_0402_5%
PCH_TP_INT# 36
2

IR_LED_L/LLB_L/AGPIO12 AGPIO7/LDT_PWROK AJ4 AGPIO8 1 @ TC92

DC2
1 2 @ SYS_PWRGD_R AGPIO8 AG5
35 EC_SYS_PWRGD SSD_1_CLKREQ# AGPIO9 PCH_PWRBT#
1 AY32 AD1 +1.8VS
29 SSD_1_CLKREQ# CLK_REQ0_L/SATA_IS0_L/SATA_ZP0_L/AGPIO92 AGPIO40 PCH_PWRBT# 35
1

PCH_WLAN_OFF# AY31
LRB751V-40T1G_SOD323-2 31 PCH_WLAN_OFF# WLAN_CLKREQ# CLK_REQ1_L/AGPIO115
RC82 CC22 AV29
31 WLAN_CLKREQ# PCH_BT_OFF# CLK_REQ2_L/AGPIO116 RPC19
@ 100K_0402_5% 0.1U_0201_6.3V6-K AP31
2 31 PCH_BT_OFF# GPU_CLKREQ# CLK_REQ3_L/SATA_IS1_L/SATA_ZP1_L/EGPIO131 TP_I2C0_SCL_R
AV35 AJ8 BLINK 1 4
16 GPU_CLKREQ# CLK_REQG_L/OSCIN/EGPIO132 BLINK/USB_OC7_L/AGPIO11 VR_VGA_PWRGD TP_I2C0_SDA_R
AR29 2 3
VR_VGA_PWRGD 15,48
2

GENINT2_L/AGPIO90 AP29
BOARD_ID2 SPKR/AGPIO91 PCH_BEEP 36
AB2 AU35
USB_OC1# USB_OC0_L/TRST_L/AGPIO16 GA20IN/AGPIO126 GATEA20 35 2.2K_0404_4P2R_5%
AG2
25 USB_OC1# USB_OC2# USB_OC1_L/TDI/AGPIO17 PXS_PWREN_R
AJ1 AV33 RC109 1 PX@ 2 1K_0402_5%
25 USB_OC2# USB_OC3# USB_OC2_L/TCK/AGPIO18 FANIN0/AGPIO84 PCH_TP_INT#_R PCH_TP_INT# PXS_PWREN 47,48
Add USB_OC3# for USB2.0 port3 AH1 AU33 RC1662 2 @ 1
25 USB_OC3# USB_OC3_L/TDO/AGPIO24 FANOUT0/AGPIO85 APU_UART0_CTS#
0_0402_5% RC3136 2 @ 1 1K_0402_1%
PCIE_WAKE#_RA RC88 1 @ 2 0_0402_5% APU_UART0_RXD RC3137 2 @ 1 1K_0402_1%
HDA_BITCLK AY6 AP23 APU_UART0_CTS# APU_UART0_RTS# RC3138 2 @ 1 1K_0402_1%
RC201 1 2 0_0402_5% HDA_SDIN0_R BA6 AZ_BITCLK/I2S_BCLK_MIC UART0_CTS_L/EGPIO135 AP25 APU_UART0_RXD
reserve UART0 for BIOS debug APU_UART0_TXD RC3139 2 @ 1 1K_0402_1%
36 HDA_SDIN0 HDA_SDIN1 AZ_SDIN0/I2S_DATA_MIC0 UART0_RXD/EGPIO136 APU_UART0_RTS#
2 1 RC92

Vinafix.com
AGPIO5 @ PCIE_WAKE# 31,35 AY5 AR25
0_0402_5% HDA_SDIN2 BA5 AZ_SDIN1/I2S_LR_PLAYBACK UART0_RTS_L/EGPIO137 AV25 APU_UART0_TXD
HDA_RST# AY4 AZ_SDIN2/I2S_DATA_PLAYBACK UART0_TXD/EGPIO138 AU23
HDA_SYNC AZ_RST_L/I2S_LR_MIC UART0_INTR/AGPIO139 PCH_SPI_PIRQ# 26
2 1 DC3 BA3
HDA_SDOUT BA4 AZ_SYNC/I2S_BCLK_PLAYBACK AP21
SDM10U45LP-7_DFN1006-2-2 AZ_SDOUT/I2S_DATA_MIC1 UART1_CTS_L/BT_I2S_BCLK/EGPIO140 AV21
@ UART1_RXD/BT_I2S_SDI/EGPIO141 AP19
Connect TouchPad to I2C port0 following CRB 10/28 UART1_RTS_L/EGPIO142 delete APU_SHUTDOWN# signal for Stoney FT4
AV23 +3VALW_APU
TP_I2C0_SCL_R AY22 UART1_TXD/BT_I2S_SDO/EGPIO143 AR21 RPC15
36 TP_I2C0_SCL_R TP_I2C0_SDA_R BA22 I2C0_SCL/EGPIO145 UART1_INTR/BT_I2S_LRCLK/AGPIO144 PCIE_WAKE#_RA 1 8
+3VALW_APU 36 TP_I2C0_SDA_R AU19 I2C0_SDA/EGPIO146 AC_PRESENT 2 7
AV19 I2C1_SCL/EGPIO147 AP27 HVB_EN 3 6
DC4 RPC3 HVB_EN 11,35
SYS_RESET# 1 2 @ SYS_PWRGD_R 1 4 I2C1SCL I2C1_SDA/EGPIO148 HVBEN_L PBTN_OUT# 4 5
2 3 I2C1SDA
2

AN4 10K_0804_8P4R_5%
LRB751V-40T1G_SOD323-2 RTCCLK SUSCLK 11,29,31
B RC84 RC85 RC20 1 10K_0404_4P2R_5% B
2.2K_0402_5% 1K_0402_5% 2.2K_0402_5% 32K_X1 BA2 RPC22
CC38 X32K_X1 USB_OC1# 1 8
@ @ @ USB_OC2#
0.1U_0201_6.3V6-K Max ESR < 65K ohm !! 2 7
1

TEST0 2 USB_OC3# 3 6
TEST1 RC102 32K_X2 AY2 4 5
TEST2 1 2 X32K_X2
20M_0402_5% 10K_0804_8P4R_5%
2

FT4 REV 0.93

YC1
RC195 RC196 RC197 1 2 PM_SLP_S3# RC203 1 @ 2 2.2K_0402_5%
15K_0402_5% 15K_0402_5% 15K_0402_5% PM_SLP_S5# RC208 1 @ 2 2.2K_0402_5%
32.768KHZ_12.5PF_202740-PG14 AMD-STONEY-FT4_BGA769
20P_0402_50V8

20P_0402_50V8

@
1

APU_S5_MUX_CTRL RC248 1 2 100K_0402_5%

1 1
STN@
CC23

CC24

APU_S5_MUX_CTRL 100K pull high follow CRB BLINK RC277 1 @ 2 10K_0402_5%

2 2 BLINK isn't strap pin, don't need pull high APU_SSD_RST# RC1672 1 @ 2 10K_0402_5%

PXS_PWREN_R/PXS_RST#_R/VR_VGA_PWRGD internal pull up 40k PCH_TP_INT# RC1661 1 @ 2 10K_0402_5%

+3VS_APU SD_LED RC97 1 @ 2 10K_0402_5%

AGPIO10 RC80 1 @ 2 10K_0402_5%

RC98 1 PX@ 2 10K_0402_5% PXS_PWREN_R
RPC4
RC100 1 @ 2 10K_0402_5% VR_VGA_PWRGD RPC21 GPU_CLKREQ# RC65 1 PX@ 2 2K_0402_5%
HDA_RST# 1 8 TC87 @ 1 HDA_RST_AUDIO# 1 8 HDA_RST#
RC101 1 @ 2 100K_0402_5% PXS_PWREN_R HDA_SYNC 2 7 2 7 HDA_SYNC HDA_BITCLK RC1675 1 @ 2 10K_0402_5%
3 6
36 HDA_SYNC_AUDIO
3 6 HDA_SDOUT
follow Checklist, HDA_BITCLK PD reserve HDA_SDIN0_R RC91 1 @ 2 10K_0402_5%
VR_VGA_PWRGD HDA_SDOUT 36 HDA_SDOUT_AUDIO HDA_BITCLK
RC104 1 UMA@2 2K_0402_5% 4 5 4 5
36 HDA_BITCLK_AUDIO
RPC24
1K_0804_8P4R_5% 33_0804_8P4R_5% RSMRST#_R 1 4
SYS_PWRGD_R 2 3
A A
1/16W_100K_5%_4P2R_0404
VR_VGA_PWRGD RPC23
CRB: CARRIZO NEED 10K PD ON UNUSED SDIN HDA_SDIN2 1 4
HDA_SDIN1
1
DG: 10K PD 2 3

10K_0404_4P2R_5%
CC4223 For EMI For EMI For EMI For EMI
HDA_SDIN0_R HDA_BITCLK HDA_SYNC HDA_SDOUT
0.1U_0201_6.3V6-K 1 1 1 1
2
@
@ CC4222 CC4220 @ CC4221 @ CC4219 Title
2P_25V_NPO_0201 56P_50V_J_NPO_0201 2P_25V_NPO_0201 2P_25V_NPO_0201 Security Classification LC Future Center Secret Data
2 2 EMC@ 2 2
Issued Date 2017/03/14 Deciphered Date 2017/03/14 FT4 (GEVENT/GPIO/SD/AZ)
Close to PCH Close to PCH Close to PCH Close to PCH
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S145AST
Date: Thursday, October 25, 2018 Sheet 7 of 50
5 4 3 2 1
 5 4 3 2 1

UC2E

CLK/SATA/USB/SPI/LPC
SATA_PTX_DRX_P0 BA10 AL8 CLK_USB48M 1 @ TC69
34 SATA_PTX_DRX_P0 SATA_PTX_DRX_N0 SATA_TX0P USBCLK/25M_48M_OSC
AY10
34 SATA_PTX_DRX_N0 SATA_TX0N USB_RCOMP
HDD AN7 RC112 1 2 11.8K_0402_1%
SATA_PRX_DTX_N0 AY12 USB_ZVSS
RPC13 34 SATA_PRX_DTX_N0 SATA_PRX_DTX_P0 SATA_RX0N USB20_P0
BA12 AW1
SATA0_DEVSLP_R 34 SATA_PRX_DTX_P0 SATA_RX0P USB_HSD0P USB20_N0 USB20_P0 36
3 2 AW2 Card Reader
USB_HSD0N USB20_N0 36
4 1 EGPIO70 AY9
BA9 SATA_TX1P AV1 USB20_P1
SATA_TX1N USB_HSD1P USB20_N1 USB20_P1 31
10K_0404_4P2R_5% AV2 Blue Tooth
D USB_HSD1N USB20_N1 31 D
STN@ BA8
AY8 SATA_RX1N AU1 USB20_P2
SATA_RX1P USB_HSD2P USB20_N2 USB20_P2 23
AU2 Camera
+0.95VS SATA_CALRN USB_HSD2N USB20_N2 23
RC113 1 2 1K_0402_1% AU11
RC114 1 2 1K_0402_1% SATA_CALRP AP11 SATA_ZVSS AT1 USB20_P3
SATA_ZVDDP USB_HSD3P USB20_N3 USB20_P3 25
AT2 LEFT USB (2.0)
USB_HSD3N USB20_N3 25
RC147 1 2 10K_0402_5% APU_TS_ON#
APU_TS_ON# AY30 AR1 USB20_P4 USB3.0 port0 must map to USB2.0 port4,
SATA_ACT_L/AGPIO130 USB_HSD4P USB20_P4 25
SATA0_DEVSLP_R AV31
DEVSLP0/EGPIO67 USB_HSD4N
AR2 USB20_N4
USB20_N4 25 LEFT USB (3.0)USB3.0
lower port1 must map to USB2.0 port5,
EGPIO70 AU31
DEVSLP1/EGPIO70 AP1 USB20_P5 USB3.0 port2 must map to USB2.0 port6
USB_HSD5P USB20_N5 USB20_P5 25
AP2 LEFT USB (3.0) upper
CLK_PCIE_GPU USB_HSD5N USB20_N5 25
RC117 1 2 0_0402_5% CLK_PCIE_GPU_R H2
15 CLK_PCIE_GPU CLK_PCIE_GPU# GFX_CLKP
RC118 1 2 0_0402_5% CLK_PCIE_GPU#_R H1 AN1 USB20_P6
15 CLK_PCIE_GPU# GFX_CLKN USB_HSD6P USB20_N6 USB20_P6 23
AN2 Touch Screen
CLK_PCIE_SSD USB_HSD6N USB20_N6 23
RC1665 1 2 0_0402_5% CLK_PCIE_SSD_R M2
29 CLK_PCIE_SSD CLK_PCIE_SSD# GPP_CLK0P
RC1664 1 2 0_0402_5% CLK_PCIE_SSD#_R M1 AM1
29 CLK_PCIE_SSD# GPP_CLK0N USB_HSD7P AM2
L2 USB_HSD7N
L1 GPP_CLK1P
GPP_CLK1N W4 USBSS_CALRN RC123 1 2 1K_0402_1% +0.95VALW
CLK_PCIE_WLAN RC119 1 2 0_0402_5% CLK_PCIE_WLAN_R K2 USB_SS_ZVSS W5 USBSS_CALRP RC124 1 2 1K_0402_1%
31 CLK_PCIE_WLAN GPP_CLK2P USB_SS_ZVDDP Connect the four USB 3.0 ports to onboard devices first
CLK_PCIE_WLAN# RC120 1 2 0_0402_5% CLK_PCIE_WLAN#_R K1
31 CLK_PCIE_WLAN# GPP_CLK2N T1 USB30_TX_P0
starting from the lower ports and then the remaining
J2 USB_SS_0TXP T2 USB30_TX_N0 USB30_TX_P0 25 ports can be used for routing to USB 3.0 connectors.
GPP_CLK3P USB_SS_0TXN USB30_TX_N0 25 Less than four USB 3.0 ports can be utilized provided
J1
GPP_CLK3N V2 USB30_RX_P0 the (3.0)
unusedlower
ports are higher-numbered consecutive
USB_SS_0RXP USB30_RX_P0 25 LEFT USB
V1 USB30_RX_N0 ports.
48M_X1 USB_SS_0RXN USB30_RX_N0 25
F2 None of the four USB 3.0 ports can be configured
X48M_X1 R1 USB30_TX_P1
48M_X2 F1 USB_SS_1TXP R2 USB30_TX_N1 USB30_TX_P1 25 as USB 2.0 external ports.
X48M_X2 USB_SS_1TXN USB30_TX_N1 25
C W2 USB30_RX_P1 LEFT USB (3.0) upper C
X14M_25M_48M_OSC USB_SS_1RXP USB30_RX_N1 USB30_RX_P1 25
TC53 @ 1 AU27 W1
X25M_48M_OSC USB_SS_1RXN USB30_RX_N1 25
P1
USB_SS_2TXP P2
USB_SS_2TXN
Y2
RC126 1 2 0_0402_5% LPCCLK0 BA25 USB_SS_2RXP Y1
11,35 CLK_PCI_EC LPCCLK0/EGPIO74 USB_SS_2RXN
RC127 1 2 0_0402_5% LPCCLK1 BA24
11 LPC_CLK1 LPCCLK1/EGPIO75
RC3144 1 2 0_0402_5% FRAME# AY24
11,35 LPC_FRAME# LFRAME_L SPI_CLK_R SPI_CLK
RC3140 1 2 0_0402_5% LAD0 BA26 AY17 RC209 1 2 0_0402_5% SPI_CLK 26
35 LPC_AD0 LAD0 SPI_CLK/ESPI_CLK/EGPIO117 SPI_SI_R SPI_SI
Add 0ohm for LPC DAT, cause RC3141 1 2 0_0402_5% LAD1 AY28 AY20 RC198 1 2 0_0402_5%
35 LPC_AD1 LAD1 SPI_DO/ESPI_DAT0/EGPIO121 SPI_SO_R SPI_SO SPI_SI 26
LPC data signal overshoot/undershoot issue 35 LPC_AD2 RC3142 1 2 0_0402_5% LAD2 AY25 BA17 RC199 1 2 0_0402_5%
RC3143 1 2 0_0402_5% LAD3 AY23 LAD2 SPI_DI/ESPI_DAT1/EGPIO120 BA18 SPI_HOLD#_R RC133 1 2 0_0402_5% SPI_HOLD# SPI_SO 26
35 LPC_AD3 LAD3 SPI_HOLD_L/ESPI_DAT3/EGPIO133 BA20 SPI_WP#_R RC132 1 2 0_0402_5% SPI_WP#
LPC_RST#_R AY27 SPI_WP_L/ESPI_DAT2/EGPIO122 AY21 SPI_CS0#_R RC202 1 2 0_0402_5% SPI_CS0#

Vinafix.com AY26 LPC_RST_L SPI_CS1_L/EGPIO118 BA21 SPI_TPM_CS_R RC243 1 TPM@ 2 0_0402_5% SPI_CS#_TPM
RC149 1 2 10K_0402_5% AGPIO21 AC1 LPC_CLKRUN_L/AGPIO88 SPI_TPM_CS_L/AGPIO76 RC16741 2 0_0402_5% SPI_CS#_TPM 26
LPC_PD_L/AGPIO21 PXS_RST# 7,15
AA8 AY18 1 @ TC54 @
35 EC_SCI# ODD_DA# LPC_PME_L/AGPIO22 ESPI_ALERT_L/LDRQ0_L
TC91 @ 1 BA27 BA30 KBRST#
LPC_SMI_L/AGPIO86 ESPI_RESET_L/KBRST_L/AGPIO129 KBRST# 35
35 SERIRQ AV27 AY19 EGPIO119 10K_0402_5% 2STN@ 1 RC144
SERIRQ/AGPIO87 SPI_CS2_L/ESPI_CS_L/EGPIO119

+3VS_APU
FT4 REV 0.93

RC46 1 2 33_0402_5% LPC_RST#_R

35 APU_LPC_RST#
AMD-STONEY-FT4_BGA769 KBRST# RC279 1 2 10K_0402_5%
1 @
CC20
150P_25V_J_NPO_0402
2
B B

48M_X1 +VCC_SPI

48M_X2 8M ROM +VCC_SPI

1
+3VALW_APU
RC140 1 2 1M_0402_5% CC27 +1.8VS
0.1U_0201_6.3V6-K +VCC_SPI RC135 1 @ 2 0_0402_5%
2 SPI_CLK KBRST#
YC2 UC3 RC192 1 2 0_0402_5%
SPI_CS0# 1 8
/CS VCC

2
1 4 SPI_SO 2 7 SPI_HOLD#
OSC1 NC2 SPI_WP# 3 DO(IO1) /HOLDor/RESET(IO3) 6 SPI_CLK +VCC_SPI
2 3 4 /WP(IO2) CLK 5 SPI_SI RC139
NC1 OSC2 GND DI(IO0) 10_0402_5%
1 1 RPC8 EMC_NS@

1
48MHZ 10PF X1E000021083400 W25Q64FWSSIQ_SO8 SPI_WP# 1 4

1000P_0402_25V7-K
CC28 CC29 SPI_HOLD# 2 3
12P_0402_50V8-J 12P_0402_50V8-J 2

2
2 2 10K_0404_4P2R_5% CC26

CC1274
10P_0402_50V8J EMC_NS@
SPI_CS0# RC138 1 2 10K_0402_5% EMC_NS@

1
1
with BOM strcture control, UC3 change to 1.8V SPI ROM for CZ
EMC

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2017/03/14 Deciphered Date 2017/03/14 FT4 (SATA/USB/LPC/SPI)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S145AST
Date: Thursday, October 25, 2018 Sheet 8 of 50
5 4 3 2 1
 5 4 3 2 1

+1.2V

+1.2V UC2F +APU_CORE_NB

18A

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
POWER

180P_50V_J_NPO_0402
1 1 1 1 3A J35 E9
+1.2V L32 VDDIO_MEM_S3_1 VDDCR_NB_1 E11

CC258

CC185

CC214

CC165
L37 VDDIO_MEM_S3_2 VDDCR_NB_2 E13
N35 VDDIO_MEM_S3_3 VDDCR_NB_3 E15
2 2 2 2 R37 VDDIO_MEM_S3_4 VDDCR_NB_4 E17
U32 VDDIO_MEM_S3_5 VDDCR_NB_5 E19 +APU_CORE_NB
VDDIO_MEM_S3_6 VDDCR_NB_6

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603
1 1 1 1 1 1 1 1 1 CD@ U35 G7
W32 VDDIO_MEM_S3_7 VDDCR_NB_7 J7

CC42

CC54

CC55

CC56

CC57

CC58

CC59

CC60

CC53
W37 VDDIO_MEM_S3_8 VDDCR_NB_8 K11
D D

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K
180P_50V_J_NPO_0402
AA35 VDDIO_MEM_S3_9 VDDCR_NB_9 K13

1U_0402_6.3V6K
1000P_16V_K_X7R_0402

1000P_16V_K_X7R_0402
2 2 2 2 2 2 2 2 2 VDDIO_MEM_S3_10 VDDCR_NB_10

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603
AC32 K15 1 1 1 1 1 1 1 1 1 1 1 1 1
AC37 VDDIO_MEM_S3_11 VDDCR_NB_11 K17

CC237

CC238

CC239

CC240

CC241

CC242

CC243

CC244

CC145

CC195

CC196

CC199

CC200
VDDIO_MEM_S3_12 VDDCR_NB_12
SIVCD@ SIVCD@ SIVCD@
AE32
AE35 VDDIO_MEM_S3_13 VDDCR_NB_13
K19
L7
Ϯϯϳ͕Ϯϯϴ^ƚƵĨĨĨŽƌ
AG32 VDDIO_MEM_S3_14 VDDCR_NB_14 L10 DƚĞƐƚĨĂŝůϭϬϭϲ EMC_PX@ 2 EMC@ 2 2 2 2 2 2 2 2 @ 2 @ 2 @ 2 @ 2
AG37 VDDIO_MEM_S3_15 VDDCR_NB_15 L15
AJ32 VDDIO_MEM_S3_16 VDDCR_NB_16 L17
AJ35 VDDIO_MEM_S3_17 VDDCR_NB_17 N7 CD@ SIVCD@
AL32 VDDIO_MEM_S3_18 VDDCR_NB_18 N11
AL37 VDDIO_MEM_S3_19 VDDCR_NB_19 N13
follow CRB reserve
AR35 VDDIO_MEM_S3_20 VDDCR_NB_20 N15
+0.95VS +APU_CORE VDDIO_MEM_S3_21 VDDCR_NB_21 N17
OK
VDDCR_NB_22 N19
22A K21 VDDCR_NB_23 R7

1000P_16V_K_X7R_0402

1000P_16V_K_X7R_0402

1000P_16V_K_X7R_0402

1000P_16V_K_X7R_0402
K23 VDDCR_CPU_1 VDDCR_NB_24 U7
10U_0603_6.3V6M

10U_0603_6.3V6M

180P_50V_J_NPO_0402

180P_50V_J_NPO_0402
VDDCR_CPU_2 VDDCR_NB_25
22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

1 1 1 1 1 1 1 1 1 1 1 1 1 K25 U11

1U_0402_6.3V6K

1U_0402_6.3V6K
CC220 K27 VDDCR_CPU_3 VDDCR_NB_26 U13
CC221

CC222

CC223

CC224

CC225

CC174

CC226

CC227

CC228

CC229

CC230

CC203
1 1 1 VDDCR_CPU_4 VDDCR_NB_27
47P_0402_50V8J K29 U15

CC215

CC216

CC137
RF_NS@ K31 VDDCR_CPU_5 VDDCR_NB_28 U17 +1.8VS +1.8VALW +3VALW_APU
2 2 2 2 2 2 2 2 2 2 2 2 2 N21 VDDCR_CPU_6 VDDCR_NB_29 U19
2 2 2 N23 VDDCR_CPU_7 VDDCR_NB_30 U21
N25 VDDCR_CPU_8 VDDCR_NB_31 W7
SIVCD@ SIVCD@ SIVCD@ N27 VDDCR_CPU_9 VDDCR_NB_32 AA11

1000P_0402_25V7-K

1000P_0402_25V7-K

1000P_0402_25V7-K
SIVCD@ VDDCR_CPU_10 VDDCR_NB_33
N29 AA13

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
SIVCD@ CD@ N31 VDDCR_CPU_11 VDDCR_NB_34 AA15
VDDCR_CPU_12 VDDCR_NB_35 1 1 1 1 1 1

2
U23 AA17

CC246

CC247

CC245

CC249

CC250

CC248

CC255

CC256

CC254
U25 VDDCR_CPU_13 VDDCR_NB_36 AA19
U27 VDDCR_CPU_14 VDDCR_NB_37 AA21

1
U29 VDDCR_CPU_15 VDDCR_NB_38 AA23 2 2 2 2 2 2
U31 VDDCR_CPU_16 VDDCR_NB_39 AE11
AA25 VDDCR_CPU_17 VDDCR_NB_40 AE13
AA27 VDDCR_CPU_18 VDDCR_NB_41 AE15 SIVCD@ SIVCD@ SIVCD@
AA29 VDDCR_CPU_19 VDDCR_NB_42 AE17
AA31 VDDCR_CPU_20 VDDCR_NB_43 AE19
+VDDCR_FCH_S5 VDDCR_CPU_21 VDDCR_NB_44 AE21
VDDCR_NB_45 AE23
AR4 VDDCR_NB_46 AE25
0.4A AR5 VDDCR_FCH_S5_1 VDDCR_NB_47 AE27
AR7 VDDCR_FCH_S5_2 VDDCR_NB_48 AE29
C +0.95VALW AU7 VDDCR_FCH_S5_3 VDDCR_NB_49 AE31 C
+RTCBATT +RTCBATT_APU VDDCR_FCH_S5_4 VDDCR_NB_50 +1.8VS
RC6 1 2
0.1A AJ11
1K_0402_5%
0.79A AL11 VDDP_S5_1 AJ15 1.5A

1000P_0402_25V7-K
AL13 VDDP_S5_2 VDD_18_1 AL17 +1.8VALW

1U_0402_6.3V6K
10U_0603_6.3V6M
+0.95VS VDDP_S5_3 VDD_18_2
1 1

1U_0402_6.3V6K

2
AJ13 +3VS_APU +3VS
0.5A

CC182

CC219

CC231
1 VDD_18_S5_1
6.9A AJ21 AL15
CC192

AJ23 VDDP_1 VDD_18_S5_2

1
2 2 AJ25 VDDP_2 AJ19 RC214 1 2 0_0402_5%
2 AJ27 VDDP_3 VDD_33_1 AL21
0.2A

1000P_0402_25V7-K
AL23 VDDP_4 VDD_33_2 +3VALW_APU

1U_0402_6.3V6K
10U_0603_6.3V6M
SIVCD@ AL25 VDDP_5 AJ17
VDDP_6 VDD_33_S5_1 0.2A 1 1

2
AL27 AL19

CC252

CC253

CC251
AL29 VDDP_7 VDD_33_S5_2
VDDP_8

1
+1.8VS +VDDIO_AZ_APU AM11 2 2
RC212 1 2 0_0402_5% AM13 VDDBT_RTC_G
0.2A VDDIO_AUDIO

1000P_0402_25V7-K
1000P_16V_K_X7R_0402 SIVCD@
FT4 REV 0.93
1U_0402_6.3V6K

1 1 2
CC236

CC234

CC235

Vinafix.com
AMD-STONEY-FT4_BGA769
@
1

2 2

SIVCD@

UC5
VCCRTC
RC231 1 2 10K_0402_5% 1
Vin +0.95VALW
3 +RTCBATT
Vout
1U_0402_6.3V6K

1U_0402_6.3V6K

1 2 1
GND
1

JCMOS1 RC8 @
CC37

CC194

SHORT PADS 470_0603_5%

AP2138N-1.5TRG1_SOT23-3 @
2

B 2 2 B
2 2 2 2 2 2
12

D QC7

CC1280

CC1281

CC1282

CC1283

CC1284

CC1285
2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M
2 EC_RTCRST#_ON
G EC_RTCRST#_ON 35
1

1 1 1 1 1 1
L2N7002KWT1G_SOT323-3S RC15 Design Guide G FT4 CRB
3

100K_0402_5%
@
@ 7*22uf 0603 11*22uf 0805 11*22uf 0603
VDDCR_CPU 2*1uf 0402 2*1uf 0402 1*1uf 0402
2

EMC_NS@ EMC_NS@ EMC_NS@ EMC_NS@EMC_NS@ EMC_NS@ 1*180pf 0402 1*180pf 0402 1*180pf 0402
11*22uf 0603 11*22uf 0603 15*22uf 0603
VDDCR_NB 1*1uf 0402 1*1uf 0402 8*0.22uf 0402 split *5
1*180pf 0402 1*180pf 0402 1*180pf 0402

VDDCR_GFX
9*22uf 0603 9*22uf 0603 2*1uf 0402 9*22uf 0603 2*1uf 0402
VDDIO_MEM_S3 3*1uf 0402 split*4 0.22uf 0402 split*4 0.22uf 0402
3*180pf 0402 1*180pf 0402 split*2 1*180pf 0402 split*2
1*10uf 0402 1*10uf 0402 2*10uf 0603
VDDCR_FCH_S5 2*1uf 0402 2*1uf 0402 1*0.22uf 0402
2*1000pf 0402 2*1000pf 0402
5*22uf 0603 2*10uf 0603 5*22uf 0603 2*10uf 0603 4*10uf 0603
VDDP 4*1000pf 0402 4*1000pf 0402 1*0.22uf 0402
1*180pf 0402 1*180pf 0402 1*180pf 0402

VDDP_GFX
+1.2V 1*10uf 0402 1*10uf 0402 1*10uf 0603
VDDP_S5 1*1uf 0402 1*1uf 0402 1*0.22uf 0402
+APU_CORE_NB +VDDCR_FCH_S5 1*1000pf 0402 1*1000pf 0402
UC7 1*10uf 0402 1*10uf 0402 1*22uf 0603
0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

1 8 VDD_18 1*1uf 0402 1*1uf 0402 1*10uf 0603

180P_0402_50V8-J
180P_50V_J_NPO_0402

VIN1_1 VOUT_1 1*1000pf 0402 1*1000pf 0402

1 1 1 1 1 1
2 7 1*10uf 0402 1*10uf 0402 1*10uf 0603
CC168

CC169

CC170

CC172

CC179

CC176

1 VIN1_2 VOUT_2
+0.775VALW 1*1uf 0402 1*1uf 0402 1*0.22uf 0402
VDD_18_S5

1000P_0402_25V7-K

1000P_16V_K_X7R_0402
CC207 3 6 APU_S5_MUX_CTRL 1*1000pf 0402 1*1000pf 0402

1U_0402_6.3V6K

1U_0402_6.3V6K
10U_0603_6.3V6M
2 2 2 2 2 2 +5VALW VIN2 SEL APU_S5_MUX_CTRL 7
10U_0603_6.3V6M 1 1 1 1 1*10uf 0402 1*10uf 0402

2
2 4 5 1*1uf 0402 1*1uf 0402 1*10uf 0603
VDD_33
CC162

CC217

CC218

CC232

CC233
SDVCD@ 1 VCC EN 1*1000pf 0402 1*1000pf 0402
1U_0402_6.3V6K

SIVCD@ SIVCD@ SIVCD@ CC208 1 9 1*10uf 0402 1*10uf 0402 1*10uf 0603
A

1
GND 2 2 2 2 A
DECOUPLING BETWEEN PROCESSOR AND DIMMs VDD_33_S5 1*1uf 0402 1*1uf 0402 1*0.22uf 0402
CC209

10U_0603_6.3V6M
2 1*1000pf 0402 1*1000pf 0402
ACROSS VDDIO AND VSS SPLIT SDVCD@
G5018RD1U_TDFN8_3X3 1*10uf 0402 1*10uf 0402
2
SDVCD@ STN@ STN@ SIVCD@ SIVCD@ 2*1000pf 0402 2*1000pf 0402 3*1uf 0402
STN@ VDDIO_AUDIO
STN@
VDDBT_RTC_G 1*1000pf 0402 1*1000pf 0402 1*0.22uf 0402

Security Classification LC Future Center Secret Data Title

Issued Date 2017/03/14 Deciphered Date 2017/03/14 FT4 (POWER&DECOUPLING)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S145AST
Date: Wednesday, October 31, 2018 Sheet 9 of 50
5 4 3 2 1
 5 4 3 2 1

UC2G UC2H

GND GND
D AJ31 L13 AC21 AU39 D
R19 VSS_215 VSS_59 L19 AC23 VSS_120 VSS_182 AW3
H23 VSS_214 VSS_60 L21 AC25 VSS_121 VSS_183 AW5
A2 VSS_213 VSS_61 L23 AC27 VSS_122 VSS_184 AW7
A8 VSS_1 VSS_62 L25 AC29 VSS_123 VSS_185 AW9
A13 VSS_2 VSS_63 L27 AC31 VSS_124 VSS_186 AW11
A18 VSS_3 VSS_64 L29 AC38 VSS_125 VSS_187 AW13
A23 VSS_4 VSS_65 L31 AC39 VSS_126 VSS_188 AW15
A32 VSS_5 VSS_66 L39 AC41 VSS_127 VSS_189 AW17
A35 VSS_6 VSS_67 L41 AE3 VSS_128 VSS_190 AW19
A39 VSS_7 VSS_68 N1 AE5 VSS_129 VSS_191 AW21
B8 VSS_8 VSS_69 N2 AE10 VSS_130 VSS_192 AW23
B13 VSS_9 VSS_70 N3 AE39 VSS_131 VSS_193 AW25
B32 VSS_10 VSS_71 N39 AG3 VSS_132 VSS_194 AW27
B39 VSS_11 VSS_72 R3 AG7 VSS_133 VSS_195 AW29
C3 VSS_12 VSS_73 R11 AG10 VSS_134 VSS_196 AW31
C5 VSS_13 VSS_74 R13 AG11 VSS_135 VSS_197 AW33
C7 VSS_14 VSS_75 R15 AG13 VSS_136 VSS_198 AW35
C9 VSS_15 VSS_76 R17 AG15 VSS_137 VSS_199 AW37
C11 VSS_16 VSS_77 R21 AG17 VSS_138 VSS_200 AW39
C13 VSS_17 VSS_78 R23 AG19 VSS_139 VSS_201 AW41
C15 VSS_18 VSS_79 R25 AG21 VSS_140 VSS_202 AY1
C17 VSS_19 VSS_80 R27 AG23 VSS_141 VSS_203 AY11
C19 VSS_20 VSS_81 R29 AG25 VSS_142 VSS_204 BA7
C21 VSS_21 VSS_82 R31 AG27 VSS_143 VSS_205 BA11
C
C23 VSS_22 VSS_83 R39 AG29 VSS_144 VSS_206 BA15 C
C25 VSS_23 VSS_84 R41 AG31 VSS_145 VSS_207 BA19
C27 VSS_24 VSS_85 U1 AG39 VSS_146 VSS_208 BA23
C29 VSS_25 VSS_86 U2 AG41 VSS_147 VSS_209 BA31
C31 VSS_26 VSS_87 U3 AJ3 VSS_148 VSS_210 BA35
C33 VSS_27 VSS_88 U10 AJ5 VSS_149 VSS_211 BA39
C35 VSS_28 VSS_89 U39 AJ10 VSS_150 VSS_212
C37 VSS_29 VSS_90 W3 AJ29 VSS_151
C39 VSS_30 VSS_91 W10 AJ39 VSS_152
C41 VSS_31 VSS_92 W11 AL1 VSS_153
E1 VSS_32 VSS_93 W13 AL2 VSS_154
E2 VSS_33 VSS_94 W15 AL3 VSS_155
VSS_34 VSS_95 VSS_156

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E3
E21
E25
E29
E35
VSS_35
VSS_36
VSS_37
VSS_38
VSS_96
VSS_97
VSS_98
VSS_99
W17
W19
W21
W23
W25
AL7
AL10
AL31
AL39
AL41
VSS_157
VSS_158
VSS_159
VSS_160
E38 VSS_39 VSS_100 W27 AM25 VSS_161
E39 VSS_40 VSS_101 W29 AM27 VSS_162
G1 VSS_41 VSS_102 W31 AM29 VSS_163
G2 VSS_42 VSS_103 W39 AM31 VSS_164
G3 VSS_43 VSS_104 W41 AN3 VSS_165
G11 VSS_44 VSS_105 AA1 AN5 VSS_166
G13 VSS_45 VSS_106 AA2 AN39 VSS_167
G23 VSS_46 VSS_107 AA3 AR3 VSS_168
B B
G27 VSS_47 VSS_108 AA5 AR11 VSS_169
G31 VSS_48 VSS_109 AA10 AR19 VSS_170
G35 VSS_49 VSS_110 AA39 AR23 VSS_171
G37 VSS_50 VSS_111 AC3 AR27 VSS_172
G39 VSS_51 VSS_112 AC7 AR31 VSS_173
G41 VSS_52 VSS_113 AC10 AR39 VSS_174
J3 VSS_53 VSS_114 AC11 AR41 VSS_175
J8 VSS_54 VSS_115 AC13 AU3 VSS_176
J39 VSS_55 VSS_116 AC15 AU9 VSS_177
L3 VSS_56 VSS_117 AC17 AU21 VSS_178
L8 VSS_57 VSS_118 AC19 AU25 VSS_179
VSS_58 VSS_119 AU29 VSS_180
VSS_181
FT4 REV 0.93
FT4 REV 0.93

AMD-STONEY-FT4_BGA769 AMD-STONEY-FT4_BGA769
@ @

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2017/03/14 Deciphered Date 2017/03/14 FT4 (VSS)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S145AST
Date: Thursday, October 25, 2018 Sheet 10 of 50
5 4 3 2 1
 5 4 3 2 1

+3VS +3VALW_APU +3VS +3VALW_APU +3VS +3VALW_APU +3VALW_APU +3VALW_APU +3VALW_APU +3VS_APU

2
RC152 RC169 RC153 RC200 RC154 RC173 RC155 RC156 RC157 RC81
10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%
@ @ @ @ @
D D

1
8,35 LPC_FRAME#

8 LPC_CLK1

8,35 CLK_PCI_EC

7 AGPIO3

7 SYS_RESET#

7,29,31 SUSCLK

7,35 HVB_EN

1
RC79
C RC159 RC160 RC161 RC162 RC163 RC164 C
2K_0402_5% 2K_0402_5% 2K_0402_1% 2K_0402_5% 2K_0402_5% 2K_0402_5% 0_0402_5%
@ @ @ @ @

2
@

STRAP PINS

Signal
LFRAME_L LPCCLK1 LPCCLK0
Vinafix.com
RTCCLK

Int pull-up
SYS_RESET_L

Int pull-up
AGPIO3

Int pull-up
HVB_EN

Type II II II I I I

SPI ROM Internal Boot Fail Timer RTC Coin Battery is Normal Power Up Enhanced reset floating
B PULL CLK Gen Enabled implemented &Reset Timing logic (for quicker B
HIGH S5 resume) Disable HVB
Default Default Default on FT4 platforms
Default Default
Default

Boot Fail Timer Reserved traditional connected to VSS

PULL LPC ROM Reserved Disabled RTC Coin Battery is reset logic
LOW not implemented Enable HVB
Default on FT4 platforms

Type I straps become valid immediately after capture with the rising edge of RSMRST_L,they are captured only once when power is first applied to the processor
Type II straps become valid after PWR_GOOD is asserted,straps are captured every time the systems powers up from the S5 state. A transition from S3 to S0 does not trigger capture.
Type II straps should be pulled up to S0 power rail to prevent leakage when the signal is connected to a device in S0 power domain.
If the LPC bus is connected to devices that are on S0 power rail, then a pull-up resistor to VDD_33 is implemented.

All Strap pins must be configured with either external pull-up or pull-down resistors.
Platforms that are designed for AOAC complaint are recommended to use the Alternate Reset by strapping this pin to ‘1’ for CZ
AGPIO3
A A

Security Classification LC Future Center Secret Data Title

Issued Date 2017/03/14 Deciphered Date 2017/03/14 FT4 (STRAPS)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S145AST
Date: Thursday, October 25, 2018 Sheet 11 of 50
5 4 3 2 1
 5 4 3 2 1

DDRB_DQ[0..63]
DDRB_DQ[0..63] 5
DDRB_DQS[0..7]
DDRB_DQS[0..7] 5
DDRB_DQS#[0..7]
DDRB_DQS#[0..7] 5
DDR4 SO-DIMM A DDRB_MA[0..13]
DDRB_MA[0..13] 5
+1.2V +1.2V DDRB_DM[0..7]
DDRB_DM[0..7] 5
JDDR1B

JDDR1A DDRB_MA3 131 132 DDRB_MA2

DDRB_MA1 133 A3 A2 134 MEM_MB_EVENT#
A1 EVENT_n MEM_MB_EVENT# 5
135 136
1 2 DDRB_CLK0 137 VDD_9 VDD_10 138 DDRB_CLK1
D
DDRB_DQ0 VSS_1 VSS_2 DDRB_DQ5 5 DDRB_CLK0 DDRB_CLK0# CK0_t CK1_t DDRB_CLK1# DDRB_CLK1 5 D
3 4 139 140
DQ5 DQ4 5 DDRB_CLK0# CK0_c CK1_c DDRB_CLK1# 5
5 6 141 142
DDRB_DQ1 7 VSS_3 VSS_4 8 DDRB_DQ4 RD2591 2 0_0402_5% 143 VDD_11 VDD_12 144 DDRB_MA0
9 DQ1 DQ0 10 Parity A0
DDRB_DQS#0 11 VSS_5 VSS_6 12 DDRB_DM0
DDRB_DQS0 13 DQS0_C DM0_n/DBIO_n/NC 14 DDRB_BA1 145 146 DDRB_MA10
DQS0_t VSS_7 DDRB_DQ7 5 DDRB_BA1 BA1 A10/AP
15 16 147 148
DDRB_DQ3 17 VSS_8 DQ6 18 DDRB_CS0# 149 VDD_13 VDD_14 150 DDRB_BA0
DQ7 VSS_9 DDRB_DQ2 5 DDRB_CS0# DDRB_MA14_WE# CS0_n BA0 DDRB_MA16_RAS# DDRB_BA0 5
19 20 151 152
DDRB_DQ6 VSS_10 DQ2 5 DDRB_MA14_WE# WE_n/A14 RAS_n/A16 DDRB_MA16_RAS# 5
21 22 153 154
23 DQ3 VSS_11 24 DDRB_DQ12 DDRB_ODT0 155 VDD_15 VDD_16 156 DDRB_MA15_CAS#
DDRB_DQ9 25 VSS_12 DQ12 26 5 DDRB_ODT0 DDRB_CS1# 157 ODT0 CAS_n/A15 158 DDRB_MA13 DDRB_MA15_CAS# 5
DQ13 VSS_13 DDRB_DQ8 5 DDRB_CS1# CS1_n A13
27 28 159 160
DDRB_DQ13 29 VSS_14 DQ8 30 DDRB_ODT1 161 VDD_17 VDD_18 162 +VREF_CA
31 DQ9 VSS_15 32 DDRB_DQS#1 5 DDRB_ODT1 163 ODT1 C0/CS2_n/NC 164
DDRB_DM1 33 VSS_16 DQS1_c 34 DDRB_DQS1 165 VDD_19 VREFCA 166 DDRB0_SA2
35 DM1_n/DBl1_n/NC DQS1_t 36 167 C1/CS3_n/NC SA2 168
DDRB_DQ10 37 VSS_17 VSS_18 38 DDRB_DQ11 DDRB_DQ37 169 VSS_53 VSS_54 170 DDRB_DQ32
39 DQ15 DQ14 40 171 DQ37 DQ36 172
DDRB_DQ14 41 VSS_19 VSS_20 42 DDRB_DQ15 DDRB_DQ33 173 VSS_55 VSS_56 174 DDRB_DQ36
43 DQ10 DQ11 44 175 DQ33 DQ32 176
DDRB_DQ16 45 VSS_21 VSS_22 46 DDRB_DQ21 DDRB_DQS#4 177 VSS_57 VSS_58 178 DDRB_DM4
47 DQ21 DQ20 48 +1.2V DDRB_DQS4 179 DQS4_c DM4_n/DBl4_n/NC 180
DDRB_DQ17 49 VSS_23 VSS_24 50 DDRB_DQ20 181 DQS4_t VSS_59 182 DDRB_DQ39
51 DQ17 DQ16 52 DDRB_DQ38 183 VSS_60 DQ39 184
DDRB_DQS#2 53 VSS_25 VSS_26 54 DDRB_DM2 185 DQ38 VSS_61 186 DDRB_DQ34
DDRB_DQS2 55 DQS2_c DM2_n/DBl2_n/NC 56 RC9 1 2 1K_0402_5% MEM_MB_EVENT# DDRB_DQ35 187 VSS_62 DQ35 188
57 DQS2_t VSS_27 58 DDRB_DQ18 189 DQ34 VSS_63 190 DDRB_DQ45
DDRB_DQ22 59 VSS_28 DQ22 60 DDRB_DQ44 191 VSS_64 DQ45 192
61 DQ23 VSS_29 62 DDRB_DQ19 193 DQ44 VSS_65 194 DDRB_DQ40
DDRB_DQ23 63 VSS_30 DQ18 64 DDRB_DQ41 195 VSS_66 DQ41 196
65 DQ19 VSS_31 66 DDRB_DQ25 197 DQ40 VSS_67 198 DDRB_DQS#5
DDRB_DQ28 67 VSS_32 DQ28 68 DDRB_DM5 199 VSS_68 DQS5_c 200 DDRB_DQS5
69 DQ29 VSS_33 70 DDRB_DQ24 201 DM5_n/DBl5_n/NC DQS5_t 202
DDRB_DQ29 71 VSS_34 DQ24 72 DDRB_DQ47 203 VSS_69 VSS_70 204 DDRB_DQ42
73 DQ25 VSS_35 74 DDRB_DQS#3 205 DQ46 DQ47 206
DDRB_DM3 75 VSS_36 DQS3_c 76 DDRB_DQS3 DDRB_DQ43 207 VSS_71 VSS_72 208 DDRB_DQ46
C DM3_n/DBl3_n/NC DQS3_t DQ42 DQ43 C
77 78 209 210
DDRB_DQ31 79 VSS_37 VSS_38 80 DDRB_DQ26 DDRB_DQ53 211 VSS_73 VSS_74 212 DDRB_DQ49
81 DQ30 DQ31 82 213 DQ52 DQ53 214
DDRB_DQ30 83 VSS_39 VSS_40 84 DDRB_DQ27 DDRB_DQ54 215 VSS_75 VSS_76 216 DDRB_DQ48
85 DQ26 DQ27 86 217 DQ49 DQ48 218
87 VSS_41 VSS_42 88 DDRB_DQS#6 219 VSS_77 VSS_78 220 DDRB_DM6
89 CB5/NC CB4/NC 90 DDRB_DQS6 221 DQS6_c DM6_n/DBl6_n/NC 222
+1.2V +1.2V 91 VSS_43 VSS_44 92 +1.2V 223 DQS6_t VSS_79 224 DDRB_DQ55
93 CB1/NC CB0/NC 94 DDRB_DQ52 225 VSS_80 DQ54 226
RD273 1 @ 2 240_0402_1% 95 VSS_45 VSS_46 96 227 DQ55 VSS_81 228 DDRB_DQ51
RD274 1 @ 2 240_0402_1% 97 DQS8_c DM8_n/DBI8_n/NC 98 DDRB_DQ50 229 VSS_82 DQ50 230
99 DQS8_t VSS_47 100 231 DQ51 VSS_83 232 DDRB_DQ57
101 VSS_48 CB6/NC 102 DDRB_DQ61 233 VSS_84 DQ60 234
103 CB2/NC VSS_49 104 ĨŽƌDDͺDͺZ^dηŽǀĞƌƐŚŽŽƚŝƐƐƵĞ 235 DQ61 VSS_85 236 DDRB_DQ60
105 VSS_50 CB7/NC 106 DDRB_DQ56 237 VSS_86 DQ57 238
107 CB3/NC VSS_51 108 MEM_MB_RST# 239 DQ56 VSS_87 240 DDRB_DQS#7
DDRB_CKE0 109 VSS_52 RESET_n 110 DDRB_CKE1 MEM_MB_RST# 5 DDRB_DM7 241 VSS_88 DQS7_c 242 DDRB_DQS7
5 DDRB_CKE0 CKE0 CKE1 DDRB_CKE1 5 DM7_n/DBl7_n/NC DQS7_t

0.1U_0201_6.3V6-K
111 112 243 244
VDD_1 VDD_2 VSS_89 VSS_90

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DDRB_BG1 113 114 DDRB_ACT# DDRB_DQ58 245 246 DDRB_DQ63
5 DDRB_BG1 BG1 ACT_n DDRB_ACT# 5 1 DQ62 DQ63
DDRB_BG0 DDR4_ALERT

CD120
115 116 247 248
5 DDRB_BG0 BG0 ALERT_n DDRB_DQ59 VSS_91 VSS_92 DDRB_DQ62
117 118 249 250
DDRB_MA12 119 VDD_3 VDD_4 120 DDRB_MA11 251 DQ58 DQ59 252
DDRB_MA9 121 A12 A11 122 DDRB_MA7 2 +VDDSPD APU_SMB_CLK 253 VSS_93 VSS_94 254 APU_SMB_DATA
123 A9 A7 124 7,31 APU_SMB_CLK 255 SCL SDA 256 DDRB0_SA0 APU_SMB_DATA 7,31
@
DDRB_MA8 125 VDD_5 VDD_6 126 DDRB_MA5 257 VDDSPD SA0 258
DDRB_MA6 A8 A5 DDRB_MA4 +2.5V VPP_1 VTT DDRB0_SA1 +0.6VS
127 128 1 1 259 260
129 A6 A4 130 CD28 CD29 VPP_2 SA1
VDD_7 VDD_8 1
1U_0402_6.3V6K 0.1U_0201_6.3V6-K CD121 261 262
22P_0402_50V8-J GND_1 GND_2
2 2 RF_NS@
RF 2 ARGOS_D4AR0-26001-1P40
ARGOS_D4AR0-26001-1P40 ME@
ME@

+3VS +VDDSPD
RD2711 2 0_0402_5%
+2.5VS
B B
+1.2V
+1.2V RD272 1 @ 2 0_0402_5%
+2.5V +2.5VS
1
1

D
RD10 1
RD258 +VREF_CA QD1
1K_0402_1%
1K_0402_1% LP2301ALT1G_SOT23-3
ϭϱŵŝů

G
>ĂLJŽƵƚEŽƚĞ͗WůĂĐĞŶĞĂƌ:Zϭ
2

2
2

@
0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K
2

DDR4_ALERT
1000P 25V K X7R 0201

24,37 SUSP
RD11 1 1 1
1K_0402_1% +0.6VS +1.2V

ĨŽůůŽǁZϭƉĐƐϰ͘ϳƵĨнϭƉĐƐϬ͘ϭƵĨ ĨŽůůŽǁZϴƉĐƐϬ͘ϭƵĨ
CD262

CD116

CD117
1

2 2 2 0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_6.3V_K_X5R_0201

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

180P_50V_J_NPO_0402
0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

4.7U_0402_6.3V6M

1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 CD16 CD17 CD18 CD20 CD21 CD22 CD23 CD58 CD59 CD60 CD61 CD62 CC211
CD249 CD251 CD250 CD248 @ @ @ @
@ @
2 2 2 2 2 2 2 2 2 2 2 2 2
2 2 2 2

+3VS +3VS +3VS

1

RD26 RD269 RD270 +2.5V +1.2V

@10K_0402_5% 10K_0402_5% 10K_0402_5% ĨŽůůŽǁZϭƉĐƐϭƵĨнϮƉĐƐϬ͘ϭƵĨнϭƉĐƐϭϴϬƉĨ

@ @
2

DDRB0_SA0 DDRB0_SA1 DDRB0_SA2

10U_0603_6.3V6M

10U_0603_6.3V6M

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603
1U_0402_6.3V6K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

180P_50V_J_NPO_0402

1 1 1 1 1 1 1
2

CD66

CD67

1 1 1 1 CD261 CD63 CD19 CD260 CD12

A RD268 RD28 RD29 CD122 CD123 CD124 CC206 22P_0402_50V8-J 22P_0402_50V8-J 22P_0402_50V8-J A
0_0402_5% 0_0402_5% 0_0402_5% RF_NS@ RF_NS@ RF_NS@
2 2 2 2 2 2 2
2 2 2 2
RF
1

CD@ SITCD@

Security Classification LC Future Center Secret Data Title

Issued Date 2017/03/14 Deciphered Date 2017/03/14 DDRIII SO-DIMM A
SPD Address = A0H THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S145AST
Date: Thursday, October 25, 2018 Sheet 12 of 50
5 4 3 2 1
 5 4 3 2 1

D D

C C

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B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2017/03/14 Deciphered Date 2017/03/14 DDRIII SO-DIMM B

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS D 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S145AST
Date: Thursday, October 25, 2018 Sheet 13 of 50
5 4 3 2 1
 5 4 3 2 1

Power-Up/Down Sequence
"Topaz" has the following requirements with regards to power-supply sequencing to
avoid damaging the ASIC:
D D
All the ASIC supplies must reach their respective nominal voltages within 20 ms
of the start of the ramp-up sequence, though a shorter ramp-up duration is
preferred. The maximum slew rate on all rails is 50 mV/ȝs. VRAM ID config
It is recommended that the 3.3-V rail ramp up first.
The 3.3-V, 1.8-V, and 0.95-V rails must reach their ready state at least 10 ȝs VRAM ID PU resistor PD resistor
Memory Type
before VDDC, VDDCI, and VMEMIO start to ramp up. PS_3[3:1] RV63 RV70
The power rails that are shared with other components on the system should be
gated for the dGPU so that when the dGPU is powered down (for example Hynix
AMD PowerXpress idle state), all the power rails are removed from the dGPU. 100 4.53K 4.99K
H5GC8H24AJR-R0C 6.0Gbps@1.35V
The gate circuits must meet the slew rate requirement (such as ” 50 mV/ȝs).
For power down, reversing the ramp-up sequence is recommended. 256Mx32 Micron
111 4.75K NC
MT51J256M32HF-70:B 6.0Gbps@1.35V

Samsung
110 3.4K 10K
K4G80325FB-HC28 6.0Gbps@1.35V
ϬΕϮϬŵƐ

VDDR3(+3VGS)
ϬΕϮϬŵƐ
C C

VDD_CT(+1.8VGS)

PCIE_VDDC(+0.95VGS)
ϭϬƵƐŵŝŶ͘

VDDR1(+1.35VGS)

VDDC/VDDCI(+VGA_CORE) ϭϬϬŵƐŵŝŶ͘

ϭϬϬƵƐŵŝŶ͘
PERSTb(GPU_RST#)

REFCLK(CLK_PCIE_VGA)
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B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2017/03/14 Deciphered Date 2017/03/14 VGA Notes List

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S145AST
Date: Thursday, October 25, 2018 Sheet 14 of 50
5 4 3 2 1
 5 4 3 2 1

PCIE_CTX_C_GRX_P[0..3] PCIE_CRX_GTX_P[0..3]
4 PCIE_CTX_C_GRX_P[0..3] PCIE_CRX_GTX_P[0..3] 4
UV1A
PCIE_CTX_C_GRX_N[0..3] PCIE_CRX_GTX_N[0..3]
4 PCIE_CTX_C_GRX_N[0..3] PCIE_CRX_GTX_N[0..3] 4

PCIE_CTX_C_GRX_P0 AF30 AH30 PCIE_CRX_C_GTX_P0 0.22U_0201_6.3V6-K 1 2 PX@ CV1 PCIE_CRX_GTX_P0

PCIE_CTX_C_GRX_N0 AE31 PCIE_RX0P PCIE_TX0P AG31 PCIE_CRX_C_GTX_N0 0.22U_0201_6.3V6-K 1 2 PX@ CV2 PCIE_CRX_GTX_N0
PCIE_RX0N PCIE_TX0N

PCIE_CTX_C_GRX_P1 AE29 AG29 PCIE_CRX_C_GTX_P1 0.22U_0201_6.3V6-K 1 2 PX@ CV3 PCIE_CRX_GTX_P1

D PCIE_RX1P PCIE_TX1P D
PCIE_CTX_C_GRX_N1 AD28 AF28 PCIE_CRX_C_GTX_N1 0.22U_0201_6.3V6-K 1 2 PX@ CV4 PCIE_CRX_GTX_N1
PCIE_RX1N PCIE_TX1N

PCIE_CTX_C_GRX_P2 AD30 AF27 PCIE_CRX_C_GTX_P2 0.22U_0201_6.3V6-K 1 2 PX@ CV5 PCIE_CRX_GTX_P2

PCIE_CTX_C_GRX_N2 AC31 PCIE_RX2P PCIE_TX2P AF26 PCIE_CRX_C_GTX_N2 0.22U_0201_6.3V6-K 1 2 PX@ CV6 PCIE_CRX_GTX_N2
PCIE_RX2N PCIE_TX2N

PCIE_CTX_C_GRX_P3 AC29 AD27 PCIE_CRX_C_GTX_P3 0.22U_0201_6.3V6-K 1 2 PX@ CV7 PCIE_CRX_GTX_P3

PCIE_CTX_C_GRX_N3 AB28 PCIE_RX3P PCIE_TX3P AD26 PCIE_CRX_C_GTX_N3 0.22U_0201_6.3V6-K 1 2 PX@ CV8 PCIE_CRX_GTX_N3
PCIE_RX3N PCIE_TX3N

AB30 AC25
AA31 PCIE_RX4P PCIE_TX4P AB25
PCIE_RX4N PCIE_TX4N

AA29 Y23
Y28 PCIE_RX5P PCIE_TX5P Y24
PCIE_RX5N PCIE_TX5N

Y30 AB27
W31 PCIE_RX6P PCIE_TX6P AB26
PCIE_RX6N PCIE_TX6N

W29 Y27
V28 PCIE_RX7P PCIE_TX7P Y26
PCIE_RX7N PCIE_TX7N

C C
V30 W24
U31 NC#V30 NC#W24 W23
NC#U31 NC#W23

U29 V27 with BOM strcture control, CV1--CV8 change to 0.22uf for CZ
T28 NC#U29 NC#V27 U26
NC#T28 NC#U26

PCI EXPRESS INTERFACE

T30 U24
R31 NC#T30 NC#U24 U23
NC#R31 NC#U23

R29 T26
P28 NC#R29 NC#T26 T27
NC#P28 NC#T27
GPU_RST# PXS_RST#
Vinafix.com P30
N31 NC#P30
NC#N31
NC#T24
NC#T23
T24
T23
change the GPU PN to AMD(EXO-S3 PRO), symbol check ok
0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

11/4 change to PC sample SA000074V10

PX@
@

N29 P27
M28 NC#N29 NC#P27 P26
1 1 NC#M28 NC#P26

M30 P24
2 2 NC#M30 NC#P24
CV669

CV632

L31 P23
NC#L31 NC#P23
B B

L29 M27
K30 NC#L29 NC#M27 N26
NC#K30 NC#N26

CLOCK
CLK_PCIE_GPU AK30
8 CLK_PCIE_GPU CLK_PCIE_GPU# PCIE_REFCLKP
AK32
8 CLK_PCIE_GPU# PCIE_REFCLKN
+3VALW +3V_GATE +0.95VGS
CALIBRATION
+3VGS RV1430 1 PX@ 2 0_0402_5% Y22 RV3 1 PX@ 2 1.69K_0402_1%
PCIE_CALR_TX
RV1429 1 @ 2 0_0402_5% 1K_0402_1% 1 PX@ 2 RV4 N10 AA22 RV5 1 PX@ 2 1K_0402_1%
TEST_PG PCIE_CALR_RX
UV2 power change to +3VALW to solve GPU_RST# glitch DV3
GPU_RST# AL27
16 GPU_RST# PERSTB GPU_RST# 2
1 VGA_PWROK
VGA_PWROK 48
1

@ VR_VGA_PWRGD 3
7,48 VR_VGA_PWRGD
RV7 1 @ 2 0_0402_5% RV6
100K_0402_5% LBAT54AWT1G SOT323
+3V_GATE PX@ PX@
2
5

UV2
A A
VCC

1
7,8 PXS_RST# IN1 GPU_RST#
4
2 OUT
GND

7,26,29,31,35 PLT_RST# IN2

Security Classification LC Future Center Secret Data Title
MC74VHC1G08DFT2G_SC70-5
ATI_EXO-PRO_PCIE
3

PX@ Issued Date 2017/03/14 Deciphered Date 2017/03/14

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S145AST
Date: Friday, October 26, 2018 Sheet 15 of 50
5 4 3 2 1
 5 4 3 2 1
RECOMMENDED SETTINGS
CONFIGURATION STRAPS 0= DO NOT INSTALL RESISTOR
1 = INSTALL 10K RESISTOR
UV1B ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE X = DESIGN DEPENDANT
GPIOS ARE USED, THEY MUST NOT CONFLICT DURING RESET NA = NOT APPLICABLE

AF2
NC#AF2 AF4 RECOMMENDED
NC#AF4 MLPS Bit Strap Name Description
SETTINGS
N9 AG3 PS_0[1] ROM_CONFIG[0] Define the ROM type when STRAP_BIOS_ROM_EN = 1,
L9 DBG_DATA16 NC#AG3 AG5 PS_0[2] ROM_CONFIG[1] Define the primary memory-aperture size when STRAP_BIOS_ROM_EN = 0.
AE9 DBG_DATA15 NC#AG5 PS_0[3] ROM_CONFIG[2] X
DPA
Y11 DBG_DATA14 AH3 001 = 256MB
AE8 DBG_DATA13 NC#AH3 AH1
AD9 DBG_DATA12 NC#AH1 PS_0[4] N/A Reserved for internal use only. Must be 1 at reset. 1
AC10 DBG_DATA11 AK3
AD7 DBG_DATA10 NC#AK3 AK1 AUD_PORT_CONN_ The LSB (least significant bit) of the strap option that
AC8 DBG_DATA9 NC#AK1 PS_0[5] PINSTRAP[0] indicates the number of audio-capable display outputs. 1
DVO
AC7 DBG_DATA8 AK5
AB9 DBG_DATA7 NC#AK5 AM3 1 = PCIe GEN3 is supported.
AB8 DBG_DATA6 NC#AM3 PS_1[1] STRAP_BIF_GEN3_EN_A 0 = PCIe GEN3 is not supported. 1= GEN3 is supported X
AB7 DBG_DATA5 AK6
AB4 DBG_DATA4 NC#AK6 AM5 0 = The CLKREQB power management capability is disabled
AB2 DBG_DATA3 NC#AM5 PS_1[2] STRAP_BIF_CLK_PM_EN 1 = The CLKREQB power management capability is enabled 0
DPB
Y8 DBG_DATA2 AJ7
D Y7 DBG_DATA1 NC#AJ7 AH6 PS_1[3] N/A Reserved for internal use only. Must be 0 at reset. 0 D
+3VGS DBG_DATA0 NC#AH6
AK8 STRAP_TX_CFG_DRV_ 0 = The transmitter half-swing is enabled
NC#AK8 AL7 PS_1[4] FULL_SWING 1 = The transmitter full-swing is enabled 1
10K_0402_5% 1 @ 2 RV8 GPU_GPIO5 NC#AL7
0 = Tx deemphasis disabled.
W6 PS_1[5] STRAP_TX_DEEMPH_EN 1 = Tx deemphasis enabled. 1= Enable X
V6 NC#W6
10K_0402_5% 1 @ 2 RV9 GPU_GPIO0 NC#V6 V4 PS_2[1] N/A Reserved. 0
10K_0402_5% 1 @ 2 RV12 GPU_GPIO8 AC6 NC#V4 U5
10K_0402_5% 1 @ 2 RV13 GPU_GPIO9 AC5 NC#AC6 NC#U5 PS_2[2] N/A Reserved. 0
10K_0402_5% 1 @ 2 RV14 GPU_GPIO10 NC#AC5 W3 VGA_VSSI_SEN 1 TV10 Test_Point_16MIL @
10K_0402_5% 1 @ 2 RV25 GPU_GPIO11 AA5 NC#W3 V2 0 = Disable the external BIOS ROM device.
10K_0402_5% 1 @ 2 RV96 GPU_GPIO12 AA6 NC#AA5 NC#V2 PS_2[3] STRAP_BIOS_ROM_EN 1 = Enable the external BIOS ROM device. 0= Disable X
DPC
10K_0402_5% 1 @ 2 RV34 GPU_GPIO13 +1.8VGS NC#AA6 Y4
10K_0402_5% 1 @ 2 RV81 GPU_GPIO22 NC#Y4 W5 0 = VGA controller capacity enabled.
10K_0402_5% 1 @ 2 RV97 GPU_VID1 NC#W5 PS_2[4] STRAP_BIF_VGA_DIS 1 = The device will not be recognized as the system’s VGA 1
10K_0402_5% 1 @ 2 RV98 GPU_GPIO21 RV93 1 2 TOPAZ@ BP_0 U1 AA3 PLL_ANALOG_OUT RV94 1 @ 2 controller.
10K_0402_5% 1 @ 2 RV99 GPU_VID5 10K_0402_5% @ TV11 1 VGA_VDDCI_SEN W1 NC#U1 NC#AA3 Y2 16.2K_0402_1% PS_2[5] N/A Reserved 1
10K_0402_5% 1 @ 2 RV106 GPU_VID2 RV95 1 2 TOPAZ@ BP_1 U3 NC#W1 NC#Y2
NC#U3
10K_0402_5% Y6
NC#Y6 NC#J8
J8  !"# Board configuration related strapping, such as for memory ID
10K_0402_5% 1 @ 2 RV1011GPU_GPIO17 @ TV12 1 PLL_ANALOG_IN AA1 PS_3[1] BOARD_CONFIG[0] 100 = Hynix 1G 000 = Hynix 2G X
NC#AA1 PS_3[2] BOARD_CONFIG[1] 111 = Micron 1G 010 = Micron 2G
5.11K_0402_1% 1 @ 2 RV1039TESTEN PS_3[3] BOARD_CONFIG[2] 110 = Samsung 1G 001 = Samsung 2G

Determines the maximum number of digital display audio endpoints

Reserve I2C that will be presented to the OS and user.(Combine with PS_0[5])
111 = No usable endpoints.
R1 AUD_PORT_CONN_ 110 = One usable endpoint.
R3 SCL PS_3[4] PINSTRAP[1] 101 = Two usable endpoints. 111= No usable endpoints.
+VGA_CORE SDA 100 = Three usable endpoints. 11
AM26 DIECRACKMON RV120 1 2 TOPAZ@ PS_3[5] AUD_PORT_CONN_ 011 = Four usable endpoints.
NC_R PINSTRAP[2] 010 = Five usable endpoints.
AK26 10K_0402_5% 001 = Six usable endpoints.
GPU_GPIO0 U6 GENERAL PURPOSE I/O NC_AVSSN#AK26
GPIO_0 000 = All endpoints are usable.
U10 AL25
T10 NC_GPIO_1 NC_G AJ25
VGA_SMB_DATA U8 NC_GPIO_2 NC_AVSSN#AJ25
RB751V-40_SOD323-2 VGA_SMB_CLK U7 SMBDATA AH24
DV1 1 2 @ GPU_GPIO5 T9 SMBCLK NC_B AG25 +1.8VGS +1.8VGS
35 VGA_AC_DET GPU_VID5 GPIO_5_AC_BATT NC_AVSSN#AG25
T8
T7 GPIO_6 DAC1 AH26

1
GPU_VR_HOT# RV104 1 PX@ 20_0402_5% GPU_GPIO8 P10 NC_GPIO_7 NC_HSYNC AJ27 RV22 1 2 4.7K_0402_5%
GPU_GPIO9 P4 GPIO_8_ROMSO NC_VSYNC TOPAZ@ RV71 RV74
GPU_GPIO10 P2 GPIO_9_ROMSI 8.45K_0402_1% 8.45K_0402_1%
GPIO_10_ROMSCK
+VGA_CORE GPU_GPIO11
GPU_GPIO12
N6
NC_GPIO_11 NC_RSET
AD22 WƵůůĚŽǁŶĨŽƌŶŽŶĞK&&ĚĞƐŝŐŶ PX@ PX@
@ Test_Point_16MIL TV3 1 N5

2
GPU_GPIO13 N3 NC_GPIO_12 AG24 PS_0 PS_1
Y9 NC_GPIO_13 NC_AVDD AE22

1
GPU_SVD 0_0402_5% 1 EXO@ 2 RV103 GPU_VID3 N1 NC_GPIO_14 NC_AVSSQ
GPIO_15_PWRCNTL_0 1 1
C 10K_0402_5% 1 @ 2 RV67 GPU_GPIO16 M4 AE23 RV77 CV15 RV80 CV16 C
0_0402_5% 1 @ 2 RV107 GPU_GPIO17 R6 GPIO_16 NC_VDD1DI AD23 2K_0402_1% .01U_0402_16V7-K 2K_0402_1% .01U_0402_16V7-K
35,48 GPU_VR_HOT# GPIO_17_THERMAL_INT NC_VSS1DI
W10 PX@ @ PX@ @
10K_0402_5% 1 PX@ 2 RV68 GPIO_19_CTF M2 NC_GPIO_18 2 2
FutureASIC/SEYMOUR/PARK

2
GPU_SVC 0_0402_5% 1 EXO@ 2 RV105 GPU_VID4 P8 GPIO_19_CTF AM12 CEC_1 1 TV5 Test_Point_16MIL @
GPU_GPIO21 P7 GPIO_20_PWRCNTL_1 CEC_1
GPU_GPIO22 N8 GPIO_21
GPU_VID2 AK10 GPIO_22_ROMCSB AK12 GPU_SVD_R RV110 1 TOPAZ@2 0_0402_5% +1.8VGS +1.8VGS
GPU_VR_HOT# 0_0402_5% GPU_VID1 GPIO_29 NC_SVI2#AK12 GPU_SVT_R GPU_SVD 48
1 @ 2 RV1012 AM10 AL11 RV109 1 TOPAZ@2 0_0402_5%
GPU_CLKREQ#_R GPIO_30 NC_SVI2#AL11 GPU_SVC_R GPU_SVT 48
0_0402_5% 1 @ 2 RV124 N7 AJ11 RV111 1 TOPAZ@2 0_0402_5%
7 GPU_CLKREQ# GPU_SVC 48

1
CLKREQB NC_SVI2#AJ11
JTAG_TRSTB L6 RV60 RV63
+3VGS JTAG_TDI L5 JTAG_TRSTB 10K_0402_5% 8.45K_0402_1%
JTAG_TCK L3 JTAG_TDI @ @
JTAG_TMS L1 JTAG_TCK AL13 GENLK_CLK 1 TV1 Test_Point_16MIL @

2
10K_0402_5% 1 @ 2 RV72 JTAG_TRSTB @ Test_Point_16MIL TV7 1JTAG_TDO K4 JTAG_TMS NC_GENLK_CLK AJ13 GENLK_VSYNC 1 TV2 Test_Point_16MIL @ PS_2 PS_3
10K_0402_5% 1 @ 2 RV75 JTAG_TDI RV64 1 PX@ 2 TESTEN K7 JTAG_TDO NC_GENLK_VSYNC

1
10K_0402_5% 1 @ 2 RV78 JTAG_TMS 1K_0402_5% AF24 TESTEN
NC#AF24 1 1
AG13 RV69 CV18 RV70 CV19
10K_0402_5% 1 @ 2 RV40 JTAG_TCK NC_SWAPLOCKA AH12 4.75K_0402_1% .01U_0402_16V7-K 2K_0402_1% .01U_0402_16V7-K
AB13 NC_SWAPLOCKB PX@ @ @ @
+VGA_CORE NC_GENERICA 2 2
W8

2
470_0402_5% 1 @ 2 RV1040GPU_CLKREQ# W9 NC_GENERICB
W7 NC_GENERICC AC19 PS_0
AD10 NC_GENERICD PS_0
2016/09/02: Pull-down GPU_CLKREQ# at GPU side NC_GENERICE_HPD4
AJ9 AD19 PS_1
NC#AJ9 PS_1

ǂ ǂ
AL9 Bit BOM

Vinafix.com
DBG_CNTL0 AE17 PS_2
PS_2 MLPS
AC14 5 4 3 2 1 R_pu( ) R_pd( ) C(nF)
@ Test_Point_16MIL TV6 1 PX_EN AB16 NC_HPD1 AE20 PS_3
PX_EN PS_3
PS_0[5:1] 1 1 0 0 1 RV71=8.45k RV77=2K CV15=NC
4.7K_0402_5% 1 @ 2 RV54
PX@ 1 2 CV25 XTALIN AE19 PS_1[5:1] 1 1 0 0 1 RV74=8.45K RV80=2K CV16=NC
@ TV15 1 NC_DBG_VREFG AC16 TS_A
NC_DBG_VREFG
PS_2[5:1] 1 1 0 0 0 RV60=NC RV69=4.75K CV18=NC
10P_0201_50V8-D
PS_3[5:1] 1 1 X X X RV63=X76 RV70=X76 CV19=NC
DDC/AUX
2

AE6
R_pu (ȍ) R_pd (ȍ)
YV1 PLL/CLOCK NC_DDC1CLK AE5
27MHZ_10PF_7V27000050

with BOM strcture control, Bits [3:1]

GND1

OSC1

PX@ NC_DDC1DATA
RV63,RV70 change to different value to
1

AD2 +VGA_CORE NC 4750 000

adjust VRAM config

1
RV46 NC_AUX1P AD4
1M_0402_5% NC_AUX1N RV24 8450 2000 001
with BOM strcture control,
GND2
OSC2

PX@ AC11 100_0402_5% when config PEG3

NC_DDC2CLK AC13 TOPAZ@ 4530 2000 010
RV74 change to 8.45K,
2

NC_DDC2DATA
RV80 change to 2K

2
XTALIN AM28 AD13 6980 4990 011
3

XTALOUT AK28 XTALIN NC_AUX2P AD11

XTALOUT NC_AUX2N 4530 4990 100
B XO_IN VGA_VSS_SEN_R
Capacitor Value (nF) Bits [5:4] B
10K_0402_5% 1 PX@ 2 RV45 AC22 AD20 RV125 1 TOPAZ@2 0_0402_5%
XO_IN2 XO_IN NC#AD20 VGA_CORE_SEN_R VGA_VSS_SEN 48
10K_0402_5% 1 PX@ 2 RV50 AB22 AC20 RV126 1 TOPAZ@2 0_0402_5% 680 00 3240 5620 101
XO_IN2 NC#AC20 VGA_CORE_SEN 48
PX@ 1 2 CV32 XTALOUT AE16 82 01 3400 10000 110
NC#AE16 AD16
NC#AD16 1
10 10 4750 NC 111
10P_0201_50V8-D SEYMOUR/FutureASIC AC1
NC_DDCVGACLK
$%!!& ' (&')' ( @ TV13 1 GPU_DPLUS
GPU_DMINUS
T4
DPLUS THERMAL NC_DDCVGADATA
AC3 RV23 NC 11 Note: 0402 1% resistors are required.
@ TV14 1 T2 100_0402_5%
DMINUS TOPAZ@
+3VGS +VDDIO_GPU
2

RV41 1 @ 2 GPIO_28_FDO R5
+3VGS GPIO28_FDO
10K_0402_5% +1.8VGS LV3 1 2 PX@ +TSVDD AD17 SVC SVD Output Voltage (V) RV234 1 2 EXO@
BLM15PD121SN1D_2P AC17 TSVDD +1.8VGS 0_0402_5%
TSVSS +VGA_CORE 0 0 1.1
2

(1.8V@20mA TSVDD) RV203 1 2 TOPAZ@

RV42 1 0 1 1.0 0_0402_5%
10K_0402_5% CV21 @
EXO@ 1U_0402_6.3V6K For Topaz, RV23/RV24 stuff 100ohm 1 0 0.9
PX@ For EXO, RV23/RV24 stuff 0hm
1

2
2 1 1 0.8
RV205 RV204 RV209
10K_0402_5% 10K_0402_5% 10K_0402_5%
ŽŶŶĞĐƚ'W/KͺϮϴƚŽϭϬ<ƉƵůů @ PX@ @
ĚŽǁŶƚŽĞŶĂďůĞD>W^͘

1
GPU_SVD
GPU_SVC
GPU_SVT
RV242 2 @ 1 0_0402_5% WRST# 35

2
RV206 RV207 RV210
10K_0402_5% 10K_0402_5% 10K_0402_5%
PX@ @ @

1
1

C QV13
GPU_RST# @ 1 2 DV2 RV128 1 @ 2 2 MMBT3904WH_SOT323-3     
15 GPU_RST# B
2.2K_0402_5% @
0.1U_0201_6.3V6-K

SDM10U45LP-7_DFN1006-2-2 @ E
3
1

+3VGS
1
RV131 +3VGS
GPIO_19_CTF 1 @ 2 RV132 100K_0402_5%
47K_0402_5% @
1

2
CV215

A A
2

RV43 RV44
2

47K_0402_5% 47K_0402_5%
G

PX@ PX@
2

VGA_SMB_CLK QV4A 1 6 PX@

S

EC_SMB_CK3 6,30,35
D

2N7002KDWH_SOT363-6
G

VGA_SMB_DATA QV4B 4 3 PX@

S

EC_SMB_DA3 6,30,35
D

2N7002KDWH_SOT363-6

Security Classification LC Future Center Secret Data Title

Issued Date 2017/03/14 Deciphered Date 2017/03/14 ATI_EXO-PRO_Main_MSIC
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S145AST
Date: Thursday, October 25, 2018 Sheet 16 of 50
5 4 3 2 1
 5 4 3 2 1

UV1F
+VGA_CORE

D AB11 D
NC_VARY_BL AB12
NC_DIGON

AL15
NC_UPHYAB_TMDPA_TX0N AK14
NC_UPHYAB_TMDPA_TX0P
AH16
NC_UPHYAB_TMDPA_TX1N AJ15
NC_UPHYAB_TMDPA_TX1P
AL17
NC_UPHYAB_TMDPA_TX2N AK16
NC_UPHYAB_TMDPA_TX2P
AH18
NC_UPHYAB_TMDPA_TX3N AJ17
NC_UPHYAB_TMDPA_TX3P
AL19
NC_TXOUT_L3P AK18
NC_TXOUT_L3N

C TMDP C

AH20
NC_UPHYAB_TMDPB_TX0N AJ19
NC_UPHYAB_TMDPB_TX0P
AL21
NC_UPHYAB_TMDPB_TX1N AK20
NC_UPHYAB_TMDPB_TX1P
AH22
NC_UPHYAB_TMDPB_TX2N AJ21
NC_UPHYAB_TMDPB_TX2P
AL23
NC_UPHYAB_TMDPB_TX3N AK22
NC_UPHYAB_TMDPB_TX3P
AK24
NC_TXOUT_U3P AJ23
NC_TXOUT_U3N

B B

Vinafix.com

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2017/03/14 Deciphered Date 2017/03/14 ATI_EXO-PRO_TMDP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S145AST
Date: Thursday, October 25, 2018 Sheet 17 of 50
5 4 3 2 1
 5 4 3 2 1

+1.8VGS (1.8V@425mA DP_VDDR)

RV48 1 PX@ 2 0_0603_5% +DP_VDDR
UV1G UV1E

PX@

PX@
10U_0603_6.3V6M

1U_0402_6.3V6K
DP POWER NC/DP POWER
1 1
AG15 AE11 AA27 A3
AG16 NC_DP_VDDR#AG15 NC#AE11 AF11 AB24 GND_1 GND_65 A30
AF16 NC_DP_VDDR#AG16 NC#AF11 AE13 AB32 GND_2 GND_66 AA13
D D
2 2 NC_DP_VDDR#AF16 NC#AE13 GND_3 GND_67

CV39

CV40
AG17 AF13 AC24 AA16
AG18 NC_DP_VDDR#AG17 NC#AF13 AG8 AC26 GND_4 GND_68 AB10
AG19 NC_DP_VDDR#AG18 NC#AG8 AG10 AC27 GND_5 GND_69 AB15
AF14 NC_DP_VDDR#AG19 NC#AG10 AD25 GND_6 GND_70 AB6
DP_VDDR#AF14 AD32 GND_7 GND_71 AC9
AE27 GND_8 GND_72 AD6
+0.95VGS AF32 GND_9 GND_73 AD8
(0.95V@560mA DP_VDDC) GND_10 GND_74
AG27 AE7
RV47 1 PX@ 2 0_0603_5% +DP_VDDC AG20 AF6 AH32 GND_11 GND_75 AG12
AG21 NC_DP_VDDC#AG20 NC#AF6 AF7 K28 GND_12 GND_76 AH10
NC_DP_VDDC#AG21 NC#AF7 GND_13 GND_77

PX@

PX@
AF22 AF8 K32 AH28

0.1U_0201_6.3V6-K
AG22 NC_DP_VDDC#AF22 NC#AF8 AF9 L27 GND_14 GND_78 B10

1U_0402_6.3V6K
AD14 NC_DP_VDDC#AG22 NC#AF9 M32 GND_15 GND_79 B12
1 1 DP_VDDC#AD14 GND_16 GND_80
N25 B14
N27 GND_17 GND_81 B16
P25 GND_18 GND_82 B18
2 2 GND_19 GND_83

CV38

CV37
AG14 AE1 P32 B20
AH14 NC_DP_VSSR_1 NC#AE1 AE3 R27 GND_20 GND_84 B22
AM14 NC_DP_VSSR_2 NC#AE3 AG1 T25 GND_21 GND_85 B24
AM16 NC_DP_VSSR_3 NC#AG1 AG6 T32 GND_22 GND_86 B26
AM18 NC_DP_VSSR_4 NC#AG6 AH5 U25 GND_23 GND_87 B6
AF23 NC_DP_VSSR_5 NC#AH5 AF10 U27 GND_24 GND_88 B8
AG23 NC_DP_VSSR_6 NC#AF10 AG9 V32 GND_25 GND_89 C1
AM20 NC_DP_VSSR_7 NC#AG9 AH8 W 25 GND_26 GND_90 C32
C
AM22 NC_DP_VSSR_8 NC#AH8 AM6 W 26 GND_27 GND_91 E28 C
AM24 NC_DP_VSSR_9 NC#AM6 AM8 W 27 GND_28 GND_92 F10
AF19 NC_DP_VSSR_10 NC#AM8 AG7 Y25 GND_29 GND_93 F12
AF20 NC_DP_VSSR_11 NC#AG7 AG11 Y32 GND_30 GND_94 F14
AE14 NC_DP_VSSR_12 NC#AG11 GND_31 GND_95 F16
DP_VSSR_13 GND_96 F18
GND_97 F2
GND_98 F20
RV49 1 @ 2 AF17 AE10 M6 GND_99 F22
150_0402_1% NC_UPHYAB_DP_CALR NC#AE10 N13 GND_32 GND_100 F24
N16 GND_33 GND_101 F26
N18 GND_34 GND_102 F6
@ N21 GND_35 GND
GND_103 F8
P6 GND_36 GND_104 G10
P9 GND_37 GND_105 G27
R12 GND_38 GND_106 G31
R15 GND_39 GND_107 G8
R17 GND_40 GND_108 H14
R20 GND_41 GND_109 H17
T13 GND_42 GND_110 H2
T16 GND_43 GND_111 H20

B
Vinafix.com T18
T21
T6
U15
U17
U20
GND_44
GND_45
GND_46
GND_47
GND_48
GND_49
GND_112
GND_113
GND_114
GND_115
GND_116
GND_117
H6
J27
J31
K11
K2
K22
B

U9 GND_50 GND_118 K6
V13 GND_51 GND_119
V16 GND_52
V18 GND_53
Y10 GND_54
Y15 GND_55
Y17 GND_56
Y20 GND_57
R11 GND_58 A32
T11 GND_59 VSS_MECH_1 AM1
AA11 GND_60 VSS_MECH_2 AM32
M12 GND_61 VSS_MECH_3
N11 GND_62
V11 GND_63
GND_64

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2017/03/14 Deciphered Date 2017/03/14 ATI_EXO-PRO_DP Power
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S145AST
Date: Thursday, October 25, 2018 Sheet 18 of 50
5 4 3 2 1
 5 4 3 2 1

+1.35VGS
For DDR3/GDDR5, 1500mA@1.5V

CV48

CV51

CV52

CV53

CV54

CV55

CV56

CV217
10U_0603_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

0.1U_0201_6.3V6-K

0.01U_6.3V_K_X7R_0201
1 1 1 1 1 1 1 1 1 UV1D +1.8VGS
CV501 (1.8V@100mA PCIE_PVDD)
33P_0402_50V8J AM30
PCIE_PVDD

PCIE
RF_PXNS@ MEM I/O

CV46

CV47
2 2 2 2 2 2 2 2 2 H13 AB23

10U_0603_6.3V6M
1U_0402_6.3V6K
VDDR1_1 NC#AB23

PX@

PX@

PX@

PX@

PX@

PX@

PX@

PX@
H16 AC23 1 1
H19 VDDR1_2 NC#AC23 AD24
RF VDDR1_3 NC#AD24
J10 AE24
J23 VDDR1_4 NC#AE24 AE25
J24 VDDR1_5 NC#AE25 AE26 2 2
VDDR1_6 NC#AE26

PX@

PX@
J9 AF25
K10 VDDR1_7 NC#AF25 AG26
+1.8VGS +VDD_CT K23 VDDR1_8 NC#AG26 +0.95VGS
(1.8V@13mA VDD_CT) VDDR1_9
D K24 D
VDDR1_10 (0.95V@1000mA PCIE_VDDC)
RV1364 1 PX@ 2 0_0402_5% K9 L23
L11 VDDR1_11 PCIE_VDDC_1 L24

CV144
L12 VDDR1_12 PCIE_VDDC_2 L25

CV64

CV65

CV66

CV67

CV68

CV69

CV71
1U_0402_6.3V6K
L13 VDDR1_13 PCIE_VDDC_3 L26

10U_0603_6.3V6M
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
1 VDDR1_14 PCIE_VDDC_4
L20 M22 1 1 1 1 1 1 1 1
L21 VDDR1_15 PCIE_VDDC_5 N22 CV502
L22 VDDR1_16 PCIE_VDDC_6 N23 33P_0402_50V8J
2 VDDR1_17 PCIE_VDDC_7

PX@
N24 RF_PXNS@
PCIE_VDDC_8 R22 2 2 2 2 2 2 2 2
PCIE_VDDC_9

PX@

PX@

PX@

PX@

PX@

PX@

PX@
T22 RF
LEVEL PCIE_VDDC_10 U22
TRANSLATION PCIE_VDDC_11 V22
AA20 PCIE_VDDC_12 +VGA_CORE
AA21 VDD_CT_1
AB20 VDD_CT_2 AA15
+3VGS AB21 VDD_CT_3 CORE VDDC_1 N15
(3.3V@25mA VDDR3) VDD_CT_4 VDDC_2 N17

CV633

CV666

CV667

CV668

CV636

CV637

CV638

CV639

CV73

CV74

CV75

CV76

CV77

CV141

CV143

CV146

CV148

CV150

CV152

CV84

CV159

CV133

CV137

CV151
10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

RV1365 1 PX@ 2 0_0402_5% +VDDR3 VDDC_3 R13

CV665

CV664
I/O VDDC_4 R16

CV149
VDDC_5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
change LV4 to SM01000MK00 (S SUPPRE_ BLM15AG221SN1 122) AA17 R18

1U_0402_6.3V6K
AA18 VDDR3_1 VDDC_6 Y21
as DFC suggest, footprint with 1 VDDR3_2 VDDC_7
AB17 T12

PX@ 1U_0201_6.3V6-M

PX@ 1U_0201_6.3V6-M
MURAT_BLM15PD121SN1D_2P AB18 VDDR3_3 VDDC_8 T15 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
VDDR3_4 VDDC_9 T17
2 VDDC_10

PX@
@TV16 1 V12 T20
@TV17 1 Y12 NC_VDDR4_1 VDDC_11 U13
NC_VDDR4_2 VDDC_12 PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@
+1.8VGS @TV18 1 U12 U16
NC_VDDR4_3 VDDC_13 U18
(1.8V@130mA MPLL_PVDD) VDDC_14 V21
LV4 1 2 PX@ +MPLL_PVDD VDDC_15 V15

CV139

CV153

CV156

CV160

CV134

CV135
22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603
BLM15AG221SN1 VDDC_16 V17

CV640

CV642

CV643

CV644

CV645

CV646

CV647

CV649

CV648

CV650

CV651
10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

VDDC_17 V20
CV26

CV34

CV27

CV661
VDDC_18

POWER
Y13
CV24

10U_0603_6.3V6M

10U_0603_6.3V6M

1U_0402_6.3V6K

2.2U_0402_6.3V6M
0.1U_0201_6.3V6-K

VDDC_19 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 Y16 CV503
VDDC_20 Y18
1 VDDC_21 AA12

PX@ 1U_0201_6.3V6-M
VDDC_22 M11 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
2 2 2 VDDC_23 N12
2 VDDC_24
PX@

PX@

PX@

U11
VDDC_25

PX@

PX@

PX@

PX@

PX@

PX@
@
@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@
C
&ŽƌD C
PLL
+0.95VGS
(0.95V@800mA BIF_VDDC)
+1.8VGS R21
BIF_VDDC_1 U21
(1.8V@75mA SPLL_PVDD) BIF_VDDC_2
1
LV5 1 2 PX@ +SPLL_PVDD +MPLL_PVDD L8 CV41
BLM15PD121SN1D_2P MPLL_PVDD 1U_0402_6.3V6K
PX@
CV29

CV30

ISOLATED
2 +VGA_CORE
CV28

10U_0603_6.3V6M

1U_0402_6.3V6K
0.1U_0201_6.3V6-K

CORE I/O
1 1 M13
+SPLL_PVDD H7 VDDCI_1 M15
1 SPLL_PVDD VDDCI_2 (GDDR3/DDR3 8.8A@1.12V VDDCI)
M16
+0.95VGS VDDCI_3 M17
2 2 VDDCI_4 M18

CV218

CV219

CV138

CV220
(0.95V@100mA SPLL_VDDC)

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603
2 VDDCI_5 M20

CV158

CV132

CV136
0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

+SPLL_VDDC VDDCI_6
PX@

PX@

@ LV6 1 2 PX@ H8 M21

SPLL_VDDC VDDCI_7
&ŽƌD BLM15PD121SN1D_2P
J7 VDDCI_8
N20 1 1 1 1 1 1 1 1
CV504
SPLL_PVSS 2.2U_0402_6.3V6M
CV35

CV36
0.1U_0201_6.3V6-K

Vinafix.com
1U_0402_6.3V6K

2 2 2 2 2 2 2 2
1 1 1

PX@

PX@
CV33 @
0.1U_0201_6.3V6-K

PX@

PX@

PX@
@ PX@ PX@ PX@
2 2 2
PX@

PX@

&ŽƌD

+3VGS
+1.8VGS

B B
CV241

CV243

CV242

CV513

CV511
10U_0603_6.3V6M
10U_0603_6.3V6M

10U_0603_6.3V6M

1U_0402_6.3V6K

1U_0402_6.3V6K
1 1 1 1 1

2 2 2 @ 2 2

@
@

@
@

+0.95VGS
CV240

CV238

CV239

CV521

0.1U_0201_6.3V6-K
10U_0603_6.3V6M

10U_0603_6.3V6M

1U_0402_6.3V6K

1 1 1 1

2 2 2 2
@

140S AST GPU VGS power change to PMIC solution, reserve old power solution capacitor
A A

Security Classification LC Future Center Secret Data Title

Issued Date 2017/03/14 Deciphered Date 2017/03/14 ATI_EXO-PRO_Power

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S145AST
Date: Thursday, October 25, 2018 Sheet 19 of 50
5 4 3 2 1
 5 4 3 2 1

UV1C
DQA0_[31..0]
DQA0_[31..0] 21 GDDR5/DDR3 GDDR5/DDR3
DQA0_0 K27 K17 MAA0_0
DQA1_[31..0] DQA0_1 J29 DQA0_0 MAA0_0/MAA_0 J20 MAA0_1
DQA1_[31..0] 21 DQA0_2 DQA0_1 MAA0_1/MAA_1 MAA0_2
H30 H23
DQA0_3 H32 DQA0_2 MAA0_2/MAA_2 G23 MAA0_3
DQA0_4 G29 DQA0_3 MAA0_3/MAA_3 G24 MAA0_4
DQA0_5 F28 DQA0_4 MAA0_4/MAA_4 H24 MAA0_5
DQA0_6 F32 DQA0_5 MAA0_5/MAA_5 J19 MAA0_6
D DQA0_6 MAA0_6/MAA_6 D
DQA0_7 F30 K19 MAA0_7
DQA0_8 C30 DQA0_7 MAA0_7/MAA_7 G20 MAA0_8
MAA0_[8..0] DQA0_9 F27 DQA0_8 MAA0_8/MAA_13 L17
MAA0_[8..0] 21 DQA0_10 DQA0_9 MAA0_9/MAA_15
A28
DQA0_11 C28 DQA0_10 J14 MAA1_0
MAA1_[8..0] DQA0_12 E27 DQA0_11 MAA1_0/MAA_8 K14 MAA1_1
MAA1_[8..0] 21 DQA0_13 DQA0_12 MAA1_1/MAA_9 MAA1_2
G26 J11
DQA0_14 D26 DQA0_13 MAA1_2/MAA_10 J13 MAA1_3
DQA0_15 F25 DQA0_14 MAA1_3/MAA_11 H11 MAA1_4
DQA0_16 A25 DQA0_15 MAA1_4/MAA_12 G11 MAA1_5
DQA0_17 C25 DQA0_16 MAA1_5/MAA_BA2 J16 MAA1_6
DQA0_18 E25 DQA0_17 MAA1_6/MAA_BA0 L15 MAA1_7
DQA0_19 D24 DQA0_18 MAA1_7/MAA_BA1 G14 MAA1_8
DQA0_20 E23 DQA0_19 MAA1_8/MAA_14 L16

MEMORY INTERFACE
DQA0_21 F23 DQA0_20 MAA1_9/RSVD
DQA0_22 D22 DQA0_21 E32 WCKA0_0
DQA0_23 DQA0_22 WCKA0_0/DQMA0_0 WCKA0#_0 WCKA0_0 21
F21 E30
DQA0_24 DQA0_23 WCKA0B_0/DQMA0_1 WCKA0_1 WCKA0#_0 21
E21 A21
DQA0_25 DQA0_24 WCKA0_1/DQMA0_2 WCKA0#_1 WCKA0_1 21
D20 C21
DQA0_26 DQA0_25 WCKA0B_1/DQMA0_3 WCKA1_0 WCKA0#_1 21
F19 E13
DQA0_27 DQA0_26 WCKA1_0/DQMA1_0 WCKA1#_0 WCKA1_0 21
A19 D12
DQA0_28 DQA0_27 WCKA1B_0/DQMA1_1 WCKA1_1 WCKA1#_0 21
D18 E3
DQA0_29 DQA0_28 WCKA1_1/DQMA1_2 WCKA1#_1 WCKA1_1 21
F17 F4
DQA0_30 DQA0_29 WCKA1B_1/DQMA1_3 WCKA1#_1 21
A17
DQA0_31 C17 DQA0_30 H28 EDCA0_0
DQA1_0 DQA0_31 EDCA0_0/QSA0_0 EDCA0_1 EDCA0_0 21
E17 C27
DQA1_1 DQA1_0 EDCA0_1/QSA0_1 EDCA0_2 EDCA0_1 21
C D16 A23 C
DQA1_2 DQA1_1 EDCA0_2/QSA0_2 EDCA0_3 EDCA0_2 21
+1.35VGS F15 E19
DQA1_3 DQA1_2 EDCA0_3/QSA0_3 EDCA1_0 EDCA0_3 21
A15 E15
DQA1_4 DQA1_3 EDCA1_0/QSA1_0 EDCA1_1 EDCA1_0 21
D14 D10
DQA1_4 EDCA1_1/QSA1_1 EDCA1_1 21
1

DQA1_5 F13 D6 EDCA1_2

DQA1_6 DQA1_5 EDCA1_2/QSA1_2 EDCA1_3 EDCA1_2 21
RV61 A13 G5
DQA1_7 DQA1_6 EDCA1_3/QSA1_3 EDCA1_3 21
40.2_0402_1% C13
PX@ DQA1_8 E11 DQA1_7 H27 DDBIA0_0
DQA1_9 DQA1_8 DDBIA0_0/QSA0_0B DDBIA0_1 DDBIA0_0 21
A11 A27
DDBIA0_1 21
2

MVREFD_A DQA1_10 C11 DQA1_9 DDBIA0_1/QSA0_1B C23 DDBIA0_2

DQA1_11 DQA1_10 DDBIA0_2/QSA0_2B DDBIA0_3 DDBIA0_2 21
F11 C19
DQA1_11 DDBIA0_3/QSA0_3B DDBIA0_3 21
1

1 DQA1_12 A9 C15 DDBIA1_0

DQA1_13 DQA1_12 DDBIA1_0/QSA1_0B DDBIA1_1 DDBIA1_0 21
RV65 CV154 C9 E9
DQA1_14 DQA1_13 DDBIA1_1/QSA1_1B DDBIA1_2 DDBIA1_1 21
100_0402_1% 1U_0402_6.3V6K F9 C5
DQA1_15 DQA1_14 DDBIA1_2/QSA1_2B DDBIA1_3 DDBIA1_2 21
PX@ PX@ D8 H4
2 DQA1_16 DQA1_15 DDBIA1_3/QSA1_3B DDBIA1_3 21
E7
2

DQA1_17 A7 DQA1_16 L18 ADBIA0

DQA1_18 DQA1_17 ADBIA0/ODTA0 ADBIA0 21
C7 K16 ADBIA1
DQA1_19 DQA1_18 ADBIA1/ODTA1 ADBIA1 21
F7
DQA1_20 A5 DQA1_19 H26 CLKA0
DQA1_21 DQA1_20 CLKA0 CLKA0 21
E5 H25 CLKA#0
DQA1_22 DQA1_21 CLKA0B CLKA#0 21
C3
DQA1_23 E1 DQA1_22 G9 CLKA1

Vinafix.com DQA1_24 DQA1_23 CLKA1 CLKA1 21

G7 H9 CLKA#1
DQA1_25 DQA1_24 CLKA1B CLKA#1 21
+1.35VGS G6
DQA1_26 G1 DQA1_25 G22 RASA#0
DQA1_27 DQA1_26 RASA0B RASA#0 21
G3 G17 RASA#1
DQA1_27 RASA1B RASA#1 21
1

DQA1_28 J6
B DQA1_28 B
RV62 DQA1_29 J1 G19 CASA#0
DQA1_30 DQA1_29 CASA0B CASA#0 21
40.2_0402_1% J3 G16 CASA#1
DQA1_31 DQA1_30 CASA1B CASA#1 21
PX@ J5
DQA1_31 H22 CSA0#_0
CSA0#_0 21
2

MVREFS_A MVREFD_A K26 CSA0B_0 J22

MVREFS_A J26 MVREFDA CSA0B_1
MVREFSA
1

1 G13 CSA1#_0
CSA1B_0 CSA1#_0 21
RV66 CV157 J25 K13
100_0402_1% 1U_0402_6.3V6K RV55 1 PX@ 2 MEM_CALRP0 K25 NC#J25 CSA1B_1
PX@ PX@ 120_0402_1% MEM_CALRP0 K20 CKEA0
2 CKEA0 CKEA0 21
J17 CKEA1
CKEA1 21
2

CKEA1
G25 WEA#0
WEA0B WEA#0 21
DRAMRST L10 H10 WEA#1
DRAM_RST WEA1B WEA#1 21
@Test_Point_16MIL TV8 1 CLKTESTA K8
@Test_Point_16MIL TV9 1 CLKTESTB L7 CLKTESTA
CLKTESTB

A DRAMRST RV56 1 PX@ 2 RV57 1 2 PX@ A

DRAM_RST 21
10_0402_5% 51.1_0402_1%
1

RV58 1
4.99K_0402_1% CV147
PX@ 120P_0402_50V8-J Title
PX@ Security Classification LC Future Center Secret Data
2

2
Issued Date 2017/03/14 Deciphered Date 2017/03/14 ATI_EXO-PRO_MEM IF
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S145AST
Date: Thursday, October 25, 2018 Sheet 20 of 50
5 4 3 2 1
 5 4 3 2 1

DQA0_[0..31] DQA1_[31..0] +1.35VGS

20 DQA0_[0..31] 20 DQA1_[31..0]

0) 1R0LUURU 0) 0LUURU
MAA0_[0..8] RV1346 1 PX@ 2 60.4_0201_1% CLKA0
20 MAA0_[0..8] +1.35VGS
RV1347 1 PX@ 2 60.4_0201_1% CLKA#0
MAA1_[8..0] RV1349 1 PX@ 2 60.4_0201_1% CLKA1
20 MAA1_[8..0]
RV1348 1 PX@ 2 60.4_0201_1% CLKA#1

1
1
UV5 UV6 RV1025 CV528
+1.35VGS 2.37K_0402_1% 1U_0402_6.3V6K
MF=0 MF=1 MF=1 MF=0 MF=0 MF=1 MF=1 MF=0 @ @
2

2
A4 DQA0_1 A4 DQA1_11
DQ24 DQ0 DQ24 DQ0

1
EDCA0_0 C2 A2 DQA0_2 EDCA1_1 C2 A2 DQA1_15 VREFD2_A1
1 20 EDCA0_0 EDC0 EDC3 DQ25 DQ1 20 EDCA1_1 EDC0 EDC3 DQ25 DQ1
RV1018 CV522 EDCA0_1 C13 B4 DQA0_7 EDCA1_0 C13 B4 DQA1_10
20 EDCA0_1 EDC1 EDC2 DQ26 DQ2 20 EDCA1_0 EDC1 EDC2 DQ26 DQ2

1
2.37K_0402_1% 1U_0402_6.3V6K EDCA0_2 R13 B2 DQA0_5 EDCA1_2 R13 B2 DQA1_14
20 EDCA0_2 EDC2 EDC1 DQ27 DQ3 20 EDCA1_2 EDC2 EDC1 DQ27 DQ3 1
@ @ EDCA0_3 R2 E4 DQA0_6 EDCA1_3 R2 E4 DQA1_9 RV1026 CV527
2
2 20 EDCA0_3 EDC3 EDC0 DQ28 DQ4 E2 DQA0_4 Byte 0 20 EDCA1_3 EDC3 EDC0 DQ28 DQ4 E2 DQA1_13 Byte 1 5.49K_0402_1% 1U_0402_6.3V6K
DQ29 DQ5 F4 DQA0_3 DQ29 DQ5 F4 DQA1_8 @ @
D DQ30 DQ6 DQ30 DQ6 D
VREFD1_A0 DDBIA0_0 D2 F2 DQA0_0 DDBIA1_1 D2 F2 DQA1_12 2
20 DDBIA0_0 20 DDBIA1_1

2
DDBIA0_1 D13 DBI0# DBI3# DQ31 DQ7 A11 DQA0_8 DDBIA1_0 D13 DBI0# DBI3# DQ31 DQ7 A11 DQA1_1
20 DDBIA0_1 DBI1# DBI2# DQ16 DQ8 20 DDBIA1_0 DBI1# DBI2# DQ16 DQ8
1

DDBIA0_2 P13 A13 DQA0_9 DDBIA1_2 P13 A13 DQA1_0

1 20 DDBIA0_2 DBI2# DBI1# DQ17 DQ9 20 DDBIA1_2 DBI2# DBI1# DQ17 DQ9
RV1019 CV361 DDBIA0_3 P2 B11 DQA0_10 DDBIA1_3 P2 B11 DQA1_2
20 DDBIA0_3 DBI3# DBI0# DQ18 DQ10 B13 DQA0_11 20 DDBIA1_3 DBI3# DBI0# DQ18 DQ10 B13 DQA1_3
5.49K_0402_1% 1U_0402_6.3V6K
@ @ CLKA0 J12 DQ19 DQ11 E11 DQA0_14 CLKA1 J12 DQ19 DQ11 E11 DQA1_4
2 20 CLKA0
CLKA#0 J11 CK DQ20 DQ12 E13 DQA0_12 Byte 1 20 CLKA1
CLKA#1 J11 CK DQ20 DQ12 E13 DQA1_7 Byte 0
20 CLKA#0 20 CLKA#1
2

CKEA0 J3 CK# DQ21 DQ13 F11 DQA0_15 CKEA1 J3 CK# DQ21 DQ13 F11 DQA1_5
20 CKEA0 CKE# DQ22 DQ14 F13 DQA0_13 20 CKEA1 CKE# DQ22 DQ14 F13 DQA1_6
DQ23 DQ15 U11 DQA0_22 DQ23 DQ15 U11 DQA1_22 +1.35VGS
MAA0_2 H11 DQ8 DQ16 U13 DQA0_20 MAA1_4 H11 DQ8 DQ16 U13 DQA1_20
MAA0_5 K10 BA0/A2 BA2/A4 DQ9 DQ17 T11 DQA0_23 MAA1_3 K10 BA0/A2 BA2/A4 DQ9 DQ17 T11 DQA1_23
MAA0_4 K11 BA1/A5 BA3/A3 DQ10 DQ18 T13 DQA0_21 MAA1_2 K11 BA1/A5 BA3/A3 DQ10 DQ18 T13 DQA1_21
BA2/A4 BA0/A2 DQ11 DQ19 BA2/A4 BA0/A2 DQ11 DQ19

1
MAA0_3 H10 N11 DQA0_19 MAA1_5 H10 N11 DQA1_18
BA3/A3 BA1/A5 DQ12 DQ20 N13 DQA0_18 Byte 2 BA3/A3 BA1/A5 DQ12 DQ20 N13 DQA1_19 Byte 2 RV1028
1
CV530
+1.35VGS DQ13 DQ21 M11 DQA0_16 DQ13 DQ21 M11 DQA1_17 2.37K_0402_1% 1U_0402_6.3V6K
MAA0_7 K4 DQ14 DQ22 M13 DQA0_17 MAA1_0 K4 DQ14 DQ22 M13 DQA1_16 @ @
MAA0_1 H5 A8/A7 A10/A0 DQ15 DQ23 U4 DQA0_27 MAA1_6 H5 A8/A7 A10/A0 DQ15 DQ23 U4 DQA1_27 2

2
MAA0_0 H4 A9/A1 A11/A6 DQ0 DQ24 U2 DQA0_28 MAA1_7 H4 A9/A1 A11/A6 DQ0 DQ24 U2 DQA1_28
A10/A0 A8/A7 DQ1 DQ25 A10/A0 A8/A7 DQ1 DQ25
1

MAA0_6 K5 T4 DQA0_26 MAA1_1 K5 T4 DQA1_26 VREFD1_A1

1 A11/A6 A9/A1 DQ2 DQ26 A11/A6 A9/A1 DQ2 DQ26
RV1020 CV524 MAA0_8 J5 T2 DQA0_29 MAA1_8 J5 T2 DQA1_29
A12/RFU/NC DQ3 DQ27 A12/RFU/NC DQ3 DQ27

1
2.37K_0402_1% 1U_0402_6.3V6K N4 DQA0_25 N4 DQA1_25
@ @ A5 DQ4 DQ28 N2 DQA0_30 Byte 3 A5 DQ4 DQ28 N2 DQA1_30 Byte 3 RV1027
1
CV529
2 U5 VPP/NC1 DQ5 DQ29 M4 DQA0_24 U5 VPP/NC1 DQ5 DQ29 M4 DQA1_24 5.49K_0402_1% 1U_0402_6.3V6K
2

VPP/NC2 DQ6 DQ30 M2 DQA0_31 VPP/NC2 DQ6 DQ30 M2 DQA1_31 @ @

VREFD2_A0 DQ7 DQ31 DQ7 DQ31 2

2
J1 J1
MF +1.35VGS MF
1

1 J10 J10
RV1021 CV523 RV1360 1 PX@ 2 ZQ_UV3 J13 SEN B1 RV1363 1 PX@ 2 ZQ_UV4 J13 SEN B1
ZQ VDDQ1 +1.35VGS ZQ VDDQ1 +1.35VGS
5.49K_0402_1% 1U_0402_6.3V6K 120_0402_1% D1 120_0402_1% D1
@ @ VDDQ2 F1 VDDQ2 F1
2 ADBIA0 J4 VDDQ3 M1 ADBIA1 J4 VDDQ3 M1
20 ADBIA0 20 ADBIA1
2

RASA#0 G3 ABI# VDDQ4 P1 CASA#1 G3 ABI# VDDQ4 P1

20 RASA#0 CSA0#_0 G12 RAS# CAS# VDDQ5 T1 20 CASA#1 G12 RAS# CAS# VDDQ5 T1
WEA#1
20 CSA0#_0 L3 CS# WE# VDDQ6 G2 20 WEA#1 L3 CS# WE# VDDQ6 G2 +1.35VGS
CASA#0 RASA#1
20 CASA#0 L12 CAS# RAS# VDDQ7 L2 20 RASA#1 CSA1#_0 L12 CAS# RAS# VDDQ7 L2
WEA#0
20 WEA#0 WE# CS# VDDQ8 B3 20 CSA1#_0 WE# CS# VDDQ8 B3
VDDQ9 D3 VDDQ9 D3
VDDQ10 VDDQ10

1
F3 F3 1
WCKA0#_0 D5 VDDQ11 H3 WCKA1#_0 D5 VDDQ11 H3 RV1029 CV532
+1.35VGS 20 WCKA0#_0 WCKA0_0 D4 WCK01# WCK23# VDDQ12 K3 20 WCKA1#_0 WCKA1_0 D4 WCK01# WCK23# VDDQ12 K3 2.37K_0402_1% 1U_0402_6.3V6K
20 WCKA0_0 WCK01 WCK23 VDDQ13 M3 20 WCKA1_0 WCK01 WCK23 VDDQ13 M3 PX@ @
WCKA0#_1 P5 VDDQ14 P3 WCKA1#_1 P5 VDDQ14 P3 2
20 WCKA0#_1 20 WCKA1#_1

2
WCKA0_1 P4 WCK23# WCK01# VDDQ15 T3 WCKA1_1 P4 WCK23# WCK01# VDDQ15 T3
20 WCKA0_1 WCK23 WCK01 VDDQ16 20 WCKA1_1 WCK23 WCK01 VDDQ16
1

E5 E5 VREFC_A1
1 VDDQ17 VDDQ17
RV1023 CV526 N5 N5
VDDQ18 VDDQ18

1
2.37K_0402_1% 1U_0402_6.3V6K VREFD1_A0 A10 E10 VREFD1_A1 A10 E10
C VREFD1 VDDQ19 VREFD1 VDDQ19 1 C
PX@ @ VREFD2_A0 U10 N10 VREFD2_A1 U10 N10 RV1030 CV531
2 VREFC_A0 J14 VREFD2 VDDQ20 B12 VREFC_A1 J14 VREFD2 VDDQ20 B12 5.49K_0402_1% 1U_0402_6.3V6K
2

VREFC VDDQ21 D12 VREFC VDDQ21 D12 PX@ PX@

VREFC_A0 VDDQ22 F12 VDDQ22 F12 2

2
VDDQ23 H12 VDDQ23 H12
VDDQ24 VDDQ24
1

DRAM_RST J2 K12 DRAM_RST J2 K12

1 20 DRAM_RST RESET# VDDQ25 RESET# VDDQ25
RV1022 CV525 M12 M12
5.49K_0402_1% 1U_0402_6.3V6K VDDQ26 P12 VDDQ26 P12
PX@ PX@ VDDQ27 T12 VDDQ27 T12
2 VDDQ28 G13 VDDQ28 G13
2

H1 VDDQ29 L13 H1 VDDQ29 L13

K1 VSS1 VDDQ30 B14 K1 VSS1 VDDQ30 B14
B5 VSS2 VDDQ31 D14 B5 VSS2 VDDQ31 D14 +1.35VGS
VSS3 VDDQ32 VSS3 VDDQ32 UV6 SIDE
G5 F14 G5 F14
L5 VSS4 VDDQ33 M14 L5 VSS4 VDDQ33 M14
T5 VSS5 VDDQ34 P14 T5 VSS5 VDDQ34 P14

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K
VSS6 VDDQ35 VSS6 VDDQ35

PX@

PX@

PX@

PX@

PX@
B10 T14 B10 T14

CD@

CD@

CD@
D10 VSS7 VDDQ36 D10 VSS7 VDDQ36
VSS8 VSS8 1 1 1 1 1 1 1 1 1
+1.35VGS UV5 SIDE G10 G10 CV562
L10 VSS9 A1 L10 VSS9 A1 33P_0402_50V8J
P10 VSS10 VSSQ1 C1 P10 VSS10 VSSQ1 C1 RF_PXNS@
T10 VSS11 VSSQ2 E1 T10 VSS11 VSSQ2 E1 2 2 2 2 2 2 2 2 2

CV561

CV553

CV566

CV555

CV567

CV554

CV629

CV565
0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

VSS12 VSSQ3 VSS12 VSSQ3

PX@

PX@

PX@

PX@

PX@

H14 N1 H14 N1
CD@

CD@

CD@

K14 VSS13 VSSQ4 R1 K14 VSS13 VSSQ4 R1

1 1 1 1 1 1 1 1 1 VSS14 VSSQ5 VSS14 VSSQ5
U1 U1

Vinafix.com
CV505
33P_0402_50V8J VSSQ6 H2 VSSQ6 H2
G1 VSSQ7 K2 G1 VSSQ7 K2
RF_PXNS@

2 2 2 2 2 2 2 2 2 +1.35VGS VDD1 VSSQ8 +1.35VGS VDD1 VSSQ8

L1 A3 L1 A3
CV85

CV86

CV87

CV88
CV552

CV155

CV628

CV635

VDD2 VSSQ9 VDD2 VSSQ9 UV6 SIDE

G4 C3 G4 C3 +1.35VGS
L4 VDD3 VSSQ10 E3 L4 VDD3 VSSQ10 E3
C5 VDD4 VSSQ11 N3 C5 VDD4 VSSQ11 N3
R5 VDD5 VSSQ12 R3 R5 VDD5 VSSQ12 R3
VDD6 VSSQ13 VDD6 VSSQ13

PX@

PX@

PX@

PX@

PX@
C10 U3 C10 U3

CD@
CD@ CD@

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
R10 VDD7 VSSQ14 C4 R10 VDD7 VSSQ14 C4
VDD8 VSSQ15 VDD8 VSSQ15 1 1 1 1 1 1 1 1
D11 R4 D11 R4
G11 VDD9 VSSQ16 F5 G11 VDD9 VSSQ16 F5
+1.35VGS L11 VDD10 VSSQ17 M5 L11 VDD10 VSSQ17 M5
UV5 SIDE VDD11 VSSQ18 VDD11 VSSQ18 2 2 2 2 2 2 2 2
P11 F10 P11 F10

CV573

CV572

CV571

CV575

CV574

CV568

CV569

CV570
G14 VDD12 VSSQ19 M10 G14 VDD12 VSSQ19 M10
L14 VDD13 VSSQ20 C11 L14 VDD13 VSSQ20 C11
VDD14 VSSQ21 VDD14 VSSQ21
PX@

PX@

R11 R11
CD@
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

VSSQ22 VSSQ22
PX@

PX@

PX@

PX@

PX@

A12 A12
CD@

CD@

CD@
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1 1 1 VSSQ23 VSSQ23
1 1 1 1 1 1 1 1 C12 C12
VSSQ24 E12 VSSQ24 E12
VSSQ25 N12 VSSQ25 N12
2 2 2 VSSQ26 VSSQ26 UV6 SIDE
R12 R12
CV78
CV548

CV634

2 2 2 2 2 2 2 2 VSSQ27 U12 VSSQ27 U12

CV79

CV80

CV81

CV82

CV83

CV545

CV546

CV547

B 170-BALL 170-BALL +1.35VGS B

VSSQ28 H13 VSSQ28 H13
SGRAM GDDR5 VSSQ29 K13 SGRAM GDDR5 VSSQ29 K13
VSSQ30 A14 VSSQ30 A14
VSSQ31 VSSQ31

PX@

PX@

PX@
C14 C14

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
VSSQ32 E14 VSSQ32 E14
VSSQ33 VSSQ33 1 1 1
N14 N14
VSSQ34 R14 VSSQ34 R14
VSSQ35 U14 VSSQ35 U14
VSSQ36 VSSQ36 2 2 2

CV577

CV576

CV626
H5GQ1H24AFR-T2L_BGA170 H5GQ1H24AFR-T2L_BGA170
@ @

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2017/02/08 Deciphered Date 2017/02/08 ATI_EXO-PRO_VRAM_A

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S145AST
Date: Thursday, October 25, 2018 Sheet 21 of 51
5 4 3 2 1
 5 4 3 2 1

D D

C C

Vinafix.com
B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2017/02/08 Deciphered Date 2017/02/08 ATI_EXO-PRO_VRAM_B

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S145AST
Date: Thursday, October 25, 2018 Sheet 22 of 51
5 4 3 2 1
 5 4 3 2 1

LCD POWER CIRCUIT B+ to +LEDVDD POWER CMOS Camera

V20B+ +LEDVDD

+3VS +LCDVDD_CON
U7 ϮϴϬŵŝů ϮϴϬŵŝů
R22 1 @ 2 0_0805_5%

C1106 22P_0402_50V8-J

4.7U_0805_25V6-K

0.1U_0201_25V6-K
5 1 R4 1 2 0_0805_5% C25
IN OUT
1 1 1 C23

1U_0402_6.3V6K
1 2 1 F2
GND +3VS

C1
C23 0.1u for G HSW panel blink issue +3VS_CMOS
PCH_ENVDD 4 3 C2 1 2 W=40mils
EN OCB 4.7U_0603_6.3V6K2 RF_NS@ 2 2 R120 1 2 0_0402_5%
D 2 2 D

0.1U_0201_6.3V6-K

.047U_0201_6.3V6K
SY6288C20AAC_SOT23-5 3A_32V_0497003PKRHF 1 1

EMC_NS@
CD@

C24
C3
F2 change to SP040004S00 F3 @ C24 close to JEDP1
PCH_ENVDD 1 2 2 2
6 PCH_ENVDD @

1
R35 0.5A_32V_ERBRD0R50X
100K_0402_5%

+3VS

2
APU output enable Voh min is 1.8V-0.45V=1.35V R8 R9
100K_0402_1% 100K_0402_1%

@ @

1
+3VS EDP_AUX
EDP_AUX#
2

2
R10
PCH_ENBKL R11 1 @ 2 4.7K_0402_5% R13 R15
0_0402_5% @ 100K_0402_1% 100K_0402_1%
ME@
1

@ @ JEDP1
C C

1
R12 1 2 0_0402_5% DISPOFF# R19 1 2 0_0402_5% INVT_PWM 1
35 BKOFF# 6 PCH_EDP_PWM +LEDVDD 1
2
3 2
3

1
R14 1 2 0_0402_5% ENBKL 4
6 PCH_ENBKL ENBKL 35 4
R20 5
can cost down R20 for CZ 5
1

100K_0402_5% APU_EDP_TX0+ C19 1 2 0.1U_0201_6.3V6-K EDP_TX0+ 6

6 APU_EDP_TX0+ APU_EDP_TX0- EDP_TX0- 6
R16 C16 1 2 0.1U_0201_6.3V6-K 7
6 APU_EDP_TX0- 7
100K_0402_5% 8

2
APU_EDP_TX1+ C17 1 2 0.1U_0201_6.3V6-K EDP_TX1+ 9 8
6 APU_EDP_TX1+ APU_EDP_TX1- EDP_TX1- 9
C18 1 2 0.1U_0201_6.3V6-K 10
6 APU_EDP_TX1-
2

11 10
APU_EDP_AUX C20 1 2 0.1U_0201_6.3V6-K EDP_AUX 12 11
6 APU_EDP_AUX APU_EDP_AUX# EDP_AUX# 12
C21 1 2 0.1U_0201_6.3V6-K 13
6 APU_EDP_AUX# 13
14
L12 EMC_NS@ DISPOFF# 15 14
USB20_N2 1 00 2 USB20_N2_R INVT_PWM 16 15
001 2
6 APU_EDP_HPD
17
18
16
17
4 00

Vinafix.com
+LCDVDD_CON 18
USB20_P2 USB20_P2_R
004
3 W=60mils 19
3 20 19
EXC24CH900U_4P 21 20
DMIC_CLK DISPOFF# INVT_PWM 22 21
36 DMIC_CLK 22
36 DMIC_DATA 23
23
33P_0402_50V8J
C11

+3VS_CMOS 24
24
EMC_NS@

C12

C13
1 1 1 25
26 25
27 26
EMC_NS@ EMC_NS@ R182 1 2 0_0402_5% USB20_P2_R 28 27
470P_0201_50V7-K

470P_0201_50V7-K
2 2 2 8 USB20_P2 28
R183 1 2 0_0402_5% USB20_N2_R 29 31
B 8 USB20_N2 29 GND1 B
30 32
30 GND2

@ W=40mils
F12 1 2 HIGHS_FC5AF301-3181H

EMC 0.5A_32V_ERBRD0R50X
+3VS

Touch Screen RTS1 1 @ 2 0_0402_5%

+5VS +5VS_TS

USB20_P6_CONN
RTS2 1 TS@ 2 0_0402_5%
L15 USB20_N6_CONN JTS1
1
USB20_P6 1
00 2 USB20_P6_CONN CTS1 1
00
1 2 1
3

+5VS_TS 0.1u_0201_10V6K 2

USB20_N6 00
4 00 3 USB20_N6_CONN F11 1
@
2
TS@
2 35 EC_TS_ON
RTS3 2 TS@ 1 0_0402_5% TS_RS 3
4
2
3
4 3 4
1

D2 RTS4 1 TS@ 2 0_0402_5% USB20_N6_CONN 5

8 USB20_N6 USB20_P6_CONN 5
EXC24CH900U_4P 0.5A_32V_ERBRD0R50X RTS5 1 TS@ 2 0_0402_5% 6
1

8 USB20_P6 6
EMC_NS@ 7
GND1 8
D753 GND2
AZC199-02S.R7G_SOT23-3 HIGHS_WS83061-S0171-HF
2

&ŽƌD/ AZ5725-01F.R7GR_DFN1006P2X2
EMC_NS@ ME@
2

A EMC_NS@ change symbol to SP021412291 by amy 0620 A

1

&Žƌ^

Security Classification LC Future Center Secret Data Title

Issued Date 2017/03/14 Deciphered Date 2017/03/14 eDP/CMOS/Touch screen

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S145AST
Date: Thursday, October 25, 2018 Sheet 23 of 50
5 4 3 2 1
 5 4 3 2 1

D3
HDMI_DET 1   9 HDMI_DET
L2 EMC@
HDMI_CLK-_C 1
00
001 2
2 HDMI_CLK-_CON
C26
1 2 EMC_NS@
3.3P_0201_50V8-C
HDMIDAT_R 2   8 HDMIDAT_R

HDMI_CLK+_C
00
4 00 3 HDMI_CLK+_CON 1 2 EMC_NS@ +3VS
HDMICLK_R 4  
7 HDMICLK_R
4 3 C27 3.3P_0201_50V8-C +5VS_HDMI 5 6 +5VS_HDMI
 
EXC24CH900U_4P
D 3 
D
L3 EMC@
HDMI_TX0-_C 1
00
00
1 2
2 HDMI_TX0-_CON 1 2 EMC_NS@ 8

5
C28 3.3P_0201_50V8-C

G
HDMI_TX0+_C 00
4 00 3 HDMI_TX0+_CON 1 2 EMC_NS@
Q1B
AZ1045-04F_DFN2510P10E-10-9
4 3 C29 3.3P_0201_50V8-C EMC_NS@
EXC24CH900U_4P APU_DDC_CLK 4 3 HDMICLK_R

S
6 APU_DDC_CLK

D
EMC
L4 EMC@ L2N7002KDW1T1G_SOT363-6

2
00
HDMI_TX1-_C 1 2 HDMI_TX1-_CON 1 2 EMC_NS@

G
1 2
00 C30 3.3P_0201_50V8-C Q1A

4 00
HDMI_TX1+_C
004 3
3 HDMI_TX1+_CON
C31
1 2 EMC_NS@
3.3P_0201_50V8-C APU_DDC_DATA 1 6 HDMIDAT_R

S
6 APU_DDC_DATA

D
EXC24CH900U_4P
L2N7002KDW1T1G_SOT363-6
L5 EMC@
HDMI_TX2-_C HDMI_TX2-_CON
00
1 2 1 2 EMC_NS@
1 2 +5VS_HDMI
00
C32 3.3P_0201_50V8-C

00
+5VS +5VS_HDMI_F +5VS_HDMI

004
HDMI_TX2+_C 4 3 HDMI_TX2+_CON 1 2 EMC_NS@ D5
3

2
C33 3.3P_0201_50V8-C 2 F1
EXC24CH900U_4P D4 1 1 2
3
+3VS RB491D_SOT23-3 1.1A_8V_1206L110THYR
EMC
@ LBAT54SWT1G_SOT323-3 @

1
1 3 Q22

S
1
LP2301ALT1G_SOT23-3 2 1
Follow Zx05 and beema C34

C
Q43 CC1279

G
2

4
3
C LMBT3904WT1G_SOT323-3 B 2 R202 1 2 150K_0402_5% 10U 6.3V M X5R 0402 0.1u_0201_10V6K C
1 2 RP2
12,37 SUSP @

1
2.2K_0404_4P2R_5%
HDMI_CLK-_C

E
R29 1 2 499_0402_1% R257
6 APU_HDMI_HPD
100K_0402_5%

1
2
1
HDMI_CLK+_C HDMI_DET

3
R30 1 2 499_0402_1%
R260

2
HDMI_TX0-_C R31 1 2 499_0402_1% 100K_0402_5%
+5VS_HDMI
HDMI_TX0+_C R32 1 2 499_0402_1% JHDMI1

2
HDMI_TX1-_C R33 1 2 499_0402_1% 18 15 HDMICLK_R
+5V_Power SCL 16 HDMIDAT_R
HDMI_TX1+_C R34 1 2 499_0402_1% SDA
C38 1 2 0.1U_0201_6.3V6-K HDMI_TX0+_C R46 2 @ 1 0_0402_5% HDMI_TX0+_CON 7
HDMI_TX2-_C 6 APU_HDMI_TX0+ HDMI_TX0-_C HDMI_TX0-_CON TMDS_Data0+
R37 1 2 499_0402_1% C37 1 2 0.1U_0201_6.3V6-K R45 2 @ 1 0_0402_5% 9 13

Vinafix.com
6 APU_HDMI_TX0- HDMI_TX1+_C HDMI_TX1+_CON TMDS_Data0- CEC
C40 1 2 0.1U_0201_6.3V6-K R48 2 @ 1 0_0402_5% 4 17
HDMI_TX2+_C 6 APU_HDMI_TX1+ HDMI_TX1-_C HDMI_TX1-_CON TMDS_Data1+ DDC/CEC_Ground HDMI_DET
R38 1 2 499_0402_1% C39 1 2 0.1U_0201_6.3V6-K R47 2 @ 1 0_0402_5% 6 19
6 APU_HDMI_TX1- HDMI_TX2+_C HDMI_TX2+_CON TMDS_Data1- Hot_Plug_Detect
C42 1 2 0.1U_0201_6.3V6-K R50 2 @ 1 0_0402_5% 1
6 APU_HDMI_TX2+ HDMI_TX2-_C HDMI_TX2-_CON TMDS_Data2+
C41 1 2 0.1U_0201_6.3V6-K R49 2 @ 1 0_0402_5% 3
6 APU_HDMI_TX2- TMDS_Data2-
1

Q13 D 8 14
2 5 TMDS_Data0_Shield Utility
+3VS TMDS_Data1_Shield
G 2
TMDS_Data2_Shield
L2N7002KWT1G_SOT323-3 S 20
3

11 GND1 21
R42 1 @ 2 C36 1 2 0.1U_0201_6.3V6-K HDMI_CLK+_C R44 2 @ 1 0_0402_5% HDMI_CLK+_CON 10 TMDS_Clock_Shield GND2 22
6 APU_HDMI_CLK+ HDMI_CLK-_C HDMI_CLK-_CON TMDS_Clock+ GND3
C35 1 2 0.1U_0201_6.3V6-K R43 2 @ 1 0_0402_5% 12 23
6 APU_HDMI_CLK- TMDS_Clock- GND4
100K_0402_5%

B B
ALLTO_C128AF-K1935-L
ME@

D6 D7
HDMI_CLK+_CON 1   9 HDMI_CLK+_CON HDMI_TX1-_CON 1   9 HDMI_TX1-_CON

HDMI_CLK-_CON 2   8 HDMI_CLK-_CON HDMI_TX1+_CON 2   8 HDMI_TX1+_CON

HDMI_TX0+_CON 4   7 HDMI_TX0+_CON HDMI_TX2-_CON 4   7 HDMI_TX2-_CON

HDMI_TX0-_CON 5   6 HDMI_TX0-_CON HDMI_TX2+_CON 5   6 HDMI_TX2+_CON

3  3 

8 8

AZ1045-04F_DFN2510P10E-10-9 AZ1045-04F_DFN2510P10E-10-9
EMC_NS@ EMC_NS@

EMC

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2017/03/14 Deciphered Date 2017/03/14 HDMI_CONN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S145AST
Date: Thursday, October 25, 2018 Sheet 24 of 50
5 4 3 2 1
 A B C D E

+USB_VCCA

LEFT SIDE USB3.0 PORT x2 C8811 1 2 100U_1206_6.3V6M

C8806 1 2 47U_6.3V_M_X5R_0805_H1.25
@
+5VALW +USB_VCCA C1117 1 2 47U_6.3V_M_X5R_0805_H1.25
U2 @
5 1 C125 1 2
IN OUT @ 1U_0402_10V6K
1
C128 2 C127 1 2
1U_0402_10V6K GND @ 1U_0402_10V6K
4 3 USB_OC1#
2 25,35 USB_ON# ENB OCB USB_OC1# 7 JUSB1 ME@
SY6288D20AAC_SOT23-5 1
C2078 USB30_TX_P0 C126 1 20.1U_6.3V_K_X5R_0201 USB30_TX_C_P0 R95 1 @ 2 0_0402_5% USB30_TX_R_P0 9
8 USB30_TX_P0 1 StdA_SSTX+
1000P_0201_50V7-K
EMC_NS@ USB30_TX_N0 C124 1 20.1U_6.3V_K_X5R_0201 USB30_TX_C_N0 R96 1 @ 2 0_0402_5% USB30_TX_R_N0 8 VBUS
Low Active 2A 2 8 USB30_TX_N0 USB20_P4 1 2 0_0402_5% USB20_P4_R 3 StdA_SSTX-
R97 @
8 USB20_P4 7 D+
USB20_N4 R93 1 @ 2 0_0402_5% USB20_N4_R 2 GND_DRAIN 10
8 USB20_N4 USB30_RX_P0 1 2 0_0402_5% USB30_RX_R_P0 6 D- GND_2 11
R94 @
8 USB30_RX_P0 4 StdA_SSRX+ GND_3 12
USB30_RX_N0 R98 1 @ 2 0_0402_5% USB30_RX_R_N0 5 GND_1 GND_4 13
8 USB30_RX_N0 StdA_SSRX- GND_5

00
ALLTO_C19043-10905-L
1 1

00
L13 EMC@
USB30_RX_N0 USB30_RX_R_N0
1
1 2
2
ͳͲȀͳ͸’†ƒ–‡‘
USB30_RX_P0

00
4
4
EXC24CH900U_4P
3
3 USB30_RX_R_P0

+USB_VCCA
USB20_P4_R

USB20_N4_R D12 EMC@

00

AZ5725-01F.R7GR_DFN1006P2X2
L16 EMC@ USB30_RX_R_N0 9 1USB30_RX_R_N0
 
USB30_TX_C_N0 1 2 USB30_TX_R_N0

2
1 2

00
D11 USB30_RX_R_P0 8 2 USB30_RX_R_P0
 
D13

1
USB30_TX_C_P0 4 3 USB30_TX_R_P0 AZC199-02S.R7G_SOT23-3 USB30_TX_R_N0 7 4USB30_TX_R_N0
 
4 3 EMC@
EXC24CH900U_4P USB30_TX_R_P0 6 5 USB30_TX_R_P0
 

2
3

00

EMC_NS@

2
00
L8 EMC@ 8
USB20_P4 4 3 USB20_P4_R
4 3 AZ1045-04F_DFN2510P10E-10-9

00

1
USB20_N4 1 2 USB20_N4_R
1 2
EXC24CH900U_4P
EMC
EMC

Follow S145WHL
+5VALW +USB_VCCD +USB_VCCD
U132
5 1
IN OUT
1
C8808 2
1U_0402_10V6K GND
USB_ON# 4 3 USB_OC3#
2 ENB OCB USB_OC3# 7 C8810 1 2 100U_1206_6.3V6M
SY6288D20AAC_SOT23-5 1
C8809 C8807 1 2 47U_6.3V_M_X5R_0805_H1.25
1000P_0201_50V7-K @
EMC_NS@ C8804 1 2 47U_6.3V_M_X5R_0805_H1.25
Low Active 2A 2 @
C2060 1 2
@ 1U_0402_10V6K
C2059 1 2
@ 1U_0402_10V6K
JUSB3
1
USB20_N3 R942 1 @ 2 0_0402_5% USB20_N3_R 2 VBUS
8 USB20_N3 USB20_P3 USB20_P3_R D-
R3103 1 @ 2 0_0402_5% 3
8 USB20_P3 4 D+ 5
GND GND1 6
GND2 7
GND3 8
GND4
ALLTO_C107G1-10803-L
ME@

ͳͲͳ͹’†ƒ–‡‘
FOR ESD Close to Connector
2 USB20_P3_R 2
+USB_VCCD

USB20_N3_R

AZ5725-01F.R7GR_DFN1006P2X2
3

2
D43
AZC199-02S.R7G_SOT23-3

1
EMC@
D34

00

1
L17 EMC@
USB20_P3 4 3 USB20_P3_R EMC_NS@
4 3

USB20_N3 USB20_N3_R

2
1 2
1 2

2
EXC24CH900U_4P
1

+USB_VCCB
Follow S145WHL, U25 change to SA000074Q00

USB3.0 PORT

ͶͳͲ͵…Šƒ‰‡–‘ͳͲͲͳͲͳ͸

www.teknisi-indonesia.com
+5VALW +USB_VCCB C4103 1 2 100U_1206_6.3V6M
U25
5 1 C8802 @1 2 47U_6.3V_M_X5R_0805_H1.25
IN OUT
1
C8799 2 C8803 @1 2 47U_6.3V_M_X5R_0805_H1.25
1U_0402_10V6K GND
USB_ON# 4 3 USB_OC2# C8800 @1 2 1U_0402_10V6K
25,35 2 USB_ON# ENB OCB USB_OC2# 7
SY6288D20AAC_SOT23-5 C8801 @1 2 1U_0402_10V6K

1 JUSB2
Low Active 2A C8798 ME@
1000P_0201_50V7-K
EMC_NS@ USB30_TX_P1 C43 1 20.1U_6.3V_K_X5R_0201 USB30_TX_C_P1 R24 1 @ 2 0_0402_5% USB30_TX_R_P1 9
2 8 USB30_TX_P1 1 StdA_SSTX+
USB30_TX_N1 C48 1 20.1U_6.3V_K_X5R_0201 USB30_TX_C_N1 R26 1 @ 2 0_0402_5% USB30_TX_R_N1 8 VBUS
8 USB30_TX_N1 USB20_P5_S 1 2 0_0402_5% USB20_P5_R 3 StdA_SSTX-
R23 @
UARTA_P80_EN 7 D+
USB20_N5_S R25 1 @ 2 0_0402_5% USB20_N5_R 2 GND_DRAIN 10
USB30_RX_P1 R60 1 @ 2 0_0402_5% USB30_RX_R_P1 6 D- GND_2 11
8 USB30_RX_P1 4 StdA_SSRX+ GND_3 12
USB30_RX_N1 R64 1 @ 2 0_0402_5% USB30_RX_R_N1 5 GND_1 GND_4 13
8 USB30_RX_N1 StdA_SSRX- GND_5

00
L1 EMC@ ALLTO_C19043-10905-L
USB30_RX_N1 1 2 USB30_RX_R_N1
2

2 Debug@ 1
NODEBUG@

1 2 R537 R538
ͳͲȀͳ͸’†ƒ–‡‘
0_0402_5%

100K_0402_5%

USB30_RX_P1 4 3 USB30_RX_R_P1
4 3
EXC24CH900U_4P
1

00
L6 EMC@
USB30_TX_C_N1 1 2 USB30_TX_R_N1
1 2
3
FOR ESD Close to Connector 3
USB30_TX_C_P1 4 3 USB30_TX_R_P1
4 3 USB20_P5_R +USB_VCCB
EXC24CH900U_4P
USB20_N5_R
D1 EMC@
USB30_RX_R_N1 9 1USB30_RX_R_N1
AZ5725-01F.R7GR_DFN1006P2X2
3

 

D751 USB30_RX_R_P1 8 2 USB30_RX_R_P1

 
AZC199-02S.R7G_SOT23-3
1

EMC@ USB30_TX_R_N1 7 4USB30_TX_R_N1

 
D752

00
1

USB30_TX_R_P1 6 5 USB30_TX_R_P1
 
L18 EMC@ EMC_NS@
USB20_P5_S 4 3 USB20_P5_R
4 3  3

0
2

USB20_N5_S 1 2 USB20_N5_R 8
2

1 2
1

AZ1045-04F_DFN2510P10E-10-9
EXC24CH900U_4P

‘”‡„—‰ —…–‹‘

2 Debug@ 1 USB_UART_SEL
7 USBDEBUG
R531 0_0402_5%

U129

R533 2 Debug@ 1 0_0402_5% EC_TX_C 1 10 R4692 2 Debug@ 1 0_0402_5% +3VALW

31,35 EC_TX 1D+ VCC USB20_P5 USB20_P5_S
R539 2NODEBUG@
1 0_0402_5%
R536 2 Debug@ 1 0_0402_5% EC_RX_C 2 9 USB_UART_SEL
31,35 EC_RX 1D- S
3 8 USB20_P5_S USB20_N5 R541 2NODEBUG@
1 0_0402_5% USB20_N5_S
8 USB20_P5 2D+ D+
NCY3958Y USB20_N5_S
4 7
8 USB20_N5 2D- D-
5 6
GND1 OE#
11
GND2

NCT3958Y_DFN10_3X3
Debug@


‡”‡Ž†‡„—‰
Set input Set input
+3VALW
Set output Low ENABLE
1

R547
̴ͺͲ̴ ͺͲ Debug@ 10K_0402_5%
2

Set input DISABLE USB_UART_SEL

4 4

Set output Low ENABLE

1

D
UARTA_P80_EN 2
G L2N7002KWT1G_SOT323-3
Q56
S Debug@
3

͓  
H X DISABLE

L L D(+/-) to 1D(+/-)

L H D(+/-) to 2D(+/-)

Security Classification LC Future Center Secret Data Title

Issued Date 2017/03/14 Deciphered Date 2017/03/14 USB3.0 PORT (LEFT)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S145AST
Date: Thursday, October 25, 2018 Sheet 25 of 50
A B C D E
 5 4 3 2 1

+1.8VS
ͳ RTPM17 2 TPM@ 1 0_0402_5%
+1.8V_TPM +3VALW +1.8V_TPM

+1.8VALW

RTPM18 2 @ 1 0_0402_5%

2
RTPM14 RTPM38
TPM@ @ RTPM38 staff for NationZ
0_0603_5% 0_0603_5%
D +1.8VS +1.8V_TPM +1.8V_TPM D

1
1

1
RTPM34 RTPM35
TPM@ @
10K_0402_5% 10K_0402_5%
D755 2 1 1 1 1 2

2
CTPM1 CTPM2 CTPM3 CTPM4 CTPM5 CTPM6
2 1 TPM_SPI_PIRQ# @ TPM@ 0.1U_0201_6.3V6-K 0.1U_0201_6.3V6-K TPM@ TPM@
7 PCH_SPI_PIRQ#
10U_0603_6.3V6M 4.7U_0402_6.3V6M TPM@ TPM@ 0.1U_0402_10V7K 10U_0603_6.3V6M
@ 1 2 2 2 2 1
RB751V-40_SOD323-2
SCS00008K00

RTPM36 2 TPM@1 0_0402_5% UTPM2

22

1
TPM@

NiC2

NiC1
VPS
TPM_SPI_PIRQ# 18
SPI_PIRQ 3 TPM_GP2 RTPM27 2 TPM@ 1 10K_0402_5%
NiC6 +1.8V_TPM
4 TPM_PIN4 RTPM24 2 @ 1 0_0402_5%
NiC7 +1.8V_TPM
SPI_SI RTPM20 2 TPM@1 0_0402_5% TPM_SPI_SI 21 5
8 SPI_SI MOSI NiC8
SPI_SO RTPM21 2 TPM@1 0_0402_5% TPM_SPI_SO 24 10
C 8 SPI_SO MISO NiC9 C
11
NiC10 12
NiC11 13
SPI_CS_R# 20 NiC12 14
SPI_CS NiC13 +1.8V_TPM
15
SPI_CLK RTPM22 2 TPM@1 0_0402_5% TPM_SPI_CLK 19 NiC14 16
8 SPI_CLK SPI_CLK NiC15 25
TPM_PLT_RST# 17 NiC16 26
+1.8V_TPM SPI_RST NiC17 27 TPM_PIN27 RTPM25 1 @ 2 10K_0402_5%
6 NiC18 28
GPIO NiC19 31
NiC20
1

7
RTPM23 PP
TPM@
10K_0402_5% 29 TPM_PIN29 PIN29 reserve for TPM MS low power mode
NiC21

1
SCS00008K00 30
2

NiC22

GND1

GND2
D264 @ RTPM30

NiC3

NiC4

NiC5
7,15,29,31,35 PLT_RST# 1

RB751V-40_SOD323-2 Vinafix.com
2 TPM_PLT_RST# @
10K_0402_5%

23

32

33
+5VALW ST33HTPH2E32AHB4_VQFN32_5X5 +1.8V_TPM

1TPM_PIN2
RTPM28
1

B B

1
RTPM37
10K_0402_5% RTPM32
TPM@ @
3

10K_0402_5%
2

0_0402_5%
QTPM1B
D2

2
5 PJT7838_SOT363-6 TPM_PIN29 RTPM29 2 @ 1 0_0402_5% PLT_RST#
G2 TPM@
D754

2
S2
6

2 1
QTPM1A TPM@
D1

2 PJT7838_SOT363-6 @
G1 TPM@ RB751V-40_SOD323-2
SCS00008K00
S1
1

+3VS_APU +1.8V_TPM
2

RTPM33 RTPM26
A 10K_0402_5% TPM@ A
TPM@ 10K_0402_5%
TPM@
1

D750 1 2 CUS357 SPI_CS_R# Title

8 SPI_CS#_TPM Security Classification LC Future Center Secret Data
Issued Date 2017/03/14 Deciphered Date 2017/03/14 TPM
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
RTPM19 2 @ 1 0_0402_5% B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S145AST
Date: Thursday, October 25, 2018 Sheet 26 of 50
5 4 3 2 1
 5 4 3 2 1

+3VALW +3VALW +APU_CORE

D D
1 1 1
CS33 CS34 CS30
0.1U_0201_6.3V6-K 0.1U_0201_6.3V6-K 0.1U_0201_6.3V6-K
2 2 2

CS36

+3VS 1 2 +3VALW
0.1U_0201_6.3V6-K

C C

Vinafix.com

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2017/03/14 Deciphered Date 2017/03/14 DP to CRT Convert(IT6515FN)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S145AST
Date: Thursday, October 25, 2018 Sheet 27 of 50
5 4 3 2 1
 5 4 3 2 1

D D

C C

Vinafix.com
B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2017/03/14 Deciphered Date 2017/03/14 LAN_RTL8111GUL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S145AST
Date: Thursday, October 25, 2018 Sheet 28 of 50
5 4 3 2 1
 5 4 3 2 1

+3VS EĞĞĚƐŚŽƌƚ +3VS_SSD1

J8 @ Min 3A
1 2
1 2

10U_0402_6.3V6-M

4.7U_0402_6.3V6M

C7
JUMP_43X79

C2037
1 1 1 1 1

0.1U_6.3V_K_X5R_0201
10U 6.3V M X5R 0402
C2093

C2094

C2095

10U_0603_6.3V6M
@ +3VS_SSD1
2 2 2 2 2
CD@ CD@
D D
JSSD1

1 2
3 GND_1 3.3V_1 4
5 GND_2 3.3V_2 6
7 PERN3 N/C_2 8
9 PERP3 N/C_3 10
11 GND_3 DAS/DSS# 12
13 PETN3 3.3V_3 14
15 PETP3 3.3V_4 16
17 GND_4 3.3V_5 18
19 PERN2 3.3V_6 20
21 PERP2 N/C_4 22
23 GND_5 N/C_5 24
25 PETN2 N/C_6 26

1
27 PETP2 N/C_7 28
4 PCIE_CRX_DTX_N1 29 GND_6 N/C_8 30 R72
31 PERN1 N/C_9 32
4 PCIE_CRX_DTX_P1 PERP1 N/C_10 10K_0402_5%
33 34
PCIE_CTX_C_DRX_N1 35 GND_7 N/C_11 36 @
4 PCIE_CTX_C_DRX_N1

2
PCIE_CTX_C_DRX_P1 37 PETN1 N/C_12 38
4 PCIE_CTX_C_DRX_P1 PETP1 DEVSLP
39 40
PCIE_CRX_DTX_N0 41 GND_8 N/C_13 42
4 PCIE_CRX_DTX_N0 PCIE_CRX_DTX_P0 43 PERN0/SATA-B+ N/C_14 44
4 PCIE_CRX_DTX_P0 45 PERP0/SATA-B- N/C_15 46
PCIE_CTX_C_DRX_N0 47 GND_9 N/C_16 48
4 PCIE_CTX_C_DRX_N0 PCIE_CTX_C_DRX_P0 PETN0/SATA-A- N/C_17 SSD_RST#
49 50
4 PCIE_CTX_C_DRX_P0 PETP0/SATA-A+ PERST# SSD_1_CLKREQ_Q#
51 52 R4679 1 2 0_0402_5%
GND_10 CLKREQ# SSD_1_CLKREQ# 7
53 54 1 @ TP265
8 CLK_PCIE_SSD# REFCLKN PEWAKE#
55 56
8 CLK_PCIE_SSD REFCLKP N/C_18
57 58
GND_11 N/C_19
59 NC NC 60
61 NC NC 62
63 NC NC 64
65 NC NC 66 @
67 68 SUSCLK_SSD1 R1 1 2 0_0402_5%
SSD_DET1 69 N/C_1 SUSCLK 70 SUSCLK 7,11,31
C C
71 PEDET 3.3V_7 72
GND_12 3.3V_8 74 +3VS_SSD1
73
75 GND_13 3.3V_9
GND_14
77 76
PEG1 PEG2

ARGOS_NASM0-S6701-TS40
ME@

Change Symbol to SP011511122 Bourne 0705

Vinafix.com
+3VS_SSD1

B +3VS_SSD1 B

2
@
R5 1 2 0_0402_5%
RC33
1

10K_0402_5%
R7
@ DV4

1
10K_0402_5%
PLT_RST# 2
7,15,26,31,35 PLT_RST# SSD_RST#
1
2

APU_SSD_RST# 3
SSD_DET1 7 APU_SSD_RST#
R41 1 2 0_0402_5%
7 SSD_SATA_PCIE_DET1#
LBAT54AWT1G_SOT323-3
@
1

1
10K_0402_5% @ ^^ͺdη R6
100K_0402_5%
R40
ϬͲͲ^d
ϭͲͲW/
2

2
@

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2017/03/14 Deciphered Date 2017/03/14 LAN_Transformer

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S145AST
Date: Thursday, October 25, 2018 Sheet 29 of 50
5 4 3 2 1
 5 4 3 2 1

+3VS +3VS

REMOTE+/-_R, REMOTE1+/-, REMOTE2+/-:

Fintek thermal sensor Trace width/space:10/10 mil
placed near DIMM Trace length:<8"

2
+3VS R881 R882
U1 4.7K_0402_5% 4.7K_0402_5% REMOTE1+
Near GPU&VRAM REMOTE2+
Near CPU core
@ @ 1 1

1
D C C D

1
1 10 EC_SMB_CK3 C45 2 Q15 C46 2 Q16
VCC SCL EC_SMB_CK3 6,16,35 B B
3300P_0402_50V7-K MMBT3904WH_SOT323-3 3300P_0402_50V7-K MMBT3904WH_SOT323-3
1 REMOTE1+ 2 9 EC_SMB_DA3 @ 2 E @ 2 E
EC_SMB_DA3 6,16,35

3
DP1 SDA REMOTE1- REMOTE2-
THEM_ALERT# @ @
C47 REMOTE1- 3 8
.1U_0402_10V6-K DN1 ALERT#
@ 2 REMOTE2+ 4 7 THERM_L
DP2 THERM#
REMOTE2- 5 6
DN2 GND

F75303M_MSOP10
@

Near GPU&VRAM
Near CPU

+5VLP +5VLP +3VALW

+5VLP +3VALW

HW thermal sensor

1
2

C254 R106 R107 R101 R103

C 0.1U_0603_25V7-M 21.5K_0402_1% 21.5K_0402_1% PX@ 13.7K_0402_1% 13.7K_0402_1% C
@ @ @
1

2
U18 NTC_V1 NTC_V2
1 8 TMSNS1 R108 1 @ 2 0_0402_5% NTC_V1
VCC TMSNS1 NTC_V1 35

1
2 7 PHYST1 R175 1 @ 2 10K_0402_5% RT2 RT3
GND RHYST1 PX@ 100K_0402_1%_TSM0B104F4251RZ 100K_0402_1%_TSM0B104F4251RZ
3 6 TMSNS2 R176 1 @ 2 0_0402_5% NTC_V2
OT1 TMSNS2 NTC_V2 35

2
4 5 PHYST2 R177 1 @ 2 10K_0402_5%
45 EC_ON_R OT2 RHYST2
G718TM1U_SOT23-8

2
@
R102 R4689 R4691 R4690
PX@
over temperature threshold: 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5%

RSET=3*RTMH @ @

1
92+/-30C
Hysteresis temperature threshold.
RHYST=(RSET*RTML)/(3*RTML-RSET) EC_AGND EC_AGND
56+/-30C

Near MB edge
Vinafix.com for layout optimized, change the EC_AGND to GND
B

+3VALW

JFAN1
1

35 EC_FAN_PWM
1
R109 +5VS 2 1
35 EC_FAN_SPEED 2
13.7K_0402_1% 3
R52 1 2 0_0603_5% +5VS_FAN 4 3
4
2

1 1 5
NTC_V3 C50 6 GND1
35 NTC_V3 GND2
C49
10U_0805_10V6K 0.1u_0201_10V6K
2 @ 2 HIGHS_WS33040-S0351-HF
1

ME@
RT4
100K_0402_1%_TSM0B104F4251RZ
2
2

A R104 R105 A
0_0402_5% 0_0402_5%
@
1

Security Classification LC Future Center Secret Data Title

EC_AGND Thermal sensor/FAN CONN/TPM
Issued Date 2017/03/14 Deciphered Date 2017/03/14
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S145AST
Date: Thursday, October 25, 2018 Sheet 30 of 50
5 4 3 2 1
 A B C D E

Mini-Express Card(WLAN/WiMAX)
+3VS_WLAN

JWLAN1 ME@
1 1 2 1
3 GND1 3.3VAUX1 4
8 USB20_P1 USB_D+ 3.3VAUX2
5 6 1 T2 @
8 USB20_N1 USB_D- LED1#
7 8
9 GND2 PCM_CLK/I2S_SCK 10
11 SDIO_CLK PCM_SYNC/I2S_WS 12
13 SDIO_CMD PCM_IN/I2S_SD_IN 14
15 SDIO_DATA0 PCM_OUT/I2S_SD_OUT 16 1 T3 @
17 SDIO_DATA1 LED#2 18
19 SDIO_DATA2 GND11 20
21 SDIO_DATA3 UART_WAKE# 22
23 SDIO_WAKE# UART_RXD
SDIO_RESET#

KEY E
25 PIN24~PIN31 NC PIN 24
27 26
29 28
31 30

33 32
35 GND3 UART_TXD 34
4 PCIE_PTX_C_DRX_P1 PETP0 UART_CTS
37 36
4 PCIE_PTX_C_DRX_N1 PETN0 UART_RTS EC_TX_RSVD
39 38 R62 1 @ 2 0_0402_5%
41 GND4 VENDOR_DEFINED1 40 EC_RX_RSVD R63 1 @ 2 0_0402_5%
4 PCIE_PRX_DTX_P1 PERP0 VENDOR_DEFINED2
43 42
4 PCIE_PRX_DTX_N1 PERN0 VENDOR_DEFINED3
45 44 R88 2 1 0_0402_5%
GND5 COEX3 EC_RX 25,35
47 46
8 CLK_PCIE_WLAN REFCLKP0 COEX2
49 48
8 CLK_PCIE_WLAN# REFCLKN0 COEX1 SUSCLK_R
51 50 R55 2 1 0_0402_5%
WLAN_CLKREQ_Q# GND6 SUSCLK SUSCLK 7,11,29
2 53 52 2
CLKREQ0# PERST0# BT_OFF# PLT_RST# 7,15,26,29,35
R4686 1 @ 2 0_0402_5% 55 54 R53 1 2 1K_0402_5%
7,35 PCIE_WAKE# PEWAKE0# W_DISABLE2# WLAN_OFF# PCH_BT_OFF# 7
57 56 R56 2 1 0_0402_5%
GND7 W_DISABLE1# PCH_WLAN_OFF# 7
R57 1 @ 2 0_0402_5%
35 LAN_WAKE#
59 58 APU_SMB_DATA_R R58 1 @ 2 0_0402_5%
RSRVD/PETP1 I2C_DATA APU_SMB_CLK_R R59 APU_SMB_DATA 7,12
61 60 1 @ 2 0_0402_5%
RSRVD/PETN1 I2C_CLK APU_SMB_CLK 7,12
63 62
65 GND8 ALERT# 64 EC_TX_R R89 2 1 0_0402_5%
RSRVD/PERP1 RSRVD EC_TX 25,35
67 66
69 RERVD/PERN1 UIM_SWP/PERST1# 68 +3VS_WLAN
GND9 UIM_POWER_SNK/CLKREQ1#

1
71 70
73 RSRVD/REFCLKP1 UIM_POWER_SRC/GPIO1/PEWAKE1# 72 R186
75 RSRVD/REFCLKN1 3.3VAUX3 74 100K_0402_5%
GND10 3.3VAUX4
77 76

Vinafix.com

2
GND15 GND14

ARGOS_NASE0-S6701-TS40

3 +3VS EĞĞĚƐŚŽƌƚ
@
+3VS_WLAN 3
J2

22UC_6.3VC_MC_X5RC_0603
1 2
1 2
JUMP_43X79

0.1U_0201_6.3V6-K
10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

1 1 1 1

C8797

C6

C8805
@ @ @ @

C53
2 2 2 2
R61 2 1 0_0402_5% WLAN_CLKREQ_Q#
7 WLAN_CLKREQ#

Not support AOAC, delete AOAC power circuit 1015

+3VS

+3VS_WLAN
U131 @
5 1
IN OUT
2
GND
4 4
PWR_WLAN_EN 4 3
35 PWR_WLAN_EN EN OCB

SY6288C20AAC_SOT23-5

Security Classification LC Future Center Secret Data Title

Issued Date 2017/03/14 Deciphered Date 2017/03/14 NGFF WLAN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S145AST
Date: Thursday, October 25, 2018 Sheet 31 of 50
A B C D E
 5 4 3 2 1

D D

C C

Vinafix.com
B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2017/03/14 Deciphered Date 2017/03/14 NA

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S145AST
Date: Thursday, October 25, 2018 Sheet 32 of 50
5 4 3 2 1
 5 4 3 2 1

D D

C C

Vinafix.com
B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2017/03/14 Deciphered Date 2017/03/14 NA

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S145AST
Date: Thursday, October 25, 2018 Sheet 33 of 50
5 4 3 2 1
 A B C D E F G H

1 SATA HDD Conn. 1

+5VS_HDD

C1107 22P_0402_50V8-J

C1108 22P_0402_50V8-J
JHDD1 ME@

C78 10U_0805_10V6K
1 1 1 1 1 1 1

C75 0.1U_0201_6.3V6-K

C76 1U_0603_25V6M

C77 10U_0805_10V6K
C74 10 11
1000P_0201_50V7-K SATA_PTX_DRX_P0 C66 1 20.01U_6.3V_K_X7R_0201 SATA_PTX_C_DRX_P0 9 10 GND1
8 SATA_PTX_DRX_P0 9
EMC_NS@ @ @ SATA_PTX_DRX_N0 C67 1 20.01U_6.3V_K_X7R_0201 SATA_PTX_C_DRX_N0 8 12
2 2 2 2 2 2 2 8 SATA_PTX_DRX_N0 8 GND2

RF_NS@

RF_NS@
7
@ SATA_PRX_DTX_N0 SATA_PRX_C_DTX_N0 7
C68 1 20.01U_6.3V_K_X7R_0201 6
8 SATA_PRX_DTX_N0 SATA_PRX_DTX_P0 C69 1 20.01U_6.3V_K_X7R_0201 SATA_PRX_C_DTX_P0 5 6
8 SATA_PRX_DTX_P0 4 5
EMC 4
3
2 3
1 2

EĞĞĚƐŚŽƌƚ
+5VS +5VS_HDD 1
HIGHS_FC5AF101-2931H

J3 1 2 @
1 2
JUMP_43X79

2 2

Vinafix.com
3 3

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2017/03/14 Deciphered Date 2017/03/14 HDD/ODD CONN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S145AST
Date: Thursday, October 25, 2018 Sheet 34 of 50
A B C D E F G H
 5 4 3 2 1

RE1 1 2 0_0603_5% +3VL

+3VL_EC +3VL_EC_R

ůŽƐĞ RE3 1 @ 2 0_0603_5% +3VALW LE1 1 2 0_0603_5%

1 1
CE3 0.1U_0201_6.3V6-K +3VL_EC CE4 CE5
1 2 VCOREVCC 1000P 25V K X7R 0201
ůůĐĂƉĂĐŝƚŽƌƐĐůŽƐĞƚŽ LE2 1 2 0_0603_5% 2
0.1U_0201_6.3V6-K
EC_AGND 2

1 1 1 1 1 1 EC_AGND
+3VS +3VL_EC_R CE21 CE22 CE23 CE24 CE25
CE11
0.1U_0201_6.3V6-K
0.1U_0201_6.3V6-K 0.1U_0201_6.3V6-K 0.1U_0201_6.3V6-K
D 2 2 2 2
0.1U_0201_6.3V6-K 2 2 @
0.1U_0201_6.3V6-K D
RE6 1 2 0_0402_5%

ŵŝŶŝŵƵŵƚƌĂĐĞǁŝĚƚŚϭϮŵŝů
+3VS

114
121
127
12

11

26
50
92

74
3
UE1 EC_FAN_SPEED RE10 1 2 10K_0402_5%
EC_FAN_PWM RE11 1 @ 2 10K_0402_5%

VBAT

VSTBY(PLL)
VCC

AVCC
VSTBY1
VSTBY2
VSTBY3
VSTBY4
VSTBY5
VCORE
ENBKL RE9 1 @ 2 100K_0402_5%
EC_LID_OUT# RE93 1 @ 2 10K_0402_5%
EC_GFX_PWRGD RE279 1 @ 2 10K_0402_5%

+5VALW
16 WRST# 4 24
+3VL_EC 8 KBRST# 5 KBRST#/GPB6 PWM0/GPA0 25 PWR_LED# 36
8 SERIRQ 6 SERIRQ/GPM6 PWM1/GPA1 28 BATT_CHG_LED# 36 USB_ON# RE15 1 2 10K_0402_5%
8,11 LPC_FRAME# LFRAME#/GPM5 PWM2/GPA2 BATT_LOW_LED# 36
DE1 7 29
1 2 @ 8 LPC_AD3 8 LAD3/GPM3 PWM3/GPA3 30 VGA_AC_DET 16 +3VL_EC
8 LPC_AD2 LAD2/GPM2 PWM PWM4/GPA4 EC_FAN_PWM
9 31
8 LPC_AD1 10 LAD1/GPM1 PWM5/GPA5 32 EC_FAN_PWM 30
SUSP# RE18 1 @ 2 100K_0402_5%
LRB751V-40T1G_SOD323-2 8 LPC_AD0 CLK_PCI_EC 13 LAD0/GPM0 PWM6/SSCK/GPA6 34 EC_APU_ALWEN BEEP# 36 LAN_WAKE#
LPC RE5 1 2 10K_0402_5%
8,11 CLK_PCI_EC LPCCLK/GPM4 PWM7/RIG1#/GPA7 EC_APU_ALWEN 46 EC_ON
RE8 1 2 100K_0402_5% WRST# 14 120 RE29 1 @ 2 0_0402_5% RE58 1 @ 2 100K_0402_5%
15 WRST# TMRI0/GPC4 124 HVB_EN 7,11
SUSP#
EC_RX 16 ECSMI#/GPD4 TMRI1/GPC6 SUSP# 37,45,46
1 25,31 EC_RX PWUREQ#/BBO/SMCLK2ALT/GPC7
EC_TX 17 66
CE12 25,31 EC_TX APU_LPC_RST# 22 LPCPD#/GPE6 ADC0/GPI0 67 NTC_V1 30
1U_0402_6.3V6K 8 APU_LPC_RST# LPCRST#/GPD2 ADC1/GPI1 NTC_V2 30
23 68
2 8 EC_SCI# 126 ECSCI#/GPD3 ADC2/GPI2 69 BATT_TEMP 43,44 +3VL
7 GATEA20 GA20/GPB5 ADC ADC3/GPI3 ENBKL 23
70 RE276 1 @ 2 0_0402_5%
IT8586E/AX ADC4/GPI4
ADC5/DCD1#/GPI5
71
72
ADP_I 44
RE275 1 2 0_0402_5%
IDCHG 44
LID_SW# RE38 1 2 100K_0402_5%
ADC6/DSR1#/GPI6 PSYS 44
KSI0 58
KSI0/STB#
LQFP-128L ADC7/CTS1#/GPI7
73 NTC_V3
NTC_V3 30 Add NTC_V3 for thermistor
KSI[0..7] KSI1 59 78 EC_APU_ALWEN RE278 1 2 100K_0402_5%
36 KSI[0..7] 60 KSI1/AFD# DAC2/TACH0B/GPJ2 79 MAINPWON1_EC VR_APU_PWRGD 49 2_5VEN
KSI2 RE26 1 @ 2 1K_0402_5% RE277 1 @ 2 100K_0402_5%
KSO[0..17] 61 KSI2/INIT# DAC3/TACH1B/GPJ3 80 H_PROCHOT#_EC MAINPWON 45
KSI3 DAC SUSP# RE19 1 2 100K_0402_5%
36 KSO[0..17] KSI3/SLIN# DAC4/DCD0#/GPJ4
KSI4 62 81 SYSON RE21 1 2 100K_0402_5%
63 KSI4 DAC5/RIG0#/GPJ5 EC_RTCRST#_ON 9
KSI5 BKOFF# RE40 1 2 10K_0402_5%
KSI6 64 KSI5 85 RE57 1 2 0_0402_5% PWR_WLAN_EN RE293 1 @ 2 10K_0402_5%
C
+3VL_EC +3VALW KSI6 PS2CLK0/TMB0/CEC/GPF0 EC_ON 45,46 EC_ON set Push Pull EC_ON
C
KSI7 65 86 RE285 1 2 100K_0402_5%
36 KSI7 PS2DAT0/TMB1/GPF1 87 PBTN_OUT# 7
KSO0 RE91 1 2 0_0402_5%
KSO1 37 KSO0/PD0 GPF2 88
KSO1/PD1 Int. K/B PS2 GPF3 APUALW_PWRGD 46
KSO2 38 89 1 TE2 @
KSO2/PD2 Matrix PS2CLK2/GPF4
1

KSO3 39 90 EC_LID_OUT# RE90 1 2 0_0402_5%

KSO3/PD3 PS2DAT2/GPF5 EC_LID_OUT# 36 GPU_VR_HOT# 16,48
RE274 RE273 KSO4 40
0_0402_5% 0_0402_5% KSO5 41 KSO4/PD4 96 GPU_EC_HOT#
KSO5/PD5 EXTERNAL SERIAL FLASH GPH3/ID3 CAPS_LED# 36

1
@ KSO6 42 97 QE6 D 1
43 KSO6/PD6 GPH4/ID4 98 1 @ EC_VR_ON 49 2
KSO7 ACOFF TC88 CE26
2

KSO8 44 KSO7/PD7 GPH5/ID5 99 G 47P_0201_25V8-J

45 KSO8/ACK# GPH6/ID6 EC_SYS_PWRGD 7
KSO9 @
KSO10 46 KSO9/BUSY 101 2N7002KW_SOT323-3 S 2
Need EC modify GPH6 to OD output

3
KSO11 51 KSO10/PE NC1 102
KSO11/ERR# NC2 @
2
1

KSO12 52 SPI Flash ROM 103

RPE5 KSO13 53 KSO12/SLCT NC3 105
KSO14 54 KSO13 NC4
2.2K_0404_4P2R_5% KSO14
KSO15 55 GPG0 def mode GPO H
KSO15
KSO16 56 108 ACIN# GPG1 def mode GPO L internal Pull down H_PROCHOT#
3
4

EC_SMB_CK2 KSO17 57 KSO16/SMOSI/GPC3 AC_IN# 109 LID_SW# RE34 1 2 0_0402_5%

UART LID_SW# 36 H_PROCHOT# 6,46

Vinafix.com
EC_SMB_DA2 KSO17/SMISO/GPC5 LID_SW# 44,49 VR_HOT#

1
ON/OFF 110 82 QE1 D 1
EC_ON 36 ON/OFF EC_ON_L PWRSW# EGAD/GPE1 EC_MUTE# 36 2_5VEN H_PROCHOT#_EC
RE59 1 @ 2 0_0402_5% 111 SM Bus 83 RE71 1 2 0_0402_5% 2 CE14
EC_SMB_CK1 115 XLP_OUT EGCS#/GPE2 84 G 47P_0402_50V8J
43,44 EC_SMB_CK1 EC_SMB_DA1 116 SMCLK1/GPC1 EGCLK/GPE3
Nano G not support adapt ID( GPI7) 10/20 @
43,44 EC_SMB_DA1 117 SMDAT1/GPC2 77 2
GPIO L2N7002KWT1G_SOT323-3 S
Add SMBUS for POWER 46 EC_SMB_CK2 PM_SLP_S5# 7

3
118 SMCLK2/PECI/GPF6 GPJ1 100 GPG2
46 EC_SMB_DA2 SMDAT2/PECIRQT#/GPF7 SSCE0#/GPG2 @
core IC 10/20 6,16,30 EC_SMB_CK3
EC_SMB_CK3
EC_SMB_DA3
94
95 CRX1/SIN1/SMCLK3/GPH1/ID1 SSCE1#/GPG0
106
104
EC_GFX_PWRGD
1 TE1 @
PD reserve Junjun0824
+3VL_EC 6,16,30 EC_SMB_DA3 CTX1/SOUT1/GPH2/SMDAT3/ID2 DSR0#/GPG6 107 SYSON
+3VL DTR1#/SBUSY/GPG1/ID7 119 BKOFF#
CRX0/GPC0 123 BKOFF# 23 1 0_0402_5% PWR_WLAN_EN
RE294 2 @ RE89 1 2 0_0402_5%
CTX0/TMA0/GPB2 PWR_WLAN_EN 31
RE27 1 2 0_0402_5% 112 18 PM_SLP_S3# 7
LAN_WAKE# 125 VSTBY0 RI1#/GPD0 21
31 LAN_WAKE# GPE4 RI2#/GPD1 PIN 21, NANO is 4 pin FAN, so delete EC_FAN_ANTI Need EC modify GPJ4 to OD output
WAKE UP 76 NOVO# 36
TACH2/GPJ0
2
1

48 EC_TS_ON
RPE2 Change PCH_CMOSP form PIN117 to pin35 TACH1A/TMA1/GPD7 47 EC_FAN_SPEED EC_TS_ON
EC_FAN_SPEED
23
30
USB_ON# 33 TACH0A/GPD6 19 RE92 1 2 0_0402_5%
2.2K_0404_4P2R_5% 25 USB_ON# GINT/CTS0#/GPD5 L80HLAT/BAO/GPE0 PCH_PWRBT# 7
35 GPIO 20 @
B 37 PCH_CMOSP RTS1#/GPE5 L80LLAT/GPE7 NUM_LED# 36 B

ˈ CZL and STN have no VDDCR_GFX, so delete VDDFX_PD and EC_GFX_PD

93
7 EC_RSMRST#
3
4

EC_SMB_CK1 CLKRUN#/GPH0/ID0
EC_SMB_DA1
PIN 48 20
Need EC modify GPH0 to OD output
2
7,31 PCIE_WAKE# 128 CK32KE/GPJ7 +3VL
+3VS 7 AC_PRESENT CK32K/GPJ6 Clock

1
RE56
2
1

AVSS

100K_0402_5%
VSS1

VSS2
VSS3
VSS4
VSS5
VSS6

Change GPIO setting, high active APUALW_PWRGD

RPE3 NOVO#
7,15,26,29,31 PLT_RST#
2.2K_0404_4P2R_5%

2
IT8586E-AX_LQFP128_14X14 ACIN# RE88 1 2 0_0402_5%
1

27
49
91
113
122

75

1000P_0402_25V7-K
3
4

EC_SMB_CK3

1
EC_SMB_DA3 D QE2 2 1

˄EC_SMB2˅ pull high 1K

2
2

CC1278
CC1277
ACIN 44 0.01U_0201_25V6-K
G CE29 EMC_NS@
EC_AGND EMC_NS@
AMD request SIC/SID 0.1U_0201_6.3V6-K

1
L2N7002KWT1G_SOT323-3 S 1 2
@

3
@

@
DE2 1 2 RB751V-40_SOD323-2

SYSON RE86 1 2 0_0402_5% Factory EC flash for STN

1_2VEN 46
Mirror Core strap CLK_PCI_EC RE2 1 2 10_0402_5% EMC_NS@ CE2 1 2 10P_0402_50V8J
+3VL_EC EC_SMB_CK1 PAD 1 @ VR_APU_PWRGD EMC_NS@ +3VS
EC_SMB_DA1 1 IT1 APU_LPC_RST# 1 2 220P_0402_50V7K
@ PAD @ EMC_NS@ CE1
IT2
DE3 1 2 RB751V-40_SOD323-2 PAD 1 @ 1
1 IT3
PAD @ CE20 SYSON EMC_NS@ CE13 1 2 0.1U_0201_6.3V6-K
IT4
GPG2 RE44 2 @ 1 10K_0402_5% PAD 1 @ 1U_0402_6.3V6K
2_5VEN IT5 BATT_TEMP
RE87 1 @ 2 1K_0402_5% EMC_NS@ CE16 1 2 100P_0402_50V8J 1
2_5VEN 46 2
RE46 2 STN@1 10K_0402_5%
ACIN# EMC_NS@ CE17 1 2 100P_0402_50V8J CE19
A
ǁŚĞŶŵŝƌƌŽƌ͕'W'ϮƉƵůůŚŝŐŚ KSI7 PAD 1 @
IT6 2
0.1U_0201_6.3V6-K A

ǁŚĞŶŶŽŵŝƌƌŽƌ͕'W'ϮƉƵůůůŽǁ
KSI6
WRST#
PAD 1
PAD 1
@
@
IT7
IT8
ĨŽƌsZͺWhͺWtZ'ƵŶĚĞƌƐŚŽŽƚŝƐƐƵĞ ON/OFF EMC_NS@ CE18 1 2 1U_0402_6.3V6K
EMC_NS@
PM_SLP_S3# EMC_NS@ CE27 1 2 0.1U_0201_6.3V6-K

PM_SLP_S5# EMC_NS@ CE28 1 2 0.1U_0201_6.3V6-K

EMC

Security Classification LC Future Center Secret Data Title

Issued Date 2017/03/14 Deciphered Date 2017/03/14 EC ITE8586LQFP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S145AST
Date: Thursday, October 25, 2018 Sheet 35 of 50
5 4 3 2 1
 5 4 3 2 1

ON/OFF switch
PW R_LED#
+3VL +3VALW

K/B Connector

2
JKB1 ME@

1
R82 R83 1
100K_0402_5% 100K_0402_5% R268 1 2 0_0402_5% D46 ON/OFFBTN# 2 1

1
AZ5123-01F.R7GR_DFN1006P2X2 PWR_LED# R285 1 2 200_0402_1% 3 2
KSI[0..7] EMC_NS@ R279 1 15@ 2 200_0402_1% NUM_LED#_R 4 3
KSI[0..7] 35 35 NUM_LED#

1
D15 KSO17 R281 1 15@ 2 0_0402_5% KSO17_R 5 4
@ KSO[0..17] KSO16_R 5
NOVO# 2 KSO16 R280 1 15@ 2 0_0402_5% 6
35 NOVO# NOVO_BTN# KSO[0..17] 35 6

2
1 KSI1 7
ON/OFF R85 1 @ 2 0_0402_5% 3 KSI7 8 7

2
KSI6 9 8
LBAT54CWT1G_SOT323-3 KSO9 10 9
KSI4 11 10
D @ 11 D
KSI5 12
KSO0 13 12
KSI2 14 13
KSI3 15 14
+3VALW +3VL KSO5 16 15
KSO1 17 16
KSI0 18 17

2
EMC_NS@ KSO2 19 18
R111 R114 PWR_CAPS_LED C133 1 2 100P_0201_25V8J KSO4 20 19
100K_0402_5% 100K_0402_5% CAPS_LED# NUM_LED#_R ON/OFFBTN# KSO7 21 20
@ KSO8 22 21
KSO6 23 22

1
KSO3 24 23

1
ON/OFFBTN# R119 1 2 0_0402_5% ON/OFF KSO12 25 24
ON/OFF 35 25
D23 D22 D30 KSO13 26

1
AZ5123-01F.R7GR_DFN1006P2X2 AZ5123-01F.R7GR_DFN1006P2X2 AZ5123-01F.R7GR_DFN1006P2X2 KSO14 27 26
J5 1 2 @ EMC_NS@ EMC_15_NS@ EMC@ KSO11 28 27
KSO10 29 28
SHORT PADS KSO15 30 29
CAPS_LED# CAPS_LED#_R 30

2
EMC_NS@ R275 1 2 200_0402_1% 31 34
CAPS_LED# 35 CAPS_LED# PWR_CAPS_LED 31 GND2
J6 1 2 @ C117 1 2 100P_0201_25V8J +3VALW R84 1 2 0_0402_5% 32 33

2
32 GND1
SHORT PADS NUM_LED#_R C118 1 2 100P_0201_25V8J HIGHS_FC8AR321-3160-1H

EMC_15_NS@ For EMC

C +3VS TP_PW R
TP/B Connector LID Connector IO Connector RA3025 1 2 1K_0402_5% CA41 1 2 C
0.1U_0201_6.3V6-K
R141 1 2 0_0402_5% Change from PS2 mode to I2C mode 10/19
0.1U_6.3V_K_X5R_0201

1 DA1
JTP1 35 BEEP# 2
R4677 1 2 0_0402_5% EC_LID_OUT#_R 1 1 PC_BEEP1 RA211 1 2 1K_0402_5% CA40 1 2 PC_BEEP
35 EC_LID_OUT# TP_INT# 1
R4678 1 2 0_0402_5% 2 7 PCH_BEEP
3 0.1U_0201_6.3V6-K
7 PCH_TP_INT#

1
2 3 2
C114

3 1
TP_I2C0_SDA_R RC1657 1 @ 2 0_0402_5% TP_I2C0_SDA 4 LBAT54CWT1G_SOT323-3 RA14
TP_I2C0_SCL_R RC1656 1 @ 2 0_0402_5% TP_I2C0_SCL 5 4 C1105 10K_0402_5% J1
5 U23 @
6 @ 0.01U_0201_6.3V7-K 1
TP_PWR 6 2 +5VS 1
1 2

2
GND 2
100P_0201_25V8J

100P_0201_25V8J
7 RA3026 1 2 0_0402_5% PC_BEEP 3
1 1 1
EMC_NS@

EMC_NS@
GND1 LID_SW# @ 3
8 3 4
GND2 OUTPUT LID_SW# 35 +3VS 4
C1104 +3VL 5
HIGHS_FC5AF061-2931H @ 0.01U_0201_6.3V7-K NOVO_BTN# 6 5

1
2 2 2 2 EC_MUTE# 7 6
C115

C116

ME@ VCC 35 EC_MUTE# 7

D17 8

1
AZ5123-01F.R7GR_DFN1006P2X2 USB20_N0 9 8
+VCC_LID AH9247-W-7_SC59-3 8 USB20_N0 USB20_P0 9
TP_PWR +3VL R267 1 2 0_0402_5% EMC_NS@ 8 USB20_P0 10
11 10
+1.8VS DMIC_CLK 12 11
23 DMIC_CLK DMIC_DATA 12

2
13
23 DMIC_DATA
2
1

14 13

2
RPC20 HDA_BITCLK_AUDIO 15 14
7 HDA_BITCLK_AUDIO HDA_SDOUT_AUDIO 15
2.2K_0404_4P2R_5% 16
7 HDA_SDOUT_AUDIO HDA_SDIN0 16
17
TP_I2C0_SCL 7 HDA_SDIN0 HDA_SYNC_AUDIO 17
For EMC 18
7 HDA_SYNC_AUDIO
3
4
5

TP_I2C0_SDA 19 18
+3VALW 19
20
G2

+1.8VS

2
21 20
TP_I2C0_SDA_R R4687 1 2 0_0402_5% 4 3 TP_I2C0_SDA DT1 22 GND1
7 TP_I2C0_SDA_R S2 D2 GND2
EMC_NS@
HIGHS_FC5AF201-1151H
2

Q158B
ME@
PJT7838_SOT363-6
G1

B
7 TP_I2C0_SCL_R TP_I2C0_SCL_R R4688 1

Reserve level shift as I2C at APU side is 1.8V Level

2 0_0402_5% 1
S1

Q158A
D1

PJT7838_SOT363-6
6

Vinafix.com 10/28
TP_I2C0_SCL

1 AZC199-02S.R7G_SOT23-3

EMC
B

LED PWR_LED# LED1 1 2 R142 1 2 1.5K_0402_5%

35 PWR_LED# +5VALW
1

L-C192WDT-LCFC_WHITE
D31
1

AZ5725-01F.R7GR_DFN1006P2X2
EMC_NS@
2
2

BATT_LOW_LED# LED2 1 2 R143 1 2 470_0402_5%

35 BATT_LOW_LED# +3VALW
1

L-C192JFCT-LCFC_SUPER_AMBER
D32
1

AZ5725-01F.R7GR_DFN1006P2X2
EMC_NS@
2

A A
2

BATT_CHG_LED# LED3 1 2 R144 1 2 1.5K_0402_5%

35 BATT_CHG_LED# +5VALW
1

L-C192WDT-LCFC_WHITE
D33
1

AZ5725-01F.R7GR_DFN1006P2X2
EMC_NS@

Security Classification LC Future Center Secret Data Title

2

Issued Date 2017/03/14 Deciphered Date 2017/03/14 KBD/PWR/IO/LED/TP Conn.

2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S145AST
Date: Thursday, October 25, 2018 Sheet 36 of 50
5 4 3 2 1
 A B C D E

+5VLP +5VALW

1
R156 R157
100K_0402_5% 100K_0402_5%
@
1 1

2
SUSP
12,24 SUSP

1
Q6 D
2
35,45,46 SUSP# G

L2N7002KWT1G_SOT323-3 S

3
+1.8VALW to +1.8VS AONS32314 AONS32314
VDS=30V VGS=20V, ID=32A, VDS=30V VGS=20V, ID=32A,
Rds=8.7mohm @ VGS=10V +0.95VALW to +0.95VS Rds=8.7mohm @ VGS=10V
+1.8VALW Q39 +1.8VS +/- 5% 1.5A
2
+/- 2% AONS32314_DFN8-5
VGS(th)=2.25V Max
Q41
VGS(th)=2.25V Max
2
+0.95VALW +0.95VS
1 +/- 1.5% AONS32314_DFN8-5
2 1 1
1 5 3 C142 1
C141 C140 1U_0402_6.3V6K 2 1 1
10U_0603_6.3V6M 10U_0603_6.3V6M 1 5 3 C147

1
2 2 C146 C145 1U_0402_6.3V6K
4

@ 2 R213 @ 10U_0603_6.3V6M 10U_0603_6.3V6M

1
470_0603_5% @ 2 2

4
2 R188 @
470_0603_5%

2
Q39 change to SB00001NY00 R206
Q41 change to SB00001NY00

2
R211 R194 R214 1 2 1.8VS_GATE
1.8VS_GATE_R 1 2 1 2 1.8VS_GATE 2 1
V20B+ R193 0_0402_5%
0_0402_5% 0_0402_5% 130K_0402_5% 0.95VS_GATE_R 1 2 1 R190 20.95VS_GATE 2 R189 1
V20B+
1

1
1 D Q45 Q46 D 0_0402_5% 470K_0402_5%
R212 2 SUSP 2 0_0402_5% @ @

1
C143 1M_0402_5% G G 1 D Q37 Q40 D
0.01U_0201_25V6-K R187 2 SUSP 2
2 S L2N7002KWT1G_SOT323-3 S
L2N7002KWT1G_SOT323-3 C144 820K_0402_5% G G
2

3
0.01U_0201_25V6-K
@ 2 S L2N7002KWT1G_SOT323-3 S
L2N7002KWT1G_SOT323-3

Vinafix.com

3
@ @ @
3 3

+3VALW to +3VALW_APU +3VALW

Need Short +3VALW_APU 320AST 0.6VS discharge Stuff
140S AST unstaff
&ŽƌŝƐŚĂƌŐĞ
J7 @
1 2 +0.6VS +2.5V +1.8VS
1 2

JUMP_43X79

1
Id=3.2A R159 R935 R939
47_0603_5% 47_0603_5% 47_0603_5%
LP2301ALT1G_SOT23-3 @ @ @
@

2
3 1
S

Q29

1
1 1 D Q8 D Q156 D Q157
2 SUSP 2 SUSP 2 SUSP
G
2

C129 C130 G G G
0.1U_0201_6.3V6-K 0.01U_0201_6.3V7-K
2 @ 2 S L2N7002KWT1G_SOT323-3 2N7002KW_SOT323-3 S REV@ 2N7002KW_SOT323-3 S REV@
@

3
REV@
35 PCH_CMOSP R158 1 @ 2 0_0402_5%
1

4 4
1
R164 C131
100K_0402_5% 0.1U_0201_6.3V6-K
@ 2 @
Security Classification LC Future Center Secret Data Title
2

Issued Date 2017/03/14 Deciphered Date 2017/03/14 DC V TO VS INTERFACE

reserve to cut off APU 3VALW when clear CMOS THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S145AST
Date: Thursday, October 25, 2018 Sheet 37 of 50
A B C D E
 5 4 3 2 1

Hole
PCB Fedical Mark PAD
H2
D D
HOLEA
FD4901 FD4902 FD4903 FD4904 FD4905 FD4906

1
PAD_C10P0D8P0

H3 H4 H5 H6 H7 H8
HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
1

1
PAD_CT7P0B6P0D3P2 PAD_CT7P0B6P0D3P2 PAD_CT7P0B6P0D3P2 PAD_CT7P0B6P0D3P2 PAD_CT7P0B6P0D3P2 PAD_CT7P0B6P0D3P2

H9 H10
HOLEA HOLEA
1

C C

PAD_C7P0D4P0 PAD_C7P0D4P0
H17 H18
HOLEA HOLEA

H11 H12 H13

HOLEA HOLEA HOLEA

1
PAD_O2P5X3P0D2P5X3P0N PAD_O2P5X3P0D2P5X3P0N
1

PAD_C7P0D2P8 PAD_C7P0D2P8 PAD_C7P0D2P8

H19
HOLEA
H14
HOLEA

Vinafix.com
1
1

PAD_C2P5D2P5N

PAD_C7P0D2P4

H15 H16
HOLEA HOLEA
1

PAD_CT7P0B10P0D4P0 PAD_CT7P0B10P0D4P0
B SODIMM Shielding B

SH7
SH6
SH1 SH2 SH5 SHIELDING_SUL-35A2M_9P2X3P3_1P
SHIELDING_SUL-35A2M_9P2X3P3_1P
SHIELDING_SUL-35A2M_9P2X3P3_1P SHIELDING_SUL-35A2M_9P2X3P3_1P SHIELDING_SUL-35A2M_9P2X3P3_1P

1
1
1

1
1
1

1
SH8
SHIELDING_SUL-35A2M_9P2X3P3_1P

1
1

+VGA_CORE +3VS
A
For EMC A

1 1

C168 C169
0.1U_0201_6.3V6-K 0.1U_0201_6.3V6-K
2 @ 2 @

Security Classification LC Future Center Secret Data Title

Issued Date 2017/03/14 Deciphered Date 2017/03/14 Hole

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S145AST
Date: Thursday, October 25, 2018 Sheet 38 of 50
5 4 3 2 1
 5 4 3 2 1

HDMI@
ZZZ1 ZZZ2 UV1 PX@

PCB PN HDMI PN R17M-M1-70 GPU

DA600014L00 RO00000040J SA000086K00
PCB HDMI GPU
D D

UC2 UC2

AMD A6-9225 2.6G/2C/1M/FT4 AMD E2-9000 1.8G/2C/1M/FT4

A6@ E2@
SA000091V00 SA00007WW10

UC2
UC2

AMD A9-9425 3.1G/2C/1M/FT4

A9@ AMD A4-9125 2.3G/2C/1M/FT4
SA000091U00 A4@
SA000091X00 APU type
C C

ZZZ3 S8GX2@ ZZZ5 H8GX2@ ZZZ6 M8GX2@

Samsung Hynix Micron

X7646D12003 X7646D12001 X7646D12002

VRAM X76 BOM

Vinafix.com
UV5 H8G_VR@ UV6 H8G_VR@ RV63 H8G_VR@ RV70 H8G_VR@

H5GC8H24AJR-R0C H5GC8H24AJR-R0C 4.53K_0402_1% 4.99K_0402_1%

SA000081630 SA000081630 SD03445318J SD03449918J

VRAM_Hynix 8GX2
B B

UV5 M8G_VR@ UV6 M8G_VR@ RV63 M8G_VR@

MT51J256M32HF-70:B MT51J256M32HF-70:B 4.75K_0402_1%

SA000081730 SA000081730 SD03447518J
VRAM_Micro 8GX2

RV70
UV5 S8G_VR@ UV6 S8G_VR@ RV63 S8G_VR@ S8G_VR@

K4G80325FB-HC28 K4G80325FB-HC28 3.4K_0402_1% 10K_0402_1%

SA000081C00 SA000081C00 SD03434018J SD03410028J

VRAM_Samsung 8GX2

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2017/03/14 Deciphered Date 2017/03/14 Virtual symbol

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. 140S AST
Date: Thursday, October 25, 2018 Sheet 39 of 50
5 4 3 2 1
 5 4 3 2 1

EC_APU_ALWEN 1 +0.775VALW

V V
PU604 Compare
UC4
APUALW_PWRGD 2 V V QC1/QC2/QC3/QC4
PU603 PU601
A3 ACIN#
V

V
D D

AC A1 +VDDCR_FCH_S5
APU_S5_MUX_CTRL
MODE VIN +0.95VALW +1.8VALW
A5 B5

V V
A2
+3VALW

V
PU301

V
BATT B2
B+
PU401 A5 B5
V V V
BATT 3
MODE ALW_PWRGD EC_RSMRST#

V
B1

V
V +APU_CORE_NB

V V
EC 4 PBTN_OUT#
EC_ON A4

V
+APU_CORE
PM_SLP_S3#
B4 5
PM_SLP_S5# APU

V
VR_GFX_PWRGD

V V
10 EC_SYS_PWRGD

V
+APU_GFX
PLT_RST# 11
B3

V
A5

V
ON/OFF 12 VVVVV
KBRST#
B5 V

V
C C

PXS_PWREN
V SYSON 6 PU501

V
+VSYSMEM
+5VALW +3VGS

V
QV6

V
7
V SUSP#,SUSP

V
SUSP# 6 U13 +1.35VGS

V
U13
V

+3VS QV9
+5VS

Vinafix.com

V
PU10 +1.8VGS
+1.5VS QV2
V

PU501
VGA
+0.675VS

V
Q39 +0.95VGS

V
+1.8VS QV3

V
B B
+VGA_CORE

V
Q41
PU701
+0.95VS

VGA_PWRGD
VDDGFX_PD
8
EC_GFX_ON V +APU_GFX
V

PU901
+APU_GFX

8 VR_GFX_PWRGD

EC_VR_ON
+APU_CORE
V

PU801
+APU_CORE

+APU_CORE_NB
V

A PU801 A
+APU_CORE_NB

9
VR_APU_PWRGD

Security Classification LC Future Center Secret Data Title

Issued Date 2017/03/14 Deciphered Date 2017/03/14 Power sequence Block

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S145AST
Date: Thursday, October 25, 2018 Sheet 40 of 50
5 4 3 2 1
 5 4 3 2 1

D D

C C

Vinafix.com
B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2017/03/14 Deciphered Date 2017/03/14 DP to CRT Convert(IT6515FN)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S145AST
Date: Thursday, October 25, 2018 Sheet 41 of 50
5 4 3 2 1
 5 4 3 2 1

B+
+5VLP/ 100mA
RT
LV5083 +5VALW/8A
Adaptor Converter
EC_ON EN FOR SYSTEM PGOOD
+3VALW/6A

+3VLP/ 100mA
D D

ALW_PWRGD

LCFC +1.2V/6A
LCFC5028
1.2VEN S5 PMIC +0.6VS/1A
SUSP# S3
TI FOR SYS PGOOD

BQ24780SRUYR +5VALW
Battery Charger +0.95VALW/6A
EC_APU_ALWEN EN
PGOOD APUALW_PWRGD
Switch Mode
C
+3VALW +1.8VALW/3A C

EC_APU_ALWEN EN PGOOD APUALW_PWRGD

SMBus +1.8VALW
+0.775VALW/0.5A
EC_APU_ALWEN EN

+3.3VALW

Battery +2.5V/0.5A

Vinafix.com
2.5VEN EN

Li-ion
2S1P
RT
LV5095B +1.35VGA /8A
Converter
B
FOR 1.35VGS B

PXS_PWREN EN PGOOD

RT
RT3662EBGQW
Switch Mode +VGA_CORE/28A
FOR VGA_CORE
PXS_PWREN EN PGOOD VR_VGA_PWRGD

RT APU_CORE/22A
RT3661AB
Switch Mode
APU_SVID VIDs
APU_CORE_NB/18A
EN FOR CPU CORE&NB
EC_VR_ON PGOOD VR_APU_PWRGD
A A

Security Classification LC Future Center Secret Data Title

Issued Date 2017/03/14 Deciphered Date 2017/03/14 Power Diagram

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S145AST
Date: Monday, November 12, 2018 Sheet 42 of 50
5 4 3 2 1
 5 4 3 2 1

PL101
HCB2012KF-121T50_0805
1 2 VIN VBAT
PL103
HCB2012KF-121T50_0805
BATT+
EMC_NS@ 1 2
EMC@
D PL102 D
HCB2012KF-121T50_0805 PL104
JBATT1
1 2 HCB2012KF-121T50_0805
EMC@ 1 1 2
PJ101 1 2 EMC@

1000P_0402_50V7K

0.01U_0402_25V7K
9 2 3 EC_SMCA

PC106

EMC@ PC107
JDCIN1 PF101 JUMP_43X79
GND1 3

1
1 APDIN 1 2 APDIN1 1 2 10 4 EC_SMDA
1 2 1 2 GND2 4 5
GND1 @ 5

EMC@
3 7A_24VDC_429007.WRML 6 AZC199-02S.R7G_SOT23-3

2
GND2 4 6 7 PD103
GND3 5 7 8 EMC_NS@

1000P_0402_50V7K

1000P_0402_50V7K
100P_0402_50V8J

100P_0402_50V8J
GND4 8

2
PC101EMC@

PC102EMC@

PC103EMC@

PC104EMC@
6
GND5

1
7 ME@
GND6
ME@ SUYIN_125022HB008M202ZL

1
100_0402_1%

100_0402_1%
PR106

PR105
HIGHS_PJSS0026-8B01H

2
1
EC_SMB_CK1 35,44

C EC_SMB_DA1 35,44 C

1 2
PR107 +3VALW
100K_0402_1%

BATT_TEMP_IN 1 2
BATT_TEMP 35,44
PR108
10K_0402_1%

VCCRTC +3VL Vinafix.com RTC_VCC PRTC1

B B
PD101
BATT CR2032 3V 220MAH
2 RTC@
1 JRTC1
3 2 1 1
2 1
2
35mm cable
PR104 3
1U_0402_10V6K

2 LBAT54CWT1G_SOT323-3 GND1
4
PC105

1K_0603_1%
GND2
ME@ GC02001YB00 main source
1
@ HIGHS_WS33020-S0351-HF GC02001Z800 2nd source

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2017/03/14 Deciphered Date 2017/03/14 DCIN / RTC
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S145AST
Date: Monday, November 12, 2018 Sheet 43 of 50
5 4 3 2 1
 5 4 3 2 1

D PQ201 D
AONS32314_DFN8-5
PQ202
AON7408L_DFN8-5 PJ201
@ PR201
P2 P3 JUMP_43X79 0.01_1206_1%
1 1
2 2 S1 5 2 1 1 4
5 3 3 S2 D 2 1 V20B+
VIN S3 2 3

1000P_25V_K_X7R_0402

1000P_25V_K_X7R_0402

0.22U_25V_K_X5R_0402

0.22U_25V_K_X5R_0402
G

220P_0402_50V7K

470P_0402_50V7K

220P_0402_50V7K

470P_0402_50V7K
6800P_0402_25V7-K

6800P_0402_25V7-K
0.01U_0402_50V6-K

0.01U_0402_50V6-K
10U_25V_M_X5R_0603

10U_25V_M_X5R_0603
1 1 1 1

1 4

1
PC203

PC204

EMC_NS@ PC231

EMC_NS@ PC232

EMC_UMA@ PC233

EMC_UMA@ PC234

EMC_NS@ PC235

EMC_NS@ PC236

EMC_NS@ PC237

EMC_NS@ PC238

EMC_UMA@ PC239

EMC_UMA@ PC240

EMC_NS@ PC241

EMC_NS@ PC242
470P_0402_50V7K

0.022U_0402_25V7K
1 1

4.7_0603_5%
1

1
PC201

PR202

2
2 2 2 2

PC202
2 2

EMC_NS@

EMC_NS@
2

2
2

5
780s_ACDRV_R
780s_BATDRV 4
1 2
VIN VIN BATT+ PQ203
PC205 AON6324_DFN8-5
0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6
LBAT54CWT1G_SOT323-3

0.01U_0402_25V7K

3
2
1
1

499K_0402_1%
4.02K_0603_1%

4.02K_0603_1%

1
PR206

PR207

PC206

PC207

1
PR203
2

PC208
2

2
PD201
2

2
2
43K_0402_1%
1

PR208
V20B+

1
')UT*)ULL
C C

10U_0805_25V6K

10U_0805_25V6K
0.1U_0402_25V6
EMC_NS@
2

2
PC209

PC211

PC212
BQ24780S_VDD

ACN
ACP
PR209
0.01U_0402_25V7K

1
7.15K_0402_1%

10_1206_5%
2
2

1
PC215

PR210

2
1U_0603_25V6K 2.2U_10V_K_X5R_0603

ACP

ACN

5
PC213 PC214
1

1 2 780s_VCC 28 24 1 2

AON7380_DFN8-5
1

VCC REGN

PQ205
780s_ACDET 6
ACDET 2.2_0603_5% 0.047U_0603_16V7K
25 780s_BS1 2 2 1 4
BTST
PR211 PC216
780s_CMSRC 3 26 780s_HG
CMSRC HIDRV PR213

3
2
1
780s_ACDRV 4 0.01_1206_1%
ACDRV

Vinafix.com
PL201

ΎK<ͺϭϬŬƉƵůůŚŝŐŚнϯs>ŽĨŽƉĞŶĚƌĂŝŶŽƵƚƉƵƚĂƚΎ
27 780s_LX 1 2 1 4
PHASE 2.2UH_PCMB063T-2R2MS_8A_20% BATT+

BQ24780SRUYR_QFN28_4X4

5
PR215 1 2 0_0402_5% 780s_ACOK 5 2 3

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K
ACOK

1
35 ACIN

AON7380_DFN8-5

1
PR217 1 2 0_0402_5% 780s_SDA 11

PQ206

PC221

PC217

PC230

PC210
PR216
35,43 EC_SMB_DA1 SDA
Ύ^Dh^ͺϮ͘ϮŬƉƵůůŚŝŐŚнϯs>ͺŽĨŽƉĞŶĚƌĂŝŶŽƵƚƉƵƚĂƚΎ
23 780s_LG 4.7_0805_5%
LODRV

PU201
EMC_NS@

2
PR218 1 2 0_0402_5% 780s_SCL 12 22 4 1 2
35,43 EC_SMB_CK1

2
SCL GND
PC228
*EC-ADC*

0.1U_0402_25V6

0.1U_0402_25V6
1
PR219 1 2 0_0402_5% 780s_IADP 7 29 PC222 0.1U_0402_25V6
35 ADP_I IADP PAD

1
PC223

PC224
1000P_0603_25V7K
*EC-ADC reserve*

3
2
1
PR220 1 2 0_0402_5% 780s_IDCHG 8 18 780s_BATDRV
35 IDCHG @ EMC_NS@
INGXMK澓

2
IDCHG BATDRV 10_0603_5%
*EC-ADC*

2
780s_PMON
I[XXKTZ#狤狥狧'SG^
PR221 1 2 0_0402_5% 9 PR222
35 PSYS PMON 780s_BATSRC 780s_BATSRC_R
17 1 2
BATSRC
\URZGMK#狤9狣6
B B
20 780s_SRP 1 2 780s_SRP_R

LY]#狪狢狢18+-狢^狣狤A狫 狪C#狢狣
780s_VR_HOT 10 SRP
PROCHOT# PR224
20K_0402_1%
100P_0402_50V8J

100P_0402_50V8J

100P_0402_50V8J

Z[XHUHUUYZ
1

13 10_0603_5%
CMPIN
PR231

I[XXKTZ#狥'IUTZOT[K
BATPRES#
1

TB_STAT#

14
PC225

PC226

PC227

CMPOUT 19 780s_SRN 1 2 780s_SRN_R

780s_ILIM 21 SRN
@
2

ILIM PR225
10_0603_5%
16

15
2

0_0402_5%
PR226

35,49 VR_HOT# PR232 1 2 0_0402_5%

780s_TB#

ΎsZͺ,KdͺϭŬƉƵůůŚŝŐŚнϭ͘ϴs^ŽĨŽƉĞŶĚƌĂŝŶŽƵƚƉƵƚĂƚWhΎ
1

1 2 780s_ILIM_R 1 2
+3VALW BATT_TEMP 35,43
PR227 PR228
143K_0402_1% 32.4K_0402_1%

ΎŚĂƌŐĞĐƵƌƌĞŶƚůŝŵŝƚϳ͕ŝƐĐŚĂƌŐĞĐƵƌƌĞŶƚůŝŵŝƚϭϬĚƵƌŝŶŐƚƵƌďŽΎ
100K_0402_1%
0.1U_0402_25V6

1
1

PC229

PR230
2

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 CHARGER

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S145AST
Date: Monday, November 12, 2018 Sheet 44 of 50

5 4 3 2 1
 5 4 3 2 1

D D

PJ3501 @ +5VLP
2 1 +3VALW_VIN
V20B+ 2 1

10U_0805_25V6K

10U_0805_25V6K
EMC_NS@
JUMP_43X79

PC3534

PC3536
0.1U_0402_25V6
1

1
PC3535

25
PU3501 0.1U_0603_25V7K

2
PR3511 PC3541

VDDSW
3 +3VALW_BS 1 2 1 2
11 BOOT1 10_0603_5%
VIN1 PL3501
PJ3502 @
0_0402_5% 0_0402_5% 1 +3VALW_LX 1 2 +3VALW_P 2 1
PR3501 PR3507 LX1_1 2 2 1 +3VALW

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603
1 2 1 2 +3VALW_EN +3VALW_EN 10 LX1_2 35 1.5UH_PCMB063T-1R5MS_10A_20% JUMP_43X79
35,46 EC_ON EN1 LX1_3
1 1 1 1
6 +3VALW_P

PC3539

PC3544

PC3543

PC3542
*EC P-P 3.3V normal mode*

0.1U_0402_25V6
0_0402_5% +3VALW_PG 9 VOUT1
PGOOD1

1
@ PC3537
PD3501 @ PR3510
2 2 2 2
і
1 2 1 2 +5VALW_EN
35 MAINPWON PC3538 4
+3VALW

2
LRB751V-40T1G_SOD323-2 1 2 7 VBYP3
VCC1
+3VLP
ї 100mA
30 EC_ON_R 1U_0402_6.3V6K PJ3505
C
PJ3503 5 2
@
1
C

2
@
1 +5VALW_VIN LDO3 2 1 +3VL
V20B+ 2 1
EMC_NS@

PC3545 1 2 4.7U_0603_6.3V6K
JUMP_43X79 JUMP_43X39
0.1U_0402_25V6

PR3512
10U_0805_25V6K

10U_0805_25V6K
1

14 22 +5VALW_BS 1 2 PC3554 1 2 0.1U_0603_25V7K

PC3546

PC3547

PC3548

VIN2 BOOT2 10_0603_5%

PL3502
23 PJ3504 @
2

LX2_1 24 +5VALW_LX 1 2 +5VALW_P 2 1

LX2_2 36 2 1 +5VALW

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603
+5VALW_EN 15 LX2_3 1.5UH_PCMB063T-1R5MS_10A_20% JUMP_43X79

LV5083AGQUF_UQFN36_5X4
EN2 19 +5VALW_P
VOUT2 1 1 1 1

PC3555

PC3552

PC3553

PC3551
0.1U_0402_25V6
狥<'2=
PR3513 @

1
+3VALW_PG

@
2 1 ALW_PWRGD 16

PC3549
PGOOD2 2 2 2 2
100K_0402_5%
2 і :*)#狨'
+3VALW PC3550 VBYP5
21
+5VALW 5)6#狪'
PR3514 @ 1 2 18
VCC2
+5VLP PC3559 5<6#狣狤狢
ї 100mA
2 1 ALW_PWRGD

100K_0402_5%

Vinafix.com 1U_0402_6.3V6K
LDO5
20 1 2

4.7U_10V_K_X5R_0603
,Y]#狧狢狢1.`
狧<'2=
:*)#狪'
22UC_6.3VC_MC_X5RC_0603

33
+3VALW VINSW1
5)6#狣狢'

+3VALW_LX

+5VALW_LX
PR3517 PJ3506 @
1U_0402_6.3V6K

1 2 +3VS_EN 29 +3VS_SW 1 2 +3VS

1 VOUTSW1 1 2
5<6#狣狤狢
1

35,37,46 SUSP#
PC3566

1U_0402_6.3V6K

,Y]#狧狢狢1.`
PC3530

PC3569

0_0402_5% JUMP_43X79
1

31 3VS_SS 1 2
2

2 SS1
@

1
@ 30 PC3562
2

ENSW1 2200P_0402_25V7-K PR3508 PR3509

2.2_0805_5% 2.2_0805_5%
PJ3507 @ EMC_NS@ EMC_NS@
B 34 28 +5VS_SW 1 2 +5VS B

1+3VALW_SN 2

1+5VALW_SN 2
+5VALW VINSW2 VOUTSW2 1 2
PR3518 JUMP_43X79
22UC_6.3VC_MC_X5RC_0603

SUSP# 1 2 +5VS_EN 26 5VS_SS 1 2

1U_0402_10V6K

1 SS2
1
PC3565

PC3531

1U_0402_10V6K
1U_0402_6.3V6K

PGND_2

PGND_1

AGND_2

AGND_3

AGND_1

1
27
PC3570

PC3568
0_0402_5% PC3561
ENSW2
1

2200P_0402_25V7-K
2

2
@

2
@ @ PC3532 PC3533
2

1000P_0402_50V7K 1000P_0402_50V7K
13

12

17

32

2
EMC_NS@ EMC_NS@

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 CHARGER

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S145AST
Date: Monday, November 12, 2018 Sheet 45 of 50
5 4 3 2 1
 5 4 3 2 1

PR1902 1 2 0_0402_5% LV5028_VDDQ_EN

35 1_2VEN
PC1909 @
2 1

0.1U_0402_10V7K

PR1904 1 2 0_0402_5% LV5028_VTT_EN

35,37,45 SUSP#
PC1908 @
D 2 1 D
PR1907
0.1U_0402_10V7K 10_0603_5%
1 2 PR1901 1 2 0_0402_5%
+5VLP EC_ON 35,45

PC1902 PC1903 @
PR1906 1 2 0_0402_5% LV5028_0.95VALW_EN 2 1 1 2
35 EC_APU_ALWEN
PC1907 @ 2.2U_10V_K_X5R_0603 0.1U_0402_10V7K
2 1
PR1909
0.1U_0402_10V7K 1 2
+1.2V_B+
10_0402_5%
PR1908 1 2 0_0402_5% LV5028_1.8VALW_EN
2 1

LV5028_PMIC_EN
PC1906 @

LV5028_VSYS
2 1 PC1901
0.1U_0402_25V6
0.1U_0402_10V7K

PR1910 1 2 10K_0402_5% LV5028_0.775VALW_EN +3VALW

PC1905 @
2 1

28

27

41
9
0.1U_0402_10V7K

VCC

PMIC_EN

GND
VSYS
LV5028_0.775VALW_EN29 LV5028_EC_SMB_DA2

100K_0402_5%
25 PR1925 1 2 0_0402_5%
EN_LDO1 SDA EC_SMB_DA2 35

1
LV5028_2.5V_EN LV5028_2.5V_EN LV5028_EC_SMB_CK2

PR1915
PR1911 1 2 0_0402_5% 1 26 PR1926 1 2 0_0402_5%
35 2_5VEN EN_LDO2 SCL EC_SMB_CK2 35
PC1904 LV5028_0.95VALW_EN 11 24 LV5028_ALERT# PR1912 1 2 0_0402_5%
2 1
@ EN_V1P0A OT H_PROCHOT# 6,35
@

2
LV5028_1.8VALW_EN 16 22 APUALW_PWRGD
EN_V1P8A PG_V1P0A APUALW_PWRGD 35
0.1U_0402_10V7K
LV5028_VDDQ_EN 31
EN_VDDQ PG_V1P8A
21 APUALW_PWRGD *1.8VALW & 0.9VALW power on ready push APUALW_PWRGD*
LV5028_VTT_EN 36 23
22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603
EN_VTT PG_VDDQ
PL1901 PJ1902
C
PJ1901
@ 12 LV5028_LX_0.95VALW 1 2 +0.95VALW_P 1 2
C

1 2 LV5028_0.95VALW_VIN 7 LX_V1P0A1 13 1 2 +0.95VALW

+5VALW 1 2 VIN_V1P0A1 LX_V1P0A2 TDC=6A
EMC_NS@

8 14
0.1U_0402_25V6

0.47UH_PCMB063T-R47MS_18A_20% 1 1 1 1 1 1
VIN_V1P0A2 LX_V1P0A3 JUMP_43X79

PC1912

PC1913

PC1914

PC1915

PC1916

PC1917
JUMP_43X39 1 LX_V1P0A4
15
Voltage =0.95V
1
PC1910

PC1911

@
VO_V1P0A
10
2 2 2 2 2
@
2
@
reference AST OPN-specific ±50mv
2

2
PJ1903
@ 17 LV5028_LX_1.8VALW PL1902
PJ1904 OVP=120%
LX_V1P8A1
+3VALW 1
1 2
2 LV5028_V1.8VALW_VIN 19
VIN_V1P8A LX_V1P8A2
18 1 2
1UH_PH041H-1R0MS_3.8A_20%
+1.8VALW_P 1
1 2
2 OCP=12A +1.8VALW
1 1 1 1 TDC=3A
EMC_NS@

20

PC1920

PC1921

PC1922

PC1923
JUMP_43X39
0.1U_0402_25V6

+1.2V_P
22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603
1 VO_V1P8A JUMP_43X79
1
PC1918

PC1919

2 Voltage =1.8V ±90mv

ї LV5028_UG_1.2V 2 2 2 2 @
PC1924 33 @ @ OVP=120%
2

2 38 UGATE_VDDQ PR1916 PC1925

10U_0603_6.3V6M

і
1 VIN_VTT
PJ1905 BS_VDDQ
32 LV5028_BST_1.2V 1 2 1 2 OCP=6A
1 2 +0.6VS_P 39 0_0603_5% 0.1U_0603_25V7-M
+0.6VS 1 2 VTT 34 LV5028_LX_1.2V

LV5028_LX_0.95VALW
LX_VDDQ

LV5028_LX_1.8VALW
22UC_6.3VC_MC_X5RC_0603
JUMP_43X39 1
40 35 LV5028_LG_1.2V

PC1926
TDC=1A @
VSNS_VTT LGATE_VDDQ
PR1917 37 +1.2V_P
2 1 2 LV5028_CS 30 VSNS_VDDQ

+1.8VALW Vinafix.com1
PJ1906
1 2
@
2
33K_0402_1%

2
@
LV5028_0.775VALW_VIN 5
CS_VDDQ

VIN_LDO1 LDO1
6 +0.775VALW_P
2
1
PJ1907
1 2
@
2
+0.775VALW
TDC=0.1A

2
JUMP_43X39 JUMP_43X39
PC1927
10U_0603_6.3V6M
PC1928
10U_0603_6.3V6M @
VDDCR_FCH_S5 Voltage PR1918
4.7_0603_5%
PR1919
4.7_0603_5%
1 1
PJ1908
@ 3 +2.5V_P 1
PJ1909
2
=0.775V ±50mv in S3 S4 S5 EMC_NS@ EMC_NS@
+2.5V

1
LV5028_2.5V_VIN 4 LDO2 1 2

24.9K_0402_1%
1 2
+3VALW 1 2 VIN_LDO2

1
2

PR1920
JUMP_43X39
2 FB_LDO2 2 TDC=0.676A

+2.5V_FB
JUMP_43X39 PC1934
10U_0603_6.3V6M
PC1935
10U_0603_6.3V6M
FB reference=0.75V
PU1901

1
B 1 1 PC1930 PC1931 B

2
LV5028RPC_QFN40_5X5 680P_0402_50V7K 680P_0402_50V7K
EMC_NS@ EMC_NS@

2
1

10.5K_0402_1%
PR1921
+1.2V_B+

2
PJ1910
1 2
1 2 V20B+

10U_0805_25V6K

10U_0805_25V6K
0.1U_0402_25V6
JUMP_43X79

EMC_NS@
1

1
PC1929

PC1932

PC1933
@

2
5
D
PQ1901
AON7408L_DFN8-5
LV5028_UG_1.2V 4
G

+1.2V_P

S3
S2
S1
PL1903 @

3
2
1
PJ1911
LV5028_LX_1.2V 1 2 2 1
2 1 +1.2V
0.47UH_PCMB063T-R47MS_18A_20% JUMP_43X118

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603
5
PR1922
PQ1902 4.7_0805_5% TDC=6A
AON7380_DFN8-5 EMC_NS@ Voltage =1.2V ±60mv

1
LV5028_LG_1.2V 4 1 1 1 1 1 1
OVP=120%
OCP=200mV/13mohm=15A

PC1937

PC1938

PC1939

PC1940

PC1941

PC1942
1
A PC1943 A
680P_0402_50V7K
2 2 2 2 2 2
EMC_NS@ @ @

3
2
1

2
Security Classification LC Future Center Secret Data Title
Issued Date 2017/03/14 Deciphered Date 2017/03/14 System PMIC
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S145AST
Date: Monday, November 12, 2018 Sheet 46 of 50
5 4 3 2 1
 A B C D

1 1

PJ3601 @ PR3601 PC3603 PL3601 @

2 1 +1.35V_VIN 10_0603_5% 0.1U_0603_25V7-M 0.68UH_PCMB063T-R68MN_16A_20% PJ3602
V20B+ 2 1 +1.35V_BST 1 2 1 2 +1.35V_LX 1 2 +1.35V_P 2 1

10U_0805_25V6K

10U_0805_25V6K
JUMP_43X79 PX@ PX@ PX@
2 1 +1.35VGS

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603
JUMP_43X118

PC3601

PC3602
PR3603 1 1 1 1 1 1
2.2_0603_5% 1 2

PC3611

PC3606

PC3607

PC3608

PC3612

PC3613
2

2
EMC_PXNS@ PR3606 PX@
TDC=10A

1/16W_41.2K_1%_0402
PX@

PX@
1K_0402_1%

2
2 2 2 2 2 2

PX@

PX@

PX@

PX@
@ @ Voltage=1.36V ±3% FB=0.6V

18

1
@ PU3601

1
PC3620
OCP=13A

PX@PR3608
VBOOT
AGND
PD3601 1 2RB751V-40_SOD323-2 12 3 PC3619 560P_0402_50V7-K
VIN4 SW_1 1000P_0402_50V7K PX@ OVP=130%

2
PX@ EMC_PXNS@

2
7,48 PXS_PWREN PR3602 1 2 +1.35VGS_EN 16 4
200K_0402_1% EN4 SW_2
PC3604 1 2 0.1U_0402_25V6

1
15 +1.35V_FB PC3605 1 20.1U_0402_25V6
PX@ PX@

31.6K_0402_1%
PXS_PWREN PR3610 1 2 +3VGS_EN 25 FB
@ @JUMP_43X39

PR3609
15K_0402_1% EN1 PJ3605
PC3614 1 2 0.1U_0402_25V6 23 +3VGS_P 1 2
@ 22 PX@
VOUT1 1 2
+3VGS
+3VALW

2
VIN1

PX@
PC3618 1 21U_0402_6.3V6K
6 PX@
PC3615 1 2 1U_0402_6.3V6K PGND_1 TDC=0.025A

LV5095AGQUF_UQFN29_4X4
7
@ 24 PGND_2 Voltage=3.3V ±9%
+5VALW VCC_SW
PC3616 2 1 1U_0402_10V6K PGND_3
8
Rdson=36mohm
PX@ PX@ 9
PXS_PWREN PR3604 1 2 +1.8VGS_EN 19 PGND_4
20K_0402_1% EN2 10
PC3621 1 2 0.1U_0402_25V6 PGND_5
PX@ 21 11
+1.8VALW VIN2 PGND_6
@JUMP_43X39
PJ3603
PC3622 1 2 1U_0402_6.3V6K 20 +1.8VGS_P 1 2 TDC=0.33A
PXS_PWREN @ PX@ +0.95VGS_EN
VOUT2 1 2
+1.8VGS Voltage=1.8V ±3%
PR3617 1 2 28 PC3623 1 21U_0402_6.3V6K
EN3
2

PC3609 1 2 0.1U_0402_25V6
47.5K_0402_1% PX@ PJ3604
@ Rdson=18mohm 2

1 26 +0.95VGS_P 1 2
PX@ VIN3_1 VOUT3_1 1 2
+0.95VGS TDC=1.905A
2 27 PC3625 2 11U_0402_6.3V6K JUMP_43X39
+0.95VALW VIN3_2 VOUT3_2
PX@ Voltage=0.95V ±3%
PC3624 1 2 1U_0402_6.3V6K 29
VIN3_3
@ Rdson=5mohm

TH_ALT

PGOOD
VCC
14

17

13
2

1
+1.35V_VCC
PR3611 PR3612
100K_0402_1% 100K_0402_1%
@ @

2
Vinafix.com

1
PC3629
1U_0402_6.3V6K
PX@

2
3 3

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/15 Deciphered Date 2013/08/15 PWR_1.35VGS

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
A2 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S145AST
Date: Monday, November 12, 2018 Sheet 47 of 50
A B C D
 5 4 3 2 1

PR2401 1 2 4.7_0603_5% VGA_VCC PR2402 2 1 4.7_0402_5%

D +5VALW +VDDIO_GPU 1 2 +VGA_CORE D
PX@ PX@ PR2421
PC2404 2 1 2.2U_10V_K_X5R_0402 14 19 VGA_VDDIO PC2405 1 2 2.2U_0402_6.3V6-K 10_0402_5%
@
VCC VDDIO
PX@ PX@ *local sense
PR2403 1 2 0_0603_5% VGA_PVCC PR2404 2 1 4.7_0402_5%
+5VALW
PX@ PX@
V20B+ VR output
1 2capacity*

1
27 1 VGA_VIN PR2424
PC2407 2 1 2.2U_10V_K_X5R_0402 PVCC VIN PC2408 1 2 1U_0402_25V6-K PC2416 10_0402_5%
@
PX@ PX@ 100P_0402_50V8J

2
0_0402_5% PX@
196K_0402_1% PR2410 21
2 PR2408 1 VGA_SET1_2 1 2 VGA_SET1 11 VSEN VGA_CORE_SEN 16
SET1
0_0402_5%
PX@ PX@ PU2401
PX@ PC2411 2 1 100P_0402_50V8J PC2412 2 1 150P_0402_50V8-J
PR2405 11.3K_0402_1% RT3662EBGQW_WQFN32_4X4 PX@ PX@ *remote sense

1
1 2 VGA_SET1_1 1 PR2406 2 PC2418
PX@ PX@ 3 VGA_COMP PR2414 2 1 30K_0402_1% PR2415 2 1 10K_0402_1% 0.1U_0402_25V6
GPU side* V20B+
0_0402_5% COMP
PX@ PX@ @

2
324K_0402_1% PR2413 60.4K_0402_1% 4 VGA_FB
2 PR2409 1 VGA_TSEN_2 1 2VGA_TSEN_1 2 PR2419 1 VGA_TSEN 10 FB

10U_0805_25V6K

10U_0805_25V6K
0.1U_0402_25V6
TSEN 2

EMC_PX@PC2401

PC2402

PC2403
PX@ PX@ RGND

1
VGA_VSS_SEN 16
PX@

1
PH2401

5
1 2 VGA_TSEN_3 1 2 2 1 PC2419

2
PX@

PX@
PR2417 PR2418 0.1U_0402_25V6
PX@ PX@
PX@ 100K_0402_1%_TSM0B104F4251RZ

AON6380_DFN8-5
2
22

PQ2401
0_0402_5% 24K_0402_1% @
GPU_VREF_PINSET 13 NC 23 VGA_BOOT1 PR2411 1 2 2.2_0603_5% PC2409 2 10.22U_0603_25V7K
GPU_VREF_PINSET VREF_PINSET BOOT1
2 1 VRFF_R_1 2 1 24
PX@ PX@ VGA_UGATE1 4
UGATE1

PX@
PC2420 .47U_0402_6.3V6K PR2420
3.9_0402_1%
PX@ 25 VGA_PHASE1
PX@ PHASE1 *L/DCR=PC2414*(PR2407//PR2416)*
1 2 VGA_IMON_2 1 2 2 1 VGA_IMON 12 26 VGA_LGATE1 PL2401

3
2
1
PH2402 PR2422 PX@ PR2423 PX@ IMON LGATE1 0.22UH_CMMS063T-R22MS2R107_26A_20%
C PX@
100K_0402_1%_TSM0B104F4251RZ 12.1K_0402_1% 7.87K_0402_1% VGA_PHASE1 1 2
C

1 2 VGA_IMON_1
PX@
+VGA_CORE
PR2425
PX@

EMC_PXNS@ EMC_PXNS@
14.3K_0402_1% 7 VGA_ISEN1P
PX@ 110K_0402_5% ISEN1P

1
PR2432 2 @ @

4.7_0805_5%
1 1 1 1

330U_D2_2V_Y

330U_D2_2V_Y

330U_D2_2V_Y

330U_D2_2V_Y
AON6324_DFN8-5

AON6324_DFN8-5
+3VGS

2
8 VGA_ISEN1N

PQ2403

PQ2402

PR2412
ISEN1N PJ2401 PJ2402 + + + +

PC2413

PC2406

PC2410

PC2430
0.1U_0402_25V6
16,35 GPU_VR_HOT# 9

PC2415
PX@ JUMPER JUMPER

1
VRHOT_L

2
PR2431 2 110K_0402_5% VGA_LGATE1 4 4
+VDDIO_GPU

2
PX@

PX@
15 2 2 2 2
PWROK

PX@

PX@

PX@

CD@
15 VGA_PWROK

PX@
20 31 1.43K_0402_1% 357_0402_1%
PX@

680P_0402_50V7K
PR2430 2 110K_0402_5% PGOOD BOOT2 1 PR2407 2 2 PR2416 1

3
2
1

3
2
1
+3VGS

PC2417
30
PX@ PX@
7,15 VR_VGA_PWRGD UGATE2

2
PR2426 1
PX@ 2 0_0402_5% VGA_SVC 16 29 PC2414 TDC=21A EDC=1.5*28A=42A
voltage=VID_VDDC-I_VDDC×1mȍ±15 m V
16 GPU_SVC SVC PHASE2 2 1
PX@
PR2427 1
PX@ 2 0_0402_5% VGA_SVD 17 LGATE2
28
0.47U_0402_25V6K
undershoot 30mV
16 GPU_SVD SVD
overshoot 50mV
PX@

VGA_ISEN1N
VGA_ISEN1P
PR2428 1 2 0_0402_5% VGA_SVT 18
16 GPU_SVT SVT

2 1 VGA_EN 32 5 VGA_VCC
7,47 PXS_PWREN EN ISEN2P
PR2429 PX@
150K_0402_1%
33
GND

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603
1 2 6
ISEN2N
PX@

PD2401
@
RB751V-40_SOD323-2 1 1 1 1 1 1
.1U_0402_10V6-K

B B
2

PC2429

PC2423

PC2424

PC2425

PX@PC2426

PX@PC2427

PX@PC2428
1

PX@
2 2 2 2 2 2
@ @

Vinafix.com
A A

Security Classification LC Future Center Secret Data Title

Issued Date 2017/03/14 Deciphered Date 2017/03/14 PWR-XXXX
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom S145AST 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Monday, November 12, 2018 Sheet 48 of 50
5 4 3 2 1
 5 4 3 2 1

PR2226 PR2269
4.7_0603_5% 4.7_0603_5%
1 2 1 2
+5VALW V20B+
1 1
PC2226 PC2290
1U_10V_K_X5R_0603 0.1U_50V_K_X5R_0402
2 2
0_0402_5% PR2225
PR2224 2.2_0603_5%
1 2 1 2
+5VALW +1.8VS

2
1
1 PC2292
PC2289 0.1U_0402_25V6

1
PC2227 1U_0402_10V6K @ PR2253
2 100_0402_1%
APU_VREF_PINSET 2
1U_10V_K_X5R_0603
1 2 +APU_CORE
PU2201 PR2254
PR2290 0_0402_5%
PC2239 1 2 82P_0402_50V9-G PC2238 1 2 150P_0402_50V8-J 1 2 APU_CORE_VSEN 1 2 APU_VDDCORE_SEN_H 6
APU_VCC 17 28 APU_VIN
VCC VIN 0_0402_5%

316K_0402_1%
34.8K_0402_1%

69.8K_0402_1%

330P_0402_50V8J
1

1
D PR2250 1 2 39K_0402_1% PR2249 1 2 10K_0402_1% PR2256 D

1
22 APU_VDDIO_R 100_0402_1%

PR2271

PR2272

PR2273

PC2255
VDDIO 1 2
APU_PVCC 34

2
PVCC 8 APU_CORE_VSEN_R PR2255

2
VSEN PR2202 0_0402_5%
@ APU_CORE_RGND
1 2 1 2
APU_VDD_SEN_L 6
APU_SET1 13 0_0402_5%
PR2232 SET1 5 APU_CORE_COMP
60.4K_0402_1% COMP
1 2
FB
6 APU_CORE_FB PR2253 and PR2256 local sense
PH2203
APU_TSEN_CORE_R 1 2 APU_TSEN_CORE 12 sense VR output capacity
TSEN 4 APU_CORE_RGND_R
PR2254 and PR2255 remote sense V20B+
RGND

5
100K_0402_1%_TSM0B104F4251RZ
sense CPU ball

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K
0.1U_0402_25V6
ZKSVKXGZ[XKYKTYKV[ZNOMNZKSVKXGZ[XKGXKG

AON6380_DFN8-5

EMC_NS@
PR2218
kevin routing

1
60.4K_0402_1% 38 APU_CORE_BOOT1 1 2 CORE_BOOT_R 1 2

PC2229

PC2230

PC2232

PC2231

PC2228
APU_TSEN_NB_R 1 2 APU_TSEN_NB 23 BOOT

PQ2203
TSEN_NB PR2237 PC2233 4
APU_VREF_PINSET @ @

2
1 2 PH2202 2.2_0603_5% 0.1U_0603_25V7-M
1

100K_0402_1%_TSM0B104F4251RZ
15K_0402_1%

33K_0402_1%

24K_0402_1%

0_0402_5% 37 APU_CORE_UGATE1
PR2270

PR2235

PR2219

ZKSVKXGZ[XKYKTYKV[ZNOMNZKSVKXGZ[XKGXKG UGATE
PR2201

3
2
1
1 2 APU_VREF_PINSET_R 15 PL2202
VREF_PINSET 0.22UH_PCME064T-R22MS0R985_28A_20%
22A
2

1
PR2275 1 APU_IMON_CORE_R
2 14.7K_0402_1% 36 APU_CORE_PHASE1 APU_CORE_PHASE1 1 2
PR2287 PR2231 PHASE +APU_CORE

1
3.9_0402_1% PH2205 8.87K_0402_1%
1 APU_IMON_CORE_NTC
2 1 2 1 2 APU_IMON_CORE 14 PR2283 PR2284
PR2268 1 1

330U_D2_2V_Y

330U_D2_2V_Y
IMON

AON6324_DFN8-5

AON6324_DFN8-5
PR2276 11.8K_0402_1% 35 APU_CORE_LGATE1 0_0402_5% 0_0402_5%
4.7_0805_5% TDC=22A EDC=29A
1 2

100K_0402_1%_TSM0B104F4251RZ LGATE @ PR2242 0.47U_0402_25V6K @ + +

Voltage=VID_VDDCR_NB-(IDDCR_NB*4.0mȍ)±20m V

PC2249

PC2251
PC2286 PR2227 EMC_NS@ 1.24K_0402_1% PC2244

PQ2204

PQ2205
/354ZKSVKXGZ[XKIUSVKTYGZOUTV[ZINUIQYOJK

1CORE_SN 2

2
.47U_0402_6.3V6K 6.34K_0402_1% 4 4 APU_CORE_ISEN+ 1 2 1 2
+3VS APU_IMON_NB_R APU_IMON_NB 2 2
PR2277 1 2 13.7K_0402_1% 1 2 16
undershoot=20mV
2

IMON_NB 9 APU_CORE_ISEN1P PR2243

ISEN1P DCR sense 1.24K_0402_1% overshoot=70mV
1 2 APU_IMON_NB_NTC 1 2 PH2206 APU_CORE_ISEN1P 1 2
kevin routing

3
2
1

3
2
1
PR2278 13K_0402_1% 100K_0402_1%_TSM0B104F4251RZ 10 APU_CORE_ISEN1N PC2234
ISEN1N
1

680P_0402_50V7K
/354ZKSVKXGZ[XKIUSVKTYGZOUTV[ZINUIQYOJK

1
PR2233 PR2222 1 2 0_0402_5% APU_VR_HOT_L 11
EMC_NS@

2
1.91K_0402_1% 35,44 VR_HOT# VRHOT_L PC2237 APU_CORE_ISEN1N
<8E.5: 5*V[RRNOMN狣狪<9'6;YOJK 0.1U_0402_25V6

2
PR2230 1 2 0_0402_5% APU_PWROK_R 18
6 APU_PWROK
2

PWROK 7 APU_NB_VSEN_R PR2289 1 2 0_0402_5%

VSEN_NB
@

1
PR2234 1 2 0_0402_5% VR_APU_PGOOD_R 3 PR2204

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603
35 VR_APU_PWRGD PGOOD PC2291 100_0402_1%
0.1U_0402_25V6 PC2206 1 2 82P_0402_50V9-G PC2205 1 2 150P_0402_50V8-J APU_NB_VSEN 1 2 +APU_CORE_NB

2
1 1 1 1 1 1 1 1 1 1 1

PC2279

PC2280

PC2281

PC2282

PC2283

PC2284

PC2285

PC2253

PC2276

PC2277

PC2278
PR2220 1 2 0_0402_5% APU_SVC_R 19 27 APU_NB_COMP PR2206 1 2 44.2K_0402_1% PR2205 1 2 10K_0402_1%
6 APU_SVC SVC COMP_NB PR2208
0_0402_5% 2 2 2 2 2 2 2 2 2 2 2
APU_SVD_R APU_NB_FB @ @
PR2223 1 2 0_0402_5% 20 26 1 2 APU_VDDNB_SEN_H 6 CD@
6 APU_SVD SVD FB_NB

C PR2228 1 2 0_0402_5% APU_SVT_R 21 PR2211 PC2211 C

6 APU_SVT SVT 2.2_0603_5% 0.1U_0603_25V7-M PR2204 local sense
30 APU_NB_BOOT 1 2 BOOT_NB_R 1 2
BOOT_NB sense VR output capacity
PR2208 remote sense V20B+

0.22U_25V_K_X5R_0402
PR2229 1 2 0_0402_5% APU_EN_R 29 sense CPU ball

EMC_UMA@
10U_0805_25V6K

10U_0805_25V6K
35 EC_VR_ON EN

AON6380_DFN8-5
31 APU_NB_UGATE
+1.8VS 1
UGATE_NB
kevin routing with APU_VDD_SEN_L

1
PC2207

PC2208

PC2209
1

PQ2201
4

PR2288
1M_0402_5%

2
1 2
NC1 32 APU_NB_PHASE
PHASE_NB
@ @ @

2
1

2 0.36UH_PCMB063T-R36MS_20A_20%
1K_0402_1%

1K_0402_1%

1K_0402_1%

3
2
1
NC2 PL2201
18A
PR2262

PR2263

PR2264

APU_NB_PHASE 1 2
39 33 APU_NB_LGATE +APU_CORE_NB
NC3 LGATE_NB

1/8W_1_5%_0805
2

EMC@
5
@ @ 40
TDC=18A EDC=24A

PR2212
.1U_0402_10V6-K

1U_0402_6.3V6K

NC4

1
25 APU_NB_ISENP

Voltage=VID_VDDCR_NB-(IDDCR_NB*4.0mȍ)±20m V
1 1

330U_D2_2V_Y

330U_D2_2V_Y
ISENP_NB
1

AON6324_DFN8-5
APU_SVC_R PR2214 PR2215
DCR sense
PC2268

PC2269

0_0402_5% 0_0402_5% + +

PC2214

PC2215
1NB_SN 2
APU_SVD_R APU_NB_ISENN
41 24
kevin routing @ @
undershoot=40mV

PQ2202
2

GND ISENN_NB 4 PR2280 0.47U_0402_25V6K

PRE-PWROK METAL VID CODES

2
2 2
APU_SVT_R 1.5K_0402_1% PC2287 overshoot=70mV

2200P_0402_50V7K
1
APU_NB_ISEN+ 1 2 1 2
RT3661ABGQW_WQFN40_5X5
SVC SVD Boot Voltage PC2288 VDDCR_FCH_S5=VDDCR_NB ±7% in S0

EMC@
PC2222
Vinafix.com
@ @ @ 0.1U_0402_25V6

3
2
1
1

0 0 1.1V
220_0402_5%

220_0402_5%

220_0402_5%

2
PR2265

PR2266

PR2267

0 1 1.0V PR2281
374_0402_1%
1 0 0.9V(Default)
2

1 2
1 1 0.8V

0.22U_6.3V_K_X5R_0402

0.22U_6.3V_K_X5R_0402
22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603
1 1 1 1 1 1

PC2270

PC2271

PC2272

PC2275

PC2273

EMC@PC2274
2 2 2 2 2 2

EMC_DIS@
CD@

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2017/03/14 Deciphered Date 2017/03/14 PWR_CPU Core

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS A1 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S145AST
Date: Monday, November 12, 2018 Sheet 49 of 50

5 4 3 2 1
 5 4 3 2 1

D
GPU D

BOARD
Config. BOARD_ID0 BOARD_ID3
14'' 0 0
15'' 0 1
17'' 1 0

C C

Vinafix.com
B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 Virtual symbol

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S145AST
Date: Monday, November 12, 2018 Sheet 50 of 50
5 4 3 2 1