PD - 95488

IRF2807ZPbF
AUTOMOTIVE MOSFET IRF2807ZSPbF
Features IRF2807ZLPbF
O Advanced Process Technology
O Ultra Low On-Resistance HEXFET® Power MOSFET
O Dynamic dv/dt Rating
D
O 175°C Operating Temperature
O Fast Switching
VDSS = 75V
O Repetitive Avalanche Allowed up to Tjmax
O Lead-Free RDS(on) = 9.4mΩ
G
Description
ID = 75A
Specifically designed for Automotive applications, S
this HEXFET® Power MOSFET utilizes the latest
processing techniques to achieve extremely low
on-resistance per silicon area. Additional fea-
tures of this design are a 175°C junction operating
temperature, fast switching speed and improved
repetitive avalanche rating . These features com-
bine to make this design an extremely efficient
and reliable device for use in Automotive applica-
tions and a wide variety of other applications. TO-220AB D2Pak TO-262
IRF2807Z IRF2807ZS IRF2807ZL

Absolute Maximum Ratings

Parameter Max. Units
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V (Silicon Limited) 89 A
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V (See Fig. 9) 63
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V (Package Limited) 75
IDM Pulsed Drain Current c 350
PD @TC = 25°C Maximum Power Dissipation 170 W
Linear Derating Factor 1.1 W/°C
VGS Gate-to-Source Voltage ± 20 V
EAS Single Pulse Avalanche Energy (Thermally Limited) d 160 mJ
EAS (tested) Single Pulse Avalanche Energy Tested Value i 200
IAR Avalanche Current c See Fig.12a,12b,15,16 A
EAR Repetitive Avalanche Energy h mJ
TJ Operating Junction and -55 to + 175 °C
TSTG Storage Temperature Range
Soldering Temperature, for 10 seconds 300 (1.6mm from case )
Mounting torque, 6-32 or M3 screw 10 lbf•in (1.1N•m)
Thermal Resistance
Parameter Typ. Max. Units
RθJC Junction-to-Case ––– 0.90 °C/W
RθCS Case-to-Sink, Flat, Greased Surface 0.50 –––
RθJA Junction-to-Ambient ––– 62
RθJA Junction-to-Ambient (PCB Mount, steady state) j ––– 40

HEXFET® is a registered trademark of International Rectifier.

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IRF2807Z/S/LPbF
Static @ TJ = 25°C (unless otherwise specified)
Parameter Min. Typ. Max. Units Conditions
V(BR)DSS Drain-to-Source Breakdown Voltage 75 ––– ––– V VGS = 0V, ID = 250µA
∆ΒVDSS/∆TJ Breakdown Voltage Temp. Coefficient ––– 0.073 ––– V/°C Reference to 25°C, ID = 1mA
RDS(on) Static Drain-to-Source On-Resistance ––– 7.5 9.4 mΩ VGS = 10V, ID = 53A f
VGS(th) Gate Threshold Voltage 2.0 ––– 4.0 V VDS = VGS, ID = 250µA
gfs Forward Transconductance 67 ––– ––– S VDS = 25V, ID = 53A
IDSS Drain-to-Source Leakage Current ––– ––– 20 µA VDS = 75V, VGS = 0V
––– ––– 250 VDS = 75V, VGS = 0V, TJ = 125°C
IGSS Gate-to-Source Forward Leakage ––– ––– 200 nA VGS = 20V
Gate-to-Source Reverse Leakage ––– ––– -200 VGS = -20V
Qg Total Gate Charge ––– 71 110 nC ID = 53A
Qgs Gate-to-Source Charge ––– 19 29 VDS = 60V
Qgd Gate-to-Drain ("Miller") Charge ––– 28 42 VGS = 10V f
td(on) Turn-On Delay Time ––– 18 ––– ns VDD = 38V
tr Rise Time ––– 79 ––– ID = 53A
td(off) Turn-Off Delay Time ––– 40 ––– RG = 6.2Ω
tf Fall Time ––– 45 ––– VGS = 10V f
LD Internal Drain Inductance ––– 4.5 ––– nH Between lead, D

6mm (0.25in.)
LS Internal Source Inductance ––– 7.5 ––– from package G

and center of die contact S

Ciss Input Capacitance ––– 3270 ––– pF VGS = 0V

Coss Output Capacitance ––– 420 ––– VDS = 25V
Crss Reverse Transfer Capacitance ––– 240 ––– ƒ = 1.0MHz, See Fig. 5
Coss Output Capacitance ––– 1590 ––– VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz
Coss Output Capacitance ––– 280 ––– VGS = 0V, VDS = 60V, ƒ = 1.0MHz
Coss eff. Effective Output Capacitance ––– 440 ––– VGS = 0V, VDS = 0V to 60V

Diode Characteristics
Parameter Min. Typ. Max. Units Conditions
IS Continuous Source Current ––– ––– 89 MOSFET symbol D

(Body Diode) A showing the

ISM Pulsed Source Current ––– ––– 350 integral reverse G

(Body Diode) c p-n junction diode.

f
S

VSD Diode Forward Voltage ––– ––– 1.3 V TJ = 25°C, IS = 53A, VGS = 0V

f
trr Reverse Recovery Time ––– 46 69 ns TJ = 25°C, IF = 53A, VDD = 25V
Qrr Reverse Recovery Charge ––– 80 120 nC di/dt = 100A/µs
ton Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)

Notes:
 Repetitive rating; pulse width limited by … Coss eff. is a fixed capacitance that gives the same charging time
max. junction temperature. (See fig. 11). as Coss while VDS is rising from 0 to 80% VDSS .
‚ Limited by TJmax, starting TJ = 25°C, L = 0.12mH, † Limited by TJmax , see Fig.12a, 12b, 15, 16 for typical repetitive
RG = 25Ω, IAS = 53A, VGS =10V. Part not avalanche performance.
recommended for use above this value. ‡ This value determined from sample failure population. 100%
ƒ ISD ≤ 53A, di/dt ≤ 420A/µs, VDD ≤ V(BR)DSS, tested to this value in production.
TJ ≤ 175°C. ˆ This is applied to D2Pak, when mounted on 1" square PCB
„ Pulse width ≤ 1.0ms; duty cycle ≤ 2%. ( FR-4 or G-10 Material ). For recommended footprint and
soldering techniques refer to application note #AN-994.

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 IRF2807Z/S/LPbF

1000 1000
VGS VGS
TOP 15V TOP 15V
10V 10V
8.0V 8.0V

ID, Drain-to-Source Current (A)

ID, Drain-to-Source Current (A)

100 7.0V 7.0V

6.0V 6.0V
5.5V 5.5V
5.0V 100 5.0V
BOTTOM 4.5V BOTTOM 4.5V
10

1
10
4.5V
4.5V
0.1

20µs PULSE WIDTH 20µs PULSE WIDTH

Tj = 25°C Tj = 175°C
0.01 1
0.1 1 10 100 1000 0.1 1 10 100 1000

VDS, Drain-to-Source Voltage (V) VDS, Drain-to-Source Voltage (V)

Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics

1000 150
Gfs, Forward Transconductance (S)

125
ID, Drain-to-Source Current (Α)

T J = 175°C
100 T J = 25°C
100

10 75

T J = 175°C
T J = 25°C 50
1

VDS = 25V 25
20µs PULSE WIDTH
0.1 0
4 6 8 10 12 0 25 50 75 100 125 150
VGS, Gate-to-Source Voltage (V) ID,Drain-to-Source Current (A)

Fig 3. Typical Transfer Characteristics Fig 4. Typical Forward Transconductance

vs. Drain Current

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 IRF2807Z/S/LPbF

100000 12.0
VGS = 0V, f = 1 MHZ
ID= 53A
C iss = C gs + C gd, C ds SHORTED
C rss = C gd VDS= 60V

VGS, Gate-to-Source Voltage (V)

10.0
C oss = C ds + C gd VDS= 38V
10000
VDS= 15V
C, Capacitance(pF)

Ciss 8.0

1000 Coss 6.0

Crss

4.0
100
2.0

10 0.0
1 10 100 0 10 20 30 40 50 60 70 80
VDS, Drain-to-Source Voltage (V) QG Total Gate Charge (nC)

Fig 5. Typical Capacitance vs. Fig 6. Typical Gate Charge vs.

Drain-to-Source Voltage Gate-to-Source Voltage

1000 10000

OPERATION IN THIS AREA

LIMITED BY R DS(on)
ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)

1000
100 TJ = 175°C

100

10
100µsec
10

T J = 25°C
1 1msec
1
Tc = 25°C
Tj = 175°C 10msec
VGS = 0V Single Pulse
0 0.1
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 1 10 100 1000
VSD, Source-to-Drain Voltage (V) VDS, Drain-to-Source Voltage (V)

Fig 7. Typical Source-Drain Diode Fig 8. Maximum Safe Operating Area

Forward Voltage

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 IRF2807Z/S/LPbF

100 2.5

RDS(on) , Drain-to-Source On Resistance

ID = 53A
90 Limited By Package
VGS = 10V
80
2.0
ID, Drain Current (A)

70

60

(Normalized)
50 1.5

40

30
1.0
20

10

0 0.5
25 50 75 100 125 150 175 -60 -40 -20 0 20 40 60 80 100 120 140 160 180

T C , Case Temperature (°C) T J , Junction Temperature (°C)

Fig 9. Maximum Drain Current vs. Fig 10. Normalized On-Resistance

Case Temperature vs. Temperature

10
Thermal Response ( Z thJC )

D = 0.50
0.20
0.1 0.10
0.05
0.02
0.01
0.01
SINGLE PULSE Notes:
( THERMAL RESPONSE ) 1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
0.001
1E-006 1E-005 0.0001 0.001 0.01 0.1

t1 , Rectangular Pulse Duration (sec)

Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case

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IRF2807Z/S/LPbF

15V 300

EAS , Single Pulse Avalanche Energy (mJ)

ID

250
TOP 22A
L DRIVER
VDS 38A
BOTTOM 53A
200
RG D.U.T +
V
- DD
IAS A
VGS
20V 150
tp 0.01Ω

100
Fig 12a. Unclamped Inductive Test Circuit
V(BR)DSS 50

tp
0
25 50 75 100 125 150 175

Starting T J , Junction Temperature (°C)

I AS

Fig 12c. Maximum Avalanche Energy

Fig 12b. Unclamped Inductive Waveforms
vs. Drain Current
QG
10 V
QGS QGD
5.0

VG
VGS(th) Gate threshold Voltage (V)

4.0

Charge
ID = 250µA
Fig 13a. Basic Gate Charge Waveform 3.0

Current Regulator
Same Type as D.U.T.

2.0
50KΩ

12V .2µF
.3µF

+
V
D.U.T. - DS 1.0
-75 -50 -25 0 25 50 75 100 125 150 175 200
VGS
T J , Temperature ( °C )
3mA

IG ID
Current Sampling Resistors

Fig 14. Threshold Voltage vs. Temperature

Fig 13b. Gate Charge Test Circuit
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 IRF2807Z/S/LPbF

1000

Duty Cycle = Single Pulse

100 Allowed avalanche Current vs

Avalanche Current (A)

0.01 avalanche pulsewidth, tav

assuming ∆ Tj = 25°C due to
avalanche losses
10 0.05
0.10

0.1
1.0E-08 1.0E-07 1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01

tav (sec)

Fig 15. Typical Avalanche Current vs.Pulsewidth

200 Notes on Repetitive Avalanche Curves , Figures 15, 16:

TOP Single Pulse (For further info, see AN-1005 at www.irf.com)
BOTTOM 10% Duty Cycle 1. Avalanche failures assumption:
ID = 53A Purely a thermal phenomenon and failure occurs at a
EAR , Avalanche Energy (mJ)

150 temperature far in excess of T jmax. This is validated for

every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is
not exceeded.
100 3. Equation below based on circuit and waveforms shown in
Figures 12a, 12b.
4. PD (ave) = Average power dissipation per single
avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for
50
voltage increase during avalanche).
6. I av = Allowable avalanche current.
7. ∆T = Allowable rise in junction temperature, not to exceed
Tjmax (assumed as 25°C in Figure 15, 16).
0 tav = Average time in avalanche.
25 50 75 100 125 150 175 D = Duty cycle in avalanche = tav ·f
Starting T J , Junction Temperature (°C) ZthJC(D, tav ) = Transient thermal resistance, see figure 11)

PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC

Iav = 2DT/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
Fig 16. Maximum Avalanche Energy
vs. Temperature
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IRF2807Z/S/LPbF

Driver Gate Drive

D.U.T P.W.
Period D=
P.W.
Period
+

ƒ
*
VGS=10V
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
- • Low Leakage Inductance D.U.T. ISD Waveform
Current Transformer
+
‚ Reverse
Recovery Body Diode Forward
-
„ + Current Current
- di/dt
D.U.T. VDS Waveform
Diode Recovery
 dv/dt
VDD

RG • dv/dt controlled by RG V DD Re-Applied

• Driver same type as D.U.T. + Voltage Body Diode Forward Drop
• I SD controlled by Duty Factor "D" - Inductor Curent
• D.U.T. - Device Under Test

Ripple ≤ 5% ISD

* VGS = 5V for Logic Level Devices

Fig 17. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs

RD
V DS

VGS
D.U.T.
RG
+
-VDD

10V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %

Fig 18a. Switching Time Test Circuit

VDS
90%

10%
VGS
td(on) tr t d(off) tf

Fig 18b. Switching Time Waveforms

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 IRF2807Z/S/LPbF
TO-220AB Package Outline
Dimensions are shown in millimeters (inches)

10.54 (.415) 3.78 (.149) -B-

2.87 (.113) 10.29 (.405) 3.54 (.139) 4.69 (.185)
2.62 (.103) 4.20 (.165)
-A- 1.32 (.052)
1.22 (.048)
6.47 (.255)
6.10 (.240)
4
15.24 (.600)
14.84 (.584)
LEAD ASSIGNMENTS
1.15 (.045) LEAD ASSIGNMENTS
MIN HEXFET
1 - GATE
IGBTs, CoPACK
1 2 3 2 - DRAIN
1- GATE 1- GATE
3 - SOURCE
2- DRAIN 2- COLLECTOR
3- SOURCE
4 - DRAIN 3- EMITTER
4- DRAIN 4- COLLECTOR
14.09 (.555)
13.47 (.530) 4.06 (.160)
3.55 (.140)

0.93 (.037) 0.55 (.022)

3X 3X
0.69 (.027) 0.46 (.018)
1.40 (.055)
3X
1.15 (.045) 0.36 (.014) M B A M
2.92 (.115)
2.64 (.104)
2.54 (.100)
2X
NOTES:
1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982. 3 OUTLINE CONFORMS TO JEDEC OUTLINE TO-220AB.
2 CONTROLLING DIMENSION : INCH 4 HEATSINK & LEAD MEASUREMENTS DO NOT INCLUDE BURRS.

TO-220AB Part Marking Information

E XAMPL E : T HIS IS AN IR F 1010

L OT CODE 1789
AS S E MB L E D ON WW 19, 1997 INT E R NAT IONAL PAR T NU MB E R
IN T HE AS S E MB L Y L INE "C" R E CT IF IE R
L OGO
Note: "P" in assembly line
position indicates "Lead-Free" DAT E CODE
YE AR 7 = 1997
AS S E MB L Y
L OT CODE WE E K 19
L INE C

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IRF2807Z/S/LPbF
D2Pak Package Outline
Dimensions are shown in millimeters (inches)

D2Pak Part Marking Information

T HIS IS AN IRF530S WIT H PART NUMBE R
LOT CODE 8024 INT ERNAT IONAL
AS S EMB LE D ON WW 02, 2000 RE CT IFIER F 530S
IN THE AS S E MB LY LINE "L " L OGO
DAT E CODE
Note: "P" in as s embly line YE AR 0 = 2000
pos ition indicates "Lead-Free" AS S E MBL Y
LOT CODE WE EK 02
LINE L

OR
PART NUMB ER
INT ERNAT IONAL
RECT IFIER F530S
LOGO
DAT E CODE
P = DES IGNAT ES LEAD-FREE
AS S EMB LY PRODUCT (OPT IONAL)
LOT CODE YEAR 0 = 2000
WEEK 02
A = AS S EMB LY S IT E CODE

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 IRF2807Z/S/LPbF

TO-262 Package Outline

Dimensions are shown in millimeters (inches)

TO-262 Part Marking Information

EXAMPLE: T HIS IS AN IRL3103L
LOT CODE 1789 PART NUMBER
INTERNATIONAL
AS SEMBLED ON WW 19, 1997
RECT IFIER
IN T HE ASS EMBLY LINE "C" LOGO
DAT E CODE
Note: "P" in assembly line
pos ition indicates "Lead-F ree" YEAR 7 = 1997
ASS EMBLY
LOT CODE WEEK 19
LINE C

OR
PART NUMBER
INT ERNAT IONAL
RECT IF IER
LOGO
DAT E CODE
P = DES IGNAT ES LEAD-F REE
ASS EMBLY PRODUCT (OPTIONAL)
LOT CODE YEAR 7 = 1997
WEEK 19
A = ASS EMBLY SIT E CODE

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IRF2807Z/S/LPbF
D2Pak Tape & Reel Information
Dimensions are shown in millimeters (inches)

TRR

1.60 (.063)
1.50 (.059)
1.60 (.063)
4.10 (.161) 1.50 (.059)
3.90 (.153) 0.368 (.0145)
0.342 (.0135)

FEED DIRECTION 1.85 (.073) 11.60 (.457)

1.65 (.065) 11.40 (.449) 24.30 (.957)
15.42 (.609)
23.90 (.941)
15.22 (.601)
TRL
1.75 (.069)
10.90 (.429) 1.25 (.049)
10.70 (.421) 4.72 (.136)
16.10 (.634) 4.52 (.178)
15.90 (.626)

FEED DIRECTION

13.50 (.532) 27.40 (1.079)

12.80 (.504) 23.90 (.941)

330.00 60.00 (2.362)

(14.173) MIN.
MAX.

30.40 (1.197)
NOTES : MAX.
1. COMFORMS TO EIA-418. 26.40 (1.039) 4
2. CONTROLLING DIMENSION: MILLIMETER. 24.40 (.961)
3. DIMENSION MEASURED @ HUB.
3
4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.

TO-220AB package is not recommended for Surface Mount Application.

Data and specifications subject to change without notice.
This product has been designed and qualified for the Automotive [Q101] market.
Qualification Standards can be found on IR’s Web site.

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 06/04
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