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Experiment 5

This document describes using XOR and XNOR gates to generate and check parity for error detection in data transmission. It provides examples of even and odd parity calculation and explains how a parity generator/checker circuit works. The procedure outlines creating a VHDL file to simulate an even parity generator and checker and test it by checking the parity and errors for different data patterns. It asks two questions about using XOR vs XNOR gates for parity and the limitation of parity for detecting even number of bit errors.

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111 views3 pages

Experiment 5

This document describes using XOR and XNOR gates to generate and check parity for error detection in data transmission. It provides examples of even and odd parity calculation and explains how a parity generator/checker circuit works. The procedure outlines creating a VHDL file to simulate an even parity generator and checker and test it by checking the parity and errors for different data patterns. It asks two questions about using XOR vs XNOR gates for parity and the limitation of parity for detecting even number of bit errors.

Uploaded by

AAAAALLENN
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Experiment V

Use of XOR/XNOR Gates to Generate & Check Parity

OBJECTIVES:
 Demonstrate the use of XOR and XNOR gates to generate and check parity.

MATERIALS:
 Quartus II sofrware 13.1 or higher.
 IBM or compatible computer with Pentium III or higher, 128 M-byte RAM or more, and 8 G-
byte Or larger hard drive.
 XC FPGA Board with Altera FPGA (Cyclone IV EP4CE6E22C8)

DISCUSSION:
A parity checker circuit is used to detect a 1-bit error, as could occur in data transmission. Such an
error can be caused by an electrical noise “hit”, or by a hardware failure such as a bit “stuck at 0” or
“stuck at 1”. Parity can be even or odd and requires that an extra bit (the parity bit) be generated and
“tacked onto” the data. The value of the parity bit is derived from the data. The following examples
illustrate even and odd parity.
1) Even parity
Determine the parity bit for the 4 bit data 1001 using even parity.
The number of 1 bit in 1001 is 2, an even number. To have even parity for this data, we must keep the
total number of 1s, including the parity bit, even. Hence, the parity bit should be a 0. Note that, as a
binary number, 1001 is odd (value is 9). But whether the value of 1001 is odd or even is not important.
Only the number of 1s is important.
Data: 1001 Parity bit: 0 Data with parity: 10010
2) Odd Parity
Determine the parity bit for the 8 bit data 10110111.
The number of 1 bit in 10110111 is 6, an even number. To have even parity for this data, we must
make sure the total number of 1s, including the parity bit, is an odd number. Therefore, the parity bit
must be 1. Again, the numerical value of the data is not important, all that counts is the number of 1s
in the data.
Data: 10110111 Parity bit: 1 Data with parity: 101101111

PROCEDURE:
1. Open Quartus II and create a new project.
2. Create a VHDL file named “eparity” and write the code for parity.

1
3. Check the Parity and the Error pattern with your simulation and fill the table.

Data Tx Parity Data Rx Error

00 0 1 0 0 0 0 1 00 0 1 0 0 0 0 0

0 0
0 0 0 0 1 1 1 1
0 0 00 0 0 00

01 0 0 0 00 0
1 01 0 0 0 0 0 0
0

01 0 0 0 00
1 0
01 0 000 0 0 1

0 1 1 1 0 0 0 0 1 0 0 0 0
0 1
0 1 1

0 1 1 0 00 0 0 0
1 1 1 0 0 0 0 0 1

2
4. Analysis the time-sequence

VHDLcodeisdiferentfomclanguage.cl anguagecoderwnsstepbystep.fwmtoptobottom.bu.tn

thenesutt.tw/hputofcheckbitRxBalnuystheinitial
VADLcoderunssimnltaneously.Thetefegwhe.in Txrunsandcalcutat.es

istriggereditheerrorcanbeoutputon.ly
valneo.whenthethrrded.ge

completethewrifcatiomsothere.is
aftetTxcompletesthe.ca/culationandtransfrsittoRxto
alwaysadiferenaofthree.ge

Question
1. If you are asked to build an 8 bit odd parity generator/ checker with the output ERROR=1 when
there is a 1 bit error, which type of gates, XOR or XNOR is simpler to use? Explain.

ItissimpkrtowseXOR.emorisoinitig.TT
X 13 1 00 0 1 1 0 0 Rx B 1 0 0 0 1 10 1

Emrcanbedefedbyi.soit s ompier.Erexample.TN
1 ④ 0 ⊕ 0 ④ 0 ④ 1④ 1 ⊕0 ④ 0 =
1

2. Why can’t a parity generator/checker detect even-bit errors? Given an example in your
explanation.
is 1 0 00 11 0 0 , Rxis 1 00 1 1 1 10
, paritg.jo

Whenthenumberemsisoddithepangofthenumbe.ro
hted.whenthenuhnberise.eu
f willchange.theemorcanbe.de
1

theparitgofthenwmberoflwillnotcha.ge
,
,

sotteenorcannotbedetecte.de

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