PIC16(L)F15313/23

Full-Featured 8/14-Pin Microcontrollers

Description
PIC16(L)F15313/23 microcontrollers feature Analog, Core Independent Peripherals and Communication Peripherals,
combined with eXtreme Low-Power (XLP) technology for a wide range of general purpose and low-power applications.
The devices feature multiple PWMs, multiple communication, temperature sensor, and memory features like Memory
Access Partition (MAP) to support customers in data protection and bootloader applications, and Device Information
Area (DIA) which stores factory calibration values to help improve temperature sensor accuracy.

Core Features Power-Saving Functionality

• C Compiler Optimized RISC Architecture • DOZE mode: Ability to Run the CPU Core Slower
• Operating Speed: than the System Clock
- DC – 32 MHz clock input • IDLE mode: Ability to halt CPU Core while Internal
- 125 ns minimum instruction cycle Peripherals Continue Operating
• Interrupt Capability • SLEEP mode: Lowest Power Consumption
• 16-Level Deep Hardware Stack • Peripheral Module Disable (PMD):
• Timers: - Ability to disable hardware module to
- 8-bit Timer2 with Hardware Limit Timer (HLT) minimize active power consumption of
- 16-bit Timer0/1 unused peripherals
• Low-Current Power-on Reset (POR)
• Configurable Power-up Timer (PWRTE) eXtreme Low-Power (XLP) Features
• Brown-out Reset (BOR)
• Low-Power BOR (LPBOR) Option • Sleep mode: 50 nA @ 1.8V, typical
• Windowed Watchdog Timer (WWDT): • Watchdog Timer: 500 nA @ 1.8V, typical
- Variable prescaler selection • Operating Current:
- Variable window size selection - 8 A @ 32 kHz, 1.8V, typical
- All sources configurable in hardware or - 32 A/MHz @ 1.8V, typical
software
• Programmable Code Protection Digital Peripherals
• Four Configurable Logic Cells (CLC):
Memory - Integrated combinational and sequential logic
• 3.5 KB Flash Program Memory • Complementary Waveform Generator (CWG):
• 256 Bytes Data SRAM - Rising and falling edge dead-band control
• Direct, Indirect and Relative Addressing modes - Full-bridge, half-bridge, 1-channel drive
• Memory Access Partition (MAP): - Multiple signal sources
- Write protect • Two Capture/Compare/PWM (CCP) module:
- Customizable Partition - 16-bit resolution for Capture/Compare modes
• Device Information Area (DIA) - 10-bit resolution for PWM mode
• Device Configuration Information (DCI) • Four 10-Bit PWMs
• Numerically Controlled Oscillator (NCO):
Operating Characteristics - Generates true linear frequency control and
increased frequency resolution
• Operating Voltage Range: - Input Clock: 0 Hz < FNCO < 32 MHz
- 1.8V to 3.6V (PIC16LF15313/23) - Resolution: FNCO/220
- 2.3V to 5.5V (PIC16F15313/23) • One EUSART, RS-232, RS-485, LIN compatible
• Temperature Range:
- Industrial: -40°C to 85°C
- Extended: -40°C to 125°C

 2017 Microchip Technology Inc. Preliminary DS40001897A-page 1

 PIC16(L)F15313/23
Digital Peripherals (Cont.) Flexible Oscillator Structure
• I/O Pins: • High-Precision Internal Oscillator:
- Individually programmable pull-ups - Software selectable frequency range up to 32
- Slew rate control MHz, ±1% typical
- Interrupt-on-change with edge-select • x2/x4 PLL with Internal and External Sources
- Input level selection control (ST or TTL) • Low-Power Internal 32 kHz Oscillator
- Digital open-drain enable (LFINTOSC)
• Peripheral Pin Select (PPS): • External Oscillator Block with:
- Enables pin mapping of digital I/O - Three crystal/resonator modes up to 20 MHz
- Three external clock modes up to 32 MHz
Analog Peripherals • Fail-Safe Clock Monitor:
- Allows for safe shutdown if primary clock
• Analog-to-Digital Converter (ADC): stops
- 10-bit with up to 43 external channels • Oscillator Start-up Timer (OST):
- Operates in Sleep - Ensures stability of crystal oscillator
• Up to two Comparators: resources
- FVR, DAC and external input pin available on
inverting and noninverting input
- Software selectable hysteresis
- Outputs available internally to other modules,
or externally through PPS
• 5-Bit Digital-to-Analog Converter (DAC):
- 5-bit resolution, rail-to-rail
- Positive Reference Selection
- Unbuffered I/O pin output
- Internal connections to ADCs and
comparators
• Voltage Reference:
- Fixed Voltage Reference with 1.024V, 2.048V
and 4.096V output levels
• Zero-Cross Detect module:
- AC high voltage zero-crossing detection for
simplifying TRIAC control
- Synchronized switching control and timing

 2017 Microchip Technology Inc. Preliminary DS40001897A-page 2

 PIC16(L)F15313/23
TABLE 1: PIC16(L)F153XX FAMILY TYPES

Program Flash Memory (KW)

Program Flash Memory (KB)

Peripheral Module Disable

Memory Access Partition
Window Watchdog Timer

Device Information Area

Storage Area Flash (B)

8-bit/ (with HLT) Timer

Temperature Indicator

Peripheral Pin Select

Zero-Cross Detect

EUSART/ I2C-SPI
Data Sheet Index

CCP/10-bit PWM
Comparator

16-bit Timer
Data SRAM

10-bit ADC

5-bit DAC

Debug (1)
I/OPins
(bytes)

CWG
NCO
CLC
Device

PIC16(L)F15313 (C) 2 3.5 224 256 6 5 1 1 1 2 Y 2/4 1 1 4 Y Y Y Y 1/1 Y Y I

PIC16(L)F15323 (C) 2 3.5 224 256 12 11 1 2 1 2 Y 2/4 1 1 4 Y Y Y Y 1/1 Y Y I
PIC16(L)F15324 (D) 4 7 224 512 12 11 1 2 1 2 Y 2/4 1 1 4 Y Y Y Y 2/1 Y Y I
PIC16(L)F15325 (B) 8 14 224 1024 12 11 1 2 1 2 Y 2/4 1 1 4 Y Y Y Y 2/1 Y Y I
PIC16(L)F15344 (D) 4 7 224 512 18 17 1 2 1 2 Y 2/4 1 1 4 Y Y Y Y 2/1 Y Y I
PIC16(L)F15345 (B) 8 14 224 1024 18 17 1 2 1 2 Y 2/4 1 1 4 Y Y Y Y 2/1 Y Y I
PIC16(L)F15354 (A) 4 7 224 512 25 24 1 2 1 2 Y 2/4 1 1 4 Y Y Y Y 2/2 Y Y I
PIC16(L)F15355 (A) 8 14 224 1024 25 24 1 2 1 2 Y 2/4 1 1 4 Y Y Y Y 2/2 Y Y I
PIC16(L)F15356 (E) 16 28 224 2048 25 24 1 2 1 2 Y 2/4 1 1 4 Y Y Y Y 2/2 Y Y I
PIC16(L)F15375 (E) 8 14 224 1024 36 35 1 2 1 2 Y 2/4 1 1 4 Y Y Y Y 2/2 Y Y I
PIC16(L)F15376 (E) 16 28 224 2048 36 35 1 2 1 2 Y 2/4 1 1 4 Y Y Y Y 2/2 Y Y I
PIC16(L)F15385 (E) 8 14 224 1024 44 43 1 2 1 2 Y 2/4 1 1 4 Y Y Y Y 2/2 Y Y I
PIC16(L)F15386 (E) 16 28 224 2048 44 43 1 2 1 2 Y 2/4 1 1 4 Y Y Y Y 2/2 Y Y I
Note 1: I - Debugging integrated on chip.
Data Sheet Index:
A: DS40001853 PIC16(L)F15354/5 Data Sheet, 28-Pin
B: DS40001865 PIC16(L)F15325/45 Data Sheet, 14/20-Pin
C: DS40001897 PIC16(L)F15313/23 Data Sheet, 8/14-Pin
D: DS40001889 PIC16(L)F15324/44 Data Sheet, 14/20-Pin
E: DS40001866 PIC16(L)F15356/75/76/85/86 Data Sheet, 28/40/48-Pin

Note: For other small form-factor package availability and marking information, visit www.microchip.com/packaging or
contact your local sales office.

 2017 Microchip Technology Inc. Preliminary DS40001897A-page 3

 PIC16(L)F15313/23
TABLE 2: PACKAGES
Device PDIP SOIC DFN TSSOP UQFN (4x4)
PIC16(L)F15313   
PIC16(L)F15323    

 2017 Microchip Technology Inc. Preliminary DS40001897A-page 4

 PIC16(L)F15313/23
PIN DIAGRAMS

8-PIN PDIP, SOIC, MSOP

PIC16(L)F15313
VDD 1 8 VSS
RA5 2 7 RA0/ICSPDAT
RA4 3 6 RA1/ICSPCLK
VPP/MCLR/RA3 4 5 RA2

Note: See Table 3 for location of all peripheral functions.

14-PIN PDIP, SOIC, TSSOP 14 VSS

VDD 1

PIC16(L)F15323
RA5 2 13 RA0/ICSPDAT
RA4 3 12 RA1/ICSPCLK
VPP/MCLR/RA3 4 11 RA2
RC5 5 10 RC0
RC4 6 9 RC1
RC3 7 8 RC2

Note: See Table 4 for location of all peripheral functions.

16-PIN UQFN (4X4)

VDD

Vss
NC
NC

16 15 14 13

RA5 1 12 RA0/ICSPDAT
RA4 2 PIC16(L)F15323 11 RA1/ICSPCLK
MCLR/VPP/RA3 3 10 RA2
RC5 4 9 RC0

5 6 7 8
RC2
RC3

RC1
RC4

Note 1: See Table 4 for location of all peripheral functions.

2: It is recommended that the exposed bottom pad be connected to VSS.

 2017 Microchip Technology Inc. Preliminary DS40001897A-page 5

 PIN ALLOCATION TABLES
 2017 Microchip Technology Inc.

TABLE 3: 8-PIN ALLOCATION TABLE (PIC16(L)F15313)

8-Pin PDIP/SOIC/

Comparator
Reference

Interrupt
EUSART

Pull-up
Timers
MSOP

MSSP

CLKR

Basic
PWM

CWG
I/O(2)

NCO
ADC

DAC

CCP

ZCD

CLC
RA0 7 ANA0 ― C1IN0+ ― DAC1OUT ― ― ― ― ― ― TX1/ CLCIN3(1) ― IOCA0 Y ICSPDAT
CK1(1)
RA1 6 ANA1 VREF+ C1IN0- ― DAC1REF+ T0CKI(1) ― ― ― SCK1(4) ― RX1/ CLCIN2(1) ― IOCA1 Y ICSPCLK
SCL1(1,4) DT1(1)
RA2 5 ANA2 ― ― ― ― ― ― ― CWG1IN(1) SDA1(1,4) ZCD1 ― ― ― INT(1) Y ―
SDI1(1) IOCA2
RA3 4 ― ― ― ― ― ― ― ― ― SS1(1) ― ― CLCIN0(1) ― IOCA3 Y MCLR
VPP
RA4 3 ANA4 ― C1IN1- ― ― T1G(1) ― ― ― ― ― ― ― ― IOCA4 Y CLKOUT
OSC2
Preliminary

RA5 2 ANA5 ― ― ― ― T1CKI(1) CCP1(1) ― ― ― ― ― CLCIN1(1) ― IOCA5 Y CLKIN

ADACT(1) T2IN(1) CCP2(1) OSC1
EIN
VDD 1 ― ― ― ― ― ― ― ― ― ― ― ― ― ― ― ― VDD
VSS 8 ― ― ― ― ― ― ― ― ― ― ― ― ― ― ― ― VSS
― ― ― C1OUT NCO1OUT ― TMR0 CCP1 PWM3OUT CWG1A SDO1 ― DT1(3) CLC1OUT CLKR ― ― ―
― ― ― ― ― ― ― CCP2 PWM4OUT CWG1B SCK1 ― CK1 CLC2OUT ― ― ― ―

PIC16(L)F15313/23
OUT(2)
― ― ― ― ― ― ― ― PWM5OUT CWG1C SCL1(3,4) ― TX1 CLC3OUT ― ― ― ―
― ― ― ― ― ― ― ― PWM6OUT CWG1D SDA1(3,4) ― ― CLC4OUT ― ― ― ―
Note 1: This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx pins.
2: All digital output signals shown in this row are PPS re-mappable. These signals may be mapped to output onto one of several PORTx pin options.
3: This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and PPS output registers.
4: These pins are configured for I2C logic levels. PPS assignments to the other pins will operate, but input logic levels will be standard TTL/ST as selected by the INLVL register, instead of the I2C
specific or SMBUS input buffer thresholds.
DS40001897A-page 6
 2017 Microchip Technology Inc.

TABLE 4: 14-Pin PDIP/SOIC/TSSOP 14/16-PIN ALLOCATION TABLE (PIC16(L)F15323)

16-Pin QFN/UQFN

Comparator
Reference

EUSART

Interrupt

Pull-up
Timers

MSSP

CLKR

Basic
PWM

CWG
I/O(2)

NCO
ADC

DAC

CCP

ZCD

CLC
RA0 13 12 ANA0 ― C1IN0+ ― DAC1OUT ― ― ― ― ― ― ― ― ― IOCA0 Y ICSPDAT
RA1 12 11 ANA1 VREF+ C1IN0- ― DAC1REF+ T0CKI(1) ― ― ― ― ― ― ― ― IOCA1 Y ICSPCLK
C2IN0-
RA2 11 10 ANA2 ― ― ― ― ― ― ― CWG1IN(1) ― ZCD1 ― ― ― INT(1) Y ―
IOCA2
RA3 4 3 ― ― ― ― ― ― ― ― ― ― ― ― ― ― IOCA3 Y MCLR
VPP
RA4 3 2 ANA4 ― ― ― ― T1G(1) ― ― ― ― ― ― ― ― IOCA4 Y CLKOUT
OSC2
Preliminary

RA5 2 1 ANA5 ― ― ― ― T1CKI(1) ― ― ― ― ― CLCIN3(1) ― IOCA5 Y CLKIN

T2IN OSC1
EIN
RC0 10 9 ANC0 ― C2IN0+ ― ― ― ― ― ― SCK1(1) ― TX2(1) ― ― IOCC0 Y ―
SCL1(1,4) CK2(1)
RC1 9 8 ANC1 ― C1IN1- ― ― ― ― ― ― SDA1(1,4) ― RX2(1) CLCIN2(1) ― IOCC1 Y ―
C2IN1- SDI1(1) DT2(1)
RC2 8 7 ANC2 ― C1IN2- ― ― ― ― ― ― ― ― ― ― ― IOCC2 Y ―

PIC16(L)F15313/23
C2IN2-
RC3 7 6 ANC3 ― C1IN3- ― ― ― CCP2(1) ― ― SS1(1) ― ― CLCIN0(1) ― IOCC3 Y ―
C2IN3-
RC4 6 5 ANC4 ― ― ― ― ― ― ― ― ― ― TX1(1) CLCIN1(1) ― IOCC4 Y ―
CK1(1)
RC5 5 4 ANC5 ― ― ― ― ― CCP1(1) ― ― ― ― RX1(1) ― ― IOCC5 Y ―
DT1(1)
VDD 1 16 ― ― ― ― ― ― ― ― ― ― ― ― ― ― ― ― VDD
VSS 14 13 ― ― ― ― ― ― ― ― ― ― ― ― ― ― ― ― VSS
Note 1: This is a PPS re-mappable input signal. The input function may be moved from the default location shown to one of several other PORTx pins.
2: All digital output signals shown in this row are PPS re-mappable. These signals may be mapped to output onto one of several PORTx pin options.
DS40001897A-page 7

3: This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and PPS output registers.
4: These pins are configured for I2C logic levels. PPS assignments to the other pins will operate, but input logic levels will be standard TTL/ST as selected by the INLVL register, instead of the I2C specific or
SMBUS input buffer thresholds.
 TABLE 4: 14/16-PIN ALLOCATION TABLE (PIC16(L)F15323) (CONTINUED)
 2017 Microchip Technology Inc.

14-Pin PDIP/SOIC/TSSOP

16-Pin QFN/UQFN

Comparator
Reference

EUSART

Interrupt

Pull-up
Timers

MSSP

CLKR

Basic
PWM

CWG
I/O(2)

NCO
ADC

DAC

CCP

ZCD

CLC
OUT(2) ― ― ― ― C1OUT NCO1OUT ― TMR0 CCP1 PWM3OUT CWG1A SDO1 ― DT1(3) CLC1OUT CLKR ― ― ―
― ― ― ― C2OUT ― ― ― CCP2 PWM4OUT CWG1B SCK1 ― CK1 CLC2OUT ― ― ― ―
― ― ― ― ― ― ― ― ― PWM5OUT CWG1C SCL1(3,4) ― TX1 CLC3OUT ― ― ― ―
― ― ― ― ― ― ― ― ― PWM6OUT CWG1D SDA1(3,4) ― DT2(3) CLC4OUT ― ― ― ―
CK2
TX2
Note 1: This is a PPS re-mappable input signal. The input function may be moved from the default location shown to one of several other PORTx pins.
2: All digital output signals shown in this row are PPS re-mappable. These signals may be mapped to output onto one of several PORTx pin options.
3: This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and PPS output registers.
4: These pins are configured for I2C logic levels. PPS assignments to the other pins will operate, but input logic levels will be standard TTL/ST as selected by the INLVL register, instead of the I2C specific or
Preliminary

SMBUS input buffer thresholds.

PIC16(L)F15313/23
DS40001897A-page 8
 PIC16(L)F15313/23
Table of Contents
1.0 Device Overview ........................................................................................................................................................................ 11
2.0 Guidelines for Getting Started with PIC16(L)F15313/23 Microcontrollers.................................................................................. 22
3.0 Enhanced Mid-Range CPU ........................................................................................................................................................ 25
4.0 Memory Organization ................................................................................................................................................................. 27
5.0 Device Configuration .................................................................................................................................................................. 75
6.0 Device Information Area............................................................................................................................................................. 86
7.0 Device Configuration Information ............................................................................................................................................... 88
8.0 Resets ........................................................................................................................................................................................ 89
9.0 Oscillator Module (with Fail-Safe Clock Monitor) ..................................................................................................................... 100
10.0 Interrupts .................................................................................................................................................................................. 117
11.0 Power-Saving Operation Modes .............................................................................................................................................. 139
12.0 Windowed Watchdog Timer (WWDT) ...................................................................................................................................... 146
13.0 Nonvolatile Memory (NVM) Control.......................................................................................................................................... 154
14.0 I/O Ports ................................................................................................................................................................................... 172
15.0 Peripheral Pin Select (PPS) Module ........................................................................................................................................ 185
16.0 Peripheral Module Disable ....................................................................................................................................................... 194
17.0 Interrupt-On-Change ................................................................................................................................................................ 202
18.0 Fixed Voltage Reference (FVR) .............................................................................................................................................. 209
19.0 Temperature Indicator Module ................................................................................................................................................. 212
20.0 Analog-to-Digital Converter (ADC) Module .............................................................................................................................. 215
21.0 5-Bit Digital-to-Analog Converter (DAC1) Module.................................................................................................................... 229
22.0 Numerically Controlled Oscillator (NCO) Module ..................................................................................................................... 234
23.0 Comparator Module.................................................................................................................................................................. 244
24.0 Zero-Cross Detection (ZCD) Module........................................................................................................................................ 254
25.0 Timer0 Module ......................................................................................................................................................................... 260
26.0 Timer1 Module with Gate Control............................................................................................................................................. 266
27.0 Timer2 Module With Hardware Limit Timer (HLT).................................................................................................................... 279
28.0 Capture/Compare/PWM Modules ............................................................................................................................................ 299
29.0 Pulse-Width Modulation (PWM) ............................................................................................................................................... 311
30.0 Complementary Waveform Generator (CWG) Module ............................................................................................................ 318
31.0 Configurable Logic Cell (CLC).................................................................................................................................................. 343
32.0 Master Synchronous Serial Port (MSSP1) Module .................................................................................................................. 360
33.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ............................................................... 411
34.0 Reference Clock Output Module .............................................................................................................................................. 439
35.0 In-Circuit Serial Programming™ (ICSP™) ............................................................................................................................... 443
36.0 Instruction Set Summary .......................................................................................................................................................... 445
37.0 Electrical Specifications............................................................................................................................................................ 458
38.0 DC and AC Characteristics Graphs and Charts ....................................................................................................................... 487
39.0 Development Support............................................................................................................................................................... 488
40.0 Packaging Information.............................................................................................................................................................. 492

 2017 Microchip Technology Inc. Preliminary DS40001897A-page 9

 PIC16(L)F15313/23

TO OUR VALUED CUSTOMERS

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Most Current Data Sheet

To obtain the most up-to-date version of this data sheet, please register at our Worldwide Website at:
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You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).

Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
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When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
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 2017 Microchip Technology Inc. Preliminary DS40001897A-page 10

 PIC16(L)F15313/23
1.0 DEVICE OVERVIEW
TABLE 1-1: DEVICE PERIPHERAL
The PIC16(L)F15313/23 are described within this data
SUMMARY
sheet. The PIC16(L)F15313/23 devices are available in

PIC16(L)F15313
PIC16(L)F15323
8/14-pin PDIP, SSOP, SOIC, DFN, and UQFN
packages. Figure 1-1 and Figure 1-2 shows the block
diagrams of the PIC16(L)F15313/23 devices. Table 1-2 Peripheral
and Table 1-3 shows the pinout descriptions.
Reference Table 1-1 for peripherals available per device.
Analog-to-Digital Converter ● ●
Digital-to-Analog Converter (DAC1) ● ●
Fixed Voltage Reference (FVR) ● ●
Numerically Controlled Oscillator (NCO1) ● ●
Temperature Indicator Module (TIM) ● ●
Zero-Cross Detect (ZCD1) ● ●
Capture/Compare/PWM Modules (CCP)
CCP1 ● ●
CCP2 ● ●
Comparator Module (Cx)
C1 ● ●
C2 ●
Configurable Logic Cell (CLC)
CLC1 ● ●
CLC2 ● ●
CLC3 ● ●
CLC4 ● ●
Complementary Waveform Generator (CWG)
CWG1 ● ●
Enhanced Universal Synchronous/Asynchronous
Receiver/Transmitter (EUSART)
EUSART1 ● ●
Master Synchronous Serial Ports (MSSP)
MSSP1 ● ●
Pulse-Width Modulator (PWM)
PWM3 ● ●
PWM4 ● ●
PWM5 ● ●
PWM6 ● ●
Timers
Timer0 ● ●
Timer1 ● ●
Timer2 ● ●

 2017 Microchip Technology Inc. Preliminary DS40001897A-page 11

 PIC16(L)F15313/23
1.1 Register and Bit Naming 1.1.2.3 Bit Fields
Conventions Bit fields are two or more adjacent bits in the same
register. Bit fields adhere only to the short bit naming
1.1.1 REGISTER NAMES convention. For example, the three Least Significant
When there are multiple instances of the same bits of the COG1CON0 register contain the mode
peripheral in a device, the peripheral control registers control bits. The short name for this field is MD. There
will be depicted as the concatenation of a peripheral is no long bit name variant. Bit field access is only
identifier, peripheral instance, and control identifier. possible in C programs. The following example
The control registers section will show just one demonstrates a C program instruction for setting the
instance of all the register names with an ‘x’ in the place COG1 to the Push-Pull mode:
of the peripheral instance number. This naming COG1CON0bits.MD = 0x5;
convention may also be applied to peripherals when
Individual bits in a bit field can also be accessed with
there is only one instance of that peripheral in the
long and short bit names. Each bit is the field name
device to maintain compatibility with other devices in
appended with the number of the bit position within the
the family that contain more than one.
field. For example, the Most Significant mode bit has
1.1.2 BIT NAMES the short bit name MD2 and the long bit name is
G1MD2. The following two examples demonstrate
There are two variants for bit names: assembly program sequences for setting the COG1 to
• Short name: Bit function abbreviation Push-Pull mode:
• Long name: Peripheral abbreviation + short name Example 1:
MOVLW ~(1<<G1MD1)
1.1.2.1 Short Bit Names ANDWF COG1CON0,F
Short bit names are an abbreviation for the bit function. MOVLW 1<<G1MD2 | 1<<G1MD0
For example, some peripherals are enabled with the IORWF COG1CON0,F
EN bit. The bit names shown in the registers are the Example 2:
short name variant.
BSF COG1CON0,G1MD2
Short bit names are useful when accessing bits in C BCF COG1CON0,G1MD1
programs. The general format for accessing bits by the BSF COG1CON0,G1MD0
short name is RegisterNamebits.ShortName. For
example, the enable bit, EN, in the COG1CON0 regis- 1.1.3 REGISTER AND BIT NAMING
ter can be set in C programs with the instruction EXCEPTIONS
COG1CON0bits.EN = 1.
1.1.3.1 Status, Interrupt, and Mirror Bits
Short names are generally not useful in assembly
programs because the same name may be used by Status, interrupt enables, interrupt flags, and mirror bits
different peripherals in different bit positions. When this are contained in registers that span more than one
occurs, during the include file generation, all instances peripheral. In these cases, the bit name shown is
of that short bit name are appended with an underscore unique so there is no prefix or short name variant.
plus the name of the register in which the bit resides to
avoid naming contentions. 1.1.3.2 Legacy Peripherals
There are some peripherals that do not strictly adhere
1.1.2.2 Long Bit Names to these naming conventions. Peripherals that have
Long bit names are constructed by adding a peripheral existed for many years and are present in almost every
abbreviation prefix to the short name. The prefix is device are the exceptions. These exceptions were
unique to the peripheral thereby making every long bit necessary to limit the adverse impact of the new
name unique. The long bit name for the COG1 enable conventions on legacy code. Peripherals that do
bit is the COG1 prefix, G1, appended with the enable adhere to the new convention will include a table in the
bit short name, EN, resulting in the unique bit name registers section indicating the long name prefix for
G1EN. each peripheral instance. Peripherals that fall into the
exception category will not have this table. These
Long bit names are useful in both C and assembly pro-
peripherals include, but are not limited to, the following:
grams. For example, in C the COG1CON0 enable bit
can be set with the G1EN = 1 instruction. In assembly, • EUSART
this bit can be set with the BSF COG1CON0,G1EN • MSSP
instruction.

 2017 Microchip Technology Inc. Preliminary DS40001897A-page 12

 2017 Microchip Technology Inc.

FIGURE 1-1: PIC16(L)F15313 BLOCK DIAGRAM

Rev. 10-000039T
Program 1/13/2017

Flash Memory
RAM

PORTA
Timing
Generation

CLKOUT
EXTOSC
CLKIN Oscillator
CPU

(Note 3)
Preliminary

MCLR

ADC

PIC16(L)F15313/23
PWM6 PWM5 PWM4 PWM3 Timer2 Timer1 Timer0 C1 TIM DAC FVR
10-bit

CWG1 NCO1 EUSART1 MSSP1 CLC4 CLC3 CLC2 CLC1 ZCD1 CCP1 CCP2
DS40001897A-page 13

Note 1: See applicable chapters for more information on peripherals.

2: See Table 1-1 for peripherals available on specific devices.
3: See Figure 3-1.
 2017 Microchip Technology Inc.

FIGURE 1-2: PIC16(L)F15323 BLOCK DIAGRAM

Rev. 10-000039U
Program 1/13/2017

Flash Memory
RAM

PORTA
Timing
Generation

CLKOUT
EXTOSC PORTC
CLKIN Oscillator
CPU

(Note 3)
Preliminary

MCLR

ADC

PIC16(L)F15313/23
PWM6 PWM5 PWM4 PWM3 Timer2 Timer1 Timer0 C2 C1 TIM DAC FVR
10-bit

CWG1 NCO1 EUSART1 MSSP1 CLC4 CLC3 CLC2 CLC1 ZCD1 CCP1 CCP2
DS40001897A-page 14

Note 1: See applicable chapters for more information on peripherals.

2: See Table 1-1 for peripherals available on specific devices.
3: See Figure 3-1.
 PIC16(L)F15313/23

TABLE 1-2: PIC16(L)F15313 PINOUT DESCRIPTION

Input
Name Function Output Type Description
Type

RA0/ANA0/C1IN0+/DAC1OUT/TX1/ RA0 TTL/ST CMOS/OD General purpose I/O.

CK1(1)/CLCIN3(1)/ICSPDAT/IOCA0
ANA0 AN — ADC Channel A0 input.

C1IN0+ AN — Comparator 1 positive input.

DAC1OUT — AN Digital-to-Analog Converter output.

TX1 — CMOS EUSART1 asynchronous transmit.

(1)
CK1 TTL/ST CMOS/OD EUSART1 synchronous mode clock input/output.

CLCIN3(1) TTL/ST — Configurable Logic Cell source input.

In-Circuit Serial Programming™ and debugging data input/
ICSPDAT ST CMOS
output.
IOCA0 TTL/ST — Interrupt-on-change input.
RA1/ANA1/VREF+/C1IN0-/DAC1REF+/ RA1 TTL/ST CMOS/OD General purpose I/O.
T0CKI(1)/SCK1(4)/SCL1(1,4)/RX1/
DT1(1)/CLCIN2(1)/ICSPCLK/IOCA1 ANA1 AN — ADC Channel A1 input.

VREF+ AN — External ADC and/or DAC positive reference input.

C1IN0- AN — Comparator 1 negative input.

DAC1REF+ TTL/ST AN DAC positive reference.

(1)
T0CKI TTL/ST — Timer0 clock input.
2
SCK1 (4)
I C OD I2C, OD, MSSP1 I2C input/output.
MSSP1 SPI clock input/output (default input location, SCK1
SCL1(1,4) TTL/ST CMOS/OD
is a PPS remappable input and output).
RX1 TTL/ST — EUSART1 Asynchronous mode receiver data input.
(1)
DT1 TTL/ST CMOS/OD EUSART1 Synchronous mode data input/output.
(1)
CLCIN2 TTL/ST — Configurable Logic Cell source input.

ICSPCLK ST — In-Circuit Serial Programming™ and debugging clock input.

IOCA1 TTL/ST — Interrupt-on-change input.

RA2/ANA2/CWG1IN(1)/SDA1(1,4)/ RA2 TTL/ST CMOS/OD General purpose I/O.
SDI1(1)/ZCD1/INT(1)/IOCA2
ANA2 AN — ADC Channel A2 input.

CWG1IN(1) TTL/ST — Complementary Waveform Generator 1 input.

SDA1(1,4) I2C OD MSSP1 I2C serial data input/output.

SDI1(1) TTL/ST — MSSP1 SPI serial data input.

Zero-cross detect input pin (with constant current sink/
ZCD1 AN AN
source).
INT(1) TTL/ST — External interrupt request input.

IOCA2 TTL/ST — Interrupt-on-change input.

Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open-Drain
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C
HV = High Voltage XTAL = Crystal levels
Note 1: This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx
pins. Refer to Table 15-3 for details on which PORT pins may be used for this signal.
2: All output signals shown in this row are PPS remappable. These signals may be mapped to output onto one of several PORTx pin
options as described in Table 15-3.
3: This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and
PPS output registers.
4: These pins are configured for I2C logic levels. The SCLx/SDAx signals may be assigned to any of the RB1/RB2/RC3/RC4 pins. PPS
assignments to the other pins (e.g., RA5) will operate, but input logic levels will be standard TTL/ST, as selected by the INLVL register,
instead of the I2C specific or SMBus input buffer thresholds.

 2017 Microchip Technology Inc. Preliminary DS40001897A-page 15

 PIC16(L)F15313/23
TABLE 1-2: PIC16(L)F15313 PINOUT DESCRIPTION (CONTINUED)
Input
Name Function Output Type Description
Type

RA3/SS1(1)/CLCIN0(1)/VPP/MCLR/ RA3 TTL/ST CMOS/OD General purpose I/O.

IOCA3
SS1(1) TTL/ST — MSSP1 SPI slave select input.

CLCIN0(1) TTL/ST — Configurable Logic Cell source input.

VPP HV — ICSP™ High-Voltage Programming mode entry input.

MCLR ST — Master clear input with internal weak pull up resistor.

IOCA3 TTL/ST — Interrupt-on-change input.

RA4/ANA4/C1IN1-/T1G(1)/CLKOUT/ RA4 TTL/ST CMOS/OD General purpose I/O.
OSC2/IOCA4
ANA4 AN — ADC Channel A4 input.

C1IN1- AN — Comparator 1 negative input.

(1)
T1G ST — Timer1 Gate input.

CLKOUT — CMOS/OD FOSC/4 digital output (in non-crystal/resonator modes).

External Crystal/Resonator (LP, XT, HS modes) driver out-
OSC2 — XTAL
put.
IOCA4 TTL/ST — Interrupt-on-change input.
RA5/ANA5/ADACT(1)/T1CKI(1)/T2IN(1)/ RA5 TTL/ST CMOS/OD General purpose I/O.
CCP1(1)/CCP2(1)/CLCIN1(1)/CLKIN/
OSC1/EIN/IOCA5 ANA5 AN — ADC Channel A5 input.
(1)
ADACT TTL/ST — ADC Auto-Conversion Trigger input.

T1CKI(1) TTL/ST — Timer1 external digital clock input.

T2IN(1) TTL/ST — Timer2 external input.

Capture/compare/PWM1 (default input location for capture
CCP1(1) TTL/ST CMOS/OD
function).
Capture/compare/PWM2 (default input location for capture
CCP2(1) TTL/ST CMOS/OD
function).
CLCIN1(1) TTL/ST — Configurable Logic Cell source input.

CLKIN TTL/ST — External digital clock input.

OSC1 XTAL — External Crystal/Resonator (LP, XT, HS modes) driver input.

EIN TTL/ST — External digital clock input.

IOCA5 TTL/ST — Interrupt-on-change input.

VDD VDD Power — Positive supply voltage input.
VSS VSS Power — Ground reference.
Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open-Drain
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C
HV = High Voltage XTAL = Crystal levels
Note 1: This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx
pins. Refer to Table 15-3 for details on which PORT pins may be used for this signal.
2: All output signals shown in this row are PPS remappable. These signals may be mapped to output onto one of several PORTx pin
options as described in Table 15-3.
3: This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and
PPS output registers.
4: These pins are configured for I2C logic levels. The SCLx/SDAx signals may be assigned to any of the RB1/RB2/RC3/RC4 pins. PPS
assignments to the other pins (e.g., RA5) will operate, but input logic levels will be standard TTL/ST, as selected by the INLVL register,
instead of the I2C specific or SMBus input buffer thresholds.

 2017 Microchip Technology Inc. Preliminary DS40001897A-page 16

 PIC16(L)F15313/23
TABLE 1-2: PIC16(L)F15313 PINOUT DESCRIPTION (CONTINUED)
Input
Name Function Output Type Description
Type

OUT(2) C1OUT — CMOS/OD Comparator 1 output.

SDO1 — CMOS/OD MSSP1 SPI serial data output.

SCK1 — CMOS/OD MSSP1 SPI serial clock output.

(3)
DT1 — CMOS/OD EUSART Synchronous mode data output.

TX1 — CMOS/OD EUSART1 Asynchronous mode transmitter data output.

CK1 — CMOS/OD EUSART1 Synchronous mode clock output.

SCL1(3,4) — CMOS/OD MSSP1 I2C output.

SDA1(3,4) — CMOS/OD MSSP1 I2C output.

TMR0 — CMOS/OD Timer0 output.

CCP1 — CMOS/OD CCP1 output (compare/PWM functions).

CCP2 — CMOS/OD CCP2 output (compare/PWM functions).

PWM3OUT — CMOS/OD PWM3 output.

PWM4OUT — CMOS/OD PWM4 output.

PWM5OUT — CMOS/OD PWM5 output.

PWM6OUT — CMOS/OD PWM6 output.

CWG1A — CMOS/OD Complementary Waveform Generator 1 output A.

CWG1B — CMOS/OD Complementary Waveform Generator 1 output B.

CWG1C — CMOS/OD Complementary Waveform Generator 1 output C.

CWG1D — CMOS/OD Complementary Waveform Generator 1 output D.

CLC1OUT — CMOS/OD Configurable Logic Cell 1 output.

CLC2OUT — CMOS/OD Configurable Logic Cell 2 output.

CLC3OUT — CMOS/OD Configurable Logic Cell 3 output.

CLC4OUT — CMOS/OD Configurable Logic Cell 4 output.

NCO1OUT — CMOS/OD Numerically Controller Oscillator output.

CLKR — CMOS/OD Clock Reference module output.

Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open-Drain
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C
HV = High Voltage XTAL = Crystal levels
Note 1: This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx
pins. Refer to Table 15-3 for details on which PORT pins may be used for this signal.
2: All output signals shown in this row are PPS remappable. These signals may be mapped to output onto one of several PORTx pin
options as described in Table 15-3.
3: This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and
PPS output registers.
4: These pins are configured for I2C logic levels. The SCLx/SDAx signals may be assigned to any of the RB1/RB2/RC3/RC4 pins. PPS
assignments to the other pins (e.g., RA5) will operate, but input logic levels will be standard TTL/ST, as selected by the INLVL register,
instead of the I2C specific or SMBus input buffer thresholds.

 2017 Microchip Technology Inc. Preliminary DS40001897A-page 17

 PIC16(L)F15313/23

TABLE 1-3: PIC16(L)F15323 PINOUT DESCRIPTION

Input
Name Function Output Type Description
Type

RA0/ANA0/C1IN0+/DAC1OUT/ RA0 TTL/ST CMOS/OD General purpose I/O.

ICSPDAT/IOCA0
ANA0 AN — ADC Channel A0 input.

C1IN0+ AN — Comparator 1 positive input.

DAC1OUT — AN Digital-to-Analog Converter output.

In-Circuit Serial Programming™ and debugging data input/
ICSPDAT ST CMOS
output.
IOCA0 TTL/ST — Interrupt-on-change input.
RA1/ANA1/VREF+/C1IN0-/C2IN0-/ RA1 TTL/ST CMOS/OD General purpose I/O.
DAC1REF+/T0CKI(1)/ICSPCLK/IOCA1
ANA1 AN — ADC Channel A1 input.

VREF+ AN — External ADC and/or DAC positive reference input.

C1IN0- AN — Comparator 1 negative input.

C2IN0- AN — Comparator 2 negative input.

DAC1REF+ TTL/ST AN DAC positive reference.

T0CKI(1) TTL/ST — Timer0 clock input.

ICSPCLK ST — In-Circuit Serial Programming™ and debugging clock input.

IOCA1 TTL/ST — Interrupt-on-change input.

RA2/ANA2/CWG1IN(1)/ZCD1/INT(1)/ RA2 TTL/ST CMOS/OD General purpose I/O.
IOCA2
ANA2 AN — ADC Channel A2 input.

CWG1IN(1) TTL/ST — Complementary Waveform Generator 1 input.

Zero-cross detect input pin (with constant current sink/
ZCD1 AN AN
source).
INT(1) TTL/ST — External interrupt request input.

IOCA2 TTL/ST — Interrupt-on-change input.

RA3/MCLR/VPP/IOCA3 RA3 TTL/ST CMOS/OD General purpose I/O.

MCLR ST — Master clear input with internal weak pull up resistor.

VPP HV — ICSP™ High-Voltage Programming mode entry input.

IOCA3 TTL/ST — Interrupt-on-change input.

RA4/ANA4/T1G(1)/CLKOUT/OSC2/ RA4 TTL/ST CMOS/OD General purpose I/O.
IOCA4
ANA4 AN — ADC Channel A4 input.
(1)
T1G ST — Timer1 Gate input.

CLKOUT — CMOS/OD FOSC/4 digital output (in non-crystal/resonator modes).

External Crystal/Resonator (LP, XT, HS modes) driver out-
OSC2 — XTAL
put.
IOCA4 TTL/ST — Interrupt-on-change input.
Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open-Drain
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C
HV = High Voltage XTAL = Crystal levels
Note 1: This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx
pins. Refer to Table 15-3 for details on which PORT pins may be used for this signal.
2: All output signals shown in this row are PPS remappable. These signals may be mapped to output onto one of several PORTx pin
options as described in Table 15-3.
3: This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and
PPS output registers.
4: These pins are configured for I2C logic levels. The SCLx/SDAx signals may be assigned to any of the RB1/RB2/RC3/RC4 pins. PPS
assignments to the other pins (e.g., RA5) will operate, but input logic levels will be standard TTL/ST, as selected by the INLVL register,
instead of the I2C specific or SMBus input buffer thresholds.

 2017 Microchip Technology Inc. Preliminary DS40001897A-page 18

 PIC16(L)F15313/23
TABLE 1-3: PIC16(L)F15323 PINOUT DESCRIPTION (CONTINUED)
Input
Name Function Output Type Description
Type

RA5/ANA5/T1CKI(1)/T2IN/CLCIN3(1)/ RA5 TTL/ST CMOS/OD General purpose I/O.

CLKIN/OSC1/EIN/IOCA5
ANA5 AN — ADC Channel A5 input.

T1CKI(1) TTL/ST — Timer1 external digital clock input.

T2IN TTL/ST — Timer2 external input.

CLCIN3(1) TTL/ST — Configurable Logic Cell source input.

CLKIN TTL/ST — External digital clock input.

OSC1 XTAL — External Crystal/Resonator (LP, XT, HS modes) driver input.

EIN TTL/ST — External digital clock input.

IOCA5 TTL/ST — Interrupt-on-change input.

RC0/ANC0/C2IN0+/SCL1(1,4)/SCK1(1)/ RC0 TTL/ST CMOS/OD General purpose I/O.
IOCC0
ANC0 AN — ADC Channel C0 input.

C2IN0+ AN — Comparator 2 positive input.

SCL1(1,4) I2C OD I2C, OD, MSSP1 I2C input/output.

MSSP1 SPI clock input/output (default input location, SCK1
SCK1(1) TTL/ST CMOS/OD
is a PPS remappable input and output).
IOCC0 TTL/ST — Interrupt-on-change input.
RC1/ANC1/C1IN1-/C2IN1-/SDA1(1,4)/ RC1 TTL/ST CMOS/OD General purpose I/O.
SDI1(1)/CLCIN2(1)/IOCC1
ANC1 AN — ADC Channel C1 input.

C1IN1- AN — Comparator 1 negative input.

C2IN1- AN — Comparator 2 negative input.

SDA1(1,4) I2C OD MSSP1 I2C serial data input/output.

SDI1(1) TTL/ST — MSSP1 SPI serial data input.

CLCIN2(1) TTL/ST — Configurable Logic Cell source input.

IOCC1 TTL/ST — Interrupt-on-change input.

RC2/ANC2/C1IN2-/C2IN2-/IOCC2 RC2 TTL/ST CMOS/OD General purpose I/O.

ANC2 AN — ADC Channel C2 input.

C1IN2- AN — Comparator 1 negative input.

C2IN2- AN — Comparator 2 negative input.

IOCC2 TTL/ST — Interrupt-on-change input.

Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open-Drain
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C
HV = High Voltage XTAL = Crystal levels
Note 1: This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx
pins. Refer to Table 15-3 for details on which PORT pins may be used for this signal.
2: All output signals shown in this row are PPS remappable. These signals may be mapped to output onto one of several PORTx pin
options as described in Table 15-3.
3: This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and
PPS output registers.
4: These pins are configured for I2C logic levels. The SCLx/SDAx signals may be assigned to any of the RB1/RB2/RC3/RC4 pins. PPS
assignments to the other pins (e.g., RA5) will operate, but input logic levels will be standard TTL/ST, as selected by the INLVL register,
instead of the I2C specific or SMBus input buffer thresholds.

 2017 Microchip Technology Inc. Preliminary DS40001897A-page 19

 PIC16(L)F15313/23
TABLE 1-3: PIC16(L)F15323 PINOUT DESCRIPTION (CONTINUED)
Input
Name Function Output Type Description
Type

RC3/ANC3/C1IN3-/C2IN3-/CCP2(1)/ RC3 TTL/ST CMOS/OD General purpose I/O.

SS1(1)/CLCIN0(1)/IOCC3
ANC3 AN — ADC Channel C3 input.

C1IN3- AN — Comparator 1 positive input.

C2IN3- AN — Comparator 2 positive input.

Capture/compare/PWM2 (default input location for capture
CCP2(1) TTL/ST CMOS/OD
function).
SS1(1) TTL/ST — MSSP1 SPI slave select input.

CLCIN0(1) TTL/ST — Configurable Logic Cell source input.

IOCC3 TTL/ST — Interrupt-on-change input.

RC4/ANC4/TX1(1)/CK1(1)/CLCIN1(1)/ RC4 TTL/ST CMOS/OD General purpose I/O.
IOCC4
ANC4 AN — ADC Channel C4 input.

TX1 — CMOS EUSART1 asynchronous transmit.

(1)
CLCIN1 TTL/ST — Configurable Logic Cell source input.

CK1(1) TTL/ST CMOS/OD EUSART1 synchronous mode clock input/output.

IOCC4 TTL/ST — Interrupt-on-change input.

RC5/ANC5/CCP1(1)/RX1(1)/DT1(1)/ RC5 TTL/ST CMOS/OD General purpose I/O.
IOCC5
ANC5 AN — ADC Channel C5 input.
Capture/compare/PWM1 (default input location for capture
CCP1(1) TTL/ST CMOS/OD
function).
RX1(1) TTL/ST — EUSART1 Asynchronous mode receiver data input.
DT1(1) TTL/ST CMOS/OD EUSART1 Synchronous mode data input/output.

IOCC5 TTL/ST — Interrupt-on-change input.

VDD VDD Power — Positive supply voltage input.
VSS VSS Power — Ground reference.
Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open-Drain
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C
HV = High Voltage XTAL = Crystal levels
Note 1: This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx
pins. Refer to Table 15-3 for details on which PORT pins may be used for this signal.
2: All output signals shown in this row are PPS remappable. These signals may be mapped to output onto one of several PORTx pin
options as described in Table 15-3.
3: This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and
PPS output registers.
4: These pins are configured for I2C logic levels. The SCLx/SDAx signals may be assigned to any of the RB1/RB2/RC3/RC4 pins. PPS
assignments to the other pins (e.g., RA5) will operate, but input logic levels will be standard TTL/ST, as selected by the INLVL register,
instead of the I2C specific or SMBus input buffer thresholds.

 2017 Microchip Technology Inc. Preliminary DS40001897A-page 20

 PIC16(L)F15313/23
TABLE 1-3: PIC16(L)F15323 PINOUT DESCRIPTION (CONTINUED)
Input
Name Function Output Type Description
Type

OUT(2) C1OUT — CMOS/OD Comparator 1 output.

C2OUT — CMOS/OD Comparator 2 output.

SDO1 — CMOS/OD MSSP1 SPI serial data output.

SCK1 — CMOS/OD MSSP1 SPI serial clock output.

DT1(3) — CMOS/OD EUSART Synchronous mode data output.

TX1 — CMOS/OD EUSART1 Asynchronous mode transmitter data output.

CK1 — CMOS/OD EUSART1 Synchronous mode clock output.

SCL1 (3,4) — CMOS/OD MSSP1 I2C output.

SDA1(3,4) — CMOS/OD MSSP1 I2C output.

TMR0 — CMOS/OD Timer0 output.

CCP1 — CMOS/OD CCP1 output (compare/PWM functions).

CCP2 — CMOS/OD CCP2 output (compare/PWM functions).

PWM3OUT — CMOS/OD PWM3 output.

PWM4OUT — CMOS/OD PWM4 output.

PWM5OUT — CMOS/OD PWM5 output.

PWM6OUT — CMOS/OD PWM6 output.

CWG1A — CMOS/OD Complementary Waveform Generator 1 output A.

CWG1B — CMOS/OD Complementary Waveform Generator 1 output B.

CWG1C — CMOS/OD Complementary Waveform Generator 1 output C.

CWG1D — CMOS/OD Complementary Waveform Generator 1 output D.

CLC1OUT — CMOS/OD Configurable Logic Cell 1 output.

CLC2OUT — CMOS/OD Configurable Logic Cell 2 output.

CLC3OUT — CMOS/OD Configurable Logic Cell 3 output.

CLC4OUT — CMOS/OD Configurable Logic Cell 4 output.

NCO1OUT — CMOS/OD Numerically Controller Oscillator output.

CLKR — CMOS/OD Clock Reference module output.

Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open-Drain
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C
HV = High Voltage XTAL = Crystal levels
Note 1: This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx
pins. Refer to Table 15-3 for details on which PORT pins may be used for this signal.
2: All output signals shown in this row are PPS remappable. These signals may be mapped to output onto one of several PORTx pin
options as described in Table 15-3.
3: This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and
PPS output registers.
4: These pins are configured for I2C logic levels. The SCLx/SDAx signals may be assigned to any of the RB1/RB2/RC3/RC4 pins. PPS
assignments to the other pins (e.g., RA5) will operate, but input logic levels will be standard TTL/ST, as selected by the INLVL register,
instead of the I2C specific or SMBus input buffer thresholds.

 2017 Microchip Technology Inc. Preliminary DS40001897A-page 21

 PIC16(L)F15313/23
2.0 GUIDELINES FOR GETTING 2.2 Power Supply Pins
STARTED WITH
2.2.1 DECOUPLING CAPACITORS
PIC16(L)F15313/23
The use of decoupling capacitors on every pair of
MICROCONTROLLERS power supply pins (VDD and VSS) is required.
Consider the following criteria when using decoupling
2.1 Basic Connection Requirements
capacitors:
Getting started with the PIC16(L)F15313/23 family of 8- • Value and type of capacitor: A 0.1 F (100 nF),
bit microcontrollers requires attention to a minimal set 10-25V capacitor is recommended. The capacitor
of device pin connections before proceeding with should be a low-ESR device, with a resonance
development. frequency in the range of 200 MHz and higher.
The following pins must always be connected: Ceramic capacitors are recommended.
• All VDD and VSS pins • Placement on the printed circuit board: The
(see Section 2.2 “Power Supply Pins”) decoupling capacitors should be placed as close
to the pins as possible. It is recommended to
• MCLR pin
place the capacitors on the same side of the
(see Section 2.3 “Master Clear (MCLR) Pin”)
board as the device. If space is constricted, the
These pins must also be connected if they are being capacitor can be placed on another layer on the
used in the end application: PCB using a via; however, ensure that the trace
• ICSPCLK/ICSPDAT pins used for In-Circuit Serial length from the pin to the capacitor is no greater
Programming™ (ICSP™) and debugging purposes than 0.25 inch (6 mm).
(see Section 2.4 “ICSP™ Pins”) • Handling high-frequency noise: If the board is
• OSCI and OSCO pins when an external oscillator experiencing high-frequency noise (upward of
source is used tens of MHz), add a second ceramic type capaci-
(see Section 2.5 “External Oscillator Pins”) tor in parallel to the above described decoupling
capacitor. The value of the second capacitor can
Additionally, the following pins may be required:
be in the range of 0.01 F to 0.001 F. Place this
• VREF+/VREF- pins are used when external voltage second capacitor next to each primary decoupling
reference for analog modules is implemented capacitor. In high-speed circuit designs, consider
The minimum mandatory connections are shown in implementing a decade pair of capacitances as
Figure 2-1. close to the power and ground pins as possible
(e.g., 0.1 F in parallel with 0.001 F).
FIGURE 2-1: RECOMMENDED • Maximizing performance: On the board layout
MINIMUM CONNECTIONS from the power supply circuit, run the power and
return traces to the decoupling capacitors first,
and then to the device pins. This ensures that the
C2 decoupling capacitors are first in the power chain.
VDD Equally important is to keep the trace length
between the capacitor and the power pins to a
VDD

VSS

R1 minimum, thereby reducing PCB trace

R2 inductance.
MCLR
2.2.2 TANK CAPACITORS
C1
PIC16(L)F153xx On boards with power traces running longer than
six inches in length, it is suggested to use a tank capac-
VSS itor for integrated circuits, including microcontrollers, to
supply a local power source. The value of the tank
capacitor should be determined based on the trace
resistance that connects the power supply source to
the device, and the maximum current drawn by the
Key (all values are recommendations): device in the application. In other words, select the tank
C1: 10nF, 16V ceramic capacitor so that it meets the acceptable voltage sag at
C2: 0.1uF, 16V ceramic the device. Typical values range from 4.7 F to 47 F.
R1: 10 kΩ
R2: 100Ω to 470Ω

 2017 Microchip Technology Inc. Preliminary DS40001897A-page 22

 PIC16(L)F15313/23
2.3 Master Clear (MCLR) Pin 2.4 ICSP™ Pins
The MCLR pin provides two specific device The ICSPCLK and ICSPDAT pins are used for In-Cir-
functions: Device Reset, and Device Programming cuit Serial Programming™ (ICSP™) and debugging
and Debugging. If programming and debugging are purposes. It is recommended to keep the trace length
not required in the end application, a direct between the ICSP connector and the ICSP pins on the
connection to VDD may be all that is required. The device as short as possible. If the ICSP connector is
addition of other components, to help increase the expected to experience an ESD event, a series resistor
application’s resistance to spurious Resets from is recommended, with the value in the range of a few
voltage sags, may be beneficial. A typical tens of ohms, not to exceed 100Ω.
configuration is shown in Figure 2-1. Other circuit Pull-up resistors, series diodes and capacitors on the
designs may be implemented, depending on the ICSPCLK and ICSPDAT pins are not recommended as
application’s requirements. they will interfere with the programmer/debugger com-
During programming and debugging, the resistance munications to the device. If such discrete components
and capacitance that can be added to the pin must are an application requirement, they should be
be considered. Device programmers and debuggers removed from the circuit during programming and
drive the MCLR pin. Consequently, specific voltage debugging. Alternatively, refer to the AC/DC character-
levels (VIH and VIL) and fast signal transitions must istics and timing requirements information in the
not be adversely affected. Therefore, specific values respective device Flash programming specification for
of R1 and C1 will need to be adjusted based on the information on capacitive loading limits, and pin input
application and PCB requirements. For example, it is voltage high (VIH) and input low (VIL) requirements.
recommended that the capacitor, C1, be isolated For device emulation, ensure that the “Communication
from the MCLR pin during programming and Channel Select” (i.e., ICSPCLK/ICSPDAT pins),
debugging operations by using a jumper (Figure 2-2). programmed into the device, matches the physical
The jumper is replaced for normal run-time connections for the ICSP to the Microchip debugger/
operations. emulator tool.
Any components associated with the MCLR pin For more information on available Microchip
should be placed within 0.25 inch (6 mm) of the pin. development tools connection requirements, refer to
Section 39.0 “Development Support”.
FIGURE 2-2: EXAMPLE OF MCLR PIN
CONNECTIONS
VDD

R1
R2
MCLR

JP PIC16(L)F153xx

C1

Note 1: R1  10 k is recommended. A suggested

starting value is 10 k. Ensure that the
MCLR pin VIH and VIL specifications are met.
2: R2  470 will limit any current flowing into
MCLR from the external capacitor, C1, in the
event of MCLR pin breakdown, due to
Electrostatic Discharge (ESD) or Electrical
Overstress (EOS). Ensure that the MCLR pin
VIH and VIL specifications are met.

 2017 Microchip Technology Inc. Preliminary DS40001897A-page 23

 PIC16(L)F15313/23
2.5 External Oscillator Pins 2.6 Unused I/Os
Many microcontrollers have options for at least two Unused I/O pins should be configured as outputs and
oscillators: a high-frequency primary oscillator and a driven to a logic low state. Alternatively, connect a 1 kΩ
low-frequency secondary oscillator (refer to to 10 kΩ resistor to VSS on unused pins and drive the
Section 9.0 “Oscillator Module (with Fail-Safe output to logic low.
Clock Monitor)” for details). The PIC16(L)F15313/23
devices do not have a secondary oscillator. FIGURE 2-3: SUGGESTED
The oscillator circuit should be placed on the same PLACEMENT OF THE
side of the board as the device. Place the oscillator OSCILLATOR CIRCUIT
circuit close to the respective oscillator pins with no
Single-Sided and In-Line Layouts:
more than 0.5 inch (12 mm) between the circuit
components and the pins. The load capacitors should Copper Pour Primary Oscillator
be placed next to the oscillator itself, on the same side (tied to ground) Crystal
of the board. DEVICE PINS
Use a grounded copper pour around the oscillator cir-
cuit to isolate it from surrounding circuits. The
grounded copper pour should be routed directly to the
Primary OSC1
MCU ground. Do not run any signal traces or power Oscillator
traces inside the ground pour. Also, if using a two-sided C1 ` OSC2
board, avoid any traces on the other side of the board
where the crystal is placed. C2 GND
`
Layout suggestions are shown in Figure 2-3. In-line
SOSCO
packages may be handled with a single-sided layout
that completely encompasses the oscillator pins. With SOSCI
Secondary Oscillator
fine-pitch packages, it is not always possible to com- (SOSC)
pletely surround the pins and components. A suitable Crystal `
solution is to tie the broken guard sections to a mirrored
ground layer. In all cases, the guard trace(s) must be
SOSC: C1 SOSC: C2
returned to ground.
In planning the application’s routing and I/O assign-
ments, ensure that adjacent port pins, and other
signals in close proximity to the oscillator, are benign Fine-Pitch (Dual-Sided) Layouts:
(i.e., free of high frequencies, short rise and fall times, Top Layer Copper Pour
and other similar noise). (tied to ground)

For additional information and design guidance on

oscillator circuits, refer to these Microchip Application Bottom Layer
Copper Pour
Notes, available at the corporate website (tied to ground)
(www.microchip.com):
• AN826, “Crystal Oscillator Basics and Crystal OSCO
Selection for rfPIC™ and PICmicro® Devices”
• AN849, “Basic PICmicro® Oscillator Design” C2
Oscillator
• AN943, “Practical PICmicro® Oscillator Analysis GND Crystal
and Design”
C1
• AN949, “Making Your Oscillator Work”
OSCI

DEVICE PINS

 2017 Microchip Technology Inc. Preliminary DS40001897A-page 24

 PIC16(L)F15313/23
3.0 ENHANCED MID-RANGE CPU The hardware stack is 16-levels deep and has
Overflow and Underflow Reset capability. Direct,
This family of devices contains an enhanced mid-range Indirect, and Relative Addressing modes are available.
8-bit CPU core. The CPU has 48 instructions. Interrupt Two File Select Registers (FSRs) provide the ability to
capability includes automatic context saving. read program and data memory.

FIGURE 3-1: CORE DATA PATH DIAGRAM

Rev. 10-000055D
1/12/2017

15 Configuration
15 Data Bus 8
Program Counter

Flash
MUX

Program
Memory
16-Level Stack
RAM
(15-bit)

14
Program 12
Program Memory RAM Addr
Bus
Read (PMR)
Addr MUX
Instruction Reg
Indirect
Direct Addr 7 Addr
12
5 12

BSR Reg
15
FSR0 Reg

15 FSR1 Reg

STATUS Reg
8

3 MUX
Power-up
Instruction
Timer
Decode and
Power-on
Control
Reset ALU
8
Watchdog
CLKIN Timer
Timing Brown-out
CLKOUT Generation Reset W Reg

Internal
Oscillator VDD VSS
Block

 2017 Microchip Technology Inc. Preliminary DS40001897A-page 25

 PIC16(L)F15313/23
3.1 Automatic Interrupt Context
Saving
During interrupts, certain registers are automatically
saved in shadow registers and restored when returning
from the interrupt. This saves stack space and user
code. See Section 10.5 “Automatic Context Saving”
for more information.

3.2 16-Level Stack with Overflow and

Underflow
These devices have a hardware stack memory 15 bits
wide and 16 words deep. A Stack Overflow or
Underflow will set the appropriate bit (STKOVF or
STKUNF) in the PCON0 register, and if enabled, will
cause a software Reset. See Section 4.5 “Stack” for
more details.

3.3 File Select Registers

There are two 16-bit File Select Registers (FSR). FSRs
can access all file registers and program memory,
which allows one Data Pointer for all memory. When an
FSR points to program memory, there is one additional
instruction cycle in instructions using INDF to allow the
data to be fetched. General purpose memory can also
be addressed linearly, providing the ability to access
contiguous data larger than 80 bytes. See Section 4.6
“Indirect Addressing” for more details.

3.4 Instruction Set

There are 48 instructions for the enhanced mid-range
CPU to support the features of the CPU. See
Section 36.0 “Instruction Set Summary” for more
details.

 2017 Microchip Technology Inc. Preliminary DS40001897A-page 26

 PIC16(L)F15313/23
4.0 MEMORY ORGANIZATION 4.1 Program Memory Organization
These devices contain the following types of memory: The enhanced mid-range core has a 15-bit program
counter capable of addressing 32K x 14 program
• Program Memory
memory space. Table 4-1 shows the memory sizes
- Configuration Words implemented. The Reset vector is at 0000h and the
- Device ID interrupt vector is at 0004h (see Figure 4-1).
- User ID
- Program Flash Memory
- Device Information Area (DIA)
- Device Configuration Information (DCI)
- Revision ID
• Data Memory
- Core Registers
- Special Function Registers
- General Purpose RAM
- Common RAM
The following features are associated with access and
control of program memory and data memory:
• PCL and PCLATH
• Stack
• Indirect Addressing
• NVMREG access

TABLE 4-1: DEVICE SIZES AND ADDRESSES

Device Program Memory Size (Words) Last Program Memory Address
PIC16(L)F15313/23 2048 07FFh

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 PIC16(L)F15313/23
4.1.1 READING PROGRAM MEMORY AS
FIGURE 4-1: PROGRAM MEMORY MAP DATA
AND STACK FOR There are three methods of accessing constants in
PIC16(L)F15313/23 program memory. The first method is to use tables of
RETLW instructions. The second method is to set an
Rev. 10-000040C
7/30/2013 FSR to point to the program memory. The third method
is to use the NVMREG interface to access the program
PC<14:0> memory. For an example of NVMREG interface use,
CALL, CALLW reference Section 13.3, NVMREG Access.
RETURN, RETLW 15
Interrupt, RETFIE 4.1.1.1 RETLW Instruction
Stack Level 0 The RETLW instruction can be used to provide access
Stack Level 1 to tables of constants. The recommended way to create
such a table is shown in Example 4-1.

Stack Level 15 EXAMPLE 4-1: RETLW INSTRUCTION

constants
BRW ;Add Index in W to
Reset Vector 0000h ;program counter to
;select data
RETLW DATA0 ;Index0 data
RETLW DATA1 ;Index1 data
Interrupt Vector 0004h RETLW DATA2
On-chip 0005h RETLW DATA3
Program Page 0
Memory 07FFh
Rollover to Page 0 0800h my_function
;… LOTS OF CODE…
MOVLW DATA_INDEX
call constants
;… THE CONSTANT IS IN W

The BRW instruction makes this type of table very

simple to implement.

4.1.1.2 Indirect Read with FSR

The program memory can be accessed as data by
setting bit 7 of an FSRxH register and reading the
matching INDFx register. The MOVIW instruction will
Rollover to Page 0 7FFFh
place the lower eight bits of the addressed word in the
W register. Writes to the program memory cannot be
performed via the INDF registers. Instructions that read
the program memory via the FSR require one extra
instruction cycle to complete. Example 4-2
demonstrates reading the program memory via an
FSR.

 2017 Microchip Technology Inc. Preliminary DS40001897A-page 28

 PIC16(L)F15313/23
The HIGH directive will set bit 7 if a label points to a 4.2 Memory Access Partition (MAP)
location in the program memory. This applies to the
assembly code Example 4-2 shown below. User Flash is partitioned into:
• Application Block
EXAMPLE 4-2: ACCESSING PROGRAM • Boot Block, and
• Storage Area Flash (SAF) Block
MEMORY VIA FSR
constants The user can allocate the memory usage by setting
RETLW DATA0 ;Index0 data the BBEN bit, selecting the size of the partition defined
RETLW DATA1 ;Index1 data by BBSIZE[2:0] bits and enabling the Storage Area
RETLW DATA2 Flash by the SAFEN bit of the Configuration Word (see
RETLW DATA3
Register 5-4). Refer to Table 4-2 for the different user
my_function
;… LOTS OF CODE… Flash memory partitions.
MOVLW LOW constants
MOVWF FSR1L
4.2.1 APPLICATION BLOCK
MOVLW HIGH constants Default settings of the Configuration bits (BBEN = 1
MOVWF FSR1H
MOVIW 0[FSR1] and SAFEN = 1) assign all memory in the user Flash
;THE PROGRAM MEMORY IS IN W area to the Application Block.

4.2.2 BOOT BLOCK

If BBEN = 1, the Boot Block is enabled and a specific
address range is alloted as the Boot Block based on
the value of the BBSIZE bits of Configuration Word
(Register 5-4) and the sizes provided in .

4.2.3 STORAGE AREA FLASH

Storage Area Flash (SAF) is enabled by clearing the
SAFEN bit of the Configuration Word in Register 5-4. If
enabled, the SAF block is placed at the end of memory
and spans 128 words. If the Storage Area Flash (SAF)
is enabled, the SAF area is not available for program
execution.

4.2.4 MEMORY WRITE PROTECTION

All the memory blocks have corresponding write
protection fuses WRTAPP, WRTB and WRTC bits in
the Configuration Word 4 (Register 5-4). If
write-protected locations are written from NVMCON
registers, memory is not changed and the WRERR bit
defined in Register 12-5 is set as explained in
Section 13.3.8 “WRERR Bit”.

4.2.5 MEMORY VIOLATION

A Memory Execution Violation Reset occurs while
executing an instruction that has been fetched from
outside a valid execution area, clearing the MEMV bit.
Refer to Section 8.12 “Memory Execution Violation”
for the available valid program execution areas and the
PCON1 register definition (Register 8-3) for MEMV bit
conditions.

 2017 Microchip Technology Inc. Preliminary DS40001897A-page 29

 PIC16(L)F15313/23

TABLE 4-2: MEMORY ACCESS PARTITION

Partition
REG Address BBEN = 1 BBEN = 1 BBEN = 0 BBEN = 0
SAFEN = 1 SAFEN = 0 SAFEN = 1 SAFEN = 0
00 0000h
•••
BOOT BLOCK(4) BOOT BLOCK(4)
Last Boot Block Memory
Address
APPLICATION
Last Boot Block Memory BLOCK(4)
Address + 1(1)
APPLICATION
••• APPLICATION
PFM BLOCK(4)
Last Program Memory BLOCK(4)
Address - 80h APPLICATION
Last Program Memory BLOCK(4)
Address - 7Fh(2)
••• SAF(4) SAF(4)
Last Program Memory
Address
CONFIG Config Memory Address(3) CONFIG
Note 1: Last Boot Block Memory Address is based on BBSIZE<2:0> given in .
2: Last Program Memory Address is the Flash size given in Table 4-1.
3: Config Memory Address are the address locations of the Configuration Words given in Table 13-2.
4: Each memory block has a corresponding write protection fuse defined by the WRTAPP, WRTB and WRTC
bits in the Configuration Word (Register 5-4).

 2017 Microchip Technology Inc. Preliminary DS40001897A-page 30

 PIC16(L)F15313/23
4.3 Data Memory Organization 4.3.1 BANK SELECTION
The data memory is partitioned into 64 memory banks The active bank is selected by writing the bank number
with 128 bytes in each bank. Each bank consists of: into the Bank Select Register (BSR). All data memory
can be accessed either directly (via instructions that
• 12 core registers use the file registers) or indirectly via the two File Select
• Up to 100 Special Function Registers (SFR) Registers (FSR). See Section 4.6 “Indirect
• Up to 80 bytes of General Purpose RAM (GPR) Addressing” for more information.
• 16 bytes of common RAM Data memory uses a 13-bit address. The upper six bits
of the address define the Bank address and the lower
FIGURE 4-2: BANKED MEMORY seven bits select the registers/RAM in that bank.
PARTITIONING
Rev. 10-000041B
4.3.2 CORE REGISTERS
9/21/2016

The core registers contain the registers that directly

affect the basic operation. The core registers occupy
7-bit Bank Offset Memory Region the first 12 addresses of every data memory bank
00h
(addresses x00h/x08h through x0Bh/x8Bh). These
Core Registers registers are listed below in Table 4-3.
(12 bytes)
0Bh TABLE 4-3: CORE REGISTERS
0Ch
Special Function Registers(1)
Addresses BANKx
(up to 100 bytes maximum)
1Fh x00h or x80h INDF0
20h x01h or x81h INDF1
x02h or x82h PCL
x03h or x83h STATUS
x04h or x84h FSR0L
x05h or x85h FSR0H
x06h or x86h FSR1L
x07h or x87h FSR1H
General Purpose RAM
(80 bytes maximum) x08h or x88h BSR
x09h or x89h WREG
x0Ah or x8Ah PCLATH
x0Bh or x8Bh INTCON

6Fh
70h
Common RAM
(16 bytes)
7Fh

Note 1: This table shows the address for an example

bank with 20 Bytes of SFRs only.

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 PIC16(L)F15313/23
4.3.2.1 STATUS Register For example, CLRF STATUS will clear bits <4:3> and
<1:0>, and set the Z bit. This leaves the STATUS
The STATUS register, shown in Register 4-1, contains:
register as ‘000u u1uu’ (where u = unchanged).
• the arithmetic status of the ALU
It is recommended, therefore, that only BCF, BSF,
• the Reset status SWAPF and MOVWF instructions are used to alter the
The STATUS register can be the destination for any STATUS register, because these instructions do not
instruction, like any other register. If the STATUS affect any Status bits. For other instructions not
register is the destination for an instruction that affects affecting any Status bits, refer to Section 36.0
the Z, DC or C bits, then the write to these three bits is “Instruction Set Summary”.
disabled. These bits are set or cleared according to the
Note 1: The C and DC bits operate as Borrow
device logic. Furthermore, the TO and PD bits are not
and Digit Borrow out bits, respectively, in
writable. Therefore, the result of an instruction with the
subtraction.
STATUS register as destination may be different than
intended.
REGISTER 4-1: STATUS: STATUS REGISTER
U-0 U-0 U-0 R-1/q R-1/q R/W-0/u R/W-0/u R/W-0/u
— — — TO PD Z DC(1) C(1)
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition

bit 7-5 Unimplemented: Read as ‘0’

bit 4 TO: Time-Out bit
1 = After power-up, CLRWDT instruction or SLEEP instruction
0 = A WDT time-out occurred
bit 3 PD: Power-Down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2 Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1 DC: Digit Carry/Digit Borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1)
1 = A carry-out from the 4th low-order bit of the result occurred
0 = No carry-out from the 4th low-order bit of the result
bit 0 C: Carry/Borrow bit(1) (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1)
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred

Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the
second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order
bit of the source register.

 2017 Microchip Technology Inc. Preliminary DS40001897A-page 32

 PIC16(L)F15313/23
4.3.3 SPECIAL FUNCTION REGISTER
The Special Function Registers are registers used by
the application to control the desired operation of
peripheral functions in the device. The Special Function
Registers occupy the 20 bytes of the data banks 0-59
and 100 bytes of the data banks 60-63, after the core
registers.
The SFRs associated with the operation of the
peripherals are described in the appropriate peripheral
chapter of this data sheet.

4.3.4 GENERAL PURPOSE RAM

There are up to 80 bytes of GPR in each data memory
bank.

4.3.4.1 Linear Access to GPR

The general purpose RAM can be accessed in a
non-banked method via the FSRs. This can simplify
access to large memory structures. See Section 4.6.2
“Linear Data Memory” for more information.

4.3.5 COMMON RAM

There are 16 bytes of common RAM accessible from all
banks.

4.3.6 DEVICE MEMORY MAPS

The memory maps are as shown in through .

 2017 Microchip Technology Inc. Preliminary DS40001897A-page 33

 TABLE 4-4: PIC16(L)F15313/23 MEMORY MAP, BANKS 0-7
 2017 Microchip Technology Inc.

BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7

000h 080h 100h 180h 200h 280h 300h 380h
Core Register Core Register Core Register Core Register Core Register Core Register Core Register Core Register
(Table 4-3) (Table 4-3) (Table 4-3) (Table 4-3) (Table 4-3) (Table 4-3) (Table 4-3) (Table 4-3)
00Bh 08Bh 10Bh 18Bh 20Bh 28Bh 30Bh 38Bh
00Ch PORTA 08Ch — 10Ch — 18Ch SSP1BUF 20Ch TMR1L 28Ch TMR2 30Ch CCPR1L 38Ch PWM6DCL
00Dh — 08Dh — 10Dh — 18Dh SSP1ADD 20Dh TMR1H 28Dh PR2 30Dh CCPR1H 38Dh PWM6DCH
00Eh PORTC(2) 08Eh — 10Eh — 18Eh SSP1MASK 20Eh T1CON 28Eh T2CON 30Eh CCP1CON 38Eh PWM6CON
00Fh — 08Fh — 10Fh — 18Fh SSP1STAT 20Fh T1GCON 28Fh T2HLT 30Fh CCP1CAP 38Fh —
010h — 090h — 110h — 190h SSP1CON1 210h T1GATE 290h T2CLK 310h CCPR2L 390h —
011h — 091h — 111h — 191h SSP1CON2 211h T1CLK 291h T2ERS 311h CCPR2H 391h —
012h TRISA 092h — 112h — 192h SSP1CON3 212h — 292h — 312h CCP2CON 392h —
013h — 093h — 113h — 193h — 213h — 293h — 313h CCP2CAP 393h —
014h TRISC(2) 094h — 114h — 194h — 214h — 294h — 314h PWM3DCL 394h —
015h — 095h — 115h — 195h — 215h — 295h — 315h PWM3DCH 395h —
016h — 096h — 116h — 196h — 216h — 296h — 316h PWM3CON 396h —
017h — 097h — 117h — 197h — 217h — 297h — 317h — 397h —
018h LATA 098h — 118h — 198h — 218h — 298h — 318h PWM4DCL 398h —
019h — 099h — 119h RC1REG1 199h — 219h — 299h — 319h PWM4DCH 399h —
01Ah LATC(2) 09Ah — 11Ah TX1REG1 19Ah — 21Ah — 29Ah — 31Ah PWM4CON 39Ah —
01Bh — 09Bh ADRESL 11Bh SP1BRG1L 19Bh — 21Bh — 29Bh — 31Bh — 39Bh —
— 09Ch 11Ch 19Ch — 21Ch — 29Ch — 31Ch 39Ch —
Preliminary

01Ch ADRESH SP1BRG1H PWM5DCL

01Dh — 09Dh ADCON0 11Dh RC1STA1 19Dh — 21Dh — 29Dh — 31Dh PWM5DCH 39Dh —
01Eh — 09Eh ADCON1 11Eh TX1STA1 19Eh — 21Eh — 29Eh — 31Eh PWM5CON 39Eh —
01Fh — 09Fh ADACT 11Fh BAUD1CON1 19Fh — 21Fh — 29Fh — 31Fh — 39Fh —
020h 0A0h 120h 1A0h 220h 2A0h 320h 3A0h

General General 32Fh

Purpose Purpose Unimplemented Unimplemented Unimplemented 330h Unimplemented Unimplemented

PIC16(L)F15313/23
General Register Register Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’
Purpose 80 Bytes 80 Bytes
Register
96 Bytes

0EFh 16Fh 1EFh 26Fh 2EFh 36Fh 3EFh

0F0h Common RAM 170h Common RAM 1F0h Common RAM 270h Common RAM 2F0h Common RAM 370h Common RAM 3F0h Common RAM
Accesses Accesses Accesses Accesses Accesses Accesses Accesses
07Fh 0FFh 70h-7Fh 17Fh 70h-7Fh 1FFh 70h-7Fh 27Fh 70h-7Fh 2FFh 70h-7Fh 37Fh 70h-7Fh 3FFh 70h-7Fh

Note 1: Unimplemented locations read as ‘0’.

2: Present only in PIC16(L)F15323.
DS40001897A-page 34
 TABLE 4-5: PIC16(L)F15313/23 MEMORY MAP, BANKS 8-15
 2017 Microchip Technology Inc.

BANK 8 BANK 9 BANK 10 BANK 11 BANK 12 BANK 13 BANK 14 BANK 15

400h 480h 500h 580h 600h 680h 700h 780h
Core Register Core Register Core Register Core Register Core Register Core Register Core Register Core Register
(Table 4-3) (Table 4-3) (Table 4-3) (Table 4-3) (Table 4-3) (Table 4-3) (Table 4-3) (Table 4-3)
40Bh 48Bh 50Bh 58Bh 60Bh 68Bh 70Bh 78Bh
40Ch — 48Ch — 50Ch — 58Ch NCO1ACCL 60Ch CWG1CLK 68Ch — 70Ch PIR0 78Ch —
40Dh — 48Dh — 50Dh — 58Dh NCO1ACCH 60Dh CWG1DAT 68Dh — 70Dh PIR1 78Dh —
40Eh — 48Eh — 50Eh — 58Eh NCO1ACCU 60Eh CWG1DBR 68Eh — 70Eh PIR2 78Eh —
40Fh — 48Fh — 50Fh — 58Fh NCO1INCL 60Fh CWG1DBF 68Fh — 70Fh PIR3 78Fh —
410h — 490h — 510h — 590h NCO1INCH 610h CWG1CON0 690h — 710h PIR4 790h —
411h — 491h — 511h — 591h NCO1INCU 611h CWG1CON1 691h — 711h PIR5 791h —
412h — 492h — 512h — 592h NCO1CON 612h CWG1AS0 692h — 712h PIR6 792h —
413h — 493h — 513h — 593h NCO1CLK 613h CWG1AS1 693h — 713h PIR7 793h —
414h — 494h — 514h — 594h — 614h CWG1STR 694h — 714h — 794h —
415h — 495h — 515h — 595h — 615h — 695h — 715h — 795h —
416h — 496h — 516h — 596h — 616h — 696h — 716h PIE0 796h PMD0
417h — 497h — 517h — 597h — 617h — 697h — 717h PIE1 797h PMD1
418h — 498h — 518h — 598h — 618h — 698h — 718h PIE2 798h PMD2
419h — 499h — 519h — 599h — 619h — 699h — 719h PIE3 799h PMD3
41Ah — 49Ah — 51Ah — 59Ah — 61Ah — 69Ah — 71Ah PIE4 79Ah PMD4
Preliminary

41Bh — 49Bh — 51Bh — 59Bh — 61Bh — 69Bh — 71Bh PIE5 79Bh PMD5
41Ch — 49Ch — 51Ch — 59Ch TMR0 61Ch — 69Ch — 71Ch PIE6 79Ch —
41Dh — 49Dh — 51Dh — 59Dh PR0 61Dh — 69Dh — 71Dh PIE7 79Dh —
41Eh — 49Eh — 51Eh — 59Eh T0CON0 61Eh — 69Eh — 71Eh — 79Eh —
41Fh — 49Fh — 51Fh — 59Fh T0CON1 61Fh — 69Fh — 71Fh — 79Fh —
420h 4A0h 520h 5A0h 620h 6A0h 720h 7A0h

Unimplemented Unimplemented Unimplemented

PIC16(L)F15313/23
Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented
Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’

46Fh 4EFh 56Fh 5EFh 66Fh 6EFh 76Fh 7EFh

470h Common RAM 4F0h Common RAM 570h Common RAM 5F0h Common RAM 670h Common RAM 6F0h Common RAM 770h Common RAM 7F0h Common RAM
Accesses Accesses Accesses Accesses Accesses Accesses Accesses Accesses
47Fh 70h-7Fh 4FFh 70h-7Fh 57Fh 70h-7Fh 5FFh 70h-7Fh 67Fh 70h-7Fh 6FFh 70h-7Fh 77Fh 70h-7Fh 7FFh 70h-7Fh

Note 1: Unimplemented locations read as ‘0’.

DS40001897A-page 35
 TABLE 4-6: PIC16(L)F15313/23 MEMORY MAP, BANKS 16-23
 2017 Microchip Technology Inc.

BANK 16 BANK 17 BANK 18 BANK 19 BANK 20 BANK 21 BANK 22 BANK 23

800h 880h 900h 980h A00h A80h B00h B80h
Core Register Core Register Core Register Core Register Core Register Core Register Core Register Core Register
(Table 4-3) (Table 4-3) (Table 4-3) (Table 4-3) (Table 4-3) (Table 4-3) (Table 4-3) (Table 4-3)
80Bh 88Bh 90Bh 98Bh A0Bh A8Bh B0Bh B8Bh
80Ch WDTCON0 88Ch CPUDOZE 90Ch FVRCON 98Ch — A0Ch — A8Ch — B0Ch — B8Ch —
80Dh WDTCON1 88Dh OSCCON1 90Dh — 98Dh — A0Dh — A8Dh — B0Dh — B8Dh —
80Eh WDTL 88Eh OSCCON2 90Eh DAC1CON0 98Eh — A0Eh — A8Eh — B0Eh — B8Eh —
80Fh WDTH 88Fh OSCCON3 90Fh DAC1CON1 98Fh CMOUT A0Fh — A8Fh — B0Fh — B8Fh —
810h WDTU 890h OSCSTAT1 910h — 990h CM1CON0 A10h — A90h — B10h — B90h —
811h BORCON 891h OSCEN 911h — 991h CM1CON1 A11h — A91h — B11h — B91h —
812h VREGCON(2) 892h OSCTUNE 912h — 992h CM1NCH A12h — A92h — B12h — B92h —
813h PCON0 893h OSCFRQ 913h — 993h CM1PCH A13h — A93h — B13h — B93h —
814h PCON1 894h — 914h — 994h CM2CON0(3) A14h — A94h — B14h — B94h —
815h — 895h CLKRCON 915h — 995h CM2CON1(3) A15h — A95h — B15h — B95h —
816h — 896h CLKCLK 916h — 996h CM2NCH(3) A16h — A96h — B16h — B96h —
817h — 897h — 917h — 997h CM2PCH(3) A17h — A97h — B17h — B97h —
818h — 898h — 918h — 998h — A18h — A98h — B18h — B98h —
819h — 899h — 919h — 999h — A19h — A99h — B19h — B99h —
81Ah NVMADRL 89Ah — 91Ah — 99Ah — A1Ah — A9Ah — B1Ah — B9Ah —
Preliminary

81Bh NVMADRH 89Bh — 91Bh — 99Bh — A1Bh — A9Bh — B1Bh — B9Bh —

81Ch NVMDATL 89Ch — 91Ch — 99Ch — A1Ch — A9Ch — B1Ch — B9Ch —
81Dh NVMDATH 89Dh — 91Dh — 99Dh — A1Dh — A9Dh — B1Dh — B9Dh —
81Eh NVMCON1 89Eh — 91Eh — 99Eh — A1Eh — A9Eh — B1Eh — B9Eh —
81Fh NVMCON2 89Fh — 91Fh ZCDCON 99Fh — A1Fh — A9Fh — B1Fh — B9Fh —
820h 8A0h 920h 9A0h A20h AA0h B20h BA0h
Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented

PIC16(L)F15313/23
Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’
86Fh 8EFh 96Fh 9EFh A6Fh AEFh B6Fh BEFh
870h Common RAM 8F0h Common RAM 970h Common RAM 9F0h Common RAM A70h Common RAM AF0h Common RAM B70h Common RAM BF0h Common RAM
Accesses Accesses Accesses Accesses Accesses Accesses Accesses Accesses
87Fh 70h-7Fh 8FFh 70h-7Fh 97Fh 70h-7Fh 9FFh 70h-7Fh A7Fh 70h-7Fh AFFh 70h-7Fh B7Fh 70h-7Fh BFFh 70h-7Fh

Note 1: Unimplemented locations read as ‘0’.

2: Register not implemented on LF devices.
3: Present only on PIC16(L)F15323.
DS40001897A-page 36
 TABLE 4-7: PIC16(L)F15313/23 MEMORY MAP, BANKS 56-63
 2017 Microchip Technology Inc.

BANK 56 BANK 57 BANK 58 BANK 59 BANK 60 BANK 61 BANK 62 BANK 63

1C00h 1C80h 1D00h 1D80h 1E00h 1E80h 1F00h 1F80h
Core Register Core Register Core Register Core Register Core Register Core Register Core Register Core Register
(Table 4-3) (Table 4-3) (Table 4-3) (Table 4-3) (Table 4-3) (Table 4-3) (Table 4-3) (Table 4-3)
1C0Bh 1C8Bh 1D0Bh 1D8Bh 1E0Bh 1E8Bh 1F0Bh 1F8Bh
1C0Ch — 1C8Ch — 1D0Ch — 1D8Ch — 1E0Ch 1E8Ch 1F0Ch 1F8Ch
1C0Dh — 1C8Dh — 1D0Dh — D8Dh1 — 1E0Dh 1E8Dh 1F0Dh 1F8Dh
1C0Eh — 1C8Eh — 1D0Eh — 1D8Eh — 1E0Eh 1E8Eh 1F0Eh 1F8Eh
1C0Fh — 1C8Fh — 1D0Fh — 1D8Fh — 1E0Fh 1E8Fh 1F0Fh 1F8Fh
1C10h — 1C90h — 1D10h — 1D90h — 1E10h 1E90h 1F10h 1F90h
1C11h — 1C91h — 1D11h — 1D91h — 1E11h 1E91h 1F11h 1F91h
1C12h — 1C92h — 1D12h — 1D92h — 1E12h 1E92h 1F12h 1F92h
1C13h — 1C93h — 1D13h — 1D93h — 1E13h 1E93h 1F13h 1F93h
1C14h — 1C94h — 1D14h — 1D94h — 1E14h 1E94h 1F14h 1F94h
1C15h — 1C95h — 1D15h — 1D95h — 1E15h 1E95h 1F15h 1F95h
1C16h — 1C96h — 1D16h — 1D96h — 1E16h 1E96h 1F16h 1F96h
1C17h — 1C97h — 1D17h — 1D97h — 1E17h CLC Controls 1E97h nnnPPS Controls 1F17h RxyPPS Controls 1F97h
(See Table 4-8 for
1C18h — 1C98h — 1D18h — 1D98h — 1E18h (See Table 4-8 for 1E98h (See Table 4-8 for 1F18h (See Table 4-8 for 1F98h register mapping
1C19h — 1C99h — 1D19h — 1D99h — 1E19h register mapping 1E99h register mapping 1F19h register mapping 1F99h details)
1C1Ah — 1C9Ah — 1D1Ah — 1D9Ah — 1E1Ah details) 1E9Ah details) 1F1Ah details) 1F9Ah
Preliminary

1C1Bh — 1C9Bh — 1D1Bh — 1D9Bh — 1E1Bh 1E9Bh 1F1Bh 1F9Bh

1C1Ch — 1C9Ch — 1D1Ch — 1D9Ch — 1E1Ch 1E9Ch 1F1Ch 1F9Ch
1C1Dh — 1C9Dh — 1D1Dh — 1D9Dh — 1E1Dh 1E9Dh 1F1Dh 1F9Dh
1C1Eh — 1C9Eh — 1D1Eh — 1D9Eh — 1E1Eh 1E9Eh 1F1Eh 1F9Eh
1C1Fh — 1C9Fh — 1D1Fh — 1D9Fh — 1E1Fh 1E9Fh 1F1Fh 1F9Fh
1C20h 1CA0h 1D20h 1DA0h 1E20h 1EA0h 1F20h 1FA0h

PIC16(L)F15313/23
Unimplemented Unimplemented Unimplemented Unimplemented
Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’

1C6Fh 1CEFh 1D6Fh 1DEFh 1E6Fh 1EEFh 1F6Fh 1FEFh

1C70h Common RAM 1CF0h Common RAM 1D70h Common RAM 1DF0h Common RAM 1E70h Common RAM 1EF0h Common RAM 1F70h Common RAM 1FF0h Common RAM
Accesses Accesses Accesses Accesses Accesses Accesses Accesses Accesses
1C7Fh 70h-7Fh 1CFFh 70h-7Fh 1D7Fh 70h-7Fh 1DFFh 70h-7Fh 1E7Fh 70h-7Fh 1EFFh 70h-7Fh 1F7Fh 70h-7Fh 1FFFh 70h-7Fh

Note 1: Unimplemented locations read as ‘0’.

2: The banks 24-55 have been omitted from the tables in the data sheet since the banks have unimplemented registers.
DS40001897A-page 37
 PIC16(L)F15313/23

TABLE 4-8: PIC16(L)F15313/23 MEMORY MAP, BANKS 60, 61, 62, AND 63
Bank 60 Bank 61 Bank 62 Bank 63
1E0Ch — 1E8Ch — 1F0Ch — 1F8Ch —
1E0Dh — 1E8Dh — 1F0Dh — 1F8Dh —
1E0Eh — 1E8Eh — 1F0Eh — 1F8Eh —
1E0Fh CLCDATA 1E8Fh PPSLOCK 1F0Fh — 1F8Fh —
1E10h CLC1CON 1E90h INTPPS 1F10h RA0PPS 1F90h —
1E11h CLC1POL 1E91h T0CKIPPS 1F11h RA1PPS 1F91h —
1E12h CLC1SEL0 1E92h T1CKIPPS 1F12h RA2PPS 1F92h —
1E13h CLC1SEL1 1E93h T1GPPS 1F13h RA3PPS 1F93h —
1E14h CLC1SEL2 1E94h — 1F14h RA4PPS 1F94h —
1E15h CLC1SEL3 1E95h — 1F15h RA5PPS 1F95h —
1E16h CLC1GLS0 1E96h — 1F16h — 1F96h —
1E17h CLC1GLS1 1E97h — 1F17h — 1F97h —
1E18h CLC1GLS2 1E98h — 1F18h — 1F98h —
1E19h CLC1GLS3 1E99h — 1F19h — 1F99h —
1E1Ah CLC2CON 1E9Ah — 1F1Ah — 1F9Ah —
1E1Bh CLC2POL 1E9Bh — 1F1Bh — 1F9Bh —
1E1Ch CLC2SEL0 1E9Ch T2INPPS 1F1Ch — 1F9Ch —
1E1Dh CLC2SEL1 1E9Dh — 1F1Dh — 1F9Dh —
1E1Eh CLC2SEL2 1E9Eh — 1F1Eh — 1F9Eh —
1E1Fh CLC2SEL3 1E9Fh — 1F1Fh — 1F9Fh —
1E20h CLC2GLS0 1EA0h — 1F20h RC0PPS(1) 1FA0h —

1E21h CLC2GLS1 1EA1h CCP1PPS 1F21h RC1PPS(1) 1FA1h —

1E22h CLC2GLS2 1EA2h CCP2PPS 1F22h RC2PPS(1) 1FA2h —

1E23h CLC2GLS3 1EA3h — 1F23h RC3PPS(1) 1FA3h —

1E24h CLC3CON 1EA4h — 1F24h RC4PPS(1) 1FA4h —

1E25h CLC3POL 1EA5h — 1F25h RC5PPS(1) 1FA5h —

1E26h CLC3SEL0 1EA6h — 1F26h — 1FA6h —
1E27h CLC3SEL1 1EA7h — 1F27h — 1FA7h —
1E28h CLC3SEL2 1EA8h — 1F28h — 1FA8h —
1E29h CLC3SEL3 1EA9h — 1F29h — 1FA9h —
1E2Ah CLC3GLS0 1EAAh — 1F2Ah — 1FAAh —
1E2Bh CLC3GLS1 1EABh — 1F2Bh — 1FABh —
1E2Ch CLC3GLS2 1EACh — 1F2Ch — 1FACh —
1E2Dh CLC3GLS3 1EADh — 1F2Dh — 1FADh —
1E2Eh CLC4CON 1EAEh — 1F2Eh — 1FAEh —
1E2Fh CLC4POL 1EAFh — 1F2Fh — 1FAFh —
1E30h CLC4SEL0 1EB0h — 1F30h — 1FB0h —
1E31h CLC4SEL1 1EB1h CWG1PPS 1F31h — 1FB1h —
1E32h CLC4SEL2 1EB2h — 1F32h — 1FB2h —
1E33h CLC4SEL3 1EB3h — 1F33h — 1FB3h —
1E34h CLC4GLS0 1EB4h — 1F34h — 1FB4h —
1E35h CLC4GLS1 1EB5h — 1F35h — 1FB5h —
1E36h CLC4GLS2 1EB6h — 1F36h — 1FB6h —
1E37h CLC4GLS3 1EB7h — 1F37h — 1FB7h —
1E38h — 1EB8h — 1F38h ANSELA 1FB8h —
1E39h — 1EB9h — 1F39h WPUA 1FB9h —
1E3Ah — 1EBAh — 1F3Ah ODCONA 1FBAh —
1E3Bh — 1EBBh CLCIN0PPS 1F3Bh SLRCONA 1FBBh —
1E3Ch — 1EBCh CLCIN1PPS 1F3Ch INLVLA 1FBCh —
1E3Dh — 1EBDh CLCIN2PPS 1F3Dh IOCAP 1FBDh —
1E3Eh — 1EBEh CLCIN3PPS 1F3Eh IOCAN 1FBEh —
1E3Fh — 1EBFh — 1F3Fh IOCAF 1FBFh —
1E40h — 1EC0h — 1F40h — 1FC0h —

Legend: = Unimplemented data memory locations, read as ‘0’

Note 1: Present only in PIC16(L)F15323.

 2017 Microchip Technology Inc. Preliminary DS40001897A-page 38

 PIC16(L)F15313/23
TABLE 4-8: PIC16(L)F15313/23 MEMORY MAP, BANKS 60, 61, 62, AND 63 (CONTINUED)
Bank 60 Bank 61 Bank 62 Bank 63
1E41h — 1EC1h — 1F41h — 1FC1h —
1E42h — 1EC2h — 1F42h — 1FC2h —
1E43h — 1EC3h ADACTPPS 1F43h — 1FC3h —
1E44h — 1EC4h — 1F44h — 1FC4h —
1E45h — 1EC5h SSP1CLKPPS 1F45h — 1FC5h —
1E46h — 1EC6h SSP1DATPPS 1F46h — 1FC6h —
1E47h — 1EC7h SSP1SSPPS 1F47h — 1FC7h —
1E48h — 1EC8h — 1F48h — 1FC8h —
1E49h — 1EC9h — 1F49h — 1FC9h —
1E4Ah — 1ECAh — 1F4Ah — 1FCAh —
1E4Bh — 1ECBh RXDT1PPS 1F4Bh — 1FCBh —
1E4Ch — 1ECCh TXCK1PPS 1F4Ch — 1FCCh —
1E4Dh — 1ECDh — 1F4Dh — 1FCDh —
1E4Eh — 1ECEh — 1F4Eh ANSELC(1) 1FCEh —
1E4Fh — 1ECFh — 1F4Fh WPUC(1) 1FCFh —
1E50h — 1ED0h — 1F50h ODCONC(1) 1FD0h —
1E51h — 1ED1h — 1F51h SLRCONC(1) 1FD1h —
1E52h — 1ED2h — 1F52h INLVLC(1) 1FD2h —
1E53h — 1ED3h — 1F53h IOCCP(1) 1FD3h —
1E54h — 1ED4h — 1F54h IOCCN(1) 1FD4h —
1E55h — 1ED5h — 1F55h IOCCF(1) 1FD5h —
1E56h — 1ED6h — 1F56h — 1FD6h —
1E57h — 1ED7h — 1F57h — 1FD7h —
1E58h — 1ED8h — 1F58h — 1FD8h —
1E59h — 1ED9h — 1F59h — 1FD9h —
1E5Ah — 1EDAh — 1F5Ah — 1FDAh —
1E5Bh — 1EDBh — 1F5Bh — 1FDBh —
1E5Ch — 1EDCh — 1F5Ch — 1FDCh —
1E5Dh — 1EDDh — 1F5Dh — 1FDDh —
1E5Eh — 1EDEh — 1F5Eh — 1FDEh —
1E5Fh — 1EDFh — 1F5Fh — 1FDFh —
1E60h — 1EE0h — 1F60h — 1FE0h —
1E61h — 1EE1h — 1F61h — 1FE1h —
1E62h — 1EE2h — 1F62h — 1FE2h —
1E63h — 1EE3h — 1F63h — 1FE3h BSR_ICDSHAD
1E64h — 1EE4h — 1F64h — 1FE4h STATUS_SHAD
1E65h — 1EE5h — 1F65h — 1FE5h WREG_SHAD
1E66h — 1EE6h — 1F66h — 1FE6h BSR_SHAD
1E67h — 1EE7h — 1F67h — 1FE7h PCLATH_SHAD
1E68h — 1EE8h — 1F68h — 1FE8h FSR0L_SHAD
1E69h — 1EE9h — 1F69h — 1FE9h FSR0H_SHAD
1E6Ah — 1EEAh — 1F6Ah — 1FEAh FSR1L_SHAD
1E6Bh — 1EEBh — 1F6Bh — 1FEBh FSR1H_SHAD
1E6Ch — 1EECh — 1F6Ch — 1FECh —
1E6Dh — 1EEDh — 1F6Dh — 1FEDh STKPTR
1E6Eh — 1EEEh — 1F6Eh — 1FEEh TOSL
1E6Fh — 1EEFh — 1F6Fh — 1FEFh TOSH

Legend: = Unimplemented data memory locations, read as ‘0’

Note 1: Present only in PIC16(L)F15323.

 2017 Microchip Technology Inc. Preliminary DS40001897A-page 39

 PIC16(L)F15313/23

TABLE 4-9: SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-63 (ALL BANKS)
Bank Offset Value on: Value on:
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bank 0-Bank 63 POR, BOR MCLR

All Banks
Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a
x00h or x80h INDF0 xxxx xxxx xxxx xxxx
physical register)
Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a
x01h or x81h INDF1 xxxx xxxx xxxx xxxx
physical register)
x02h or x82h PCL PCL 0000 0000 0000 0000
x03h or x83h STATUS — — — TO PD Z DC C ---1 1000 ---q quuu
x04h or x84h FSR0L FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu
x05h or x85h FSR0H FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000
x06h or x86h FSR1L FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu
x07h or x87h FSR1H FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000
x08h or x88h BSR — — BSR<5:0> --00 0000 --00 0000
x09h or x89h WREG Working Register 0000 0000 uuuu uuuu
x0Ah or x8Ah PCLATH — Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000
x0Bh or x8Bh INTCON GIE PEIE — — — — — INTEDG 00-- ---1 00-- ---1
Legend: x = unknown, u = unchanged, q = depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations
unimplemented, read as ‘0’.
Note 1: These Registers can be accessed from any bank.

 2017 Microchip Technology Inc. Preliminary DS40001897A-page 40

 2017 Microchip Technology Inc.

TABLE 4-10: SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-63

Value on: Value on:
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
POR, BOR MCLR

Bank 0

CPU CORE REGISTERS; see Table 4-9 for specifics

00Ch PORTA — — RA5 RA4 RA3 RA2 RA1 RA0 --xx xxxx --uu uuuu
00Dh — Unimplemented ---- ---- ---- ----
00Eh PORTC(1) — — RC5 RC4 RC3 RC2 RC1 RC0 --xx xxxx --uu uuuu
00Fh — Unimplemented — —
010h — Unimplemented — —
011h — Unimplemented ---- ---- ---- ----
012h TRISA — — TRISA5 TRISA4 — TRISA2 TRISA1 TRISA0 --11 -111 --11 -111
013h — Unimplemented — —
014h TRISC(1) — — TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 --11 1111 --11 1111
015h — Unimplemented — —
Preliminary

016h — Unimplemented — —
017h — Unimplemented — —
018h LATA — — LATA5 LATA4 — LATA2 LATA1 LATA0 --xx xxxx --uu uuuu
019h — — Unimplemented —
01Ah LATC(1) — — LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 --xx xxxx --uu uuuu
01Bh — Unimplemented — —

PIC16(L)F15313/23
01Ch — Unimplemented — —
01Dh — Unimplemented — —
01Eh — Unimplemented — —
01Fh — Unimplemented — —
Legend: x = unknown, u = unchanged, q = depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’.
Note 1: Present only in PIC16(L)F15323.
DS40001897A-page 41
 TABLE 4-10: SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-63 (CONTINUED)
 2017 Microchip Technology Inc.

Value on: Value on:

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
POR, BOR MCLR

Bank 1

CPU CORE REGISTERS; see Table 4-3 for specifics

08Ch
— — Unimplemented — —
09Ah
09Bh ADRESL ADC Result Register Low xxxx xxxx uuuu uuuu
09Ch ADRESH ADC Result Register High xxxx xxxx uuuu uuuu
09Dh ADCON0 CHS<5:0> GO/DONE ADON 0000 0000 0000 0000
09Eh ADCON1 ADFM ADCS<2:0> — — ADPREF<1:0> 0000 --00 0000 --00
09Fh ADACT — — — ADACT<4:0> ---0 0000 ---0 0000
Legend: x = unknown, u = unchanged, q = depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’.
Preliminary

PIC16(L)F15313/23
DS40001897A-page 42
 TABLE 4-10: SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-63 (CONTINUED)
 2017 Microchip Technology Inc.

Value on: Value on:

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
POR, BOR MCLR

Bank 2

CPU CORE REGISTERS; see Table 4-3 for specifics

10Ch
— — Unimplemented — —
118h
119h RC1REG EUSART Receive Data Register 0000 0000 0000 0000
11Ah TX1REG EUSART Transmit Data Register 0000 0000 0000 0000
11Bh SP1BRGL SP1BRG<7:0> 0000 0000 0000 0000
11Ch SP1BRGH SP1BRG<15:8> 0000 0000 0000 0000
11Dh RC1STA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 0000 0000 0000
11Eh TX1STA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010
11Fh BAUD1CON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 01-0 0-00 01-0 0-00
Legend: x = unknown, u = unchanged, q = depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’.
Preliminary

PIC16(L)F15313/23
DS40001897A-page 43
 TABLE 4-10: SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-63 (CONTINUED)
 2017 Microchip Technology Inc.

Value on: Value on:

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
POR, BOR MCLR

Bank 3

CPU CORE REGISTERS; see Table 4-3 for specifics

18Ch SSP1BUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx xxxx xxxx
18Dh SSP1ADD ADD<7:0> 0000 0000 0000 0000
18Eh SSP1MSK MSK<7:0> 1111 1111 1111 1111
18Fh SSP1STAT SMP CKE D/A P S R/W UA BF 0000 0000 0000 0000
190h SSP1CON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
191h SSP1CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 0000 0000
192h SSP1CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 0000 0000 0000 0000
193h
— — Unimplemented — —
19Fh
Legend: x = unknown, u = unchanged, q = depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’.
Preliminary

PIC16(L)F15313/23
DS40001897A-page 44
 TABLE 4-10: SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-63 (CONTINUED)
 2017 Microchip Technology Inc.

Value on: Value on:

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
POR, BOR MCLR

Bank 4

CPU CORE REGISTERS; see Table 4-3 for specifics

20Ch TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register 0000 0000 uuuu uuuu
20Dh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register 0000 0000 uuuu uuuu
20Eh T1CON — — CKPS<1:0> — SYNC RD16 ON --00 -000 --uu -u0u
20Fh T1GCON GE GPOL GTM GSPM GGO/DONE GVAL — — 0000 0x-- uuuu ux--
210h T1GATE — — — GSS<4:0> ---0 0000 ---u uuuu
211h T1CLK — — — — CS<3:0> ---- 0000 ---- uuuu
212h
— — Unimplemented — —
21Fh
Legend: x = unknown, u = unchanged, q = depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’.
Preliminary

PIC16(L)F15313/23
DS40001897A-page 45
 TABLE 4-10: SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-63 (CONTINUED)
 2017 Microchip Technology Inc.

Value on: Value on:

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
POR, BOR MCLR

Bank 5

CPU CORE REGISTERS; see Table 4-3 for specifics

28Ch T2TMR Holding Register for the 8-bit TMR2 Register 0000 0000 0000 0000
28Dh T2PR TMR2 Period Register 1111 1111 1111 1111
28Eh T2CON ON CKPS<2:0> OUTPS<3:0> 0000 0000 0000 0000
28Fh T2HLT PSYNC CKPOL CKSYNC MODE<4:0> 0000 0000 0000 0000
290h T2CLKCON — — — — CS<3:0> ---- 0000 ---- 0000
291h T2RST — — — — RSEL<3:0> ---- 0000 ---- 0000
292h
— — Unimplemented — —
29Fh
Legend: x = unknown, u = unchanged, q = depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’.
Preliminary

PIC16(L)F15313/23
DS40001897A-page 46
 TABLE 4-10: SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-63 (CONTINUED)
 2017 Microchip Technology Inc.

Value on: Value on:

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
POR, BOR MCLR

Bank 6

CPU CORE REGISTERS; see Table 4-3 for specifics

30Ch CCPR1L Capture/Compare/PWM Register 1 (LSB) xxxx xxxx uuuu uuuu

30Dh CCPR1H Capture/Compare/PWM Register 1 (MSB) xxxx xxxx uuuu uuuu
30Eh CCP1CON EN — OUT FMT MODE<3:0> 0-00 0000 0-00 0000
30Fh CCP1CAP — — — — — CTS<2:0> ---- -000 ---- -000
310h CCPR2L Capture/Compare/PWM Register 2 (LSB) xxxx xxxx uuuu uuuu
311h CCPR2H Capture/Compare/PWM Register 2 (MSB) xxxx xxxx uuuu uuuu
312h CCP2CON EN — OUT FMT MODE<3:0> 0-00 0000 0-00 0000
313h CCP2CAP — — — — — CTS<2:0> ---- -000 ---- -000
314h PWM3DCL DC<1:0> — — — — — — xx-- ---- uu-- ----
315h PWM3DCH DC<9:0> xxxx xxxx uuuu uuuu
316h PWM3CON EN — OUT POL — — — — 0-00 ---- 0-00 ----
Preliminary

317h — Unimplemented — —
318h PWM4DCL DC<1:0> — — — — — — xx-- ---- uu-- ----
319h PWM4DCH DC<9:0> xxxx xxxx uuuu uuuu
31Ah PWM4CON EN — OUT POL — — — — 0-00 ---- 0-00 ----
31Bh — Unimplemented — —
31Ch PWM5DCL DC<1:0> — — — — — — xx-- ---- uu-- ----

PIC16(L)F15313/23
31Dh PWM5DCH DC<9:0> xxxx xxxx uuuu uuuu
31Eh PWM5CON EN — OUT POL — — — — 0-00 ---- 0-00 ----
31Fh — Unimplemented — —
Legend: x = unknown, u = unchanged, q = depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’.
DS40001897A-page 47
 TABLE 4-10: SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-63 (CONTINUED)
 2017 Microchip Technology Inc.

Value on: Value on:

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
POR, BOR MCLR

Bank 7

CPU CORE REGISTERS; see Table 4-3 for specifics

38Ch PWM6DCL DC<1:0> — — — — — — xx-- ---- uu-- ----

38Dh PWM6DCH DC<9:0> xxxx xxxx uuuu uuuu
38Eh PWM6CON EN — OUT POL — — — — 0-00 ---- 0-00 ----
38Fh
— — Unimplemented — —
39Fh
Legend: x = unknown, u = unchanged, q = depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’.
Preliminary

PIC16(L)F15313/23
DS40001897A-page 48
 TABLE 4-10: SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-63 (CONTINUED)
 2017 Microchip Technology Inc.

Value on: Value on:

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
POR, BOR MCLR

Bank 8-10

CPU CORE REGISTERS; see Table 4-3 for specifics

x0Ch/
x8Ch
— — Unimplemented
x1Fh/
x9Fh
Legend: x = unknown, u = unchanged, q = depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’.
Preliminary

PIC16(L)F15313/23
DS40001897A-page 49
 TABLE 4-10: SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-63 (CONTINUED)
 2017 Microchip Technology Inc.

Value on: Value on:

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
POR, BOR MCLR

Bank 11

CPU CORE REGISTERS; see Table 4-3 for specifics

58Ch NCO1ACCL NCO1ACC<7:0> 0000 0000 0000 0000

58Dh NCO1ACCH NCO1ACC<15:8> 0000 0000 0000 0000
58Eh NCO1ACCU — — — — NCO1ACC<19:16> ---- 0000 ---- 0000
58Fh NCO1INCL NCO1INC<7:0> 0000 0001 0000 0001
590h NCO1INCH NCO1INC<15:8> 0000 0000 0000 0000
591h NCO1INCU — — — — NCO1INC<19:16> ---- 0000 ---- 0000
592h NCO1CON N1EN — N1OUT N1POL — — — N1PFM 0-00 ---0 0-00 ---0
593h NCO1CLK N1PWS<2:0> — — N1CKS<2:0> 000- -000 000- -000
594h — Unimplemented — —
595h — Unimplemented — —
596h — Unimplemented — —
Preliminary

597h — Unimplemented — —
598h — Unimplemented — —
599h — Unimplemented — —
59Ah — Unimplemented — —
59Bh — Unimplemented — —
59Ch TMR0L Holding Register for the Least Significant Byte of the 16-bit TMR0 Register 0000 0000 0000 0000

PIC16(L)F15313/23
59Dh TMR0H Holding Register for the Most Significant Byte of the 16-bit TMR0 Register 1111 1111 1111 1111
59Eh T0CON0 T0EN — T0OUT T016BIT T0OUTPS<3:0> 0-00 0000 0-00 0000
59Fh T0CON1 T0CS<2:0> T0ASYNC T0CKPS<3:0> 0000 0000 0000 0000
Legend: x = unknown, u = unchanged, q = depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’.
DS40001897A-page 50
 TABLE 4-10: SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-63 (CONTINUED)
 2017 Microchip Technology Inc.

Value on: Value on:

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
POR, BOR MCLR

Bank 12

CPU CORE REGISTERS; see Table 4-3 for specifics

60Ch CWG1CLKCON — — — — — — — CS ---- ---0 ---- ---0

60Dh CWG1DAT — — — — DAT<3:0> ---- 0000 ---- 0000
60Eh CWG1DBR — — DBR<5:0> --00 0000 --00 0000
60Fh CWG1DBF — — DBF<5:0> --00 0000 --00 0000
610h CWG1CON0 EN LD — — — MODE<2:0> 00-- -000 00-- -000
611h CWG1CON1 — — IN — POLD POLC POLB POLA --x- 0000 --u- 0000
612h CWG1AS0 SHUTDOWN REN LSBD<2:0> LSAC<2:0> — — 0001 01-- 0001 01--
613h CWG1AS1 — — — AS4E AS3E AS2E AS1E AS0E ---0 0000 ---u 0000
614h CWG1STR OVRD OVRC OVRB OVRA STRD STRC STRB STRA 0000 0000 0000 0000
615h
— — Unimplemented — —
61Fh
Preliminary

Legend: x = unknown, u = unchanged, q = depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’.

PIC16(L)F15313/23
DS40001897A-page 51
 TABLE 4-10: SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-63 (CONTINUED)
 2017 Microchip Technology Inc.

Value on: Value on:

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
POR, BOR MCLR

Bank 13

CPU CORE REGISTERS; see Table 4-3 for specifics

68Ch
— — Unimplemented — —
69Fh
Legend: x = unknown, u = unchanged, q = depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’.
Preliminary

PIC16(L)F15313/23
DS40001897A-page 52
 TABLE 4-10: SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-63 (CONTINUED)
 2017 Microchip Technology Inc.

Value on: Value on:

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
POR, BOR MCLR

Bank 14

CPU CORE REGISTERS; see Table 4-3 for specifics

70Ch PIR0 — — TMR0IF IOCIF — — — INTF --00 ---0 --00 ---0

70Dh PIR1 OSFIF CSWIF — — — — — ADIF 00-- --00 00-- --00
70Eh PIR2 — ZCDIF — — — — C2IF(1) C1IF -0-- --00 -0-- --00

70Fh PIR3 — — RC1IF TX1IF — — BCL1IF SSP1IF --00 --00 --00 --00
710h PIR4 — — — — — — TMR2IF TMR1IF ---- --00 ---- --00
711h PIR5 CLC4IF CLC3IF CLC2IF CLC1IF — — — TMR1GIF 0000 ---0 0000 ---0
712h PIR6 — — — — — — CCP2IF CCP1IF ---- --00 ---- --00
713h PIR7 — — NVMIF NCO1IF — — — CWG1IF --00 ---0 --00 ---0
714h — Unimplemented — —
715h — Unimplemented — —
716h PIE0 — — TMR0IE IOCIE — — — INTE --00 ---0 --00 ---0
Preliminary

717h PIE1 OSFIE CSWIE — — — — — ADIE 00-- --00 00-- --00

718h PIE2 — ZCDIE — — — — C2IE(1) C1IE -0-- --00 -0-- --00

719h PIE3 — — RC1IE TX1IE — — BCL1IE SSP1IE --00 --00 --00 --00
71Ah PIE4 — — — — — — TMR2IE TMR1IE ---- --00 ---- --00
71Bh PIE5 CLC4IE CLC3IE CLC2IE CLC1IE — — — TMR1GIE 0000 ---0 0000 ---0
71Ch PIE6 — — — — — — CCP2IE CCP1IE

PIC16(L)F15313/23
---- --00 ---- --00
71Dh PIE7 — — NVMIE NCO1IE — — — CWG1IE --00 ---0 --00 ---0
71Eh — Unimplemented — —
71Fh — Unimplemented — —
Legend: x = unknown, u = unchanged, q = depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’.
Note 1: Present only on PIC16(L)F15323.
DS40001897A-page 53
 TABLE 4-10: SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-63 (CONTINUED)
 2017 Microchip Technology Inc.

Value on: Value on:

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
POR, BOR MCLR

Bank 15

CPU CORE REGISTERS; see Table 4-3 for specifics

78Ch
— — Unimplemented — —
795h
796h PMD0 SYSCMD FVRMD — — — NVMMD CLKRMD IOCMD 00-- -000 00-- -000
797h PMD1 NCO1MD — — — — TMR2MD TMR1MD TMR0MD 0--- -000 0--- -000
798h PMD2 — DAC1MD ADCMD — — CMP2MD(1) CMP1MD ZCDMD -00- -000 -00- -000
799h PMD3 — — PWM6MD PWM5MD PWM4MD PWM3MD CCP2MD CCP1MD --00 0000 --00 0000
79Ah PMD4 — UART1MD — MSSP1MD — — — CWG1MD -0-0 ---0 -0-0 ---0
79Bh PMD5 — — — CLC4MD CLC3MD CLC2MD CLC1MD — ---0 000- ---0 000-
79Ch — Unimplemented — —
79Dh — Unimplemented — —
79Eh — Unimplemented — —
Preliminary

79Fh — Unimplemented — —
Legend: x = unknown, u = unchanged, q = depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’.
Note 1: Present only on PIC16(L)F15323.

PIC16(L)F15313/23
DS40001897A-page 54
 TABLE 4-10: SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-63 (CONTINUED)
 2017 Microchip Technology Inc.

Value on: Value on:

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
POR, BOR MCLR

Bank 16

CPU CORE REGISTERS; see Table 4-3 for specifics

80Ch WDTCON0 — — WDTPS<4:0> SWDTEN --qq qqq0 --qq qqq0

80Dh WDTCON1 — WDTCS<2:0> — WINDOW<2:0> -qqq -qqq -qqq -qqq

80Eh WDTPSL PSCNT<7:0> 0000 0000 0000 0000

80Fh WDTPSH PSCNT<15:8> 0000 0000 0000 0000
810h WDTTMR — WDTTMR<3:0> STATE PSCNT17 PSCNT16 xxxx x000 xxxx x000
811h BORCON SBOREN — — — — — — BORRDY 1--- ---q u--- ---u
812h VREGCON — — — — — — VREGPM(1) — ---- --0- ---- --0-
813h PCON0 STKOVF STKUNF WDTWV RWDT RMCLR RI POR BOR 0011 110q qqqq qquu
814h PCON1 — — — — — — MEMV — ---- --1- ---- --u-
815h — Unimplemented — —
Preliminary

816h — Unimplemented — —
817h — Unimplemented — —
818h — Unimplemented — —
819h — Unimplemented — —
81Ah NVMADRL NVMADR<7:0> xxxx xxxx uuuu uuuu
81Bh NVMADRH — NVMADR<14:8> -xxx xxxx -uuu uuuu
81Ch NVMDATL NVMDAT<7:0>

PIC16(L)F15313/23
0000 0000 0000 0000
81Dh NVMDATH — — NVMDAT<13:8> --00 0000 --00 0000
81Eh NVMCON1 — NVMREGS LWLO FREE WRERR WREN WR RD -000 x000 -000 q000
81Fh NVMCON2 NVMCON2<7:0> xxxx xxxx uuuu uuuu
Legend: x = unknown, u = unchanged, q = depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’.
Note 1: Present only on PIC16F15313/23.
DS40001897A-page 55
 TABLE 4-10: SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-63 (CONTINUED)
 2017 Microchip Technology Inc.

Value on: Value on:

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
POR, BOR MCLR

Bank 17

CPU CORE REGISTERS; see Table 4-3 for specifics

88Ch CPUDOZE IDLEN DOZEN ROI DOE — DOZE2 DOZE1 DOZE0 0000 -000 u000 -000
88Dh OSCCON1 — NOSC<2:0> NDIV<3:0> -qqq 0000 -qqq 0000
88Eh OSCCON2 — COSC<2:0> CDIV<3:0> -qqq qqqq -qqq qqqq
88Fh OSCCON3 CSWHOLD — — ORDY NOSCR — — — 0--0 0--- 0--0 0---
890h OSCSTAT EXTOR HFOR MFOR LFOR — ADOR — PLLR q000 -q-0 qqqq -q-q
891h OSCEN EXTOEN HFOEN MFOEN LFOEN — ADOEN — — 0000 -0-- 0000 -0--
892h OSCTUNE — — HFTUN<5:0> --10 0000 --10 0000
893h OSCFRQ — — — — — HFFRQ<2:0> ---- -qqq ---- -qqq
894h — Unimplemented — —
895h CLKRCON CLKREN — — CLKRDC<1:0> CLKRDIV<2:0> 0--x xxxx 0--u uuuu
896h CLKRCLK — — — — CLKRCLK<3:0> ---- 0000 ---- 0000
Preliminary

897h
— — Unimplemented — —
89Fh
Legend: x = unknown, u = unchanged, q = depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’.

PIC16(L)F15313/23
DS40001897A-page 56
 TABLE 4-10: SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-63 (CONTINUED)
 2017 Microchip Technology Inc.

Value on: Value on:

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
POR, BOR MCLR

Bank 18

CPU CORE REGISTERS; see Table 4-3 for specifics

90Ch FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR<1:0> ADFVR<1:0> 0x00 xxxx 0q00 uuuu
90Dh — Unimplemented — —
90Eh DAC1CON0 EN — OE1 OE2 PSS<1:0> — NSS 0-00 00-0 0-00 00-0
90Fh DAC1CON1 — — — DAC1R<4:0> ---0 0000 ---0 0000
910h
— — Unimplemented — —
91Eh
91Fh ZCDCON ZCDSEN — ZCDOUT ZCDPOL — — ZCDINTP ZCDINTN 0-x0 --00 0-x0 --00
Legend: x = unknown, u = unchanged, q = depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’.
Preliminary

PIC16(L)F15313/23
DS40001897A-page 57
 TABLE 4-10: SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-63 (CONTINUED)
 2017 Microchip Technology Inc.

Value on: Value on:

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
POR, BOR MCLR

Bank 19

CPU CORE REGISTERS; see Table 4-3 for specifics

98Ch — Unimplemented — —
98Dh — Unimplemented — —
98Eh — Unimplemented — —
98Fh CMOUT — — — — — — MC2OUT MC1OUT ---- --00 ---- --00
990h CM1CON0 EN OUT — POL — — HYS SYNC 00-0 --00 00-0 --00
991h CM1CON1 — — — — — — INTP INTN ---- --00 ---- --00
992h CM1NCH — — — — — NCH<2:0> ---- -000 ---- -000
993h CM1PCH — — — — — PCH<2:0> ---- -000 ---- -000
994h CM2CON0(1) EN OUT — POL — — HYS SYNC 00-0 --00 00-0 --00
995h CM2CON1(1) — — — — — — INTP INTN ---- --00 ---- --00
996h CM2NCH(1) — — — — — NCH<2:0> ---- -000 ---- -000
Preliminary

997h CM2PCH(1) — — — — — PCH<2:0> ---- -000 ---- -000

994h
— — Unimplemented — —
99Fh
Legend: x = unknown, u = unchanged, q = depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’.
Note 1: Present only on PIC16(L)F15323.

PIC16(L)F15313/23
DS40001897A-page 58
 TABLE 4-10: SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-63 (CONTINUED)
 2017 Microchip Technology Inc.

Value on: Value on:

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
POR, BOR MCLR

Bank 20

CPU CORE REGISTERS; see Table 4-3 for specifics

A0Ch
— — Unimplemented — —
A1Fh
Legend: x = unknown, u = unchanged, q = depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’.
Preliminary

PIC16(L)F15313/23
DS40001897A-page 59
 TABLE 4-10: SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-63 (CONTINUED)
 2017 Microchip Technology Inc.

Value on: Value on:

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
POR, BOR MCLR

Bank 21-59

CPU CORE REGISTERS; see Table 4-3 for specifics

x0Ch/
x8Ch
— — Unimplemented — —
x1Fh/
x9Fh
Legend: x = unknown, u = unchanged, q = depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’.
Preliminary

PIC16(L)F15313/23
DS40001897A-page 60
 TABLE 4-10: SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-63 (CONTINUED)
 2017 Microchip Technology Inc.

Value on: Value on:

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
POR, BOR MCLR

Bank 60

CPU CORE REGISTERS; see Table 4-3 for specifics

1E0Ch — Unimplemented — —
1E0Dh — Unimplemented — —
1E0Eh — Unimplemented — —
1E0Fh CLCDATA — — — — MLC4OUT MLC3OUT MLC2OUT MLC1OUT ---- xxxx ---- uuuu
1E10h CLCCON LC1EN — LC1OUT LC1INTP LC1INTN LC1MODE<2:0> 0-00 0000 0-00 0000
1E11h CLC1POL LC1POL — — — LC1G4POL LC1G3POL LC1G2POL LC1G1POL 0--- xxxx 0--- uuuu
1E12h CLC1SEL0 — — LC1D1S<5:0> --xx xxxx --uu uuuu
1E13h CLC1SEL1 — — LC1D2S<5:0> --xx xxxx --uu uuuu
1E14h CLC1SEL2 — — LC1D3S<5:0> --xx xxxx --uu uuuu
1E15h CLC1SEL3 — — LC1D4S<5:0> --xx xxxx --uu uuuu
1E16h CLC1GLS0 LC1G1D4T LC1G4D3N LC1G1D3T LC1G1D3N LC1G1D2T LC1G1D2N LC1G1D1T LC1G1D1N xxxx xxxx uuuu uuuu
Preliminary

1E17h CLC1GLS1 LC1G2D4T LC1G4D3N LC1G2D3T LC1G2D3N LC1G2D2T LC1G2D2N LC1G2D1T LC1G2D1N xxxx xxxx uuuu uuuu
1E18h CLC1GLS2 LC1G3D4T LC1G4D3N LC1G3D3T LC1G3D3N LC1G3D2T LC1G3D2N LC1G3D1T LC1G3D1N xxxx xxxx uuuu uuuu
1E19h CLC1GLS3 LC1G4D4T LC1G4D3N LC1G4D3T LC1G4D3N LC1G4D2T LC1G4D2N LC1G4D1T LC1G4D1N xxxx xxxx uuuu uuuu
1E1Ah CLC2CON LC2EN — LC2OUT LC2INTP LC2INTN LC2MODE<2:0> 0-00 0000 0-00 0000
1E1Bh CLC2POL LC2POL — — — LC2G4POL LC2G3POL LC2G2POL LC2G1POL 0--- xxxx 0--- uuuu
1E1Ch CLC2SEL0 — — LC2D1S<5:0> --xx xxxx --uu uuuu

PIC16(L)F15313/23
1E1Dh CLC2SEL1 — — LC2D2S<5:0> --xx xxxx --uu uuuu
1E1Eh CLC2SEL2 — — LC2D3S<5:0> --xx xxxx --uu uuuu
1E1Fh CLC2SEL3 — — LC2D4S<5:0> --xx xxxx --uu uuuu
1E20h CLC2GLS0 LC2G1D4T LC2G4D3N LC2G1D3T LC2G1D3N LC2G1D2T LC2G1D2N LC2G1D1T LC2G1D1N xxxx xxxx uuuu uuuu
1E21h CLC2GLS1 LC2G2D4T LC2G4D3N LC2G2D3T LC2G2D3N LC2G2D2T LC2G2D2N LC2G2D1T LC2G2D1N xxxx xxxx uuuu uuuu
1E22h CLC2GLS2 LC2G3D4T LC2G4D3N LC2G3D3T LC2G3D3N LC2G3D2T LC2G3D2N LC2G3D1T LC2G3D1N xxxx xxxx uuuu uuuu
1E23h CLC2GLS3 LC2G4D4T LC2G4D3N LC2G4D3T LC2G4D3N LC2G4D2T LC2G4D2N LC2G4D1T LC2G4D1N xxxx xxxx uuuu uuuu
1E24h CLC3CON LC3EN — LC3OUT LC3INTP LC3INTN LC3MODE 0-00 0000 0-00 0000
1E25h CLC3POL LC3POL — — — LC3G4POL LC3G3POL LC3G2POL LC3G1POL 0--- xxxx 0--- uuuu
DS40001897A-page 61

1E26h CLC3SEL0 — — LC3D1S<5:0> --xx xxxx --uu uuuu

1E27h CLC3SEL1 — — LC3D2S<5:0> --xx xxxx --uu uuuu
1E28h CLC3SEL2 — — LC3D3S<5:0> --xx xxxx --uu uuuu
1E29h CLC3SEL3 — — LC3D4S<5:0> --xx xxxx --uu uuuu
1E2Ah CLC3GLS0 LC3G1D4T LC3G4D3N LC3G1D3T LC3G1D3N LC3G1D2T LC3G1D2N LC3G1D1T LC3G1D1N xxxx xxxx uuuu uuuu
Legend: x = unknown, u = unchanged, q = depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’.
 TABLE 4-10: SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-63 (CONTINUED)
 2017 Microchip Technology Inc.

Value on: Value on:

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
POR, BOR MCLR

Bank 60 (Continued)
1E2Bh CLC3GLS1 LC3G2D4T LC3G4D3N LC3G2D3T LC3G2D3N LC3G2D2T LC3G2D2N LC3G2D1T LC3G2D1N xxxx xxxx uuuu uuuu
1E2Ch CLC3GLS2 LC3G3D4T LC3G4D3N LC3G3D3T LC3G3D3N LC3G3D2T LC3G3D2N LC3G3D1T LC3G3D1N xxxx xxxx uuuu uuuu
1E2Dh CLC3GLS3 LC3G4D4T LC3G4D3N LC3G4D3T LC3G4D3N LC3G4D2T LC3G4D2N LC3G4D1T LC3G4D1N xxxx xxxx uuuu uuuu
1E2Eh CLC4CON LC4EN — LC4OUT LC4INTP LC4INTN LC4MODE<2:0> 0-00 0000 0-00 0000
1E2Fh CLC4POL LC4POL — — — LC4G4POL LC4G3POL LC4G2POL LC4G1POL 0--- xxxx 0--- uuuu
1E30h CLC4SEL0 — — LC4D1S<5:0> --xx xxxx --uu uuuu
1E31h CLC4SEL1 — — LC4D2S<5:0> --xx xxxx --uu uuuu
1E32h CLC4SEL2 — — LC4D3S<5:0> --xx xxxx --uu uuuu
1E33h CLC4SEL3 — — LC4D4S<5:0> --xx xxxx --uu uuuu
1E34h CLC4GLS0 LC4G1D4T LC4G4D3N LC4G1D3T LC4G1D3N LC4G1D2T LC4G1D2N LC4G1D1T LC4G1D1N xxxx xxxx uuuu uuuu
1E35h CLC4GLS1 LC4G2D4T LC4G4D3N LC4G2D3T LC4G2D3N LC4G2D2T LC4G2D2N LC4G2D1T LC4G2D1N xxxx xxxx uuuu uuuu
1E36h CLC4GLS2 LC4G3D4T LC4G4D3N LC4G3D3T LC4G3D3N LC4G3D2T LC4G3D2N LC4G3D1T LC4G3D1N xxxx xxxx uuuu uuuu
1E37h CLC4GLS3 LC4G4D4T LC4G4D3N LC4G4D3T LC4G4D3N LC4G4D2T LC4G4D2N LC4G4D1T LC4G4D1N xxxx xxxx uuuu uuuu
Preliminary

1E38h
— — Unimplemented — —
1E6Fh
Legend: x = unknown, u = unchanged, q = depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’.

PIC16(L)F15313/23
DS40001897A-page 62
 TABLE 4-10: SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-63 (CONTINUED)
 2017 Microchip Technology Inc.

Value on: Value on:

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
POR, BOR MCLR

Bank 61

CPU CORE REGISTERS; see Table 4-3 for specifics

1E8Ch — Unimplemented — —
1E8Dh — Unimplemented — —
1E8Eh — Unimplemented — —
1E8Fh PPSLOCK — — — — — — — PPSLOCKED ---- ---0 ---- ---0
1E90h INTPPS — — INTPPS<5:0> --00 1000 --uu uuuu
1E91h T0CKIPPS — — T0CKIPPS<5:0> --00 0100 --uu uuuu
1E92h T1CKIPPS — — T1CKIPPS<5:0> --01 0000 --uu uuuu
1E93h T1GPPS — — T1GPPS<5:0> --00 1101 --uu uuuu
1E94h
— — Unimplemented — —
1E9Bh
1E9Ch T2INPPS — — T2INPPS<5:0> --01 0011 --uu uuuu
Preliminary

1E9Dh
— — Unimplemented — —
1EA0h
1EA1h CCP1PPS — — CCP1PPS<5:0> --01 0010 --uu uuuu
1EA2h CCP2PPS — — CCP2PPS<5:0> --01 0001 --uu uuuu
1EA3h
— — Unimplemented — —
1EB0h

PIC16(L)F15313/23
1EB1h CWG1PPS — — CWG1PPS<5:0> --00 1000 --uu uuuu
1EB2h
— — Unimplemented — —
1EBAh
1EBBh CLCIN0PPS — — CLCIN0PPS<5:0> --00 0000 --uu uuuu
1EBCh CLCIN1PPS — — CLCIN1PPS<5:0> --00 0001 --uu uuuu
1EBDh CLCIN2PPS — — CLCIN2PPS<5:0> --00 1110 --uu uuuu
1EBEh CLCIN3PPS — — CLCIN3PPS<5:0> --00 1111 --uu uuuu
1EBFh
— — Unimplemented — —
1EC2h
DS40001897A-page 63

1EC3h ADACTPPS — — CLCIN3PPS<5:0> --001100 --uuuuuu

1EC4h — Unimplemented — —
Legend: x = unknown, u = unchanged, q = depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’.
 TABLE 4-10: SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-63 (CONTINUED)
 2017 Microchip Technology Inc.

Value on: Value on:

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
POR, BOR MCLR

Bank 61 (Continued)
1EC5h SSP1CLKPPS — — SSP1CLKPPS<5:0> --01 0011 --uu uuuu
1EC6h SSP1DATPPS — — SSP1DATPPS<5:0> --01 0100 --uu uuuu
1EC7h SSP1SSPPS — — SSP1SSPPS<5:0> --00 0101 --uu uuuu
1ECBh RX1DTPPS — — RX1DTPPS<5:0> --01 0111 --uu uuuu
1ECCh TX1CKPPS — — TX1CKPPS<5:0> --01 0110 --uu uuuu
1ECDh — Unimplemented — —
1ECEh — Unimplemented — —
1ECFh
— — Unimplemented — —
1EEFh
Legend: x = unknown, u = unchanged, q = depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’.
Preliminary

PIC16(L)F15313/23
DS40001897A-page 64
 TABLE 4-10: SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-63 (CONTINUED)
 2017 Microchip Technology Inc.

Value on: Value on:

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
POR, BOR MCLR

Bank 62

CPU CORE REGISTERS; see Table 4-3 for specifics

1F0Ch — Unimplemented — —
1F0Dh — Unimplemented — —
1F0Eh — Unimplemented — —
1F0Fh — Unimplemented — —
1F10h RA0PPS — — — RA0PPS<4:0> ---0 0000 ---u uuuu
1F11h RA1PPS — — — RA1PPS<4:0> ---0 0000 ---u uuuu
1F12h RA2PPS — — — RA2PPS<4:0> ---0 0000 ---u uuuu
1F13h RA3PPS — — — RA3PPS<4:0> ---0 0000 ---u uuuu
1F14h RA4PPS — — — RA4PPS<4:0> ---0 0000 ---u uuuu
1F15h RA5PPS — — — RA5PPS<4:0> ---0 0000 ---u uuuu
1F16h
— — Unimplemented — —
1F1Fh
Preliminary

1F20h RC0PPS(1) — — — RC0PPS<4:0> ---0 0000 ---u uuuu

1F21h RC1PPS(1) — — — RC1PPS<4:0> ---0 0000 ---u uuuu
1F22h RC2PPS(1) — — — RC2PPS<4:0> ---0 0000 ---u uuuu
1F23h RC3PPS(1) — — — RC3PPS<4:0> ---0 0000 ---u uuuu
1F24h RC4PPS(1) — — — RC4PPS<4:0> ---0 0000 ---u uuuu
1F25h RC5PPS(1) — — — RC5PPS<4:0>

PIC16(L)F15313/23
---0 0000 ---u uuuu
Legend: x = unknown, u = unchanged, q = depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’.
Note 1: Present only in PIC16(L)F15323.
DS40001897A-page 65
 TABLE 4-10: SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-63 (CONTINUED)
 2017 Microchip Technology Inc.

Value on: Value on:

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
POR, BOR MCLR

Bank 62 (Continued)
1F38h ANSELA — — ANSA5 ANSA4 — ANSA2 ANSA1 ANSA0 --11 1111 --11 1111
1F39h WPUA — — WPUA5 WPUA4 WPUA3 WPUA2 WPUA1 WPUA0 --00 0000 --00 0000
1F3Ah ODCONA — — ODCA5 ODCA4 — ODCA2 ODCA1 ODCA0 --00 0000 --00 0000
1F3Bh SLRCONA — — SLRA5 SLRA4 — SLRA2 SLRA1 SLRA0 --11 1111 --11 1111
1F3Ch INLVLA — — INLVLA5 INLVLA4 INLVLA3 INLVLA2 INLVLA1 INLVLA0 --11 1111 --11 1111
1F3Dh IOCAP — — IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0 --00 0000 --00 0000
1F3Eh IOCAN — — IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0 --00 0000 --00 0000
1F3Fh IOCAF — — IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0 --00 0000 --00 0000
1F40h
— — Unimplemented — —
1F4Dh
1F4Eh ANSELC(1) — — ANSC5 ANSC4 ANSC3 ANSC2 ANSC1 ANSC0 --11 1111 --11 1111
1F4Fh WPUC(1) — — WPUC5 WPUC4 WPUC3 WPUC2 WPUC1 WPUC0 --00 0000 --00 0000
1F50h ODCONC(1) — — ODCC5 ODCC4 ODCC3 ODCC2 ODCC1 ODCC0 --00 0000 --00 0000
Preliminary

1F51h SLRCONC(1) — — SLRC5 SLRC4 SLRC3 SLRC2 SLRC1 SLRC0 --11 1111 --11 1111
1F52h INLVLC(1) — — INLVLC5 INLVLC4 INLVLC3 INLVLC2 INLVLC1 INLVLC0 --11 1111 --11 1111
1F53h IOCCP(1) — — IOCCP5 IOCCP4 IOCCP3 IOCCP2 IOCCP1 IOCCP0 --00 0000 --00 0000
1F54h IOCCN(1) — — IOCCN5 IOCCN4 IOCCN3 IOCCN2 IOCCN1 IOCCN0 --00 0000 --00 0000
1F55h IOCCF(1) — — IOCCF5 IOCCF4 IOCCF3 IOCCF2 IOCCF1 IOCCF0 --00 0000 --00 0000
1F56h
— — Unimplemented — —

PIC16(L)F15313/23
1F6Fh
Legend: x = unknown, u = unchanged, q = depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’.
Note 1: Present only in PIC16(L)F15323.
DS40001897A-page 66
 TABLE 4-10: SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-63 (CONTINUED)
 2017 Microchip Technology Inc.

Value on: Value on:

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
POR, BOR MCLR

Bank 63

CPU CORE REGISTERS; see Table 4-3 for specifics

1F8Ch
— — Unimplemented — —
1FE3h
1FE4h STATUS_SHAD — — — — — Z DC C ---- -xxx ---- -uuu
1FE5h WREG_SHAD Working Register Shadow xxxx xxxx uuuu uuuu
1FE6h BSR_SHAD — — — Bank Select Register Shadow ---x xxxx ---u uuuu
1FE7h PCLATH_SHAD — Program Counter Latch High Register Shadow -xxx xxxx uuuu uuuu
1FE8h FSR0L_SHAD Indirect Data Memory Address 0 Low Pointer Shadow xxxx xxxx uuuu uuuu
1FE9h FSR0H_SHAD Indirect Data Memory Address 0 High Pointer Shadow xxxx xxxx uuuu uuuu
1FEAh FSR1L_SHAD Indirect Data Memory Address 1 Low Pointer Shadow xxxx xxxx uuuu uuuu
1FEBh FSR1H_SHAD Indirect Data Memory Address 1 High Pointer Shadow xxxx xxxx uuuu uuuu
1FECh — Unimplemented — —
Preliminary

1FEDh STKPTR — — — Current Stack Pointer ---1 1111 ---1 1111

1FEEh TOSL Top of Stack Low byte xxxx xxxx uuuu uuuu
1FEFh TOSH — Top of Stack High byte -xxx xxxx -uuu uuuu
Legend: x = unknown, u = unchanged, q = depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’.

PIC16(L)F15313/23
DS40001897A-page 67
 PIC16(L)F15313/23
4.4 PCL and PCLATH 4.4.2 COMPUTED GOTO
The Program Counter (PC) is 15 bits wide. The low byte A computed GOTO is accomplished by adding an offset to
comes from the PCL register, which is a readable and the program counter (ADDWF PCL). When performing a
writable register. The high byte (PC<14:8>) is not directly table read using a computed GOTO method, care should
readable or writable and comes from PCLATH. On any be exercised if the table location crosses a PCL memory
Reset, the PC is cleared. Figure 4-3 shows the five boundary (each 256-byte block). Refer to Application
situations for the loading of the PC. Note AN556, “Implementing a Table Read” (DS00556).

4.4.3 COMPUTED FUNCTION CALLS

FIGURE 4-3: LOADING OF PC IN
DIFFERENT SITUATIONS A computed function CALL allows programs to maintain
tables of functions and provide another way to execute
state machines or look-up tables. When performing a
Rev. 10-000042A
7/30/2013

table read using a computed function CALL, care

14 PCH PCL 0
PC
Instruction should be exercised if the table location crosses a PCL
with PCL as
Destination
memory boundary (each 256-byte block).
7 8
6 0 If using the CALL instruction, the PCH<2:0> and PCL
PCLATH ALU result
registers are loaded with the operand of the CALL
instruction. PCH<6:3> is loaded with PCLATH<6:3>.
14 PCH PCL 0 GOTO, The CALLW instruction enables computed calls by
PC
CALL combining PCLATH and W to form the destination
4 11 address. A computed CALLW is accomplished by
6 0
PCLATH OPCODE <10:0> loading the W register with the desired address and
executing CALLW. The PCL register is loaded with the
value of W and PCH is loaded with PCLATH.
14 PCH PCL 0
PC CALLW
4.4.4 BRANCHING
6
7
0 8 The branching instructions add an offset to the PC.
PCLATH W This allows relocatable code and code that crosses
page boundaries. There are two forms of branching,
14 PCH PCL 0
BRW and BRA. The PC will have incremented to fetch
PC BRW the next instruction in both cases. When using either
branching instruction, a PCL memory boundary may be
15
crossed.
PC + W
If using BRW, load the W register with the desired
14 PCH PCL 0
PC BRA unsigned address and execute BRW. The entire PC will
be loaded with the address PC + 1 + W.
15
If using BRA, the entire PC will be loaded with
PC + OPCODE <8:0>
PC + 1 + the signed value of the operand of the BRA
instruction.
4.4.1 MODIFYING PCL
Executing any instruction with the PCL register as the
destination simultaneously causes the Program
Counter PC<14:8> bits (PCH) to be replaced by the
contents of the PCLATH register. This allows the entire
contents of the program counter to be changed by writ-
ing the desired upper seven bits to the PCLATH regis-
ter. When the lower eight bits are written to the PCL
register, all 15 bits of the program counter will change
to the values contained in the PCLATH register and
those being written to the PCL register.

 2017 Microchip Technology Inc. Preliminary DS40001897A-page 68

 PIC16(L)F15313/23
4.5 Stack 4.5.1 ACCESSING THE STACK
All devices have a 16-level x 15-bit wide hardware The stack is accessible through the TOSH, TOSL and
stack (refer to Figure 4-4 through Figure 4-7). The STKPTR registers. STKPTR is the current value of the
stack space is not part of either program or data space. Stack Pointer. TOSH:TOSL register pair points to the
The PC is PUSHed onto the stack when CALL or TOP of the stack. Both registers are read/writable. TOS
CALLW instructions are executed or an interrupt causes is split into TOSH and TOSL due to the 15-bit size of the
a branch. The stack is POPed in the event of a PC. To access the stack, adjust the value of STKPTR,
RETURN, RETLW or a RETFIE instruction execution. which will position TOSH:TOSL, then read/write to
PCLATH is not affected by a PUSH or POP operation. TOSH:TOSL. STKPTR is five bits to allow detection of
overflow and underflow.
The stack operates as a circular buffer if the STVREN
bit is programmed to ‘0‘ (Configuration Words). This Note: Care should be taken when modifying the
means that after the stack has been PUSHed sixteen STKPTR while interrupts are enabled.
times, the seventeenth PUSH overwrites the value that
During normal program operation, CALL, CALLW and
was stored from the first PUSH. The eighteenth PUSH
interrupts will increment STKPTR while RETLW,
overwrites the second PUSH (and so on). The
RETURN, and RETFIE will decrement STKPTR.
STKOVF and STKUNF flag bits will be set on an
STKPTR can be monitored to obtain to value of stack
Overflow/Underflow, regardless of whether the Reset is
memory left at any given time. The STKPTR always
enabled.
points at the currently used place on the stack.
Note 1: There are no instructions/mnemonics Therefore, a CALL or CALLW will increment the
called PUSH or POP. These are actions STKPTR and then write the PC, and a return will
that occur from the execution of the unload the PC value from the stack and then
CALL, CALLW, RETURN, RETLW and decrement the STKPTR.
RETFIE instructions or the vectoring to Reference Figure 4-4 through Figure 4-7 for examples
an interrupt address. of accessing the stack.

FIGURE 4-4: ACCESSING THE STACK EXAMPLE 1

Rev. 10-000043A
7/30/2013

Stack Reset Disabled

TOSH:TOSL 0x0F STKPTR = 0x1F
(STVREN = 0)
0x0E
0x0D
0x0C
0x0B
Initial Stack Configuration:
0x0A
0x09 After Reset, the stack is empty. The
empty stack is initialized so the Stack
0x08 Pointer is pointing at 0x1F. If the Stack
0x07 Overflow/Underflow Reset is enabled, the
TOSH/TOSL register will return ‘0’. If the
0x06 Stack Overflow/Underflow Reset is
0x05 disabled, the TOSH/TOSL register will
return the contents of stack address
0x04 0x0F.
0x03
0x02
0x01
0x00
Stack Reset Enabled
TOSH:TOSL 0x1F 0x0000 STKPTR = 0x1F
(STVREN = 1)

 2017 Microchip Technology Inc. Preliminary DS40001897A-page 69

 PIC16(L)F15313/23
FIGURE 4-5: ACCESSING THE STACK EXAMPLE 2
Rev. 10-000043B
7/30/2013

0x0F
0x0E
0x0D
0x0C
0x0B
0x0A
0x09 This figure shows the stack configuration
after the first CALL or a single interrupt.
0x08 If a RETURN instruction is executed, the
0x07 return address will be placed in the
Program Counter and the Stack Pointer
0x06 decremented to the empty state (0x1F).
0x05
0x04
0x03
0x02
0x01
TOSH:TOSL 0x00 Return Address STKPTR = 0x00

FIGURE 4-6: ACCESSING THE STACK EXAMPLE 3

Rev. 10-000043C
7/30/2013

0x0F
0x0E
0x0D
0x0C
After seven CALLs or six CALLs and an
0x0B interrupt, the stack looks like the figure on
the left. A series of RETURN instructions will
0x0A
repeatedly place the return addresses into
0x09 the Program Counter and pop the stack.
0x08
0x07
TOSH:TOSL 0x06 Return Address STKPTR = 0x06

0x05 Return Address

0x04 Return Address
0x03 Return Address
0x02 Return Address
0x01 Return Address
0x00 Return Address

 2017 Microchip Technology Inc. Preliminary DS40001897A-page 70

 PIC16(L)F15313/23
FIGURE 4-7: ACCESSING THE STACK EXAMPLE 4
Rev. 10-000043D
7/30/2013

0x0F Return Address

0x0E Return Address
0x0D Return Address
0x0C Return Address
0x0B Return Address
0x0A Return Address When the stack is full, the next CALL or
0x09 Return Address an interrupt will set the Stack Pointer to
0x10. This is identical to address 0x00 so
0x08 Return Address the stack will wrap and overwrite the
0x07 Return Address return address at 0x00. If the Stack
Overflow/Underflow Reset is enabled, a
0x06 Return Address Reset will occur and location 0x00 will
0x05 Return Address not be overwritten.

0x04 Return Address

0x03 Return Address
0x02 Return Address
0x01 Return Address
TOSH:TOSL 0x00 Return Address STKPTR = 0x10

4.5.2 OVERFLOW/UNDERFLOW RESET

If the STVREN bit in Configuration Words
(Register 5-2) is programmed to ‘1’, the device will be
Reset if the stack is PUSHed beyond the sixteenth
level or POPed beyond the first level, setting the
appropriate bits (STKOVF or STKUNF, respectively) in
the PCON register.

4.6 Indirect Addressing

The INDFn registers are not physical registers. Any
instruction that accesses an INDFn register actually
accesses the register at the address specified by the
File Select Registers (FSR). If the FSRn address
specifies one of the two INDFn registers, the read will
return ‘0’ and the write will not occur (though Status bits
may be affected). The FSRn register value is created
by the pair FSRnH and FSRnL.
The FSR registers form a 16-bit address that allows an
addressing space with 65536 locations. These locations
are divided into three memory regions:
• Traditional/Banked Data Memory
• Linear Data Memory
• Program Flash Memory

 2017 Microchip Technology Inc. Preliminary DS40001897A-page 71

 PIC16(L)F15313/23
FIGURE 4-8: INDIRECT ADDRESSING PIC16(L)F15313/23

Rev. 10-000044F
1/13/2017

0x0000 0x0000

Traditional
Data Memory

0x1FFF
0x2000

Linear
Data Memory

0X2FEF
0X2FF0
Reserved
0x7FFF
FSR
0x8000 PC value = 0x000
Address
Range

Program
Flash Memory

0x87FF PC value = 0x7FF

 2017 Microchip Technology Inc. Preliminary DS40001897A-page 72

 PIC16(L)F15313/23
4.6.1 TRADITIONAL/BANKED DATA
MEMORY
The traditional or banked data memory is a region from
FSR address 0x000 to FSR address 0x1FFF. The
addresses correspond to the absolute addresses of all
SFR, GPR and common registers.

FIGURE 4-9: TRADITIONAL/BANKED DATA MEMORY MAP

Rev. 10-000056B
12/14/2016

Direct Addressing Indirect Addressing

From Opcode
5 BSR 0 6 0 7 FSRxH 0 7 FSRxL 0
0 0 0

Bank Select Location Select Bank Select Location Select

000000 000001 000010 111111

0x00

0x7F
Bank 0 Bank 1 Bank 2 Bank 63

 2017 Microchip Technology Inc. Preliminary DS40001897A-page 73

 PIC16(L)F15313/23
4.6.2 LINEAR DATA MEMORY 4.6.3 PROGRAM FLASH MEMORY
The linear data memory is the region from FSR To make constant data access easier, the entire
address 0x2000 to FSR address 0X2FEF. This region Program Flash Memory is mapped to the upper half of
is a virtual region that points back to the 80-byte blocks the FSR address space. When the MSB of FSRnH is
of GPR memory in all the banks. Refer to Figure 4-10 set, the lower 15 bits are the address in program
for the Linear Data Memory Map. memory which will be accessed through INDF. Only the
lower eight bits of each memory location is accessible
Note: The address range 0x2000 to 0x2FF0 rep-
via INDF. Writing to the Program Flash Memory cannot
resents the complete addressable Linear
be accomplished via the FSR/INDF interface. All
Data Memory up to Bank 50. The actual
instructions that access Program Flash Memory via the
implemented Linear Data Memory will dif-
FSR/INDF interface will require one additional
fer from one device to the other in a family.
instruction cycle to complete.
Confirm the memory limits on every
device.
FIGURE 4-11: PROGRAM FLASH
Unimplemented memory reads as 0x00. Use of the MEMORY MAP
linear data memory region allows buffers to be larger
than 80 bytes because incrementing the FSR beyond Rev. 10-000058A
7/31/2013

one bank will go directly to the GPR memory of the next

bank. 7 FSRnH 0 7 FSRnL 0
1
The 16 bytes of common memory are not included in
Location Select
the linear data memory region. 0x8000
0x0000

FIGURE 4-10: LINEAR DATA MEMORY

MAP
Rev. 10-000057B
8/24/2016
Program
Flash
Memory
(low 8 bits)
7 FSRnH 0 7 FSRnL 0

Location Select
0x2000
0x020
Bank 0
0x06F
0x7FFF
0x0A0 0xFFFF
Bank 1
0x0EF
0x120
Bank 2
0x16F

0x1920
Bank 50
0x196F
0x2FEF

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 PIC16(L)F15313/23
5.0 DEVICE CONFIGURATION
Device configuration consists of the Configuration
Words, User ID, Device ID, Device Information Area
(DIA), (see Section 6.0 “Device Information Area”),
and the Device Configuration Information (DCI)
regions, (see Section 7.0 “Device Configuration
Information”).

5.1 Configuration Words

The devices have several Configuration Words
starting at address 8007h. The Configuration bits
establish configuration values prior to the execution of
any software; Configuration bits enable or disable
device-specific features.
In terms of programming, these important
Configuration bits should be considered:
1. LVP: Low-Voltage Programming Enable bit
• 1 = ON – Low-Voltage Programming is enabled.
MCLR/VPP pin function is MCLR. MCLRE
Configuration bit is ignored.
• 0 = OFF – HV on MCLR/VPP must be used for
programming.
2. CP: User Nonvolatile Memory (NVM)
Program Memory Code Protection bit
• 1 = OFF – User NVM code protection disabled
• 0 = ON – User NVM code protection enabled

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5.2 Register Definitions: Configuration Words

REGISTER 5-1: CONFIGURATION WORD 1: OSCILLATORS

R/P-1 U-1 R/P-1 U-1 U-1 R/P-1
FCMEN — CSWEN — — CLKOUTEN
bit 13 bit 8

U-1 R/P-1 R/P-1 R/P-1 U-1 R/P-1 R/P-1 R/P-1

— RSTOSC2 RSTOSC1 RSTOSC0 — FEXTOSC2 FEXTOSC1 FEXTOSC0
bit 7 bit 0

Legend:
R = Readable bit P = Programmable bit x = Bit is unknown U = Unimplemented bit, read as
‘1’
‘0’ = Bit is cleared ‘1’ = Bit is set W = Writable bit n = Value when blank or after Bulk
Erase

bit 13 FCMEN: Fail-Safe Clock Monitor Enable bit

1 = FSCM timer enabled
0 = FSCM timer disabled
bit 12 Unimplemented: Read as ‘1’
bit 11 CSWEN: Clock Switch Enable bit
1 = Writing to NOSC and NDIV is allowed
0 = The NOSC and NDIV bits cannot be changed by user software
bit 10-9 Unimplemented: Read as ‘1’
bit 8 CLKOUTEN: Clock Out Enable bit
If FEXTOSC = EC (high, mid or low) or Not Enabled:
1 = CLKOUT function is disabled; I/O or oscillator function on OSC2
0 = CLKOUT function is enabled; FOSC/4 clock appears at OSC2
Otherwise:
This bit is ignored.
bit 7 Unimplemented: Read as ‘1’
bit 6-4 RSTOSC<2:0>: Power-up Default Value for COSC bits
This value is the Reset-default value for COSC and selects the oscillator first used by user software.
111 = EXTOSC operating per FEXTOSC bits (device manufacturing default)
110 = HFINTOSC with HFFRQ = 3’b010
101 = LFINTOSC
100 = Reserved
011 = Reserved
010 = EXTOSC with 4x PLL, with EXTOSC operating per FEXTOSC bits
001 = EXTOSC with 2x PLL, with EXTOSC operating per FEXTOSC bits
000 = HFINTOSC with CDIV = 1:1 and HFFRQ = 3’b110
bit 3 Unimplemented: Read as ‘1’
bit 2-0 FEXTOSC<2:0>:FEXTOSC External Oscillator Mode Selection bits
111 = EC (External Clock) above 8 MHz; PFM set to high power (device manufacturing default)
110 = EC (External Clock) for 100 kHz to 8 MHz; PFM set to medium power
101 = EC (External Clock) below 100 kHz
100 = Oscillator not enabled
011 = Reserved (do not use)
010 = HS (Crystal oscillator) above 4 MHz; PFM set to high power
001 = XT (Crystal oscillator) above 100 kHz, below 4 MHz; PFM set to medium power
000 = LP (Crystal oscillator) optimized for 32.768 kHz; PFM set to low power

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 PIC16(L)F15313/23
REGISTER 5-2: CONFIGURATION WORD 2: SUPERVISORS
R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 U-1
DEBUG STVREN PPS1WAY ZCDDIS BORV —
bit 13 bit 8

R/P-1 R/P-1 R/P-1 U-1 U-1 U-1 R/P-1 R/P-1

BOREN1 BOREN0 LPBOREN — — — PWRTE MCLRE
bit 7 bit 0

Legend:
R = Readable bit P = Programmable bit x = Bit is unknown U = Unimplemented bit, read as
‘1’
‘0’ = Bit is cleared ‘1’ = Bit is set W = Writable bit n = Value when blank or after Bulk
Erase
bit 13 DEBUG: Debugger Enable bit
1 = Background debugger disabled
0 = Background debugger enabled
bit 12 STVREN: Stack Overflow/Underflow Reset Enable bit
1 = Stack Overflow or Underflow will cause a Reset
0 = Stack Overflow or Underflow will not cause a Reset
bit 11 PPS1WAY: PPSLOCK One-Way Set Enable bit
1 = The PPSLOCK bit can be cleared and set only once; PPS registers remain locked after one clear/set cycle
0 = The PPSLOCK bit can be set and cleared repeatedly (subject to the unlock sequence)
bit 10 ZCDDIS: Zero-Cross Detect Disable bit
1 = ZCD disabled. ZCD can be enabled by setting the ZCDSEN bit of the ZCDCON register
0 = ZCD always enabled (ZCDSEN bit is ignored)
bit 9 BORV: Brown-out Reset Voltage Selection bit(1)
1 = Brown-out Reset voltage (VBOR) set to lower trip point level
0 = Brown-out Reset voltage (VBOR) set to higher trip point level
bit 8 Unimplemented: Read as ‘1’
bit 7-6 BOREN<1:0>: Brown-out Reset Enable bits
When enabled, Brown-out Reset Voltage (VBOR) is set by the BORV bit
11 = Brown-out Reset is enabled; SBOREN bit is ignored
10 = Brown-out Reset is enabled while running, disabled in Sleep; SBOREN bit is ignored
01 = Brown-out Reset is enabled according to SBOREN
00 = Brown-out Reset is disabled
bit 5 LPBOREN: Low-Power BOR Enable bit
1 = ULPBOR is disabled
0 = ULPBOR is enabled
bit 4-2 Unimplemented: Read as ‘1’
bit 1 PWRTE: Power-up Timer Enable bit
1 = PWRT is disabled
0 = PWRT is enabled
bit 0 MCLRE: Master Clear (MCLR) Enable bit
If LVP = 1:
RE3 pin function is MCLR (it will reset the device when driven low)
If LVP = 0:
1 = MCLR pin is MCLR (it will reset the device when driven low)
0 = MCLR pin may be used as general purpose RE3 input
Note 1: See Vbor parameter for specific trip point voltages.
2: The DEBUG bit in Configuration Words is managed automatically by device development tools including debuggers
and programmers. For normal device operation, this bit should be maintained as a ‘1’.

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REGISTER 5-3: CONFIGURATION WORD 3: WINDOWED WATCHDOG

R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1
WDTCCS2 WDTCCS1 WDTCCS0 WDTCWS2 WDTCWS1 WDTCWS0
bit 13 bit 8

U-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1

— WDTE1 WDTE0 WDTCPS4 WDTCPS3 WDTCPS2 WDTCPS1 WDTCPS0
bit 7 bit 0

Legend:
R = Readable bit P = Programmable bit x = Bit is unknown U = Unimplemented bit, read as ‘1’
‘0’ = Bit is cleared ‘1’ = Bit is set W = Writable bit n = Value when blank or after Bulk
Erase

bit 13-11 WDTCCS<2:0>: WDT Input Clock Selector bits

111 = Software Control
110 = Reserved
.
.
.
.
010 = Reserved
001 = WDT reference clock is the 31.0 kHz LFINTOSC
000 = WDT reference clock is the 31.25 kHz HFINTOSC (MFINTOSC) output
bit 10-8 WDTCWS<2:0>: WDT Window Select bits

WDTWS at POR
Software Keyed
WDTCWS Window control of access
Window delay
Value opening WDTWS? required?
Percent of time
Percent of time
111 111 n/a 100 Yes No
110 111 n/a 100
101 101 25 75
100 100 37.5 62.5
011 011 50 50 No Yes
010 010 62.5 37.5
001 001 75 25
000 000 87.5 12.5

bit 7 Unimplemented: Read as ‘1’

bit 6-5 WDTE<1:0>: WDT Operating mode:
11 =WDT enabled regardless of Sleep; SWDTEN is ignored
10 =WDT enabled while Sleep = 0, suspended when Sleep = 1; SWDTEN ignored
01 =WDT enabled/disabled by SWDTEN bit in WDTCON0
00 =WDT disabled, SWDTEN is ignored

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 PIC16(L)F15313/23
REGISTER 5-3: CONFIGURATION WORD 3: WINDOWED WATCHDOG (CONTINUED)
bit 4-0 WDTCPS<4:0>: WDT Period Select bits

WDTPS at POR
Software Control
WDTCPS Typical Time Out
Value Divider Ratio of WDTPS?
(FIN = 31 kHz)
11111(1) 01011 1:65536 216 2s Yes
11110 11110
... ... 1:32 25 1 ms No
10011 10011
10010 10010 1:8388608 223 256 s
10001 10001 1:4194304 222 128 s
10000 10000 1:2097152 221 64 s
01111 01111 1:1048576 220 32 s
19
01110 01110 1:524299 2 16 s
01101 01101 1:262144 218 8s
17
01100 01100 1:131072 2 4s
01011 01011 1:65536 216 2s
01010 01010 1:32768 215 1s
01001 01001 1:16384 214 512 ms No
01000 01000 1:8192 213 256 ms
00111 00111 1:4096 212 128 ms
11
00110 00110 1:2048 2 64 ms
00101 00101 1:1024 210 32 ms
00100 00100 1:512 29 16 ms
00011 00011 1:256 28 8 ms
00010 00010 1:128 27 4 ms
00001 00001 1:64 26 2 ms
5
00000 00000 1:32 2 1 ms

Note 1: 0b11111 is the default value of the WDTCPS bits.

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 PIC16(L)F15313/23
REGISTER 5-4: CONFIGURATION WORD 4: MEMORY
R/W-1 U-1 R/W-1 U-1 R/W-1 R/W-1
(1) (1)
LVP — WRTSAF — WRTC WRTB(1)
bit 13 12 11 10 9 bit 8

R/W-1 U-1 U-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

WRTAPP(1) — — SAFEN(1) BBEN(1) BBSIZE2 BBSIZE1 BBSIZE0
bit 7 6 5 4 3 2 1 bit 0

Legend:
R = Readable bit P = Programmable bit x = Bit is unknown U = Unimplemented bit, read
as ‘1’
‘0’ = Bit is cleared ‘1’ = Bit is set W = Writable bit n = Value when blank or after
Bulk Erase

bit 13 LVP: Low Voltage Programming Enable bit

1 = Low voltage programming enabled. MCLR/VPP pin function is MCLR. MCLRE Configuration bit is ignored.
0 = HV on MCLR/VPP must be used for programming.
The LVP bit cannot be written (to zero) while operating from the LVP programming interface. The purpose of this
rule is to prevent the user from dropping out of LVP mode while programming from LVP mode, or accidentally
eliminating LVP mode from the configuration state.
The preconditioned (erased) state for this bit is critical.
bit 12 Unimplemented: Read as ‘1’
bit 11 WRTSAF: Storage Area Flash Write Protection bit
1 = SAF NOT write-protected
0 = SAF write-protected
Unimplemented, if SAF is not supported in the device family and only applicable if SAFEN = 0.
bit 10 Unimplemented: Read as ‘1’
bit 9 WRTC: Configuration Register Write Protection bit
1 = Configuration Register NOT write-protected
0 = Configuration Register write-protected
bit 8 WRTB: Boot Block Write Protection bit
1 = Boot Block NOT write-protected
0 = Boot Block write-protected
Only applicable if BBEN = 0.
bit 7 WRTAPP: Application Block Write Protection bit
1 = Application Block NOT write-protected
0 = Application Block write-protected
bit 6-5 Unimplemented: Read as ‘1’
bit 4 SAFEN: SAF Enable bit
1 = SAF disabled
0 = SAF enabled
bit 3 BBEN: Boot Block Enable bit
1 = Boot Block disabled
0 = Boot Block enabled
bit 2-0 BBSIZE<2:0>: Boot Block Size Selection bits (See Table 5-1)
BBSIZE is used only when BBEN = 0
BBSIZ bits can only be written while BBEN = 1; after BBEN = 0, BBSIZ is write-protected.

Note 1: Bits are implemented as sticky bits. Once protection is enabled, it can only be reset through a Bulk Erase.

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TABLE 5-1: BOOT BLOCK SIZE BITS
Actual Boot Block Size
User Program Memory Size (words) Last Boot Block
BBEN BBSIZE<2:0>
Memory Access

1 xxx 0 —
0 111 512 01FFh
0 110-000 1024 03FFh
Note: The maximum boot block size is half the user program memory size. All selections higher than the
maximum are set to half size. For example, all BBSIZE = 000 - 100 produce a boot block size of 4kW on
a 8kW device.

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 PIC16(L)F15313/23

REGISTER 5-5: CONFIGURATION WORD 5: CODE PROTECTION

U-1 U-1 U-1 U-1 U-1 U-1
— — — — — —
bit 13 bit 8

U-1 U-1 U-1 U-1 U-1 U-1 U-1 R/P-1

— — — — — — — CP
bit 7 bit 0

Legend:
R = Readable bit P = Programmable bit x = Bit is unknown U = Unimplemented bit, read as ‘1’
‘0’ = Bit is cleared ‘1’ = Bit is set W = Writable bit n = Value when blank or after Bulk
Erase

bit 13-1 Unimplemented: Read as ‘1’

bit 0 CP: Program Flash Memory Code Protection bit
1 = Program Flash Memory code protection disabled
0 = Program Flash Memory code protection enabled

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 PIC16(L)F15313/23
5.3 Code Protection
Code protection allows the device to be protected from
unauthorized access. Program memory protection and
data memory are controlled independently. Internal
access to the program memory is unaffected by any
code protection setting.

5.3.1 PROGRAM MEMORY PROTECTION

The entire program memory space is protected from
external reads and writes by the CP bit in Configuration
Words. When CP = 0, external reads and writes of
program memory are inhibited and a read will return all
‘0’s. The CPU can continue to read program memory,
regardless of the protection bit settings. Self-writing the
program memory is dependent upon the write
protection setting. See Section 5.4 “Write
Protection” for more information.

5.4 Write Protection

Write protection allows the device to be protected from
unintended self-writes. Applications, such as boot
loader software, can be protected while allowing other
regions of the program memory to be modified.
The WRTAPP, WRTSAF, WRTB, WRTC bits in
Configuration Words (Register 5-4) define whether the
corresponding region of the program memory block is
protected or not.

5.5 User ID
Four memory locations (8000h-8003h) are designated
as ID locations where the user can store checksum or
other code identification numbers. These locations are
readable and writable during normal execution. See
Section 13.3.6 “NVMREG Access to Device
Information Area, Device Configuration Area, User
ID, Device ID and Configuration Words” for more
information on accessing these memory locations. For
more information on checksum calculation, see the
“PIC16(L)F153xx Memory Programming Specification”
(DS40001838).

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 PIC16(L)F15313/23
5.6 Device ID and Revision ID
The 14-bit Device ID word is located at 8006h and the
14-bit Revision ID is located at 8005h. These locations
are read-only and cannot be erased or modified.
Development tools, such as device programmers and
debuggers, may be used to read the Device ID,
Revision ID and Configuration Words. These locations
can also be read from the NVMCON register.

5.7 Register Definitions: Device and Revision

REGISTER 5-6: DEVID: DEVICE ID REGISTER

R R R R R R
DEV<13:8>
bit 13 bit 8

R R R R R R R R
DEV<7:0>
bit 7 bit 0

Legend:
R = Readable bit
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 13-0 DEV<13:0>: Device ID bits

Device DEVID<13:0> Values

PIC16F15313 11 0000 1011 1110 (30BEh)
PIC16LF15313 11 0000 1011 1111 (30BFh)
PIC16F15323 11 0000 1100 0000 (30C0h)
PIC16LF15323 11 0000 1100 0001 (30C1h)

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 PIC16(L)F15313/23

REGISTER 5-7: REVISIONID: REVISION ID REGISTER

R R R R R R R R R R R R R R
1 0 MJRREV<5:0> MNRREV<5:0>
bit 13 bit 0

Legend:
R = Readable bit
‘0’ = Bit is cleared ‘1’ = Bit is set x = Bit is unknown

bit 13-12 Fixed Value: Read-only bits

These bits are fixed with value ‘10’ for all devices included in this data sheet.
bit 11-6 MJRREV<5:0>: Major Revision ID bits
These bits are used to identify a major revision.
bit 5-0 MNRREV<5:0>: Minor Revision ID bits
These bits are used to identify a minor revision.

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 PIC16(L)F15313/23
6.0 DEVICE INFORMATION AREA The complete DIA table is shown in Table 6-1: Device
Information Area, followed by a description of each
The Device Information Area (DIA) is a dedicated region and its functionality. The data is mapped from
region in the program memory space; it is a new feature 8100h to 811Fh in the PIC16(L)F15313/23 family.
in the PIC16(L)F15313/23 family of devices. The DIA These locations are read-only and cannot be erased or
contains the calibration data for the internal modified. The data is programmed into the device
temperature indicator module, stores the Microchip during manufacturing.
Unique Identifier words and the Fixed Voltage
Reference voltage readings measured in mV.

TABLE 6-1: DEVICE INFORMATION AREA

Address Range Name of Region Standard Device Information
MUI0
MUI1
MUI2
MUI3
8100h-8108h MUI4 Microchip Unique Identifier (9 Words)
MUI5
MUI6
MUI7
MUI8
8109h MUI9 1 Word Reserved
EUI0
EUI1
EUI2
EUI3
810Ah-8111h Unassigned (8 Words)
EUI4
EUI5
EUI6
EUI7
8112h TSLR1 Unassigned (1 word)
8113h TSLR2 Temperature indicator ADC reading at 90°C (low range setting)
8114h TSLR3 Unassigned (1 word)
8115h TSHR1 Unassigned (1 word)
8116h TSHR2 Temperature indicator ADC reading at 90°C (high range setting)
8117h TSHR3 Unassigned (1 Word)
8118h FVRA1X ADC FVR1 Output voltage for 1x setting (in mV)
8119h FVRA2X ADC FVR1 Output Voltage for 2x setting (in mV)
811Ah FVRA4X(1) ADC FVR1 Output Voltage for 4x setting (in mV)
811Bh FVRC1X Comparator FVR2 output voltage for 1x setting (in mV)
811Ch FVRC2X Comparator FVR2 output voltage for 2x setting (in mV)
811Dh FVRC4X(1) Comparator FVR2 output voltage for 4x setting (in mV)
811Eh-811Fh Unassigned (2 Words)
Note 1: Value not present on LF devices.

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6.1 Microchip Unique identifier (MUI) 6.3 Analog-to-Digital Conversion Data
The PIC16(L)F15313/23 devices are individually
of the Temperature Sensor
encoded during final manufacturing with a Microchip The purpose of the temperature indicator module is to
Unique Identifier, or MUI. The MUI cannot be erased by provide a temperature-dependent voltage that can be
a Bulk Erase command or any other user-accessible measured by an analog module. Section 19.0 “Tem-
means. This feature allows for manufacturing traceabil- perature Indicator Module” explains the operation of
ity of Microchip Technology devices in applications the Temperature Indicator module and defines terms
where this is a required. It may also be used by the such as the low range and high range settings of the
application manufacturer for a number of functions that sensor.
require unverified unique identification, such as:
The DIA table contains the internal ADC measurement
• Tracking the device values of the temperature sensor for low and high
• Unique serial number range at fixed points of reference. The values are
The MUI consists of nine program words. When taken measured during test and are unique to each device.
together, these fields form a unique identifier. The MUI The right-justified ADC readings are stored in the DIA
is stored in nine read-only locations, located between memory region. The calibration data can be used to
8100h to 8109h in the DIA space. Table 6-1 lists the plot the approximate sensor output voltage, VTSENSE
addresses of the identifier words. vs. Temperature curve.
• TSLR<3:1>: Address 8112h to 8114h store the
Note: For applications that require verified unique
measurements for the low range setting of the
identification, contact your Microchip Tech-
temperature sensor at VDD = 3V.
nology sales office to create a Serialized
• TSHR<3:1>: Address 8115h to 8117h store the
Quick Turn Programming option.
measurements for the high range setting of the
temperature sensor at VDD = 3V.
6.2 External Unique Identifier (EUI) The stored measurements are made by the device
The EUI data is stored at locations 810Ah to 8111h in ADC using the internal VREF = 2.048V.
the program memory region. This region is an optional
space for placing application specific information. The 6.4 Fixed Voltage Reference Data
data is coded per customer requirements during
manufacturing. The EUI cannot be erased by a Bulk The Fixed Voltage Reference, or FVR, is a stable
Erase command. voltage reference, independent of VDD, with 1.024V,
2.048V or 4.096V selectable output levels. The output
of the FVR can be configured to supply a reference
Note: Data is stored in this address range on voltage to the following:
receiving a request from the customer. • ADC input channel
The customer may contact the local sales • ADC positive reference
representative or Field Applications • Comparator positive input
Engineer, and provide them the unique • Digital-to-Analog Converter
identifier information that is required to be
For more information on the FVR, refer to Section 18.0
stored in this region.
“Fixed Voltage Reference (FVR)”.
The DIA stores measured FVR voltages for this device
in mV for the different buffer settings of 1x, 2x or 4x at
program memory locations 8118h to 811Dh.
• FVRA1X stores the value of ADC FVR1 Output
voltage for 1x setting (in mV)
• FVRA2X stores the value of ADC FVR1 Output
Voltage for 2x setting (in mV)
• FVRA4X stores the value of ADC FVR1 Output
Voltage for 4x setting (in mV)
• FVRC1X stores the value of Comparator FVR2
output voltage for 1x setting (in mV)
• FVRC2X stores the value of Comparator FVR2
output voltage for 2x setting (in mV)
• FVRC4X stores the value of Comparator FVR2
output voltage for 4x setting (in mV)

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 PIC16(L)F15313/23
7.0 DEVICE CONFIGURATION Refer to Table 7-1 for the complete DCI table address
and description. The DCI holds information about the
INFORMATION
device which is useful for programming and bootloader
The Device Configuration Information (DCI) is a applications. These locations are read-only and cannot
dedicated region in the Program Flash Memory be erased or modified.
mapped from 8200h to 821Fh. The data stored in the
DCI memory is hard-coded into the device during
manufacturing.
TABLE 7-1: DEVICE CONFIGURATION INFORMATION FOR PIC16(L)F15313/23 DEVICES
VALUE
ADDRESS Name DESCRIPTION UNITS

8200h ERSIZ Erase Row Size 32 Words

8201h WLSIZ Number of write latches 32 Latches
8202h URSIZ Number of User Rows 64 Rows
8203h EESIZ EE Data memory size 0 Bytes
8204h PCNT Pin Count 8/14 Pins

7.1 DIA and DCI Access

The DIA and DCI data are read-only and cannot be
erased or modified. See 13.3.6 “NVMREG Access to
Device Information Area, Device Configuration
Area, User ID, Device ID and Configuration Words”
for more information on accessing these memory
locations.
Development tools, such as device programmers and
debuggers, may be used to read the DIA and DCI
regions, similar to the Device ID and Revision ID.

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 PIC16(L)F15313/23
8.0 RESETS A simplified block diagram of the On-Chip Reset Circuit
is shown in Figure 8-1.
There are multiple ways to reset this device:
• Power-on Reset (POR)
• Brown-out Reset (BOR)
• Low-Power Brown-out Reset (LPBOR)
• MCLR Reset
• WDT Reset
• RESET instruction
• Stack Overflow
• Stack Underflow
• Programming mode exit
• Memory Violation Reset (MEMV)
To allow VDD to stabilize, an optional Power-up Timer
can be enabled to extend the Reset time after a BOR
or POR event.

FIGURE 8-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

Rev. 10-000006F
8/30/2016

ICSP™ Programming Mode Exit

RESET Instruction
Memory Violation

Stack Underflow
Stack Overflow

VPP/MCLR MCLRE

WWDT Time-out/
Window violation Device
Reset

Power-on
Reset
VDD

Brown-out
R
Reset(1) Power-up
Timer
LFINTOSC 
PWRTE
LPBOR
Reset

Note 1: See Table 8-1 for BOR active conditions.

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 PIC16(L)F15313/23
8.1 Power-on Reset (POR)
The POR circuit holds the device in Reset until VDD has
reached an acceptable level for minimum operation.
Slow rising VDD, fast operating speeds or analog
performance may require greater than minimum VDD.
The PWRT, BOR or MCLR features can be used to
extend the start-up period until all device operation
conditions have been met.

8.2 Brown-out Reset (BOR)

The BOR circuit holds the device in Reset when VDD
reaches a selectable minimum level. Between the
POR and BOR, complete voltage range coverage for
execution protection can be implemented.
The Brown-out Reset module has four operating
modes controlled by the BOREN<1:0> bits in
Configuration Words. The four operating modes are:
• BOR is always on
• BOR is off when in Sleep
• BOR is controlled by software
• BOR is always off
Refer to Table 8-1 for more information.
The Brown-out Reset voltage level is selectable by
configuring the BORV bit in Configuration Words.
A VDD noise rejection filter prevents the BOR from
triggering on small events. If VDD falls below VBOR for
a duration greater than parameter TBORDC, the device
will reset. See Figure 8-2 for more information.

TABLE 8-1: BOR OPERATING MODES

Instruction Execution upon:
BOREN<1:0> SBOREN Device Mode BOR Mode
Release of POR or Wake-up from Sleep

11 X X Active Wait for release of BOR(1) (BORRDY = 1)

Awake Active Waits for release of BOR (BORRDY = 1)
10 X
Sleep Disabled Waits for BOR Reset release

1 X Active Waits for BOR Reset release (BORRDY = 1)

01
0 X Disabled
Begins immediately (BORRDY = x)
00 X X Disabled
Note 1: In this specific case, “Release of POR” and “Wake-up from Sleep”, there is no delay in start-up. The BOR
ready flag, (BORRDY = 1), will be set before the CPU is ready to execute instructions because the BOR
circuit is forced on by the BOREN<1:0> bits.

8.2.1 BOR IS ALWAYS ON 8.2.2 BOR IS OFF IN SLEEP

When the BOREN bits of Configuration Words are When the BOREN bits of Configuration Words are
programmed to ‘11’, the BOR is always on. The device programmed to ‘10’, the BOR is on, except in Sleep.
start-up will be delayed until the BOR is ready and VDD The device start-up will be delayed until the BOR is
is higher than the BOR threshold. ready and VDD is higher than the BOR threshold.
BOR protection is active during Sleep. The BOR does BOR protection is not active during Sleep. The device
not delay wake-up from Sleep. wake-up will be delayed until the BOR is ready.

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 PIC16(L)F15313/23
8.2.3 BOR CONTROLLED BY SOFTWARE 8.2.4 BOR IS ALWAYS OFF
When the BOREN bits of Configuration Words are When the BOREN bits of the Configuration Words are
programmed to ‘01’, the BOR is controlled by the programmed to ‘00’, the BOR is off at all times. The
SBOREN bit of the BORCON register. The device device start-up is not delayed by the BOR ready
start-up is not delayed by the BOR ready condition or condition or the VDD level.
the VDD level.
BOR protection begins as soon as the BOR circuit is
ready. The status of the BOR circuit is reflected in the
BORRDY bit of the BORCON register.
BOR protection is unchanged by Sleep.

FIGURE 8-2: BROWN-OUT SITUATIONS

VDD
VBOR

Internal
Reset TPWRT(1)

VDD
VBOR

Internal < TPWRT

Reset TPWRT(1)

VDD
VBOR

Internal
Reset TPWRT(1)

Note 1: TPWRT delay only if PWRTE bit is programmed to ‘0’.

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 PIC16(L)F15313/23
8.3 Register Definitions: Brown-out Reset Control
REGISTER 8-1: BORCON: BROWN-OUT RESET CONTROL REGISTER
R/W-1/u U-0 U-0 U-0 U-0 U-0 U-0 R-q/u
(1)
SBOREN — — — — — — BORRDY
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition

bit 7 SBOREN: Software Brown-out Reset Enable bit(1)

If BOREN <1:0> in Configuration Words  01:
SBOREN is read/write, but has no effect on the BOR.
If BOREN <1:0> in Configuration Words = 01:
1 = BOR Enabled
0 = BOR Disabled
bit 6-1 Unimplemented: Read as ‘0’
bit 0 BORRDY: Brown-out Reset Circuit Ready Status bit
1 = The Brown-out Reset circuit is active
0 = The Brown-out Reset circuit is inactive

Note 1: BOREN<1:0> bits are located in Configuration Words.

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 PIC16(L)F15313/23
8.4 Low-Power Brown-out Reset 8.5.2 MCLR DISABLED
(LPBOR) When MCLR is disabled, the pin functions as a general
purpose input and the internal weak pull-up is under
The Low-Power Brown-out Reset (LPBOR) is an
software control. See Section 14.1 “I/O Priorities” for
important part of the Reset subsystem. Refer to
more information.
Figure 8-1 to see how the BOR and LPBOR interact
with other modules.
8.6 Windowed Watchdog Timer
The LPBOR is used to monitor the external VDD pin.
When too low of a voltage is detected, the device is
(WWDT) Reset
held in Reset. The Watchdog Timer generates a Reset if the firmware
does not issue a CLRWDT instruction within the time-out
8.4.1 ENABLING LPBOR period and the window is open. The TO and PD bits in
The LPBOR is controlled by the LPBOR bit of the the STATUS register and the WDT bit in PCON are
Configuration Word (Register 5-1). When the device is changed to indicate a WDT Reset caused by the timer
erased, the LPBOR module defaults to disabled. overflowing, and WDTWV bit in the PCON register is
changed to indicate a WDT Reset caused by a window
8.4.2 LPBOR MODULE OUTPUT violation. See Section 12.0 “Windowed Watchdog
The output of the LPBOR module is a signal indicating Timer (WWDT)” for more information.
whether or not a Reset is to be asserted. When this
occurs, a register bit (BOR) is changed to indicate that 8.7 RESET Instruction
a BOR Reset has occurred. The same bit is set for
A RESET instruction will cause a device Reset. The RI
either the BOR or the LPBOR (refer to Register 8-3).
bit in the PCON register will be set to ‘0’. See Table 8-4
This signal is OR’d with the output of the BOR module
for default conditions after a RESET instruction has
to provide the generic BOR signal, which goes to the
occurred.
PCON register and to the power control block. Refer to
Figure 8-1 for the OR gate connections of the BOR and
LPBOR Reset signals, which eventually generates one 8.8 Stack Overflow/Underflow Reset
common BOR Reset. The device can reset when the Stack Overflows or
Underflows. The STKOVF or STKUNF bits of the PCON
8.5 MCLR register indicate the Reset condition. These Resets are
enabled by setting the STVREN bit in Configuration
The MCLR is an optional external input that can reset
Words. See Section 4.5.2 “Overflow/Underflow
the device. The MCLR function is controlled by the
Reset” for more information.
MCLRE bit of Configuration Words and the LVP bit of
Configuration Words (Table 8-2).
8.9 Programming Mode Exit
TABLE 8-2: MCLR CONFIGURATION Upon exit of In-Circuit Serial Programming™ (ICSP™)
mode, the device will behave as if a POR had just
MCLRE LVP MCLR occurred (the device does not reset upon run time
0 0 Disabled self-programming/erase operations).
1 0 Enabled
8.10 Power-up Timer
x 1 Enabled
The Power-up Timer optionally delays device execution
8.5.1 MCLR ENABLED after a BOR or POR event. This timer is typically used to
When MCLR is enabled and the pin is held low, the device allow VDD to stabilize before allowing the device to start
is held in Reset. The MCLR pin is connected to VDD running.
through an internal weak pull-up. Refer to Section 2.3 The Power-up Timer is controlled by the PWRTE bit of
“Master Clear (MCLR) Pin” for recommended MCLR the Configuration Words.
connections. The Power-up Timer provides a nominal 64 ms time out
The device has a noise filter in the MCLR Reset path. on POR or Brown-out Reset. The device is held in
The filter will detect and ignore small pulses. Reset as long as PWRT is active. The PWRT delay
allows additional time for the VDD to rise to an accept-
Note: A Reset does not drive the MCLR pin low.
able level. The Power-up Timer is enabled by clearing
the PWRTE bit in the Configuration Words. The
Power-up Timer starts after the release of the POR and
BOR. For additional information, refer to Application
Note AN607, “Power-up Trouble Shooting” (DS00607).

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 PIC16(L)F15313/23
8.11 Start-up Sequence
Upon the release of a POR or BOR, the following must
occur before the device will begin executing:
1. Power-up Timer runs to completion (if enabled).
2. Oscillator start-up timer runs to completion (if
required for oscillator source).
3. MCLR must be released (if enabled).
The total time-out will vary based on oscillator
configuration and Power-up Timer Configuration. See
Section 9.0 “Oscillator Module (with Fail-Safe
Clock Monitor)” for more information.
The Power-up Timer runs independently of MCLR
Reset. If MCLR is kept low long enough, the Power-up
Timer and oscillator start-up timer will expire. This is
useful for testing purposes or to synchronize more than
one device operating in parallel. See Figure 8-3.

FIGURE 8-3: RESET START-UP SEQUENCE

Rev. 10-000032C
9/14/2016

VDD
Internal POR
TPWRT
Power-up Timer
MCLR
Internal RESET
Int. Oscillator
FOSC
Begin Execution code execution (1) code execution (1)

Internal Oscillator, PWRTEN = 0 Internal Oscillator, PWRTEN = 1

VDD
Internal POR
TPWRT
Power-up Timer
MCLR
Internal RESET
Ext. Clock (EC)
FOSC
Begin Execution
code execution (1) code execution (1)
External Clock (EC modes), PWRTEN = 0 External Clock (EC modes), PWRTEN = 1

Note 1: Code execution begins 10 FOSC cycles after the FOSC clock is released.

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 PIC16(L)F15313/23
8.12 Memory Execution Violation
A Memory Execution Violation Reset occurs if
executing an instruction being fetched from outside the
valid execution area. The different valid execution
areas are defined as follows:
• Flash Memory: Table 4-1 shows the addresses
available on the PIC16(L)F15313/23 devices
based on user Flash size. Execution outside this
region generates a memory execution violation.
• Storage Area Flash (SAF): If Storage Area Flash
(SAF) is enabled (Section 4.2.3 “Storage Area
Flash”), the SAF area (Table 4-2) is not a valid
execution area.
Prefetched instructions that are not executed do not
cause memory execution violations. For example, a
GOTO instruction in the last memory location will
prefetch from an invalid location; this is not an error. If
an instruction from an invalid location tries to execute,
the memory violation is generated immediately, and
any concurrent interrupt requests are ignored. When a
memory execution violation is generated, the device is
reset and flag MEMV is cleared in PCON1
(Register 8-3) to signal the cause. The flag needs to be
set in code after a memory execution violation.

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 PIC16(L)F15313/23
8.13 Determining the Cause of a Reset
Upon any Reset, multiple bits in the STATUS and
PCON registers are updated to indicate the cause of
the Reset. Table 8-3 and Table 8-4 show the Reset
conditions of these registers.
TABLE 8-3: RESET STATUS BITS AND THEIR SIGNIFICANCE
STKUNF

RMCLR
STOVF

MEMV
RWDT

BOR
POR

PD
TO
RI
Condition

0 0 1 1 1 0 x 1 1 1 Power-on Reset
0 0 1 1 1 0 x 0 x u Illegal, TO is set on POR
0 0 1 1 1 0 x x 0 u Illegal, PD is set on POR
0 0 u 1 1 u 0 1 1 u Brown-out Reset
u u 0 u u u u 0 u u WWDT Reset
u u u u u u u 0 0 u WWDT Wake-up from Sleep
u u u u u u u 1 0 u Interrupt Wake-up from Sleep
u u u 0 u u u u u 1 MCLR Reset during normal operation
u u u 0 u u u 1 0 u MCLR Reset during Sleep
u u u u 0 u u u u u RESET Instruction Executed
1 u u u u u u u u u Stack Overflow Reset (STVREN = 1)
u 1 u u u u u u u u Stack Underflow Reset (STVREN = 1)
u u u u u u u u u 0 Memory violation Reset

TABLE 8-4: RESET CONDITION FOR SPECIAL REGISTERS

Program STATUS PCON0 PCON1
Condition
Counter Register Register Register
Power-on Reset 0000h ---1 1000 0011 110x ---- --1-
MCLR Reset during normal operation 0000h ---u uuuu uuuu 0uuu ---- --1-
MCLR Reset during Sleep 0000h ---1 0uuu uuuu 0uuu ---- --u-
WWDT Timeout Reset 0000h ---0 uuuu uuu0 uuuu ---- --u-
WWDT Wake-up from Sleep PC + 1 ---0 0uuu uuuu uuuu ---- --u-
WWDT Window Violation 0000h ---u uuuu uu0u uuuu ---- --u-
Brown-out Reset 0000h ---1 1000 0011 11u0 ---- --u-
(1)
Interrupt Wake-up from Sleep PC + 1 ---1 0uuu uuuu uuuu ---- --u-
RESET Instruction Executed 0000h ---u uuuu uuuu u0uu ---- --u-
Stack Overflow Reset (STVREN = 1) 0000h ---u uuuu 1uuu uuuu ---- --u-
Stack Underflow Reset (STVREN = 1) 0000h ---u uuuu u1uu uuuu ---- --u-
Memory Violation Reset (MEMV = 0) 0 -uuu uuuu uuuu uuuu ---- --0-
Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’.
Note 1: When the wake-up is due to an interrupt and Global Enable bit (GIE) is set, the return address is pushed on
the stack and PC is loaded with the interrupt vector (0004h) after execution of PC + 1.

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 PIC16(L)F15313/23
8.14 Power Control (PCONx) Registers
The Power Control (PCONx) registers contain flag bits
to differentiate between a:
• Power-on Reset (POR)
• Brown-out Reset (BOR)
• Reset Instruction Reset (RI)
• MCLR Reset (RMCLR)
• Watchdog Timer Reset (RWDT)
• Watchdog Timer Window Violation Reset
(WDTWV)
• Stack Underflow Reset (STKUNF)
• Stack Overflow Reset (STKOVF)
• Memory Violation Reset (MEMV)
The PCON0 register bits are shown in Register 8-2.
The PCON1 register bits are shown in Register 8-3.
Hardware will change the corresponding register bit
during the Reset process; if the Reset was not caused
by the condition, the bit remains unchanged
(Table 8-4).
Software should reset the bit to the inactive state after
the restart (hardware will not reset the bit).
Software may also set any PCON bit to the active state,
so that user code may be tested, but no reset action will
be generated.

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 PIC16(L)F15313/23
8.15 Register Definitions: Power Control

REGISTER 8-2: PCON0: POWER CONTROL REGISTER 0

R/W/HS-0/q R/W/HS-0/q R/W/HC-1/q R/W/HC-1/q R/W/HC-1/q R/W/HC-1/q R/W/HC-q/u R/W/HC-q/u
STKOVF STKUNF WDTWV RWDT RMCLR RI POR BOR
bit 7 bit 0

Legend:
HC = Bit is cleared by hardware HS = Bit is set by hardware
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -m/n = Value at POR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition

bit 7 STKOVF: Stack Overflow Flag bit

1 = A Stack Overflow occurred
0 = A Stack Overflow has not occurred or cleared by firmware
bit 6 STKUNF: Stack Underflow Flag bit
1 = A Stack Underflow occurred
0 = A Stack Underflow has not occurred or cleared by firmware
bit 5 WDTWV: WDT Window Violation Flag bit
1 = A WDT Window Violation Reset has not occurred or set to ‘1’ by firmware
0 = A WDT Window Violation Reset has occurred (a CLRWDT instruction was executed either without
arming the window or outside the window (cleared by hardware)
bit 4 RWDT: Watchdog Timer Reset Flag bit
1 = A Watchdog Timer Reset has not occurred or set to ‘1’ by firmware
0 = A Watchdog Timer Reset has occurred (cleared by hardware)
bit 3 RMCLR: MCLR Reset Flag bit
1 = A MCLR Reset has not occurred or set to ‘1’ by firmware
0 = A MCLR Reset has occurred (cleared by hardware)
bit 2 RI: RESET Instruction Flag bit
1 = A RESET instruction has not been executed or set to ‘1’ by firmware
0 = A RESET instruction has been executed (cleared by hardware)
bit 1 POR: Power-on Reset Status bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0 BOR: Brown-out Reset Status bit
1 = No Brown-out Reset occurred
0 = A Brown-out Reset occurred (must be set in software after a Power-on Reset or Brown-out Reset
occurs)

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 PIC16(L)F15313/23

REGISTER 8-3: PCON1: POWER CONTROL REGISTER 0

U-0 U-0 U-0 U-0 U-0 U-0 R/W/HC-1/u U-0
— — — — — — MEMV —
bit 7 bit 0

Legend:
HC = Bit is cleared by hardware
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -m/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition

bit 7-2 Unimplemented: Read as ‘0’

bit 1 MEMV: Memory Violation Flag bit
1 = No Memory Violation Reset occurred or set to ‘1’ by firmware.
0 = A Memory Violation Reset occurred (set to ‘0’ in hardware when a Memory Violation occurs))
bit 0 Unimplemented: Read as ‘0’

TABLE 8-5: SUMMARY OF REGISTERS ASSOCIATED WITH RESETS

Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
on Page
BORCON SBOREN — — — — — — BORRDY 92
PCON0 STKOVF STKUNF WDTWV RWDT RMCLR RI POR BOR 99
PCON1 — — — — — — MEMV — 99
STATUS — — — TO PD Z DC C 32
WDTCON0 — — WDTPS<4:0> SWDTEN 150
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Resets.

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 PIC16(L)F15313/23
9.0 OSCILLATOR MODULE (WITH If an external clock source is selected, the FEXTOSC
bits of Configuration Word 1 must be used to select the
FAIL-SAFE CLOCK MONITOR)
external clock mode.

9.1 Overview The external oscillator module can be configured in one

of the following clock modes, by setting the
The oscillator module has a wide variety of clock FEXTOSC<2:0> bits of Configuration Word 1:
sources and selection features that allow it to be used 1. ECL – External Clock Low-Power mode
in a wide range of applications while maximizing ECL<= 500 kHz
performance and minimizing power consumption.
2. ECM – External Clock Medium Power mode
Figure 9-1 illustrates a block diagram of the oscillator
ECM <= 8 MHz
module.
3. ECH – External Clock High-Power mode
Clock sources can be supplied from external oscillators, ECH <= 32 MHz
quartz-crystal resonators. In addition, the system clock
4. LP – 32 kHz Low-Power Crystal mode.
source can be supplied from one of two internal
oscillators and PLL circuits, with a choice of speeds 5. XT – Medium Gain Crystal or Ceramic Resonator
selectable via software. Additional clock features Oscillator mode (between 100 kHz and 4 MHz)
include: 6. HS – High Gain Crystal or Ceramic Resonator
mode (above 4 MHz)
• Selectable system clock source between external
or internal sources via software. The ECH, ECM, and ECL clock modes rely on an
• Fail-Safe Clock Monitor (FSCM) designed to external logic level signal as the device clock source.
detect a failure of the external clock source (LP, The LP, XT, and HS clock modes require an external
XT, HS, ECH, ECM, ECL) and switch crystal or resonator to be connected to the device.
automatically to the internal oscillator. Each mode is optimized for a different frequency range.
The INTOSC internal oscillator block produces low and
• Oscillator Start-up Timer (OST) ensures stability
high-frequency clock sources, designated LFINTOSC
of crystal oscillator sources.
and HFINTOSC. (see Internal Oscillator Block,
The RSTOSC bits of Configuration Word 1 determine Figure 9-1). A wide selection of device clock
the type of oscillator that will be used when the device frequencies may be derived from these clock sources.
reset, including when it is first powered up.
The internal clock modes, LFINTOSC, HFINTOSC (set
at 1 MHz), or HFINTOSC (set at 32 MHz) can be set
through the RSTOSC bits.

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 FIGURE 9-1: SIMPLIFIED PIC® MCU CLOCK SOURCE BLOCK DIAGRAM
 2017 Microchip Technology Inc.

Rev. 10-000208K
1/12/2017

CLKIN

External
Oscillator
(EXTOSC)

CLKOUT
CDIV<4:0>
4x PLL Mode
COSC<2:0>

PLLBlock 512
1001
256
111 1000
128 Sleep
001 0111

9-bit Postscaler Divider

2x PLL Mode System Clock
64
010 0110
Preliminary

LFINTOSC 32
100 0101
31kHz 16
101 0100 SYSCMD Peripheral Clock
Oscillator
8
110 0011
4
Reserved 000 0010 Sleep
2
011 0001 Idle

PIC16(L)F15313/23
1
0000
HFINTOSC

HFFRQ<2:0>

1 – 32 MHz
MFINTOSC FSCM
Oscillator

To Peripherals
DS40001897A-page 101

500 kHz
To Peripherals
31.25 kHz
To Peripherals
To Peripherals
 PIC16(L)F15313/23
9.2 Clock Source Types The Oscillator Start-up Timer (OST) is disabled when
EC mode is selected. Therefore, there is no delay in
Clock sources can be classified as external or internal. operation after a Power-on Reset (POR) or wake-up
External clock sources rely on external circuitry for the from Sleep. Because the PIC® MCU design is fully
clock source to function. Examples are: oscillator static, stopping the external clock input will have the
modules (ECH, ECM, ECL mode), quartz crystal effect of halting the device while leaving all data intact.
resonators or ceramic resonators (LP, XT and HS Upon restarting the external clock, the device will
modes). resume operation as if no time had elapsed.
Internal clock sources are contained within the
oscillator module. The internal oscillator block has two FIGURE 9-2: EXTERNAL CLOCK (EC)
internal oscillators and a dedicated Phase Lock Loop MODE OPERATION
(PLL) that are used to generate internal system clock
sources. The High-Frequency Internal Oscillator CLKIN
Clock from
(HFINTOSC) can produce a range from 1 to 32 MHz. Ext. System
The Low-Frequency Internal Oscillator (LFINTOSC) PIC® MCU
generates a 31 kHz frequency. The external oscillator
block can also be used with the PLL. See OSC2/CLKOUT
FOSC/4 or I/O(1)
Section 9.2.1.4 “4x PLL” for more details.
The system clock can be selected between external or
Note 1: Output depends upon CLKOUTEN bit of the
internal clock sources via the NOSC bits in the Configuration Words.
OSCCON1 register. See Section 9.3 “Clock
Switching” for additional information.
9.2.1.2 LP, XT, HS Modes
9.2.1 EXTERNAL CLOCK SOURCES
The LP, XT and HS modes support the use of quartz
An external clock source can be used as the device crystal resonators or ceramic resonators connected to
system clock by performing one of the following OSC1 and OSC2 (Figure 9-3). The three modes select
actions: a low, medium or high gain setting of the internal
• Program the RSTOSC<2:0> bits in the inverter-amplifier to support various resonator types
Configuration Words to select an external clock and speed.
source that will be used as the default system LP Oscillator mode selects the lowest gain setting of the
clock upon a device Reset internal inverter-amplifier. LP mode current consumption
• Write the NOSC<2:0> and NDIV<4:0> bits in the is the least of the three modes. This mode is designed to
OSCCON1 register to switch the system clock drive only 32.768 kHz tuning-fork type crystals (watch
source crystals).
See Section 9.3 “Clock Switching” for more XT Oscillator mode selects the intermediate gain
information. setting of the internal inverter-amplifier. XT mode
current consumption is the medium of the three modes.
9.2.1.1 EC Mode This mode is best suited to drive crystals and
The External Clock (EC) mode allows an externally resonators with a medium drive level specification.
generated logic level signal to be the system clock HS Oscillator mode selects the highest gain setting of the
source. When operating in this mode, an external clock internal inverter-amplifier. HS mode current consumption
source is connected to the OSC1 input. is the highest of the three modes. This mode is best
OSC2/CLKOUT is available for general purpose I/O or suited for resonators that require a high drive setting.
CLKOUT. Figure 9-2 shows the pin connections for EC Figure 9-3 and Figure 9-4 show typical circuits for
mode. quartz crystal and ceramic resonators, respectively.
EC mode has three power modes to select from through
Configuration Words:
• ECH – High power, 32 MHz
• ECM – Medium power, 8 MHz
• ECL – Low power, 0.5 MHz

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 PIC16(L)F15313/23
FIGURE 9-3: QUARTZ CRYSTAL FIGURE 9-4: CERAMIC RESONATOR
OPERATION (LP, XT OR OPERATION
HS MODE) (XT OR HS MODE)
Rev. 10-000059A
7/30/2013

PIC® MCU

PIC® MCU OSC1/CLKIN

OSC1/CLKIN C1 To Internal
Logic
C1 To Internal
Logic RP(3) RF(2) Sleep
Quartz
(2)
Crystal RF Sleep

C2 Ceramic RS(1) OSC2/CLKOUT

OSC2/CLKOUT
C2 RS(1) Resonator

Note 1: A series resistor (RS) may be required for

Note 1: A series resistor (Rs) may be required for ceramic resonators with low drive level.
quartz crystals with low drive level.
2: The value of RF varies with the Oscillator mode
2: The value of RF varies with the Oscillator mode selected (typically between 2 M to 10 M.
selected (typically between 2 MΩ and 10 MΩ).
3: An additional parallel feedback resistor (RP)
may be required for proper ceramic resonator
operation.
Note 1: Quartz crystal characteristics vary
according to type, package and
manufacturer. The user should consult the 9.2.1.3 Oscillator Start-up Timer (OST)
manufacturer data sheets for specifications
If the oscillator module is configured for LP, XT or HS
and recommended application.
modes, the Oscillator Start-up Timer (OST) counts
2: Always verify oscillator performance over 1024 oscillations from OSC1. This occurs following a
the VDD and temperature range that is Power-on Reset (POR), Brown-out Reset (BOR) or a
expected for the application. wake-up from Sleep. The OST ensures that the
3: For oscillator design assistance, reference oscillator circuit, using a quartz crystal resonator or
the following Microchip Application Notes: ceramic resonator, has started and is providing a stable
system clock to the oscillator module.
• AN826, “Crystal Oscillator Basics and
Crystal Selection for rfPIC® and PIC®
Devices” (DS00826)
• AN849, “Basic PIC® Oscillator Design”
(DS00849)
• AN943, “Practical PIC® Oscillator
Analysis and Design” (DS00943)
• AN949, “Making Your Oscillator Work”
(DS00949)

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 PIC16(L)F15313/23
9.2.1.4 4x PLL 9.2.2 INTERNAL CLOCK SOURCES
The oscillator module contains a PLL that can be used The device may be configured to use an internal
with external clock sources and internal oscillator to oscillator block as the system clock by performing one
provide a system clock source. The input frequency for of the following actions:
the PLL must fall within specifications. See the PLL • Program the RSTOSC<2:0> bits in Configuration
Clock Timing Specifications in Table 37-9. Words to select the INTOSC clock source, which
The PLL may be enabled for use by one of two will be used as the default system clock upon a
methods: device Reset.
1. Program the RSTOSC bits in the Configuration • Write the NOSC<2:0> bits in the OSCCON1
Word 1 to enable the EXTOSC with 4x PLL. register to switch the system clock source to the
2. Write the NOSC bits in the OSCCON1 register internal oscillator during run-time. See
to enable the EXTOSC with 4x PLL. Section 9.3 “Clock Switching” for more
information.
Note 1: Quartz crystal characteristics vary In INTOSC mode, CLKIN is available for general
according to type, package and purpose I/O. CLKOUT is available for general purpose
manufacturer. The user should consult the I/O or CLKOUT.
manufacturer data sheets for specifications
and recommended application. The function of the CLKOUT pin is determined by the
CLKOUTEN bit in Configuration Words.
2: Always verify oscillator performance over
the VDD and temperature range that is The internal oscillator block has two independent
expected for the application. oscillators that can produce two internal system clock
sources.
3: For oscillator design assistance, reference
the following Microchip Application Notes: 1. The HFINTOSC (High-Frequency Internal
Oscillator) is factory calibrated and operates up
• AN826, “Crystal Oscillator Basics and to 32 MHz. The frequency of HFINTOSC can be
Crystal Selection for rfPIC® and PIC® selected through the OSCFRQ Frequency
Devices” (DS00826) Selection register, and fine-tuning can be done
• AN849, “Basic PIC® Oscillator Design” via the OSCTUNE register.
(DS00849) 2. The LFINTOSC (Low-Frequency Internal
• AN943, “Practical PIC® Oscillator Oscillator) is factory-calibrated and operates at
Analysis and Design” (DS00943) 31 kHz.
• AN949, “Making Your Oscillator Work”
(DS00949)
• TB097, “Interfacing a Micro Crystal
MS1V-T1K 32.768 kHz Tuning Fork
Crystal to a PIC16F690/SS” (DS91097)
• AN1288, “Design Practices for
Low-Power External Oscillators”
(DS01288)

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9.2.2.1 HFINTOSC 9.2.2.2 Internal Oscillator Frequency
The High-Frequency Internal Oscillator (HFINTOSC) is Adjustment
a precision digitally-controlled internal clock source The internal oscillator is factory-calibrated. This
that produces a stable clock up to 32 MHz. The internal oscillator can be adjusted in software by writing
HFINTOSC can be enabled through one of the to the OSCTUNE register (Register 9-7).
following methods:
The default value of the OSCTUNE register is 00h. The
• Programming the RSTOSC<2:0> bits in value is a 6-bit two’s complement number. A value of
Configuration Word 1 to ‘110’ (1 MHz) or ‘001’ 1Fh will provide an adjustment to the maximum
(32 MHz) to set the oscillator upon device frequency. A value of 20h will provide an adjustment to
Power-up or Reset. the minimum frequency.
• Write to the NOSC<2:0> bits of the OSCCON1 When the OSCTUNE register is modified, the oscillator
register during run-time. frequency will begin shifting to the new frequency. Code
The HFINTOSC frequency can be selected by setting execution continues during this shift. There is no
the HFFRQ<2:0> bits of the OSCFRQ register. The indication that the shift has occurred.
MFINTOSC is an internal clock source within the OSCTUNE does not affect the LFINTOSC frequency.
HFINTOSC that provides two (500 kHz, 32 kHz) con- Operation of features that depend on the LFINTOSC
stant clock outputs. These constant clock outputs are clock source frequency, such as the Power-up Timer
available for selection to various peripherals, internally. (PWRT), Watchdog Timer (WDT), Fail-Safe Clock
The NDIV<3:0> bits of the OSCCON1 register allow for Monitor (FSCM) and peripherals, are not affected by the
division of the HFINTOSC output from a range between change in frequency.
1:1 and 1:512.
9.2.2.3 LFINTOSC
The Low-Frequency Internal Oscillator (LFINTOSC) is
a factory-calibrated 31 kHz internal clock source. The
LFINTOSC is the clock source for the Power-up Timer
(PWRT), Watchdog Timer (WDT) and Fail-Safe Clock
Monitor (FSCM). The LFINTOSC can also be used as
the system clock, or as a clock or input source to
certain peripherals.
The LFINTOSC is selected as the clock source through
one of the following methods:
• Programming the RSTOSC<2:0> bits of Configu-
ration Word 1 to enable LFINTOSC.
• Write to the NOSC<2:0> bits of the OSCCON1
register.

9.2.2.4 Oscillator Status and Manual Enable

The ‘ready’ status of each oscillator is displayed in the
OSCSTAT register (Register 9-4). The oscillators can
also be manually enabled through the OSCEN register
(Register 9-7). Manual enabling makes it possible to
verify the operation of the EXTOSC oscillator. This can
be achieved by enabling the selected oscillator, then
watching the corresponding ‘ready’ state of the
oscillator in the OSCSTAT register.

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9.3 Clock Switching Changing the clock post-divider without changing the
clock source (e.g., changing FOSC from 1 MHz to 2
The system clock source can be switched between MHz) is handled in the same manner as a clock source
external and internal clock sources via software using change, as described previously. The clock source will
the New Oscillator Source (NOSC) and New Divider already be active, so the switch is relatively quick.
selection request (NDIV) bits of the OSCCON1 register. CSWHOLD must be clear (CSWHOLD = 0) for the
switch to complete.
9.3.1 NEW OSCILLATOR SOURCE
The current COSC and CDIV are indicated in the
(NOSC) AND NEW DIVIDER
OSCCON2 register up to the moment when the switch
SELECTION REQUEST (NDIV) BITS
actually occurs, at which time OSCCON2 is updated
The New Oscillator Source (NOSC) and New Divider and ORDY is set. NOSCR is cleared by hardware to
selection request (NDIV) bits of the OSCCON1 register indicate that the switch is complete.
select the system clock source and the frequency that
are used for the CPU and peripherals. 9.3.2 PLL INPUT SWITCH
When new values of NOSC and NDIV are written to Switching between the PLL and any non-PLL source is
OSCCON1, the current oscillator selection will managed as described above. The input to the PLL is
continue to operate while waiting for the new clock established when NOSC selects the PLL, and main-
source to indicate that it is stable and ready. In some tained by the COSC setting.
cases, the newly requested source may already be in When NOSC and COSC select the PLL with different
use, and is ready immediately. In the case of a input sources, the system continues to run using the
divider-only change, the new and old sources are the COSC setting, and the new source is enabled per
same, and will be immediately ready. The device may NOSC. When the new oscillator is ready (and
enter Sleep while waiting for the switch as described in CSWHOLD = 0), system operation is suspended while
Section 9.3.3 “Clock Switch and Sleep”. the PLL input is switched and the PLL acquires lock.
When the new oscillator is ready, the New Oscillator is
Ready (NOSCR) bit of OSCCON3 and the Clock
Switch Interrupt Flag (CSWIF) bit of PIR1 become set Note: If the PLL fails to lock, the FSCM will
(CSWIF = 1). If Clock Switch Interrupts are enabled trigger.
(CSWIE = 1), an interrupt will be generated at that time.
The Oscillator Ready (ORDY) bit of OSCCON3 can 9.3.3 CLOCK SWITCH AND SLEEP
also be polled to determine when the oscillator is ready
If OSCCON1 is written with a new value and the device
in lieu of an interrupt.
is put to Sleep before the switch completes, the switch
If the Clock Switch Hold (CSWHOLD) bit of OSCCON3 will not take place and the device will enter Sleep
is clear, the oscillator switch will occur when the new mode.
Oscillator’s READY bit (NOSCR) is set, and the
interrupt (if enabled) will be serviced at the new When the device wakes from Sleep and the
oscillator setting. CSWHOLD bit is clear, the device will wake with the
‘new’ clock active, and the clock switch interrupt flag bit
If CSWHOLD is set, the oscillator switch is suspended,
(CSWIF) will be set.
while execution continues using the current (old) clock
source. When the NOSCR bit is set, software should: When the device wakes from Sleep and the
• set CSWHOLD = 0 so the switch can complete, or CSWHOLD bit is set, the device will wake with the ‘old’
clock active and the new clock will be requested again.
• copy COSC into NOSC to abandon the switch.
If DOZE is in effect, the switch occurs on the next clock
cycle, whether or not the CPU is operating during that
cycle.

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FIGURE 9-5: CLOCK SWITCH (CSWHOLD = 0)
OSCCON1
WRITTEN

OSC #1 OSC #2

ORDY

NOTE 2
NOSCR

NOTE 1
CSWIF

USER
CSWHOLD CLEAR

Note 1: CSWIF is asserted coincident with NOSCR; interrupt is serviced at OSC#2 speed.
2: The assertion of NOSCR is hidden from the user because it appears only for the duration of the switch.

FIGURE 9-6: CLOCK SWITCH (CSWHOLD = 1)

OSCCON1
WRITTEN

OSC #1 OSC #2

ORDY

NOSCR

NOTE 1
CSWIF

USER
CSWHOLD CLEAR

Note 1: CSWIF is asserted coincident with NOSCR, and may be cleared before or after clearing CSWHOLD = 0.

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FIGURE 9-7: CLOCK SWITCH ABANDONED
OSCCON1 OSCCON1
WRITTEN WRITTEN

OSC #1

ORDY NOTE 2

NOSCR

NOTE 1
CSWIF

CSWHOLD

Note 1: CSWIF may be cleared before or after rewriting OSCCON1; CSWIF is not automatically cleared.
2: ORDY = 0 if OSCCON1 does not match OSCCON2; a new switch will begin.

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9.4 Fail-Safe Clock Monitor 9.4.2 FAIL-SAFE OPERATION
The Fail-Safe Clock Monitor (FSCM) allows the device When the external clock fails, the FSCM switches the
to continue operating should the external oscillator fail. device clock to the HFINTOSC at 1 MHz clock
The FSCM is enabled by setting the FCMEN bit in the frequency and sets the bit flag OSFIF of the PIR1
Configuration Words. The FSCM is applicable to all register. Setting this flag will generate an interrupt if the
external Oscillator modes (LP, XT, HS, ECL, ECM, OSFIE bit of the PIE1 register is also set. The device
ECH. firmware can then take steps to mitigate the problems
that may arise from a failed clock. The system clock will
continue to be sourced from the internal clock source
FIGURE 9-8: FSCM BLOCK DIAGRAM
until the device firmware successfully restarts the
Clock Monitor external oscillator and switches back to external
Latch operation, by writing to the NOSC and NDIV bits of the
External OSCCON1 register.
S Q
Clock
9.4.3 FAIL-SAFE CONDITION CLEARING
LFINTOSC The Fail-Safe condition is cleared after a Reset,
÷ 64 R Q
Oscillator executing a SLEEP instruction or changing the NOSC
and NDIV bits of the OSCCON1 register. When
31 kHz 488 Hz switching to the external oscillator, or external oscillator
(~32 s) (~2 ms)
and PLL, the OST is restarted. While the OST is
Sample Clock running, the device continues to operate from the
Clock
INTOSC selected in OSCCON1. When the OST times
Failure
out, the Fail-Safe condition is cleared after successfully
Detected
switching to the external clock source. The OSFIF bit
should be cleared prior to switching to the external
9.4.1 FAIL-SAFE DETECTION clock source. If the Fail-Safe condition still exists, the
OSFIF flag will again become set by hardware.
The FSCM module detects a failed oscillator by
comparing the external oscillator to the FSCM sample 9.4.4 RESET OR WAKE-UP FROM SLEEP
clock. The sample clock is generated by dividing the
LFINTOSC by 64. See Figure 9-8. Inside the fail The FSCM is designed to detect an oscillator failure
detector block is a latch. The external clock sets the after the Oscillator Start-up Timer (OST) has expired.
latch on each falling edge of the external clock. The The OST is used after waking up from Sleep and after
sample clock clears the latch on each rising edge of the any type of Reset. The OST is not used with the EC
sample clock. A failure is detected when an entire Clock modes so that the FSCM will be active as soon
half-cycle of the sample clock elapses before the as the Reset or wake-up has completed. Therefore, the
external clock goes low. device will always be executing code while the OST is
operating.

FIGURE 9-9: FSCM TIMING DIAGRAM

Sample Clock

System Oscillator
Clock Failure
Output

Clock Monitor Output

(Q)
Failure
Detected
OSCFIF

Test Test Test

Note: The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in
this example have been chosen for clarity.

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9.5 Register Definitions: Oscillator Control

REGISTER 9-1: OSCCON1: OSCILLATOR CONTROL REGISTER1

U-0 R/W-f/f(1) R/W-f/f(1) R/W-f/f(1) R/W-q/q R/W-q/q R/W-q/q R/W-q/q
(2,3)
— NOSC<2:0> NDIV<3:0>(2,3,4)
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared f = determined by fuse setting

bit 7 Unimplemented: Read as ‘0’

bit 6-4 NOSC<2:0>: New Oscillator Source Request bits
The setting requests a source oscillator and PLL combination per Table 9-1.
POR value = RSTOSC (Register 5-1).
bit 3-0 NDIV<3:0>: New Divider Selection Request bits
The setting determines the new postscaler division ratio per Table 9-1.

Note 1: The default value (f/f) is set equal to the RSTOSC Configuration bits.
2: If NOSC is written with a reserved value (Table 9-1), the operation is ignored and neither NOSC nor NDIV
is written.
3: When CSWEN = 0, this register is read-only and cannot be changed from the POR value.
4: When NOSC = 110 (HFINTOSC 4 MHz), the NDIV bits will default to ‘0010’ upon Reset; for all other
NOSC settings the NDIV bits will default to ‘0000’ upon Reset.

REGISTER 9-2: OSCCON2: OSCILLATOR CONTROL REGISTER 2

U-0 R-n/n(2) R-n/n(2) R-n/n(2) R-n/n(2) R-n/n(2) R-n/n(2) R-n/n(2)
— COSC<2:0> CDIV<3:0>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 Unimplemented: Read as ‘0’

bit 6-4 COSC<2:0>: Current Oscillator Source Select bits (read-only)
Indicates the current source oscillator and PLL combination per Table 9-1.
bit 3-0 CDIV<3:0>: Current Divider Select bits (read-only)
Indicates the current postscaler division ratio per Table 9-1.

Note 1: The POR value is the value present when user code execution begins.
2: The Reset value (n/n) is the same as the NOSC/NDIV bits.

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TABLE 9-1: NOSC/COSC BIT SETTINGS TABLE 9-2: NDIV/CDIV BIT SETTINGS
NOSC<2:0>/ NDIV<3:0>/
Clock Source Clock divider
COSC<2:0> CDIV<3:0>
111 EXTOSC(1) 1111-1010 Reserved
110 HFINTOSC(2) 1001 512
101 LFINTOSC 1000 256
100 Reserved 0111 128
011 Reserved (operates like 0110 64
NOSC = 110) 0101 32
010 EXTOSC with 4x PLL(1) 0100 16
001 HFINTOSC with 2x PLL(1) 0011 8
000 Reserved (it operates like 0010 4
NOSC = 110)
0001 2
Note 1: EXTOSC configured by the FEXTOSC bits of
Configuration Word 1 (Register 5-1). 0000 1
2: HFINTOSC settings are configured with the
HFFRQ bits of the OSCFRQ register
(Register 9-6).

REGISTER 9-3: OSCCON3: OSCILLATOR CONTROL REGISTER 3

R/W/HC-0/0 U-0 U-0 R-0/0 R-0/0 U-0 U-0 U-0
CSWHOLD — — ORDY NOSCR — — —
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 CSWHOLD: Clock Switch Hold bit

1 = Clock switch will hold (with interrupt) when the oscillator selected by NOSC is ready
0 = Clock switch may proceed when the oscillator selected by NOSC is ready; if this bit
is clear at the time that NOSCR becomes ‘1’, the switch will occur
bit 6-5 Unimplemented: Read as ‘0’.
bit 4 ORDY: Oscillator Ready bit (read-only)
1 = OSCCON1 = OSCCON2; the current system clock is the clock specified by NOSC
0 = A clock switch is in progress
bit 3 NOSCR: New Oscillator is Ready bit (read-only)
1 = A clock switch is in progress and the oscillator selected by NOSC indicates a “ready” condition
0 = A clock switch is not in progress, or the NOSC-selected oscillator is not yet ready
bit 2-0 Unimplemented: Read as ‘0’

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REGISTER 9-4: OSCSTAT: OSCILLATOR STATUS REGISTER 1
R-q/q R-q/q R-q/q R-q/q U-0 R-q/q U-0 R-q/q
EXTOR HFOR MFOR LFOR — ADOR — PLLR
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 EXTOR: EXTOSC (external) Oscillator Ready bit

1 = The oscillator is ready to be used
0 = The oscillator is not enabled, or is not yet ready to be used.
bit 6 HFOR: HFINTOSC Oscillator Ready bit
1 = The oscillator is ready to be used
0 = The oscillator is not enabled, or is not yet ready to be used.
bit 5 MFOR: MFINTOSC Oscillator Ready bit
1 = The oscillator is ready to be used
0 = The oscillator is not enabled, or is not yet ready to be used.
bit 4 LFOR: LFINTOSC Oscillator Ready bit
1 = The oscillator is ready to be used
0 = The oscillator is not enabled, or is not yet ready to be used.
bit 3 Unimplemented: Read as ‘0’
bit 2 ADOR: CRC Oscillator Ready bit
1 = The oscillator is ready to be used
0 = The oscillator is not enabled, or is not yet ready to be used.
bit 1 Unimplemented: Read as ‘0’
bit 0 PLLR: PLL is Ready bit
1 = The PLL is ready to be used
0 = The PLL is not enabled, the required input source is not ready, or the PLL is not locked.

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REGISTER 9-5: OSCEN: OSCILLATOR MANUAL ENABLE REGISTER

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 U-0 U-0
EXTOEN HFOEN MFOEN LFOEN — ADOEN — —
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 EXTOEN: External Oscillator Manual Request Enable bit(1)

1 = EXTOSC is explicitly enabled, operating as specified by FEXTOSC
0 = EXTOSC could be enabled by some modules
bit 6 HFOEN: HFINTOSC Oscillator Manual Request Enable bit
1 = HFINTOSC is explicitly enabled, operating as specified by OSCFRQ
0 = HFINTOSC could be enabled by another module
bit 5 MFOEN: MFINTOSC Oscillator Manual Request Enable bit
1 = MFINTOSC is explicitly enabled
0 = MFINTOSC could be enabled by another module
bit 4 LFOEN: LFINTOSC (31 kHz) Oscillator Manual Request Enable bit
1 = LFINTOSC is explicitly enabled
0 = LFINTOSC could be enabled by another module
bit 3 Unimplemented: Read as ‘0’
bit 2 ADOEN: FRC Oscillator Manual Request Enable bit
1 = FRC is explicitly enabled
0 = FRC could be enabled by another module
bit 1-0 Unimplemented: Read as ‘0’

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REGISTER 9-6: OSCFRQ: HFINTOSC FREQUENCY SELECTION REGISTER
U-0 U-0 U-0 U-0 U-0 R/W-q/q R/W-q/q R/W-q/q
— — — — — HFFRQ<2:0>(1)
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-3 Unimplemented: Read as ‘0’

bit 2-0 HFFRQ<2:0>: HFINTOSC Frequency Selection bits
Nominal Freq (MHz):
111 = Reserved
110 = 32
101 = 16
100 = 12
011 = 8
010 = 4
001 = 2
000 = 1
Note 1: When RSTOSC=110 (HFINTOSC 1 MHz), the HFFRQ bits will default to ‘010’ upon Reset; when RSTOSC = 001
(HFINTOSC 32 MHz), the HFFRQ bits will default to ‘101’ upon Reset.

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REGISTER 9-7: OSCTUNE: HFINTOSC TUNING REGISTER
U-0 U-0 R/W-1/1 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— — HFTUN<5:0>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 Unimplemented: Read as ‘0’.

bit 5-0 HFTUN<5:0>: HFINTOSC Frequency Tuning bits
01 1111 = Maximum frequency
01 1110 =
•••
00 0001 =
00 0000 = Center frequency. Oscillator module is running at the calibrated frequency (default value).
11 1111 =
•••
10 0001 =
10 0000 = Minimum frequency.

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TABLE 9-3: SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES
Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
on Page

OSCCON1 — NOSC<2:0> NDIV<3:0> 110

OSCCON2 — COSC<2:0> CDIV<3:0> 110
OSCCON3 CWSHOLD — — ORDY NOSCR — — — 111
OSCFRQ — — — — — HFFRQ<2:0> 114
OSCSTAT EXTOR HFOR MFOR LFOR — ADOR — PLLR 112
OSCTUNE — — HFTUN<5:0> 115
OSCEN EXTOEN HFOEN MFOEN LFOEN — ADOEN — — 113
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by clock sources.

TABLE 9-4: SUMMARY OF CONFIGURATION WORD WITH CLOCK SOURCES

Register
Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0
on Page

13:8 — — FCMEN — CSWEN — — CLKOUTEN

CONFIG1 76
7:0 — RSTOSC<2:0> — FEXTOSC<2:0>
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by clock sources.

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10.0 INTERRUPTS
The interrupt feature allows certain events to preempt
normal program flow. Firmware is used to determine
the source of the interrupt and act accordingly. Some
interrupts can be configured to wake the MCU from
Sleep mode.
This chapter contains the following information for
Interrupts:
• Operation
• Interrupt Latency
• Interrupts During Sleep
• INT Pin
• Automatic Context Saving
Many peripherals produce interrupts. Refer to the
corresponding chapters for details.
A block diagram of the interrupt logic is shown in
Figure 10-1.

FIGURE 10-1: INTERRUPT LOGIC

Rev. 10-000010C
10/12/2016

TMR0IF Wake-up
TMR0IE (If in Sleep mode)

INTF
Peripheral Interrupts INTE

(ADIF) PIR1 <0>

IOCIF
(ADIE) PIE1 <0> Interrupt
IOCIE to CPU

PEIE

PIRn
PIEn GIE

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10.1 Operation 10.2 Interrupt Latency
Interrupts are disabled upon any device Reset. They Interrupt latency is defined as the time from when the
are enabled by setting the following bits: interrupt event occurs to the time code execution at the
• GIE bit of the INTCON register interrupt vector begins. The interrupt is sampled during
Q1 of the instruction cycle. The actual interrupt latency
• Interrupt Enable bit(s) of the PIEx[y] registers for
then depends on the instruction that is executing at the
the specific interrupt event(s)
time the interrupt is detected. See Figure 10-2 and
• PEIE bit of the INTCON register (if the Interrupt Figure 10-3 for more details.
Enable bit of the interrupt event is contained in the
PIEx registers)
The PIR1, PIR2, PIR3, PIR4, PIR5, PIR6, and PIR7
registers record individual interrupts via interrupt flag
bits. Interrupt flag bits will be set, regardless of the
status of the GIE, PEIE and individual interrupt enable
bits.
The following events happen when an interrupt event
occurs while the GIE bit is set:
• Current prefetched instruction is flushed
• GIE bit is cleared
• Current Program Counter (PC) is pushed onto the
stack
• Critical registers are automatically saved to the
shadow registers (See “Section 10.5 “Auto-
matic Context Saving”)
• PC is loaded with the interrupt vector 0004h
The firmware within the Interrupt Service Routine (ISR)
should determine the source of the interrupt by polling
the interrupt flag bits. The interrupt flag bits must be
cleared before exiting the ISR to avoid repeated
interrupts. Because the GIE bit is cleared, any interrupt
that occurs while executing the ISR will be recorded
through its interrupt flag, but will not cause the
processor to redirect to the interrupt vector.
The RETFIE instruction exits the ISR by popping the
previous address from the stack, restoring the saved
context from the shadow registers and setting the GIE
bit.
For additional information on a specific interrupts
operation, refer to its peripheral chapter.
Note 1: Individual interrupt flag bits are set,
regardless of the state of any other
enable bits.
2: All interrupts will be ignored while the GIE
bit is cleared. Any interrupt occurring
while the GIE bit is clear will be serviced
when the GIE bit is set again.

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FIGURE 10-2: INTERRUPT LATENCY
Rev. 10-000269E
8/31/2016

OSC1

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

CLKOUT

INT
pin
Valid Interrupt
window(1) 1 Cycle Instruction at PC

Fetch PC - 1 PC PC + 1 PC = 0x0004 PC = 0x0005 PC = 0x0006

Execute PC - 2 PC - 1 PC 123 123 PC = 0x0004 PC = 0x0005

Indeterminate Latency
Latency(2)

Note 1: An interrupt may occur at any time during the interrupt window.
2: Since an interrupt may occur any time during the interrupt window, the actual latency can vary.

FIGURE 10-3: INT PIN INTERRUPT TIMING

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1

(4)

INT pin
(1)
(1) (2)
INTF (5) Interrupt Latency

GIE

INSTRUCTION FLOW
PC PC PC + 1 PC + 1 0004h 0005h

Instruction
Fetched Inst (PC) Inst (PC + 1) — Inst (0004h) Inst (0005h)

Instruction Inst (0004h)

Inst (PC – 1) Inst (PC) Forced NOP Forced NOP
Executed

Note 1: INTF flag is sampled here (every Q1).

2: Asynchronous interrupt latency = 3-5 TCY. Synchronous latency = 3-4 TCY, where TCY = instruction cycle time.
Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
3: For minimum width of INT pulse, refer to AC specifications in Section 37.0 “Electrical Specifications”.
4: INTF may be set any time during the Q4-Q1 cycles.

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10.3 Interrupts During Sleep
Interrupts can be used to wake from Sleep. To wake
from Sleep, the peripheral must be able to operate
without the system clock. The interrupt source must
have the appropriate Interrupt Enable bit(s) set prior to
entering Sleep.
On waking from Sleep, if the GIE bit is also set, the
processor will branch to the interrupt vector. Otherwise,
the processor will continue executing instructions after
the SLEEP instruction. The instruction directly after the
SLEEP instruction will always be executed before
branching to the ISR. Refer to Section 11.0 “Power-
Saving Operation Modes” for more details.

10.4 INT Pin

The INT pin can be used to generate an asynchronous
edge-triggered interrupt. Refer to Figure 10-3. This
interrupt is enabled by setting the INTE bit of the PIE0
register. The INTEDG bit of the INTCON register
determines on which edge the interrupt will occur. When
the INTEDG bit is set, the rising edge will cause the
interrupt. When the INTEDG bit is clear, the falling edge
will cause the interrupt. The INTF bit of the PIR0 register
will be set when a valid edge appears on the INT pin. If
the GIE and INTE bits are also set, the processor will
redirect program execution to the interrupt vector.

10.5 Automatic Context Saving

Upon entering an interrupt, the return PC address is
saved on the stack. Additionally, the following registers
are automatically saved in the shadow registers:
• W register
• STATUS register (except for TO and PD)
• BSR register
• FSR registers
• PCLATH register
Upon exiting the Interrupt Service Routine, these
registers are automatically restored. Any modifications
to these registers during the ISR will be lost. If
modifications to any of these registers are desired, the
corresponding shadow register should be modified and
the value will be restored when exiting the ISR. The
shadow registers are available in Bank 31 and are
readable and writable. Depending on the user’s
application, other registers may also need to be saved.

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10.6 Register Definitions: Interrupt Control

REGISTER 10-1: INTCON: INTERRUPT CONTROL REGISTER

R/W-0/0 R/W-0/0 U-0 U-0 U-0 U-0 U-0 R/W-1/1
GIE PEIE — — — — — INTEDG
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 GIE: Global Interrupt Enable bit

1 = Enables all active interrupts
0 = Disables all interrupts
bit 6 PEIE: Peripheral Interrupt Enable bit
1 = Enables all active peripheral interrupts
0 = Disables all peripheral interrupts
bit 5-1 Unimplemented: Read as ‘0’
bit 0 INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of INT pin
0 = Interrupt on falling edge of INT pin

Note: Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE, of the INTCON register.
User software should ensure the
appropriate interrupt flag bits are clear
prior to enabling an interrupt.

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REGISTER 10-2: PIE0: PERIPHERAL INTERRUPT ENABLE REGISTER 0

U-0 U-0 R/W-0/0 R/W-0/0 U-0 U-0 U-0 R/W-0/0
— — TMR0IE IOCIE — — — INTE
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared HS = Hardware set

bit 7-6 Unimplemented: Read as ‘0’

bit 5 TMR0IE: Timer0 Overflow Interrupt Enable bit
1 = Enables the Timer0 interrupt
0 = Disables the Timer0 interrupt
bit 4 IOCIE: Interrupt-on-Change Interrupt Enable bit
1 = Enables the IOC change interrupt
0 = Disables the IOC change interrupt
bit 3-1 Unimplemented: Read as ‘0’
bit 0 INTE: INT External Interrupt Flag bit(1)
1 = Enables the INT external interrupt
0 = Disables the INT external interrupt

Note 1: The External Interrupt GPIO pin is selected by INTPPS (Register 15-1).

Note: Bit PEIE of the INTCON register must be

set to enable any peripheral interrupt
controlled by PIE1-PIE7. Interrupt sources
controlled by the PIE0 register do not
require PEIE to be set in order to allow
interrupt vectoring (when GIE is set).

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REGISTER 10-3: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1
R/W-0/0 R/W-0/0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0
OSFIE CSWIE — — — — — ADIE
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 OSFIE: Oscillator Fail Interrupt Enable bit

1 = Enables the Oscillator Fail Interrupt
0 = Disables the Oscillator Fail Interrupt
bit 6 CSWIE: Clock Switch Complete Interrupt Enable bit
1 = The clock switch module interrupt is enabled
0 = The clock switch module interrupt is disabled
bit 5-1 Unimplemented: Read as ‘0’
bit 0 ADIE: Analog-to-Digital Converter (ADC) Interrupt Enable bit
1 = Enables the ADC interrupt
0 = Disables the ADC interrupt

Note: Bit PEIE of the INTCON register must be

set to enable any peripheral interrupt
controlled by registers PIE1-PIE7

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REGISTER 10-4: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2

U-0 R/W-0/0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0
(1)
— ZCDIE — — — — C2IE C1IE
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 Unimplemented: Read as ‘0’

bit 6 ZCDIE: Zero-Cross Detection (ZCD) Interrupt Enable bit
1 = Enables the ZCD interrupt
0 = Disables the ZCD interrupt
bit 5-2 Unimplemented: Read as ‘0’
bit 1 C2IE: Comparator C2 Interrupt Enable bit
1 = Enables the Comparator C2 interrupt
0 = Disables the Comparator C2 interrupt
bit 0 C1IE: Comparator C1 Interrupt Enable bit
1 = Enables the Comparator C1 interrupt
0 = Disables the Comparator C1 interrupt

Note 1: Present only on PIC16(L)F15323.

Note: Bit PEIE of the INTCON register must be

set to enable any peripheral interrupt
controlled by registers PIE1-PIE7.

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REGISTER 10-5: PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3

U-0 U-0 R/W-0/0 R/W-0/0 U-0 U-0 R/W-0/0 R/W-0/0
— — RC1IE TX1IE — — BCL1IE SSP1IE
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 Unimplemented: Read as ‘0’

bit 5 RC1IE: USART Receive Interrupt Enable bit
1 = Enables the USART receive interrupt
0 = Enables the USART receive interrupt
bit 4 TX1IE: USART Transmit Interrupt Enable bit
1 = Enables the USART transmit interrupt
0 = Disables the USART transmit interrupt
bit 3-2 Unimplemented: Read as ‘0’
bit 1 BCL1IE: MSSP1 Bus Collision Interrupt Enable bit
1 = MSSP bus collision interrupt enabled
0 = MSSP bus collision interrupt disabled
bit 0 SSP1IE: Synchronous Serial Port (MSSP1) Interrupt Enable bit
1 = Enables the MSSP interrupt
0 = Disables the MSSP interrupt

Note: Bit PEIE of the INTCON register must be

set to enable any peripheral interrupt
controlled by PIE1-PIE7.

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REGISTER 10-6: PIE4: PERIPHERAL INTERRUPT ENABLE REGISTER 4

U-0 U-0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0
— — — — — — TMR2IE TMR1IE
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared HS = Hardware set

bit 7-2 Unimplemented: Read as ‘0’

bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enables the Timer2 to PR2 match interrupt
0 = Disables the Timer2 to PR2 match interrupt
bit 0 TMR1IE: Timer1 Overflow Interrupt Enable bit
1 = Enables the Timer1 overflow interrupt
0 = Enables the Timer1 overflow interrupt

Note: Bit PEIE of the INTCON register must be

set to enable any peripheral interrupt
controlled by registers PIE1-PIE7.

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REGISTER 10-7: PIE5: PERIPHERAL INTERRUPT ENABLE REGISTER 5

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 U-0 R/W-0/0
CLC4IE CLC3IE CLC2IE CLC1IE — — — TMR1GIE
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared HS = Hardware set

bit 7 CLC4IE: CLC4 Interrupt Enable bit

1 = CLC4 interrupt enabled
0 = CLC4 interrupt disabled
bit 6 CLC3IE: CLC3 Interrupt Enable bit
1 = CLC3 interrupt enabled
0 = CLC3 interrupt disabled
bit 5 CLC2IE: CLC2 Interrupt Enable bit
1 = CLC2 interrupt enabled
0 = CLC2 interrupt disabled
bit 4 CLC1IE: CLC1 Interrupt Enable bit
1 = CLC1 interrupt enabled
0 = CLC1 interrupt disabled
bit 3-1 Unimplemented: Read as ‘0’
bit 0 TMR1GIE: Timer1 Gate Interrupt Enable bit
1 = Enables the Timer1 gate acquisition interrupt
0 = Disables the Timer1 gate acquisition interrupt

Note: Bit PEIE of the INTCON register must be

set to enable any peripheral interrupt
controlled by registers PIE1-PIE7.

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REGISTER 10-8: PIE6: PERIPHERAL INTERRUPT ENABLE REGISTER 6

U-0 U-0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0
— — — — — — CCP2IE CCP1IE
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared HS = Hardware set

bit 7-2 Unimplemented: Read as ‘0’.

bit 1 CCP2IE: CCP2 Interrupt Enable bit
1 = CCP2 interrupt is enabled
0 = CCP2 interrupt is disabled
bit 0 CCP1IE: CCP1 Interrupt Enable bit
1 = CCP1 interrupt is enabled
0 = CCP1 interrupt is disabled

Note: Bit PEIE of the INTCON register must be

set to enable any peripheral interrupt
controlled by registers PIE1-PIE7.

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REGISTER 10-9: PIE7: PERIPHERAL INTERRUPT ENABLE REGISTER 7

U-0 U-0 R/W-0/0 R/W-0/0 U-0 U-0 U-0 R/W-0/0
— — NVMIE NCO1IE — — — CWG1IE
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared HS = Hardware set

bit 7-6 Unimplemented: Read as ‘0’.

bit 5 NVMIE: NVM Interrupt Enable bit
1 = NVM task complete interrupt enabled
0 = NVM interrupt not enabled
bit 4 NCO1IE: NCO Interrupt Enable bit
1 = NCO rollover interrupt enabled
0 = NCO rollover interrupt disabled
bit 3-1 Unimplemented: Read as ‘0’.
bit 0 CWG1IE: Complementary Waveform Generator (CWG) 2 Interrupt Enable bit
1 = CWG1 interrupt is enabled
0 = CWG1 interrupt disabled

Note: Bit PEIE of the INTCON register must be

set to enable any peripheral interrupt
controlled by registers PIE1-PIE7.

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REGISTER 10-10: PIR0: PERIPHERAL INTERRUPT STATUS REGISTER 0

U-0 U-0 R/W/HS-0/0 R-0 U-0 U-0 U-0 R/W/HS-0/0
— — TMR0IF IOCIF — — — INTF(1)
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared HS= Hardware Set

bit 7-6 Unimplemented: Read as ‘0’

bit 5 TMR0IF: Timer0 Overflow Interrupt Flag bit
1 = Timer0 register has overflowed (must be cleared in software)
0 = Timer0 register did not overflow
bit 4 IOCIF: Interrupt-on-Change Interrupt Flag bit (read-only)(2)
1 = One or more of the IOCAF-IOCEF register bits are currently set, indicating an enabled edge was
detected by the IOC module.
0 = None of the IOCAF-IOCEF register bits are currently set
bit 3-1 Unimplemented: Read as ‘0’
bit 0 INTF: INT External Interrupt Flag bit(1)
1 = The INT external interrupt occurred (must be cleared in software)
0 = The INT external interrupt did not occur

Note 1: The External Interrupt GPIO pin is selected by INTPPS (Register 15-1).
2: The IOCIF bit is the logical OR of all the IOCAF-IOCEF flags. Therefore, to clear the IOCIF flag,
application firmware must clear all of the lower level IOCAF-IOCEF register bits.

Note: Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state
of its corresponding enable bit or the
Global Enable bit, GIE, of the INTCON
register. User software should ensure the
appropriate interrupt flag bits are clear
prior to enabling an interrupt.

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REGISTER 10-11: PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1

R/W/HS-0/0 R/W/HS-0/0 U-0 U-0 U-0 U-0 U-0 R/W/HS-0/0
OSFIF CSWIF — — — — — ADIF
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared HS = Hardware set

bit 7 OSFIF: Oscillator Fail-Safe Interrupt Flag bit

1 = Oscillator fail-safe interrupt has occurred (must be cleared in software)
0 = No oscillator fail-safe interrupt
bit 6 CSWIF: Clock Switch Complete Interrupt Flag bit
1 = The clock switch module indicates an interrupt condition and is ready to complete the clock switch
operation (must be cleared in software)
0 = The clock switch does not indicate an interrupt condition
bit 5-1 Unimplemented: Read as ‘0’
bit 0 ADIF: Analog-to-Digital Converter (ADC) Interrupt Flag bit
1 = An A/D conversion or complex operation has completed (must be cleared in software)
0 = An A/D conversion or complex operation is not complete

Note: Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE, of the INTCON register.
User software should ensure the
appropriate interrupt flag bits are clear
prior to enabling an interrupt.

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REGISTER 10-12: PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2
U-0 R/W/HS-0/0 U-0 U-0 U-0 U-0 R/W/HS-0/0 R/W/HS-0/0
(1)
— ZCDIF — — — — C2IF C1IF
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared HS = Hardware set

bit 7 Unimplemented: Read as ‘0’

bit 6 ZCDIF: Zero-Cross Detect (ZCD1) Interrupt Flag bit
1 = An enabled rising and/or falling ZCD1 event has been detected (must be cleared in software)
0 = No ZCD1 event has occurred
bit 5-2 Unimplemented: Read as ‘0’
bit 1 C2IF: Comparator C2 Interrupt Flag bit
1 = Comparator 2 interrupt asserted (must be cleared in software)
0 = Comparator 2 interrupt not asserted
bit 0 C1IF: Comparator C1 Interrupt Flag bit
1 = Comparator 1 interrupt asserted (must be cleared in software)
0 = Comparator 1 interrupt not asserted

Note 1: Present only on PIC16(L)F15323.

Note: Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE, of the INTCON register.
User software should ensure the
appropriate interrupt flag bits are clear
prior to enabling an interrupt.

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REGISTER 10-13: PIR3: PERIPHERAL INTERRUPT REQUEST REGISTER 3
U-0 U-0 R/W/HS-0/0 R/W/HS-0/0 U-0 U-0 R/W/HS-0/0 R/W/HS-0/0
— — RC1IF TX1IF — — BCL1IF SSP1IF
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared HS = Hardware clearable

bit 7-6 Unimplemented: Read as ‘0’

bit 5 RC1IF: EUSART1 Receive Interrupt Flag (read-only) bit (1)
1 = The EUSART1 receive buffer is not empty (contains at least one byte)
0 = The EUSART1 receive buffer is empty
bit 4 TX1IF: EUSART1 Transmit Interrupt Flag (read-only) bit(2)
1 = The EUSART1 transmit buffer contains at least one unoccupied space
0 = The EUSART1 transmit buffer is currently full. The application firmware should not write to
TXxREG again, until more room becomes available in the transmit buffer.
bit 3-2 Unimplemented: Read as ‘0’
bit 1 BCL1IF: MSSP1 Bus Collision Interrupt Flag bit
1 = A bus collision was detected (must be cleared in software)
0 = No bus collision was detected
bit 0 SSP1IF: Synchronous Serial Port (MSSP1) Interrupt Flag bit
1 = The Transmission/Reception/Bus Condition is complete (must be cleared in software)
0 = Waiting for the Transmission/Reception/Bus Condition in progress

Note 1: The RCxIF flag is a read-only bit. To clear the RCxIF flag, the firmware must read from RCxREG enough
times to remove all bytes from the receive buffer.
2: The TXxIF flag is a read-only bit, indicating if there is room in the transmit buffer. To clear the TX1IF flag,
the firmware must write enough data to TXxREG to completely fill all available bytes in the buffer. The
TXxIF flag does not indicate transmit completion (use TRMT for this purpose instead).

Note: Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE, of the INTCON register.
User software should ensure the
appropriate interrupt flag bits are clear
prior to enabling an interrupt.

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REGISTER 10-14: PIR4: PERIPHERAL INTERRUPT REQUEST REGISTER 4
U-0 U-0 U-0 U-0 U-0 U-0 R/W/HS-0/0 R/W/HS-0/0
— — — — — — TMR2IF TMR1IF
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared HS = Hardware set

bit 7-2 Unimplemented: Read as ‘0’

bit 1 TRM2IF: Timer2 Interrupt Flag bit
1 = The TMR2 postscaler overflowed, or in 1:1 mode, a TMR2 to PR2 match occurred (must be cleared
in software)
0 = No TMR2 event has occurred
bit 0 TRM1IF: Timer1 Overflow Interrupt Flag bit
1 = Timer1 overflow occurred (must be cleared in software)
0 = No Timer1 overflow occurred

Note: Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE, of the INTCON register.
User software should ensure the
appropriate interrupt flag bits are clear
prior to enabling an interrupt.

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REGISTER 10-15: PIR5: PERIPHERAL INTERRUPT REQUEST REGISTER 5

R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 U-0 U-0 U-0 R/W/HS-0/0
CLC4IF CLC3IF CLC2IF CLC1IF — — — TMR1GIF
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared HS = Hardware set

bit 7 CLC4IF: CLC4 Interrupt Flag bit

1 = A CLC4OUT interrupt condition has occurred (must be cleared in software)
0 = No CLC4 interrupt event has occurred
bit 6 CLC3IF: CLC3 Interrupt Flag bit
1 = A CLC3OUT interrupt condition has occurred (must be cleared in software)
0 = No CLC3 interrupt event has occurred
bit 5 CLC2IF: CLC2 Interrupt Flag bit
1 = A CLC2OUT interrupt condition has occurred (must be cleared in software)
0 = No CLC2 interrupt event has occurred
bit 4 CLC1IF: CLC1 Interrupt Flag bit
1 = A CLC1OUT interrupt condition has occurred (must be cleared in software)
0 = No CLC1 interrupt event has occurred
bit 3-1 Unimplemented: Read as ‘0’
bit 0 TMR1GIF: Timer1 Gate Interrupt Flag bit
1 = The Timer1 Gate has gone inactive (the acquisition is complete)
0 = The Timer1 Gate has not gone inactive

Note: Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE, of the INTCON register.
User software should ensure the
appropriate interrupt flag bits are clear
prior to enabling an interrupt.

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REGISTER 10-16: PIR6: PERIPHERAL INTERRUPT REQUEST REGISTER 6

U-0 U-0 U-0 U-0 U-0 U-0 R/W/HS-0/0 R/W/HS-0/0
— — — — — — CCP2IF CCP1IF
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared HS = Hardware set

bit 7-2 Unimplemented: Read as ‘0’

bit 1 CCP2IF: CCP2 Interrupt Flag bit
CCPM Mode
Value
Capture Compare PWM
Capture occurred Compare match occurred Output trailing edge occurred
1
(must be cleared in software) (must be cleared in software) (must be cleared in software)
0 Capture did not occur Compare match did not occur Output trailing edge did not occur

bit 0 CCP1IF: CCP1 Interrupt Flag bit

CCPM Mode
Value
Capture Compare PWM
Capture occurred Compare match occurred Output trailing edge occurred
1
(must be cleared in software) (must be cleared in software) (must be cleared in software)
0 Capture did not occur Compare match did not occur Output trailing edge did not occur

Note: Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE, of the INTCON register.
User software should ensure the
appropriate interrupt flag bits are clear
prior to enabling an interrupt.

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REGISTER 10-17: PIR7: PERIPHERAL INTERRUPT REQUEST REGISTER 7

U-0 U-0 R/W/HS-0/0 R/W/HS-0/0 U-0 U-0 U-0 R/W/HS-0/0
— — NVMIF NCO1IF — — — CWG1IF
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared HS = Hardware set

bit 7-6 Unimplemented: Read as ‘0’

bit 5 NVMIF: Nonvolatile Memory (NVM) Interrupt Flag bit
1 = The requested NVM operation has completed
0 = NVM interrupt not asserted
bit 4 NCO1IF: Numerically Controlled Oscillator (NCO) Interrupt Flag bit
1 = The NCO has rolled over
0 = No NCO interrupt event has occurred
bit 3-1 Unimplemented: Read as ‘0’
bit 0 CWG1IF: CWG1 Interrupt Flag bit
1 = CWG1 has gone into shutdown
0 = CWG1 is operating normally, or interrupt cleared

Note: Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE, of the INTCON register.
User software should ensure the
appropriate interrupt flag bits are clear
prior to enabling an interrupt.

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 PIC16(L)F15313/23
TABLE 10-1: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS
Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
on Page

INTCON GIE PEIE — — — — — INTEDG 121

PIE0 — — TMR0IE IOCIE — — — INTE 122
PIE1 OSFIE CSWIE — — — — — ADIE 123
PIE2 — ZCDIE — — — — C2IE(1) C1IE 124
PIE3 — — RC1IE TX1IE — — BCL1IE SSP1IE 125
PIE4 — — — — — — TMR2IE TMR1IE 126
PIE5 CLC4IE CLC3IE CLC2IE CLC1IE — — — TMR1GIE 127
PIE6 — — — — — — CCP2IE CCP1IE 128
PIE7 — — NVMIE NCO1IE — — — CWG1IE 129
PIR0 — — TMR0IF IOCIF — — — INTF 130
PIR1 OSFIF CSWIF — — — — — ADIF 131
PIR2 — ZCDIF — — — — C2IF(1) C1IF 132
PIR3 — — RC1IF TX1IF — — BCL1IF SSP1IF 133
PIR4 — — — — — — TMR2IF TMR1IF 134
PIR5 CLC4IF CLC3IF CLC2IF CLC1IF — — — TMR1GIF 135
PIR6 — — — — — — CCP2IF CCP1IF 136
PIR7 — — NVMIF NCO1IF — — — CWG1IF 137
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by interrupts.
Note 1: Present only on PIC16(L)F15323.

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 PIC16(L)F15313/23
11.0 POWER-SAVING OPERATION operate, while only the CPU and PFM are affected. The
reduced execution saves power by eliminating
MODES
unnecessary operations within the CPU and memory.
The purpose of the Power-Down modes is to reduce When the Doze Enable (DOZEN) bit is set (DOZEN =
power consumption. There are three Power-Down 1), the CPU executes only one instruction cycle out of
modes: DOZE mode, IDLE mode, and SLEEP mode. every N cycles as defined by the DOZE<2:0> bits of the
CPUDOZE register. For example, if DOZE<2:0> = 100,
11.1 DOZE Mode the instruction cycle ratio is 1:32. The CPU and
memory execute for one instruction cycle and then lay
DOZE mode allows for power saving by reducing CPU
idle for 31 instruction cycles. During the unused cycles,
operation and program memory (PFM) access, without
the peripherals continue to operate at the system clock
affecting peripheral operation. DOZE mode differs from
speed.
Sleep mode because the system oscillators continue to

FIGURE 11-1: DOZE MODE OPERATION EXAMPLE

System
Clock

1 1 1 1 1 1 1 1 1 1 1 1 1

2 2 2 2 2 2 2 2 2 2 2 2 2

/ŶƐƚƌƵĐƚŝŽŶ
WĞƌŝŽĚ 3 3 3 3 3 3 3 3 3 3 3 3 3

4 4 4 4 4 4 4 4 4 4 4 4 4

1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4
CPU Clock

PFM Op’s Fetch Fetch Push 0004h Fetch Fetch

CPU Op’s Exec Exec Exec(1,2) NOP Exec Exec Exec

Interrupt
Here
(ROI = 1)
Note 1: Multi-cycle instructions are executed to completion before fetching 0004h.
2: If the pre-fetched instruction clears GIE, the ISR will not occur, but DOZEN is still cleared and the CPU will resume execution at full speed.

11.1.1 DOZE OPERATION

The Doze operation is illustrated in Figure 11-1. For
this example:
• Doze enable (DOZEN) bit set (DOZEN = 1)
• DOZE<2:0> = 001 (1:4) ratio
• Recover-on-Interrupt (ROI) bit set (ROI = 1)
As with normal operation, the PFM fetches for the next
instruction cycle. The Q-clocks to the peripherals
continue throughout.

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 PIC16(L)F15313/23
11.1.2 INTERRUPTS DURING DOZE To minimize current consumption, the following
conditions should be considered:
If an interrupt occurs and the Recover-on-Interrupt bit
is clear (ROI = 0) at the time of the interrupt, the - I/O pins should not be floating
Interrupt Service Routine (ISR) continues to execute at - External circuitry sinking current from I/O pins
the rate selected by DOZE<2:0>. Interrupt latency is - Internal circuitry sourcing current from I/O
extended by the DOZE<2:0> ratio. pins
- Current draw from pins with internal weak
If an interrupt occurs and the ROI bit is set (ROI = 1) at
pull-ups
the time of the interrupt, the DOZEN bit is cleared and
- Modules using any oscillator
the CPU executes at full speed. The prefetched
instruction is executed and then the interrupt vector I/O pins that are high-impedance inputs should be
sequence is executed. In Figure 11-1, the interrupt pulled to VDD or VSS externally to avoid switching
occurs during the 2nd instruction cycle of the Doze currents caused by floating inputs.
period, and immediately brings the CPU out of Doze. If Any module with a clock source that is not FOSC can be
the Doze-On-Exit (DOE) bit is set (DOE = 1) when the enabled. Examples of internal circuitry that might be
RETFIE operation is executed, DOZEN is set, and the sourcing current include modules such as the DAC and
CPU executes at the reduced rate based on the FVR modules. See Section 21.0 “5-Bit Digi-
DOZE<2:0> ratio. tal-to-Analog Converter (DAC1) Module”,
Section 18.0 “Fixed Voltage Reference (FVR)” for
11.2 Sleep Mode more information on these modules.
Sleep mode is entered by executing the SLEEP 11.2.1 WAKE-UP FROM SLEEP
instruction, while the Idle Enable (IDLEN) bit of the
CPUDOZE register is clear (IDLEN = 0). If the SLEEP The device can wake-up from Sleep through one of the
instruction is executed while the IDLEN bit is set following events:
(IDLEN = 1), the CPU will enter the IDLE mode 1. External Reset input on MCLR pin, if enabled.
(Section 11.2.3 “Low-Power Sleep Mode”). 2. BOR Reset, if enabled.
Upon entering Sleep mode, the following conditions 3. POR Reset.
exist: 4. Watchdog Timer, if enabled.
1. WDT will be cleared but keeps running if 5. Any external interrupt.
enabled for operation during Sleep 6. Interrupts by peripherals capable of running
2. The PD bit of the STATUS register is cleared during Sleep (see individual peripheral for more
3. The TO bit of the STATUS register is set information).
4. CPU Clock and System Clock The first three events will cause a device Reset. The
5. 31 kHz LFINTOSC, HFINTOSC are unaffected last three events are considered a continuation of
and peripherals using them may continue program execution. To determine whether a device
operation in Sleep. Reset or wake-up event occurred, refer to
6. ADC is unaffected if the dedicated FRC Section 8.12 “Memory Execution Violation”.
oscillator is selected the conversion will be left When the SLEEP instruction is being executed, the next
abandoned if FOSC is selected and ADRES will instruction (PC + 1) is prefetched. For the device to
have an incorrect value wake-up through an interrupt event, the corresponding
7. I/O ports maintain the status they had before interrupt enable bit must be enabled. Wake-up will
Sleep was executed (driving high, low, or occur regardless of the state of the GIE bit. If the GIE
high-impedance). This does not apply in the bit is disabled, the device continues execution at the
case of any asynchronous peripheral which is instruction after the SLEEP instruction. If the GIE bit is
active and may affect the I/O port value enabled, the device executes the instruction after the
8. Resets other than WDT are not affected by SLEEP instruction, the device will then call the Interrupt
Sleep mode Service Routine. In cases where the execution of the
Refer to individual chapters for more details on instruction following SLEEP is not desirable, the user
peripheral operation during Sleep. should have a NOP after the SLEEP instruction.
The WDT is cleared when the device wakes-up from
Sleep, regardless of the source of wake-up.

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 PIC16(L)F15313/23
11.2.2 WAKE-UP USING INTERRUPTS • If the interrupt occurs during or after the
execution of a SLEEP instruction
When global interrupts are disabled (GIE cleared) and
any interrupt source, with the exception of the clock - SLEEP instruction will be completely
switch interrupt, has both its interrupt enable bit and executed
interrupt flag bit set, one of the following will occur: - Device will immediately wake-up from Sleep
• If the interrupt occurs before the execution of a - WDT and WDT prescaler will be cleared
SLEEP instruction - TO bit of the STATUS register will be set
- SLEEP instruction will execute as a NOP - PD bit of the STATUS register will be cleared
- WDT and WDT prescaler will not be cleared Even if the flag bits were checked before executing a
- TO bit of the STATUS register will not be set SLEEP instruction, it may be possible for flag bits to
- PD bit of the STATUS register will not be become set before the SLEEP instruction completes. To
cleared determine whether a SLEEP instruction executed, test
the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.

FIGURE 11-2: WAKE-UP FROM SLEEP THROUGH INTERRUPT

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
CLKIN(1)
CLKOUT(2) TOST(3)

Interrupt flag Interrupt Latency (4)

GIE bit
(INTCON reg.) Processor in
Sleep

Instruction Flow
PC PC PC + 1 PC + 2 PC + 2 PC + 2 0004h 0005h
Instruction Inst(PC + 1) Inst(PC + 2) Inst(0004h) Inst(0005h)
Fetched Inst(PC) = Sleep
Instruction Sleep Inst(PC + 1) Forced NOP Forced NOP
Executed Inst(PC - 1) Inst(0004h)

Note 1: External clock. High, Medium, Low mode assumed.

2: CLKOUT is shown here for timing reference.
3: TOST = 1024 TOSC. This delay does not apply to EC and INTOSC Oscillator modes.
4: GIE = 1 assumed. In this case after wake-up, the processor calls the ISR at 0004h. If GIE = 0, execution will continue in-line.

11.2.3 LOW-POWER SLEEP MODE 11.2.3.1 Sleep Current vs. Wake-up Time
The PIC16F15313/23 device contains an internal Low In the default operating mode, the LDO and reference
Dropout (LDO) voltage regulator, which allows the circuitry remain in the normal configuration while in
device I/O pins to operate at voltages up to 5.5V while Sleep. The device is able to exit Sleep mode quickly
the internal device logic operates at a lower voltage. since all circuits remain active. In Low-Power Sleep
The LDO and its associated reference circuitry must mode, when waking-up from Sleep, an extra delay time
remain active when the device is in Sleep mode. is required for these circuits to return to the normal
The PIC16F15313/23 allows the user to optimize the configuration and stabilize.
operating current in Sleep, depending on the The Low-Power Sleep mode is beneficial for
application requirements. applications that stay in Sleep mode for long periods of
time. The Normal mode is beneficial for applications
Low-Power Sleep mode can be selected by setting the
that need to wake from Sleep quickly and frequently.
VREGPM bit of the VREGCON register. Depending on
the configuration of these bits, the LDO and reference
circuitry are placed in a low-power state when the
device is in Sleep.

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 PIC16(L)F15313/23
11.2.3.2 Peripheral Usage in Sleep 11.3.1 IDLE AND INTERRUPTS
Some peripherals that can operate in Sleep mode will IDLE mode ends when an interrupt occurs (even if
not operate properly with the Low-Power Sleep mode GIE = 0), but IDLEN is not changed. The device can
selected. The Low-Power Sleep mode is intended for re-enter IDLE by executing the SLEEP instruction.
use with these peripherals: If Recover-on-Interrupt is enabled (ROI = 1), the
• Brown-out Reset (BOR) interrupt that brings the device out of Idle also restores
• Watchdog Timer (WDT) full-speed CPU execution when doze is also enabled.
• External interrupt pin/interrupt-on-change pins
• Timer1 (with external clock source) 11.3.2 IDLE AND WDT
It is the responsibility of the end user to determine what When in IDLE, the WDT Reset is blocked and will
is acceptable for their application when setting the instead wake the device. The WDT wake-up is not an
VREGPM settings in order to ensure operation in interrupt, therefore ROI does not apply.
Sleep.
Note: The WDT can bring the device out of
Note: The PIC16LF15313/23 does not have a IDLE, in the same way it brings the device
configurable Low-Power Sleep mode. out of Sleep. The DOZEN bit is not
PIC16LF15313/23 is an unregulated affected.
device and is always in the lowest power
state when in Sleep, with no wake-up time
penalty. This device has a lower maximum
VDD and I/O voltage than the
PIC16F15313/23. See Section 37.0
“Electrical Specifications” for more
information.

11.3 IDLE Mode

When the Idle Enable (IDLEN) bit is clear (IDLEN = 0),
the SLEEP instruction will put the device into full Sleep
mode (see Section 11.2 “Sleep Mode”). When IDLEN
is set (IDLEN = 1), the SLEEP instruction will put the
device into IDLE mode. In IDLE mode, the CPU and
memory operations are halted, but the peripheral
clocks continue to run. This mode is similar to DOZE
mode, except that in IDLE both the CPU and PFM are
shut off.

Note: Peripherals using FOSC will continue

running while in Idle (but not in Sleep).
Peripherals using HFINTOSCLFINTOSC
will continue running in both Idle and
Sleep.

Note: If CLKOUT is enabled (CLKOUT = 0,

Configuration Word 1), the output will
continue operating while in Idle.

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 PIC16(L)F15313/23
11.4 Register Definitions: Voltage Regulator and DOZE Control

REGISTER 11-1: VREGCON: VOLTAGE REGULATOR CONTROL REGISTER(1)

U-0 U-0 U-0 U-0 U-0 U-0 R/W-0/0 U-1
— — — — — — VREGPM —
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-2 Unimplemented: Read as ‘0’

bit 1 VREGPM: Voltage Regulator Power Mode Selection bit
1 = Low-Power Sleep mode enabled in Sleep(2)
Draws lowest current in Sleep, slower wake-up
0 = Normal Power mode enabled in Sleep(2)
Draws higher current in Sleep, faster wake-up
bit 0 Unimplemented: Read as ‘1’. Maintain this bit set

Note 1: PIC16F15313/23 only.

2: See Section 37.0 “Electrical Specifications”.

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 PIC16(L)F15313/23
REGISTER 11-2: CPUDOZE: DOZE AND IDLE REGISTER
R/W-0/u R/W/HC/HS-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 R/W-0/0
IDLEN DOZEN(1,2) ROI DOE — DOZE<2:0>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other
Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 IDLEN: Idle Enable bit

1 = A SLEEP instruction inhibits the CPU clock, but not the peripheral clock(s)
0 = A SLEEP instruction places the device into full Sleep mode
bit 6 DOZEN: Doze Enable bit(1,2)
1 = The CPU executes instruction cycles according to DOZE setting
0 = The CPU executes all instruction cycles (fastest, highest power operation)
bit 5 ROI: Recover-on-Interrupt bit
1 = Entering the Interrupt Service Routine (ISR) makes DOZEN = 0 bit, bringing the CPU to full-speed
operation.
0 = Interrupt entry does not change DOZEN
bit 4 DOE: Doze on Exit bit
1 = Executing RETFIE makes DOZEN = 1, bringing the CPU to reduced speed operation.
0 = RETFIE does not change DOZEN
bit 3 Unimplemented: Read as ‘0’
bit 2-0 DOZE<2:0>: Ratio of CPU Instruction Cycles to Peripheral Instruction Cycles
111 =1:256
110 =1:128
101 =1:64
100 =1:32
011 =1:16
010 =1:8
001 =1:4
000 =1:2

Note 1: When ROI = 1 or DOE = 1, DOZEN is changed by hardware interrupt entry and/or exit.
2: Entering ICD overrides DOZEN, returning the CPU to full execution speed; this bit is not affected.

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 PIC16(L)F15313/23
TABLE 11-1: SUMMARY OF REGISTERS ASSOCIATED WITH POWER-DOWN MODE
Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
on Page
INTCON GIE PEIE — — — — — INTEDG 121
PIE0 — — TMR0IE IOCIE — — — INTE 122
PIE1 OSFIE CSWIE — — — — — ADIE 123
PIE2 — ZCDIE — — — — C2IE (1)
C1IE 124
PIE3 — — RC1IE TX1IE — — BCL1IE SSP1IE 125
PIE4 — — — — — — TMR2IE TMR1IE 126
PIR0 — — TMR0IF IOCIF — — — INTF 130
PIR1 OSFIF CSWIF — — — — — ADIF 131
PIR2 — ZCDIF — — — — C2IF(1) C1IF 132
PIR3 — — RC1IF TX1IF — — BCL1IF SSP1IF 133
PIR4 — — — — — — TMR2IF TMR1IF 134
IOCAP — — IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0 204
IOCAN — — IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0 204
IOCAF — — IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0 205
IOCCP(1) — — IOCCP5 IOCCP4 IOCCP3 IOCCP2 IOCCP1 IOCCP0 206
IOCCN(1) — — IOCCN5 IOCCN4 IOCCN3 IOCCN2 IOCCN1 IOCCN0 206
IOCCF(1) — — IOCCF5 IOCCF4 IOCCF3 IOCCF2 IOCCF1 IOCCF0 207
STATUS — — — TO PD Z DC C 32
VREGCON — — — — — — VREGPM — 143
CPUDOZE IDLEN DOZEN ROI DOE — DOZE<2:0> 144
WDTCON0 — — WDTPS<4:0> SWDTEN 150
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used in Power-Down mode.
Note 1: Present only in PIC16(L)F15323.

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 PIC16(L)F15313/23
12.0 WINDOWED WATCHDOG
TIMER (WWDT)
The Watchdog Timer (WDT) is a system timer that
generates a Reset if the firmware does not issue a
CLRWDT instruction within the time-out period. The
Watchdog Timer is typically used to recover the system
from unexpected events. The Windowed Watchdog
Timer (WWDT) differs in that CLRWDT instructions are
only accepted when they are performed within a
specific window during the time-out period.
The WDT has the following features:
• Selectable clock source
• Multiple operating modes
- WDT is always on
- WDT is off when in Sleep
- WDT is controlled by software
- WDT is always off
• Configurable time-out period is from 1 ms to 256
seconds (nominal)
• Configurable window size from 12.5 to 100
percent of the time-out period
• Multiple Reset conditions
• Operation during Sleep

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 PIC16(L)F15313/23
FIGURE 12-1: WATCHDOG TIMER BLOCK DIAGRAM

Rev. 10-000162B
8/21/2015

WWDT
Armed
WDT
Window
Violation
Window Closed
Window
Comparator
CLRWDT Sizes

WDTWS

RESET

Reserved 111
Reserved 110
Reserved 101
R
Reserved 100 18-bit Prescale
Reserved 011 Counter
E
Reserved 010
MFINTOSC/16 001
LFINTOSC 000

WDTCS

WDTPS

R
5-bit Overflow
WDT Time-out
WDT Counter Latch

WDTE<1:0> = 01
SWDTEN

WDTE<1:0> = 11

WDTE<1:0> = 10
Sleep

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 PIC16(L)F15313/23
12.1 Independent Clock Source 12.4 Watchdog Window
The WDT can derive its time base from either the 31 The Watchdog Timer has an optional Windowed mode
kHz LFINTOSC or 31.25 kHz MFINTOSC internal that is controlled by the WDTCWS<2:0> Configuration
oscillators, depending on the value of either the bits and WINDOW<2:0> bits of the WDTCON1 register.
WDTCCS<2:0> Configuration bits or the WDTCS<2:0> In the Windowed mode, the CLRWDT instruction must
bits of WDTCON1. Time intervals in this chapter are occur within the allowed window of the WDT period. Any
based on a minimum nominal interval of 1 ms. See CLRWDT instruction that occurs outside of this window
Section 37.0 “Electrical Specifications” for will trigger a window violation and will cause a WDT
LFINTOSC and MFINTOSC tolerances. Reset, similar to a WDT time out. See Figure 12-2 for an
example.
12.2 WDT Operating Modes The window size is controlled by the WDTCWS<2:0>
Configuration bits, or the WINDOW<2:0> bits of
The Watchdog Timer module has four operating modes
WDTCON1, if WDTCWS<2:0> = 111.
controlled by the WDTE<1:0> bits in Configuration
Words. See Table 12-1. In the event of a window violation, a Reset will be
generated and the WDTWV bit of the PCON register
12.2.1 WDT IS ALWAYS ON will be cleared. This bit is set by a POR or can be set in
When the WDTE bits of Configuration Words are set to firmware.
‘11’, the WDT is always on.
12.5 Clearing the WDT
WDT protection is active during Sleep.
The WDT is cleared when any of the following
12.2.2 WDT IS OFF IN SLEEP conditions occur:
When the WDTE bits of Configuration Words are set to • Any Reset
‘10’, the WDT is on, except in Sleep. • Valid CLRWDT instruction is executed
WDT protection is not active during Sleep. • Device enters Sleep
• Device wakes up from Sleep
12.2.3 WDT CONTROLLED BY SOFTWARE
• WDT is disabled
When the WDTE bits of Configuration Words are set to
• Oscillator Start-up Timer (OST) is running
‘01’, the WDT is controlled by the SWDTEN bit of the
WDTCON0 register. • Any write to the WDTCON0 or WDTCON1 registers

12.2.4 WDT IS OFF 12.5.1 CLRWDT CONSIDERATIONS

(WINDOWED MODE)
When the WDTE bits of the Configuration Word are set
to ‘00’, the WDT is always OFF. When in Windowed mode, the WDT must be armed
before a CLRWDT instruction will clear the timer. This is
WDT protection is unchanged by Sleep. See Table 12-1 performed by reading the WDTCON0 register. Execut-
for more details. ing a CLRWDT instruction without performing such an
arming action will trigger a window violation.
TABLE 12-1: WDT OPERATING MODES
See Table 12-2 for more information.
Device WDT
WDTE<1:0> SWDTEN
Mode Mode
12.6 Operation During Sleep
11 X X Active When the device enters Sleep, the WDT is cleared. If
Awake Active the WDT is enabled during Sleep, the WDT resumes
10 X counting. When the device exits Sleep, the WDT is
Sleep Disabled cleared again.
1 X Active The WDT remains clear until the OST, if enabled, com-
01 pletes. See Section 9.0 “Oscillator Module (with Fail-
0 X Disabled
Safe Clock Monitor)” for more information on the OST.
00 X X Disabled When a WDT time-out occurs while the device is in
Sleep, no Reset is generated. Instead, the device
12.3 Time-Out Period wakes up and resumes operation. The TO and PD bits
in the STATUS register are changed to indicate the
The WDTPS bits of the WDTCON0 register set the event. The RWDT bit in the PCON register can also be
time-out period from 1 ms to 256 seconds (nominal). used. See Section 4.3.2.1 “STATUS Register” for
After a Reset, the default time-out period is two more information.
seconds.

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 PIC16(L)F15313/23

TABLE 12-2: WDT CLEARING CONDITIONS

Conditions WDT
WDTE<1:0> = 00
WDTE<1:0> = 01 and SWDTEN = 0
WDTE<1:0> = 10 and enter Sleep
Cleared
CLRWDT Command
Oscillator Fail Detected
Exit Sleep + System Clock = EXTOSC, INTOSC
Change INTOSC divider (IRCF bits) Unaffected

FIGURE 12-2: WINDOW PERIOD AND DELAY

Rev. 10-000163A
8/15/2016

CLRWDT Instruction
(or other WDT Reset)
Window Period

Window Closed Window Open

Time-out Event
Window Delay
(window violation can occur)

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12.7 Register Definitions: Windowed Watchdog Timer Control

REGISTER 12-1: WDTCON0: WATCHDOG TIMER CONTROL REGISTER 0

U-0 U-0 R/W(3)-q/q(2) R/W(3)-q/q(2) R/W(3)-q/q(2) R/W(3)-q/q(2) R/W(3)-q/q(2) R/W-0/0
— — WDTPS<4:0>(1) SWDTEN
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition

bit 7-6 Unimplemented: Read as ‘0’

bit 5-1 WDTPS<4:0>: Watchdog Timer Prescale Select bits(1)
Bit Value = Prescale Rate
11111 = Reserved. Results in minimum interval (1:32)
•
•
•
10011 = Reserved. Results in minimum interval (1:32)

10010 = 1:8388608 (223) (Interval 256s nominal)

10001 = 1:4194304 (222) (Interval 128s nominal)
10000 = 1:2097152 (221) (Interval 64s nominal)
01111 = 1:1048576 (220) (Interval 32s nominal)
01110 = 1:524288 (219) (Interval 16s nominal)
01101 = 1:262144 (218) (Interval 8s nominal)
01100 = 1:131072 (217) (Interval 4s nominal)
01011 = 1:65536 (Interval 2s nominal) (Reset value)
01010 = 1:32768 (Interval 1s nominal)
01001 = 1:16384 (Interval 512 ms nominal)
01000 = 1:8192 (Interval 256 ms nominal)
00111 = 1:4096 (Interval 128 ms nominal)
00110 = 1:2048 (Interval 64 ms nominal)
00101 = 1:1024 (Interval 32 ms nominal)
00100 = 1:512 (Interval 16 ms nominal)
00011 = 1:256 (Interval 8 ms nominal)
00010 = 1:128 (Interval 4 ms nominal)
00001 = 1:64 (Interval 2 ms nominal)
00000 = 1:32 (Interval 1 ms nominal)
bit 0 SWDTEN: Software Enable/Disable for Watchdog Timer bit
If WDTE<1:0> = 1x:
This bit is ignored.
If WDTE<1:0> = 01:
1 = WDT is turned on
0 = WDT is turned off
If WDTE<1:0> = 00:
This bit is ignored.

Note 1: Times are approximate. WDT time is based on 31 kHz LFINTOSC.

2: When WDTCPS <4:0> in CONFIG3 = 11111, the Reset value of WDTPS<4:0> is 01011. Otherwise, the
Reset value of WDTPS<4:0> is equal to WDTCPS<4:0> in CONFIG3.
3: When WDTCPS <4:0> in CONFIG3 ≠ 11111, these bits are read-only.

 2017 Microchip Technology Inc. Preliminary DS40001897A-page 150

 PIC16(L)F15313/23

REGISTER 12-2: WDTCON1: WATCHDOG TIMER CONTROL REGISTER 1

U-0 R/W(3)-q/q(1) R/W(3)-q/q(1) R/W(3)-q/q(1) U-0 R/W(4)-q/q(2) R/W(4)-q/q(2) R/W(4)-q/q(2)
— —
WDTCS<2:0> WINDOW<2:0>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition

bit 7 Unimplemented: Read as ‘0’

bit 6-4 WDTCS<2:0>: Watchdog Timer Clock Select bits
111 = Reserved
•
•
•
010 = Reserved
001 = MFINTOSC 31.25 kHz
000 = LFINTOSC 31 kHz
bit 3 Unimplemented: Read as ‘0’
bit 2-0 WINDOW<2:0>: Watchdog Timer Window Select bits

Window delay Window opening

WINDOW<2:0>
Percent of time Percent of time
111 N/A 100
110 12.5 87.5
101 25 75
100 37.5 62.5
011 50 50
010 62.5 37.5
001 75 25
000 87.5 12.5

Note 1: If WDTCCS <2:0> in CONFIG3 = 111, the Reset value of WDTCS<2:0> is 000.
2: The Reset value of WINDOW<2:0> is determined by the value of WDTCWS<2:0> in the CONFIG3 register.
3: If WDTCCS<2:0> in CONFIG3 ≠ 111, these bits are read-only.
4: If WDTCWS<2:0> in CONFIG3 ≠ 111, these bits are read-only.

 2017 Microchip Technology Inc. Preliminary DS40001897A-page 151

 PIC16(L)F15313/23

REGISTER 12-3: WDTPSL: WDT PRESCALE SELECT LOW BYTE REGISTER

R-0/0 R-0/0 R-0/0 R-0/0 R-0/0 R-0/0 R-0/0 R-0/0
PSCNT<7:0>(1)
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-0 PSCNT<7:0>: Prescale Select Low Byte bits(1)

Note 1: The 18-bit WDT prescale value, PSCNT<17:0> includes the WDTPSL, WDTPSH and the lower bits of the WDTTMR
registers. PSCNT<17:0> is intended for debug operations and should be read during normal operation.

REGISTER 12-4: WDTPSH: WDT PRESCALE SELECT HIGH BYTE REGISTER

R-0/0 R-0/0 R-0/0 R-0/0 R-0/0 R-0/0 R-0/0 R-0/0
PSCNT<15:8>(1)
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-0 PSCNT<15:8>: Prescale Select High Byte bits(1)

Note 1: The 18-bit WDT prescale value, PSCNT<17:0> includes the WDTPSL, WDTPSH and the lower bits of the WDTTMR
registers. PSCNT<17:0> is intended for debug operations and should be read during normal operation.

REGISTER 12-5: WDTTMR: WDT TIMER REGISTER

U-0 R-0/0 R-0/0 R-0/0 R-0/0 R-0/0 R-0/0 R-0/0
— WDTTMR<3:0> STATE PSCNT<17:16>(1)
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 Unimplemented: Read as ‘0’

bit 6-3 WDTTMR<3:0>: Watchdog Timer Value bits
bit 2 STATE: WDT Armed Status bit
1 = WDT is armed
0 = WDT is not armed
bit 1-0 PSCNT<17:16>: Prescale Select Upper Byte bits(1)

Note 1: The 18-bit WDT prescale value, PSCNT<17:0> includes the WDTPSL, WDTPSH and the lower bits of the WDTTMR
registers. PSCNT<17:0> is intended for debug operations and should be read during normal operation.

 2017 Microchip Technology Inc. Preliminary DS40001897A-page 152

 PIC16(L)F15313/23
TABLE 12-3: SUMMARY OF REGISTERS ASSOCIATED WITH WATCHDOG TIMER
Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
on Page
OSCCON1 — NOSC<2:0> NDIV<3:0> 110
OSCCON2 — COSC<2:0> CDIV<3:0> 110
OSCCON3 CSWHOLD — — ORDY NOSCR — — — 111
PCON0 STKOVF STKUNF WDTWV RWDT RMCLR RI POR BOR 99
STATUS — — — TO PD Z DC C 32
WDTCON0 — — WDTPS<4:0> SWDTEN 150
WDTCON1 — WDTCS<2:0> — WINDOW<2:0> 151
WDTPSL PSCNT<7:0> 152
WDTPSH PSCNT<15:8> 152
WDTTMR — WDTTMR<4:0> STATE PSCNT<17:16> 152
Legend: – = unimplemented locations read as ‘0’. Shaded cells are not used by Watchdog Timer.

TABLE 12-4: SUMMARY OF CONFIGURATION WORD WITH WATCHDOG TIMER

Register
Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0
on Page

13:8 — — FCMEN — CSWEN — — CLKOUTEN

CONFIG1 76
7:0 — RSTOSC<2:0> — FEXTOSC<2:0>
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Watchdog Timer.

 2017 Microchip Technology Inc. Preliminary DS40001897A-page 153

 PIC16(L)F15313/23
13.0 NONVOLATILE MEMORY
TABLE 13-1: FLASH MEMORY
(NVM) CONTROL ORGANIZATION BY DEVICE
NVM consists of the Program Flash Memory (PFM). Total
Row Write
NVM is accessible by using both the FSR and INDF Program
Device Erase Latches
registers, or through the NVMREG register interface. Flash
(words) (words)
The write time is controlled by an on-chip timer. The (words)
write/erase voltages are generated by an on-chip 2048
charge pump rated to operate over the operating PIC16(L)F15313
32 32
PIC16(L)F15323 2048
voltage range of the device.
NVM can be protected in two ways; by either code It is important to understand the PFM memory structure
protection or write protection. for erase and programming operations. PFM is
Code protection (CP bit in Configuration Word 5) arranged in rows. A row consists of 32 14-bit program
disables access, reading and writing, to the PFM via memory words. A row is the minimum size that can be
external device programmers. Code protection does erased by user software.
not affect the self-write and erase functionality. Code All or a portion of a row can be programmed. Data to be
protection can only be Reset by a device programmer written into the program memory row is written to 14-bit
performing a Bulk Erase to the device, clearing all wide data write latches. These latches are not directly
nonvolatile memory, Configuration bits, and User IDs. accessible, but may be loaded via sequential writes to
Write protection prohibits self-write and erase to a the NVMDATH:NVMDATL register pair.
portion or all of the PFM, as defined by the WRT<1:0>
bits of Configuration Word 4. Write protection does not
Note: To modify only a portion of a previously
affect a device programmer’s ability to read, write, or
programmed row, the contents of the
erase the device.
entire row must be read. Then, the new
data and retained data can be written into
13.1 Program Flash Memory (PFM) the write latches to reprogram the row of
PFM consists of an array of 14-bit words as user PFM. However, any unprogrammed
memory, with additional words for User ID information, locations can be written without first
Configuration words, and interrupt vectors. PFM erasing the row. In this case, it is not
provides storage locations for: necessary to save and rewrite the other
previously programmed locations
• User program instructions
• User defined data
13.1.1 PROGRAM MEMORY VOLTAGES
PFM data can be read and/or written to through:
The PFM is readable and writable during normal
• CPU instruction fetch (read-only) operation over the full VDD range.
• FSR/INDF indirect access (read-only)
(Section 13.2 “FSR and INDF Access”) 13.1.1.1 Programming Externally
• NVMREG access (Section 13.3 “NVMREG
Access” The program memory cell and control logic support
• In-Circuit Serial Programming™ (ICSP™) write and Bulk Erase operations down to the minimum
device operating voltage. Special BOR operation is
Read operations return a single word of memory. When enabled during Bulk Erase (Section 8.2.4 “BOR is
write and erase operations are done on a row basis, the always OFF”).
row size is defined in Table 13-1. PFM will erase to a
logic ‘1’ and program to a logic ‘0’. 13.1.1.2 Self-programming
The program memory cell and control logic will support
write and row erase operations across the entire VDD
range. Bulk Erase is not available when self-
programming.

 2017 Microchip Technology Inc. Preliminary DS40001897A-page 154

 PIC16(L)F15313/23
13.2 FSR and INDF Access FIGURE 13-1: FLASH PROGRAM
MEMORY READ
The FSR and INDF registers allow indirect access to
FLOWCHART
the PFM.

13.2.1 FSR READ Rev. 10-000046D

8/15/2016

With the intended address loaded into an FSR register

a MOVIW instruction or read of INDF will read data from Start
the PFM. Read Operation

Reading from NVM requires one instruction cycle. The

CPU operation is suspended during the read, and
resumes immediately after. Read operations return a Select Memory:
PFM, DIA, DCI, Config Words, User
single byte of memory.
ID (NVMREGS)

13.2.2 FSR WRITE

Writing/erasing the NVM through the FSR registers (ex. Select
MOVWI instruction) is not supported in the Word Address
PIC16(L)F15313/23 devices. (NVMADRH:NVMADRL)

13.3 NVMREG Access

Data read now in
The NVMREG interface allows read/write access to all NVMDATH:NVMDATL
the locations accessible by FSRs, and also read/write
access to the User ID locations, and read-only access
to the device identification, revision, and Configuration
data. End
Read Operation
Writing or erasing of NVM via the NVMREG interface is
prevented when the device is write-protected.

13.3.1 NVMREG READ OPERATION

To read a NVM location using the NVMREG interface,
the user must:
1. Clear the NVMREGS bit of the NVMCON1
register if the user intends to access PFM
locations, or set NMVREGS if the user intends
to access User ID, or Configuration locations.
2. Write the desired address into the
NVMADRH:NVMADRL register pair ().
3. Set the RD bit of the NVMCON1 register to
initiate the read.
Once the read control bit is set, the CPU operation is
suspended during the read, and resumes immediately
after. The data is available in the very next cycle, in the
NVMDATH:NVMDATL register pair; therefore, it can be
read as two bytes in the following instructions.
NVMDATH:NVMDATL register pair will hold this value
until another read or until it is written to by the user.
Upon completion, the RD bit is cleared by hardware.

 2017 Microchip Technology Inc. Preliminary DS40001897A-page 155

 PIC16(L)F15313/23
EXAMPLE 13-1: PROGRAM MEMORY READ
* This code block will read 1 word of program
* memory at the memory address:
PROG_ADDR_HI : PROG_ADDR_LO
* data will be returned in the variables;
* PROG_DATA_HI, PROG_DATA_LO

BANKSEL NVMADRL ; Select Bank for NVMCON registers

MOVLW PROG_ADDR_LO ;
MOVWF NVMADRL ; Store LSB of address
MOVLW PROG_ADDR_HI ;
MOVWF NVMADRH ; Store MSB of address

BCF NVMCON1,NVMREGS ; Do not select Configuration Space

BSF NVMCON1,RD ; Initiate read

MOVF NVMDATL,W ; Get LSB of word

MOVWF PROG_DATA_LO ; Store in user location
MOVF NVMDATH,W ; Get MSB of word
MOVWF PROG_DATA_HI ; Store in user location

 2017 Microchip Technology Inc. Preliminary DS40001897A-page 156

 PIC16(L)F15313/23
13.3.2 NVM UNLOCK SEQUENCE FIGURE 13-2: NVM UNLOCK
The unlock sequence is a mechanism that protects the SEQUENCE FLOWCHART
NVM from unintended self-write programming or
erasing. The sequence must be executed and Rev. 10-000047B

completed without interruption to successfully

8/24/2015

complete any of the following operations:

• PFM Row Erase Start
• Load of PFM write latches Unlock Sequence
• Write of PFM write latches to PFM memory
• Write of PFM write latches to User IDs
The unlock sequence consists of the following steps
Write 0x55 to
and must be completed in order: NVMCON2
• Write 55h to NVMCON2
• Write AAh to NMVCON2
• Set the WR bit of NVMCON1
Write 0xAA to
Once the WR bit is set, the processor will stall internal NVMCON2
operations until the operation is complete and then
resume with the next instruction.
Initiate
Write or Erase operation
Note: The two NOP instructions after setting the (WR = 1)
WR bit that were required in previous
devices are not required for
PIC16(L)F15313/23 devices. See
End
Figure 13-2. Unlock Sequence
Since the unlock sequence must not be interrupted,
global interrupts should be disabled prior to the unlock
sequence and re-enabled after the unlock sequence is
completed.

EXAMPLE 13-2: NVM UNLOCK SEQUENCE

BCF INTCON, GIE ; Recommended so sequence is not interrupted
BANKSEL NVMCON1 ;
BSF NVMCON1, WREN ; Enable write/erase
MOVLW 55h ; Load 55h
MOVWF NVMCON2 ; Step 1: Load 55h into NVMCON2
MOVLW AAh ; Step 2: Load W with AAh
MOVWF NVMCON2 ; Step 3: Load AAH into NVMCON2
BSF NVMCON1, WR ; Step 4: Set WR bit to begin write/erase
BSF INTCON, GIE ; Re-enable interrupts

Note 1: Sequence begins when NVMCON2 is written; steps 1-4 must occur in the cycle-accurate order shown.
2: Opcodes shown are illustrative; any instruction that has the indicated effect may be used.

 2017 Microchip Technology Inc. Preliminary DS40001897A-page 157

 PIC16(L)F15313/23
13.3.3 NVMREG ERASE OF PFM FIGURE 13-3: NVM ERASE
Before writing to PFM, the word(s) to be written must FLOWCHART
be erased or previously unwritten. PFM can only be Rev. 10-000048B
8/24/2015

erased one row at a time. No automatic erase occurs

upon the initiation of the write to PFM.
Start
To erase a PFM row: Erase Operation
1. Clear the NVMREGS bit of the NVMCON1
register to erase PFM locations, or set the
NMVREGS bit to erase User ID locations. Select Memory:
2. Write the desired address into the PFM, Config Words, User ID
(NVMREGS)
NVMADRH:NVMADRL register pair (Table 13-2).
3. Set the FREE and WREN bits of the NVMCON1
register.
Select Word Address
4. Perform the unlock sequence as described in (NVMADRH:NVMADRL)
Section 13.3.2 “NVM Unlock Sequence”.
If the PFM address is write-protected, the WR bit will be
cleared and the erase operation will not take place.
Select Erase Operation
While erasing PFM, CPU operation is suspended, and (FREE=1)
resumes when the operation is complete. Upon
completion, the NVMIF is set, and an interrupt will
occur if the NVMIE bit is also set.
Write latch data is not affected by erase operations, Enable Write/Erase Operation
(WREN=1)
and WREN will remain unchanged.

Disable Interrupts
(GIE=0)

Unlock Sequence
(See Note 1)

CPU stalls while

Erase operation completes
(2 ms typical)

Disable Write/Erase Operation

(WREN = 0)

Re-enable Interrupts
(GIE = 1)

End
Erase Operation

Note 1: See Figure 13-2.

 2017 Microchip Technology Inc. Preliminary DS40001897A-page 158

 PIC16(L)F15313/23
EXAMPLE 13-3: ERASING ONE ROW OF PROGRAM FLASH MEMORY (PFM)
; This sample row erase routine assumes the following:
; 1.A valid address within the erase row is loaded in variables ADDRH:ADDRL
; 2.ADDRH and ADDRL are located in common RAM (locations 0x70 - 0x7F)

BANKSEL NVMADRL
MOVF ADDRL,W
MOVWF NVMADRL ; Load lower 8 bits of erase address boundary
MOVF ADDRH,W
MOVWF NVMADRH ; Load upper 6 bits of erase address boundary
BCF NVMCON1,NVMREGS ; Choose PFM memory area
BSF NVMCON1,FREE ; Specify an erase operation
BSF NVMCON1,WREN ; Enable writes
BCF INTCON,GIE ; Disable interrupts during unlock sequence
; -------------------------------REQUIRED UNLOCK SEQUENCE:------------------------------

MOVLW 55h ; Load 55h to get ready for unlock sequence

MOVWF NVMCON2 ; First step is to load 55h into NVMCON2
MOVLW AAh ; Second step is to load AAh into W
MOVWF NVMCON2 ; Third step is to load AAh into NVMCON2
BSF NVMCON1,WR ; Final step is to set WR bit
; --------------------------------------------------------------------------------------

BSF INTCON,GIE ; Re-enable interrupts, erase is complete

BCF NVMCON1,WREN ; Disable writes

TABLE 13-2: NVM ORGANIZATION AND ACCESS INFORMATION

Master Values NVMREG Access FSR Access

Program
NVMREGS FSR
Memory Counter (PC), Memory NVMADR< Allowed FSR
bit Programming
Function ICSP™ Type 14:0> Operations Address
(NVMCON1) Address
Address
Reset Vector 0000h 0 0000h 8000h
0001h 0001h 8001h
User Memory 0
0003h 0003h Read 8003h
PFM Read-0nly
INT Vector 0004h 0 0004h Write 8004h
0005h 0 0005h 8005h
User Memory
07FFh 0 07FFh 87FFh
8000h 0000h Read
User ID PFM 1
8003h 0003h Write
Reserved 8004h — — 0004h —
Rev ID 8005h 1 0005h
Read-Only
Device ID 8006h 1 0006h
No Access
CONFIG1 8007h 1 0007h
CONFIG2 8008h PFM 1 0008h
Read
CONFIG3 8009h 1 0009h
Write
CONFIG4 800Ah 1 000Ah
CONFIG5 800Bh 1 000Bh
PFM and 0100h- Read-Only
DIA and DCI 8100h-82FFh 1 No Access
Hard coded 02FFh

 2017 Microchip Technology Inc. Preliminary DS40001897A-page 159

 PIC16(L)F15313/23
13.3.4 NVMREG WRITE TO PROGRAM The following steps should be completed to load the
MEMORY write latches and program a row of program memory.
These steps are divided into two parts. First, each write
Program memory is programmed using the following
latch is loaded with data from the
steps:
NVMDATH:NVMDATL using the unlock sequence with
1. Load the address of the row to be programmed LWLO = 1. When the last word to be loaded into the
into NVMADRH:NVMADRL. write latch is ready, the LWLO bit is cleared and the
2. Load each write latch with data. unlock sequence executed. This initiates the
3. Initiate a programming operation. programming operation, writing all the latches into
Flash program memory.
4. Repeat steps 1 through 3 until all data is written.
Before writing to program memory, the word(s) to be Note: The special unlock sequence is required
written must be erased or previously unwritten. to load a write latch with data or initiate a
Program memory can only be erased one row at a time. Flash programming operation. If the
No automatic erase occurs upon the initiation of the unlock sequence is interrupted, writing to
write. the latches or program memory will not be
initiated.
Program memory can be written one or more words at
a time. The maximum number of words written at one 1. Set the WREN bit of the NVMCON1 register.
time is equal to the number of write latches. See 2. Clear the NVMREGS bit of the NVMCON1
Figure 13-4 (row writes to program memory with 32 register.
write latches) for more details. 3. Set the LWLO bit of the NVMCON1 register.
The write latches are aligned to the Flash row address When the LWLO bit of the NVMCON1 register is
boundary defined by the upper ten bits of ‘1’, the write sequence will only load the write
NVMADRH:NVMADRL, (NVMADRH<6:0>:NVMADRL<7:5>) latches and will not initiate the write to Flash
with the lower five bits of NVMADRL, (NVMADRL<4:0>) program memory.
determining the write latch being loaded. Write opera- 4. Load the NVMADRH:NVMADRL register pair
tions do not cross these boundaries. At the completion with the address of the location to be written.
of a program memory write operation, the data in the 5. Load the NVMDATH:NVMDATL register pair
write latches is reset to contain 0x3FFF. with the program memory data to be written.
6. Execute the unlock sequence (Section
13.3.2 “NVM Unlock Sequence”). The write
latch is now loaded.
7. Increment the NVMADRH:NVMADRL register
pair to point to the next location.
8. Repeat steps 5 through 7 until all but the last
write latch has been loaded.
9. Clear the LWLO bit of the NVMCON1 register.
When the LWLO bit of the NVMCON1 register is
‘0’, the write sequence will initiate the write to
Flash program memory.
10. Load the NVMDATH:NVMDATL register pair
with the program memory data to be written.
11. Execute the unlock sequence (Section
13.3.2 “NVM Unlock Sequence”). The entire
program memory latch content is now written to
Flash program memory.
Note: The program memory write latches are
reset to the blank state (0x3FFF) at the
completion of every write or erase
operation. As a result, it is not necessary
to load all the program memory write
latches. Unloaded latches will remain in
the blank state.
An example of the complete write sequence is shown in
Example 13-4. The initial address is loaded into the
NVMADRH:NVMADRL register pair; the data is loaded
using indirect addressing.

 2017 Microchip Technology Inc. Preliminary DS40001897A-page 160

 FIGURE 13-4: NVMREGS WRITES TO PROGRAM FLASH MEMORY WITH 32 WRITE LATCHES
 2017 Microchip Technology Inc.

Rev. 10-000004F

7 6 0 7 5 4 0 7 5 0 7 0 8/15/2016

NVMADRH NVMADRL - - NVMDATH NVMDATL

- r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 c4 c3 c2 c1 c0 6 8

14

Program Memory Write Latches

10 5
14 14 14 14

Write Latch #0 Write Latch #1 Write Latch #30 Write Latch #31
00h 01h 1Eh 1Fh
NVMADRL<4:0>
Preliminary

14 14 14 14

Row Addr Addr Addr Addr

000h 0000h 0001h 001Eh 001Fh

001h 0010h 0011h 003Eh 003Fh

PIC16(L)F15313/23
002h 0020h 0021h 005Eh 005Fh
NVMREGS=0

Row End
Addr End Addr
Address
NVMADRH<6:0> Decode Flash Program Memory
NVMADRL<7:5>
DS40001897A-page 161

Configuration Memory
User ID, Device ID, Revision ID, Configuration Words, DIA, DCI
NVMREGS = 1
 PIC16(L)F15313/23
FIGURE 13-5: PROGRAM FLASH MEMORY WRITE FLOWCHART

Rev. 10-000049C
8/24/2015

Start
Write Operation

Determine number of
words to be written into Load the value to write
PFM. The number of TABLAT
words cannot exceed the
number of words per row
(word_cnt)

Update the word counter

Write Latches to PFM
(word_cnt--)

Select access to PFM

locations using
NVMREG<1:0> bits
Disable Interrupts
(GIE = 0)
Last word to Yes
write ?
Select Row Address
TBLPTR
No
Unlock Sequence
(See note 1)

Disable Interrupts
Select Write Operation (GIE = 0)
(FREE = 0)
CPU stalls while Write
operation completes
(2 ms typical)
Unlock Sequence
Load Write Latches Only (See note 1)

Enable Write/Erase
Operation (WREN = 1) No delay when writing to Re-enable Interrupts
PFM Latches (GIE = 1)

Disable Write/Erase
Operation (WREN = 0)

Re-enable Interrupts
(GIE = 1)

End
Write Operation

Increment Address
TBLPTR++

Note 1: See Figure 13-2.

 2017 Microchip Technology Inc. Preliminary DS40001897A-page 162

 PIC16(L)F15313/23
EXAMPLE 13-4: WRITING TO PROGRAM FLASH MEMORY
; This write routine assumes the following:
; 1. 64 bytes of data are loaded, starting at the address in DATA_ADDR
; 2. Each word of data to be written is made up of two adjacent bytes in DATA_ADDR,
; stored in little endian format
; 3. A valid starting address (the least significant bits = 00000) is loaded in ADDRH:ADDRL
; 4. ADDRH and ADDRL are located in common RAM (locations 0x70 - 0x7F)
; 5. NVM interrupts are not taken into account

BANKSEL NVMADRH
MOVF ADDRH,W
MOVWF NVMADRH ; Load initial address
MOVF ADDRL,W
MOVWF NVMADRL
MOVLW LOW DATA_ADDR ; Load initial data address
MOVWF FSR0L
MOVLW HIGH DATA_ADDR
MOVWF FSR0H
BCF NVMCON1,NVMREGS ; Set Program Flash Memory as write location
BSF NVMCON1,WREN ; Enable writes
BSF NVMCON1,LWLO ; Load only write latches

LOOP
MOVIW FSR0++
MOVWF NVMDATL ; Load first data byte
MOVIW FSR0++
MOVWF NVMDATH ; Load second data byte
MOVF NVMADRL,W
XORLW 0x1F ; Check if lower bits of address are 00000
ANDLW 0x1F ; and if on last of 32 addresses
BTFSC STATUS,Z ; Last of 32 words?
GOTO START_WRITE ; If so, go write latches into memory
CALL UNLOCK_SEQ ; If not, go load latch
INCF NVMADRL,F ; Increment address
GOTO LOOP

START_WRITE
BCF NVMCON1,LWLO ; Latch writes complete, now write memory
CALL UNLOCK_SEQ ; Perform required unlock sequence
BCF NVMCON1,WREN ; Disable writes

UNLOCK_SEQ
MOVLW 55h
BCF INTCON,GIE ; Disable interrupts
MOVWF NVMCON2 ; Begin unlock sequence
MOVLW AAh
MOVWF NVMCON2
BSF NVMCON1,WR
BSF INTCON,GIE ; Unlock sequence complete, re-enable interrupts
return

 2017 Microchip Technology Inc. Preliminary DS40001897A-page 163

 PIC16(L)F15313/23
13.3.5 MODIFYING FLASH PROGRAM FIGURE 13-6: FLASH PROGRAM
MEMORY MEMORY MODIFY
When modifying existing data in a program memory FLOWCHART
row, and data within that row must be preserved, it must Rev. 10-000050B
8/21/2015

first be read and saved in a RAM image. Program

memory is modified using the following steps:
Start
1. Load the starting address of the row to be Modify Operation
modified.
2. Read the existing data from the row into a RAM
image.
Read Operation
3. Modify the RAM image to contain the new data (See Note 1)
to be written into program memory.
4. Load the starting address of the row to be
rewritten.
An image of the entire row
5. Erase the program memory row.
read must be stored in RAM
6. Load the write latches with data from the RAM
image.
7. Initiate a programming operation.

Modify Image
The words to be modified are
changed in the RAM image

Erase Operation
(See Note 2)

Write Operation
Use RAM image
(See Note 3)

End
Modify Operation

Note 1: See Figure 13-1.

2: See Figure 13-3.
3: See Figure 13-5.

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 PIC16(L)F15313/23
13.3.6 NVMREG ACCESS TO DEVICE
INFORMATION AREA, DEVICE
CONFIGURATION AREA, USER ID,
DEVICE ID AND CONFIGURATION
WORDS
NVMREGS can be used to access the following
memory regions:
• Device Information Area (DIA)
• Device Configuration Information (DCI)
• User ID region
• Device ID and Revision ID
• Configuration Words
The value of NVMREGS is set to ‘1’ in the NVMCON1
register to access these regions. The memory regions
listed above would be pointed to by PC<15> = 1, but
not all addresses reference valid data. Different access
may exist for reads and writes. Refer to Table 13-3.
When read access is initiated on an address outside
the parameters listed in Table 13-3, the NVMDATH:
NVMDATL register pair is cleared, reading back ‘0’s.

TABLE 13-3: NVMREGS ACCESS TO DEVICE INFORMATION AREA, DEVICE CONFIGURATION

AREA, USER ID, DEVICE ID AND CONFIGURATION WORDS (NVMREGS = 1)
Address Function Read Access Write Access
8000h-8003h User IDs Yes Yes
8005h-8006h Device ID/Revision ID Yes No
8007h-800Bh Configuration Words 1-5 Yes No
8100h-82FFh DIA and DCI Yes No

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 PIC16(L)F15313/23
EXAMPLE 13-5: DEVICE ID ACCESS
; This write routine assumes the following:
; 1. A full row of data are loaded, starting at the address in DATA_ADDR
; 2. Each word of data to be written is made up of two adjacent bytes in DATA_ADDR,
; stored in little endian format
; 3. A valid starting address (the least significant bits = 00000) is loaded in ADDRH:ADDRL
; 4. ADDRH and ADDRL are located in common RAM (locations 0x70 - 0x7F)
; 5. NVM interrupts are not taken into account

BANKSEL NVMADRH
MOVF ADDRH,W
MOVWF NVMADRH ; Load initial address
MOVF ADDRL,W
MOVWF NVMADRL
MOVLW LOW DATA_ADDR ; Load initial data address
MOVWF FSR0L
MOVLW HIGH DATA_ADDR
MOVWF FSR0H
BCF NVMCON1,NVMREGS ; Set PFM as write location
BSF NVMCON1,WREN ; Enable writes
BSF NVMCON1,LWLO ; Load only write latches

LOOP
MOVIW FSR0++
MOVWF NVMDATL ; Load first data byte
MOVIW FSR0++
MOVWF NVMDATH ; Load second data byte
CALL UNLOCK_SEQ ; If not, go load latch
INCF NVMADRL,F ; Increment address
MOVF NVMADRL,W
XORLW 0x1F ; Check if lower bits of address are 00000
ANDLW 0x1F ; and if on last of 32 addresses
BTFSC STATUS,Z ; Last of 32 words?
GOTO START_WRITE ; If so, go write latches into memory
GOTO LOOP

START_WRITE
BCF NVMCON1,LWLO ; Latch writes complete, now write memory
CALL UNLOCK_SEQ ; Perform required unlock sequence
BCF NVMCON1,LWLO ; Disable writes

UNLOCK_SEQ
MOVLW 55h
BCF INTCON,GIE ; Disable interrupts
MOVWF NVMCON2 ; Begin unlock sequence
MOVLW AAh
MOVWF NVMCON2
BSF NVMCON1,WR
BSF INTCON,GIE ; Unlock sequence complete, re-enable interrupts
return

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13.3.7 WRITE VERIFY
It is considered good programming practice to verify that
program memory writes agree with the intended value.
Since program memory is stored as a full row then the
stored program memory contents are compared with the
intended data stored in RAM after the last write is
complete.

FIGURE 13-7: FLASH PROGRAM

MEMORY VERIFY
FLOWCHART
Rev. 10-000051B
12/4/2015

Start
Verify Operation

This routine assumes that the last

row of data written was from an
image saved on RAM. This image
will be used to verify the data
currently stored in PFM

Read Operation(1)

NVMDAT = No
RAM image ?

Yes
Fail
Verify Operation

No Last word ?

Yes

End
Verify Operation

Note 1: See Figure 13-1.

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 PIC16(L)F15313/23
13.3.8 WRERR BIT
The WRERR bit can be used to determine if a write
error occurred.
WRERR will be set if one of the following conditions
occurs:
• If WR is set while the NVMADRH:NMVADRL
points to a write-protected address
• A Reset occurs while a self-write operation was in
progress
• An unlock sequence was interrupted
The WRERR bit is normally set by hardware, but can
be set by the user for test purposes. Once set, WRERR
must be cleared in software.

TABLE 13-4: ACTIONS FOR PFM WHEN WR = 1

Free LWLO Actions for PFM when WR = 1 Comments
1 x Erase the 32-word row of NVMADRH:NVMADRL • If WP is enabled, WR is cleared and
location. See Section 13.3.3 “NVMREG Erase WRERR is set
of PFM” • All 32 words are erased
• NVMDATH:NVMDATL is ignored
0 1 Copy NVMDATH:NVMDATL to the write latch • Write protection is ignored
corresponding to NVMADR LSBs. See Section • No memory access occurs
13.3.3 “NVMREG Erase of PFM”
0 0 Write the write-latch data to PFM row. See Sec- • If WP is enabled, WR is cleared and
tion 13.3.3 “NVMREG Erase of PFM” WRERR is set
• Write latches are reset to 3FFh
• NVMDATH:NVMDATL is ignored

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13.4 Register Definitions: Flash Program Memory Control
REGISTER 13-1: NVMDATL: NONVOLATILE MEMORY DATA LOW BYTE REGISTER
R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
NVMDAT<7:0>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-0 NVMDAT<7:0>: Read/write value for Least Significant bits of program memory

REGISTER 13-2: NVMDATH: NONVOLATILE MEMORY DATA HIGH BYTE REGISTER

U-0 U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
— — NVMDAT<13:8>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 Unimplemented: Read as ‘0’

bit 5-0 NVMDAT<13:8>: Read/write value for Most Significant bits of program memory

REGISTER 13-3: NVMADRL: NONVOLATILE MEMORY ADDRESS LOW BYTE REGISTER

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
NVMADR<7:0>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-0 NVMADR<7:0>: Specifies the Least Significant bits for program memory address

REGISTER 13-4: NVMADRH: NONVOLATILE MEMORY ADDRESS HIGH BYTE REGISTER

U-1 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
—(1) NVMADR<14:8>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 Unimplemented: Read as ‘1’

bit 6-0 NVMADR<14:8>: Specifies the Most Significant bits for program memory address

Note 1: Bit is undefined while WR = 1

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REGISTER 13-5: NVMCON1: NONVOLATILE MEMORY CONTROL 1 REGISTER

U-0 R/W-0/0 R/W-0/0 R/W/HC-0/0 R/W/HC-x/q R/W-0/0 R/S/HC-0/0 R/S/HC-0/0
— NVMREGS LWLO FREE WRERR(1,2,3) WREN WR(4,5,6) RD
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
S = Bit can only be set x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared HC = Bit is cleared by hardware

bit 7 Unimplemented: Read as ‘0’

bit 6 NVMREGS: Configuration Select bit
1 = Access DIA, DCI, Configuration, User ID and Device ID Registers
0 = Access PFM
bit 5 LWLO: Load Write Latches Only bit
When FREE = 0:
1 = The next WR command updates the write latch for this word within the row; no memory operation is initiated.
0 = The next WR command writes data or erases
Otherwise: The bit is ignored
bit 4 FREE: PFM Erase Enable bit
When NVMREGS:NVMADR points to a PFM location:
1 = Performs an erase operation with the next WR command; the 32-word pseudo-row containing the indicated
address is erased (to all 1s) to prepare for writing.
0 = All erase operations have completed normally
bit 3 WRERR: Program/Erase Error Flag bit(1,2,3)
This bit is normally set by hardware.
1 = A write operation was interrupted by a Reset, interrupted unlock sequence, or WR was written to one while
NVMADR points to a write-protected address.
0 = The program or erase operation completed normally
bit 2 WREN: Program/Erase Enable bit
1 = Allows program/erase cycles
0 = Inhibits programming/erasing of program Flash
bit 1 WR: Write Control bit(4,5,6)
When NVMREG:NVMADR points to a PFM location:
1 = Initiates the operation indicated by Table 13-4
0 = NVM program/erase operation is complete and inactive.
bit 0 RD: Read Control bit(7)
1 = Initiates a read at address = NVMADR1, and loads data to NVMDAT Read takes one instruction cycle and the
bit is cleared when the operation is complete. The bit can only be set (not cleared) in software.
0 = NVM read operation is complete and inactive

Note 1: Bit is undefined while WR = 1.

2: Bit must be cleared by software; hardware will not clear this bit.
3: Bit may be written to ‘1’ by software in order to implement test sequences.
4: This bit can only be set by following the unlock sequence of Section 13.3.2 “NVM Unlock Sequence”.
5: Operations are self-timed, and the WR bit is cleared by hardware when complete.
6: Once a write operation is initiated, setting this bit to zero will have no effect.

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REGISTER 13-6: NVMCON2: NONVOLATILE MEMORY CONTROL 2 REGISTER

W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0
NVMCON2<7:0>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
S = Bit can only be set x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-0 NVMCON2<7:0>: Flash Memory Unlock Pattern bits

To unlock writes, a 55h must be written first followed by an AAh before setting the WR bit of the
NVMCON1 register. The value written to this register is used to unlock the writes.

TABLE 13-5: SUMMARY OF REGISTERS ASSOCIATED WITH NONVOLATILE MEMORY (NVM)

Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
on Page
INTCON GIE PEIE — — — — — INTEDG 121
PIE7 — — NVMIE NCO1IE — — — CWG1IE 129
PIR7 — — NVMIF NCO1IF — — — CWG1IF 137
NVMCON1 — NVMREGS LWLO FREE WRERR WREN WR RD 170
NVMCON2 NVMCON2<7:0> 171
NVMADRL NVMADR<7:0> 169
NVMADRH —(1) NVMADR<14:8> 169
NVMDATL NVMDAT<7:0> 169
NVMDATH — — NVMDAT<13:8> 169
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by NVM.
Note 1: Unimplemented, read as ‘1’.

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 PIC16(L)F15313/23
14.0 I/O PORTS Disabling the input buffer prevents analog signal levels
on the pin between a logic high and low from causing
excessive current in the logic input circuitry. A
TABLE 14-1: PORT AVAILABILITY PER
simplified model of a generic I/O port, without the
DEVICE
interfaces to other peripherals, is shown in Figure 14-1.

PORTC
PORTA
Device FIGURE 14-1: GENERIC I/O PORT
OPERATION
PIC16(L)F15313 ● Rev. 10-000052A
7/30/2013

PIC16(L)F15323 ● ● Read LATx

Each port has standard registers for its operation.

These registers are: TRISx
• PORTx registers (reads the levels on the pins of
D Q
the device)
Write LATx
• LATx registers (output latch) Write PORTx VDD
• TRISx registers (data direction) CK

• ANSELx registers (analog select) Data Register

• WPUx registers (weak pull-up) Data bus
• INLVLx (input level control) I/O pin
• SLRCONx registers (slew rate) Read PORTx

• ODCONx registers (open-drain) To digital peripherals

Most port pins share functions with device peripherals, ANSELx

both analog and digital. In general, when a peripheral To analog peripherals
is enabled on a port pin, that pin cannot be used as a
general purpose output; however, the pin can still be VSS

read.
The Data Latch (LATx registers) is useful for 14.1 I/O Priorities
read-modify-write operations on the value that the I/O
pins are driving. Each pin defaults to the PORT data latch after Reset.
A write operation to the LATx register has the same Other functions are selected with the peripheral pin
effect as a write to the corresponding PORTx register. select logic. See Section 15.0 “Peripheral Pin Select
A read of the LATx register reads of the values held in (PPS) Module” for more information.
the I/O PORT latches, while a read of the PORTx Analog input functions, such as ADC and comparator
register reads the actual I/O pin value. inputs, are not shown in the peripheral pin select lists.
These inputs are active when the I/O pin is set for
Ports that support analog inputs have an associated
Analog mode using the ANSELx register. Digital output
ANSELx register. When an ANSEL bit is set, the digital
functions may continue to control the pin when it is in
input buffer associated with that bit is disabled.
Analog mode.
Analog outputs, when enabled, take priority over the
digital outputs and force the digital output driver to the
high-impedance state.

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14.2 PORTA Registers 14.2.3 OPEN-DRAIN CONTROL
The ODCONA register (Register 14-6) controls the
14.2.1 DATA REGISTER open-drain feature of the port. Open-drain operation is
PORTA is a 6-bit wide, bidirectional port. The independently selected for each pin. When an
corresponding data direction register is TRISA ODCONA bit is set, the corresponding port output
(Register 14-2). Setting a TRISA bit (= 1) will make the becomes an open-drain driver capable of sinking
corresponding PORTA pin an input (i.e., disable the current only. When an ODCONA bit is cleared, the
output driver). Clearing a TRISA bit (= 0) will make the corresponding port output pin is the standard push-pull
corresponding PORTA pin an output (i.e., enables drive capable of sourcing and sinking current.
output driver and puts the contents of the output latch
on the selected pin). Example 14.2.8 shows how to
initialize PORTA. Note: It is not necessary to set open-drain
control when using the pin for I2C; the I2C
Reading the PORTA register (Register 14-1) reads the
module controls the pin and makes the pin
status of the pins, whereas writing to it will write to the
open-drain.
PORT latch. All write operations are read-modify-write
operations. Therefore, a write to a port implies that the
port pins are read, this value is modified and then 14.2.4 SLEW RATE CONTROL
written to the PORT data latch (LATA). The SLRCONA register (Register 14-7) controls the
The PORT data latch LATA (Register 14-3) holds the slew rate option for each port pin. Slew rate control is
output port data, and contains the latest value of a independently selectable for each port pin. When an
LATA or PORTA write. SLRCONA bit is set, the corresponding port pin drive is
slew rate limited. When an SLRCONA bit is cleared,
EXAMPLE 14-1: INITIALIZING PORTA The corresponding port pin drive slews at the maximum
rate possible.
; This code example illustrates
; initializing the PORTA register. The
; other ports are initialized in the same 14.2.5 INPUT THRESHOLD CONTROL
; manner. The INLVLA register (Register 14-8) controls the input
voltage threshold for each of the available PORTA input
BANKSEL PORTA ; pins. A selection between the Schmitt Trigger CMOS or
CLRF PORTA ;Init PORTA
the TTL Compatible thresholds is available. The input
BANKSEL LATA ;Data Latch
CLRF LATA ;
threshold is important in determining the value of a read
BANKSEL ANSELA ; of the PORTA register and also the level at which an
CLRF ANSELA ;digital I/O interrupt-on-change occurs, if that feature is enabled.
BANKSEL TRISA ; See Table 37-4 for more information on threshold
MOVLW B'00111000' ;Set RA<5:3> as inputs levels.
MOVWF TRISA ;and set RA<2:0> as
;outputs Note: Changing the input threshold selection
should be performed while all peripheral
modules are disabled. Changing the
14.2.2 DIRECTION CONTROL threshold level during the time a module is
The TRISA register (Register 14-2) controls the active may inadvertently generate a
PORTA pin output drivers, even when they are being transition associated with an input pin,
used as analog inputs. The user should ensure the bits regardless of the actual voltage level on
in the TRISA register are maintained set when using that pin.
them as analog inputs. I/O pins configured as analog
inputs always read ‘0’.

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14.2.6 ANALOG CONTROL
The ANSELA register (Register 14-4) is used to
configure the Input mode of an I/O pin to analog.
Setting the appropriate ANSELA bit high will cause all
digital reads on the pin to be read as ‘0’ and allow
analog functions on the pin to operate correctly.
The state of the ANSELA bits has no effect on digital
output functions. A pin with its TRIS bit clear and its
ANSEL bit set will still operate as a digital output, but
the Input mode will be analog. This can cause
unexpected behavior when executing
read-modify-write instructions on the affected port.
Note: The ANSELA bits default to the Analog
mode after Reset. To use any pins as
digital general purpose or peripheral
inputs, the corresponding ANSEL bits
must be initialized to ‘0’ by user software.

14.2.7 WEAK PULL-UP CONTROL

The WPUA register (Register 14-5) controls the
individual weak pull-ups for each PORT pin.

14.2.8 PORTA FUNCTIONS AND OUTPUT

PRIORITIES
Each PORTA pin is multiplexed with other functions.
Each pin defaults to the PORT latch data after Reset.
Other output functions are selected with the peripheral
pin select logic or by enabling an analog output, such
as the DAC. See Section 15.0 “Peripheral Pin Select
(PPS) Module” for more information.
Analog input functions, such as ADC and comparator
inputs are not shown in the peripheral pin select lists.
Digital output functions may continue to control the pin
when it is in Analog mode.

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14.3 Register Definitions: PORTA

REGISTER 14-1: PORTA: PORTA REGISTER

U-0 U-0 R/W-x/u R/W-x/u R-x/u R/W-x/u R/W-x/u R/W-x/u
— — RA5 RA4 RA3 RA2 RA1 RA0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 Unimplemented: Read as ‘0’

bit 5-0 RA<5:0>: PORTA I/O Value bits(1)
1 = Port pin is > VIH
0 = Port pin is < VIL

Note 1: Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register returns
of actual I/O pin values.

REGISTER 14-2: TRISA: PORTA TRI-STATE REGISTER

U-0 U-0 R/W-1/1 R/W-1/1 U-0 R/W-1/1 R/W-1/1 R/W-1/1
— — TRISA5 TRISA4 — TRISA2 TRISA1 TRISA0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 Unimplemented: Read as ‘0’

bit 5-4 TRISA<5:4>: PORTA Tri-State Control bits
1 = PORTA pin configured as an input (tri-stated)
0 = PORTA pin configured as an output
bit 3 Unimplemented: Read as ‘0’
bit 2-0 TRISA<2:0>: PORTA Tri-State Control bits
1 = PORTA pin configured as an input (tri-stated)
0 = PORTA pin configured as an output

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REGISTER 14-3: LATA: PORTA DATA LATCH REGISTER

U-0 U-0 R/W-x/u R/W-x/u U-0 R/W-x/u R/W-x/u R/W-x/u
— — LATA5 LATA4 — LATA2 LATA1 LATA0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 Unimplemented: Read as ‘0’

bit 5-4 LATA<5:4>: RA<5:4> Output Latch Value bits(1)
bit 3 Unimplemented: Read as ‘0’
bit 2-0 LATA<2:0>: RA<2:0> Output Latch Value bits(1)

Note 1: Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register returns
actual I/O pin values.

REGISTER 14-4: ANSELA: PORTA ANALOG SELECT REGISTER

U-0 U-0 R/W-1/1 R/W-1/1 U-0 R/W-1/1 R/W-1/1 R/W-1/1
— — ANSA5 ANSA4 — ANSA2 ANSA1 ANSA0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 Unimplemented: Read as ‘0’

bit 5-4 ANSA<5:4>: Analog Select between Analog or Digital Function on pins RA<5:4>, respectively
1 =Analog input. Pin is assigned as analog input(1). Digital input buffer disabled.
0 = Digital I/O. Pin is assigned to port or digital special function.
bit 3 Unimplemented: Read as ‘0’
bit 2-0 ANSA<2:0>: Analog Select between Analog or Digital Function on pins RA<2:0>, respectively
1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled.
0 = Digital I/O. Pin is assigned to port or digital special function.

Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to
allow external control of the voltage on the pin.

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REGISTER 14-5: WPUA: WEAK PULL-UP PORTA REGISTER

U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— — WPUA5 WPUA4 WPUA3(1) WPUA2 WPUA1 WPUA0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 Unimplemented: Read as ‘0’

bit 5-0 WPUA<5:0>: Weak Pull-up Register bits(1)
1 = Pull-up enabled
0 = Pull-up disabled

Note 1: If MCLRE = 1, the weak pull-up in RA3 is always enabled; bit WPUA3 is not affected.
2: The weak pull-up device is automatically disabled if the pin is configured as an output.

REGISTER 14-6: ODCONA: PORTA OPEN-DRAIN CONTROL REGISTER

U-0 U-0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 R/W-0/0
— — ODCA5 ODCA4 — ODCA2 ODCA1 ODCA0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 Unimplemented: Read as ‘0’

bit 5-4 ODCA<5:4>: PORTA Open-Drain Enable bits
For RA<5:4> pins, respectively
1 = Port pin operates as open-drain drive (sink current only)
0 = Port pin operates as standard push-pull drive (source and sink current)
bit 3 Unimplemented: Read as ‘0’
bit 2-0 ODCA<2:0>: PORTA Open-Drain Enable bits
For RA<2:0> pins, respectively
1 = Port pin operates as open-drain drive (sink current only)
0 = Port pin operates as standard push-pull drive (source and sink current)

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REGISTER 14-7: SLRCONA: PORTA SLEW RATE CONTROL REGISTER

U-0 U-0 R/W-1/1 R/W-1/1 U-0 R/W-1/1 R/W-1/1 R/W-1/1
— — SLRA5 SLRA4 — SLRA2 SLRA1 SLRA0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 Unimplemented: Read as ‘0’

bit 5-4 SLRA<5:4>: PORTA Slew Rate Enable bits
For RA<5:4> pins, respectively
1 = Port pin slew rate is limited
0 = Port pin slews at maximum rate
bit 3 Unimplemented: Read as ‘0’
bit 2-0 SLRA<2:0>: PORTA Slew Rate Enable bits
For RA<2:0> pins, respectively
1 = Port pin slew rate is limited
0 = Port pin slews at maximum rate

REGISTER 14-8: INLVLA: PORTA INPUT LEVEL CONTROL REGISTER

U-0 U-0 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1
— — INLVLA5 INLVLA4 INLVLA3 INLVLA2 INLVLA1 INLVLA0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 Unimplemented: Read as ‘0’

bit 5-0 INLVLA<5:0>: PORTA Input Level Select bits
For RA<5:0> pins, respectively
1 = ST input used for PORT reads and interrupt-on-change
0 = TTL input used for PORT reads and interrupt-on-change

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TABLE 14-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA

Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
on Page
PORTA — — RA5 RA4 RA3 RA2 RA1 RA0 175
TRISA — — TRISA5 TRISA4 — TRISA2 TRISA1 TRISA0 175
LATA — — LATA5 LATA4 — LATA2 LATA1 LATA0 176
ANSELA — — ANSA5 ANSA4 — ANSA2 ANSA1 ANSA0 176
WPUA — — WPUA5 WPUA4 WPUA3 WPUA2 WPUA1 WPUA0 177
ODCONA — — ODCA5 ODCA4 — ODCA2 ODCA1 ODCA0 177
SLRCONA — — SLRA5 SLRA4 — SLRA2 SLRA1 SLRA0 178
INLVLA — — INLVLA5 INLVLA4 INLVLA3 INLVLA2 INLVLA1 INLVLA0 178
Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by
PORTA.

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14.4 PORTC Registers (PIC16(L)F15323 14.4.5 INPUT THRESHOLD CONTROL
only) The INLVLC register (Register 14-16) controls the input
voltage threshold for each of the available PORTC
14.4.1 DATA REGISTER input pins. A selection between the Schmitt Trigger
PORTC is a 6-bit wide bidirectional port. The CMOS or the TTL Compatible thresholds is available.
corresponding data direction register is TRISC The input threshold is important in determining the
(Register 14-10). Setting a TRISC bit (= 1) will make the value of a read of the PORTC register and also the
corresponding PORTC pin an input (i.e., put the level at which an interrupt-on-change occurs, if that
corresponding output driver in a High-Impedance mode). feature is enabled. See Table 37-4 for more information
Clearing a TRISC bit (= 0) will make the corresponding on threshold levels.
PORTC pin an output (i.e., enable the output driver and Note: Changing the input threshold selection
put the contents of the output latch on the selected pin). should be performed while all peripheral
Figure 14-1 shows how to initialize an I/O port. modules are disabled. Changing the
Reading the PORTC register (Register 14-9) reads the threshold level during the time a module is
status of the pins, whereas writing to it will write to the active may inadvertently generate a
PORT latch. All write operations are read-modify-write transition associated with an input pin,
operations. Therefore, a write to a port implies that the regardless of the actual voltage level on
port pins are read, this value is modified and then written that pin.
to the PORT data latch (LATC).
14.4.6 ANALOG CONTROL
The PORT data latch LATC (Register 14-11) holds the
output port data, and contains the latest value of a LATC The ANSELC register (Register 14-12) is used to
or PORTC write. configure the Input mode of an I/O pin to analog.
Setting the appropriate ANSELC bit high will cause all
14.4.2 DIRECTION CONTROL digital reads on the pin to be read as ‘0’ and allow
The TRISC register (Register 14-10) controls the analog functions on the pin to operate correctly.
PORTC pin output drivers, even when they are being The state of the ANSELC bits has no effect on digital
used as analog inputs. The user should ensure the bits in output functions. A pin with TRIS clear and ANSELC set
the TRISC register are maintained set when using them will still operate as a digital output, but the Input mode
as analog inputs. I/O pins configured as analog inputs will be analog. This can cause unexpected behavior
always read ‘0’. when executing read-modify-write instructions on the
affected port.
14.4.3 OPEN-DRAIN CONTROL
Note: The ANSELC bits default to the Analog
The ODCONC register (Register 14-14) controls the mode after Reset. To use any pins as
open-drain feature of the port. Open-drain operation is digital general purpose or peripheral
independently selected for each pin. When an inputs, the corresponding ANSEL bits
ODCONC bit is set, the corresponding port output must be initialized to ‘0’ by user software.
becomes an open-drain driver capable of sinking
current only. When an ODCONC bit is cleared, the 14.4.7 WEAK PULL-UP CONTROL
corresponding port output pin is the standard push-pull
The WPUC register (Register 14-13) controls the
drive capable of sourcing and sinking current.
individual weak pull-ups for each port pin.

14.4.8 PORTC FUNCTIONS AND OUTPUT

Note: It is not necessary to set open-drain
PRIORITIES
control when using the pin for I2C; the I2C
module controls the pin and makes the pin Each pin defaults to the PORT latch data after Reset.
open-drain. Other output functions are selected with the peripheral
pin select logic. See Section 15.0 “Peripheral Pin
14.4.4 SLEW RATE CONTROL Select (PPS) Module” for more information.
The SLRCONC register (Register 14-15) controls the Analog input functions, such as ADC and comparator
slew rate option for each port pin. Slew rate control is inputs, are not shown in the peripheral pin select lists.
independently selectable for each port pin. When an Digital output functions may continue to control the pin
SLRCONC bit is set, the corresponding port pin drive is when it is in Analog mode.
slew rate limited. When an SLRCONC bit is cleared,
The corresponding port pin drive slews at the maximum
rate possible.

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14.5 Register Definitions: PORTC

REGISTER 14-9: PORTC: PORTC REGISTER

U-0 U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
— — RC5 RC4 RC3 RC2 RC1 RC0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 Unimplemented: Read as ‘0’

bit 5-0 RC<5:0>: PORTC General Purpose I/O Pin bits(1)
1 = Port pin is > VIH
0 = Port pin is < VIL

Note 1: Writes to PORTC are actually written to corresponding LATC register. The actual I/O pin values are read from
the PORTC register.

REGISTER 14-10: TRISC: PORTC TRI-STATE REGISTER

U-0 U-0 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1
— — TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 Unimplemented: Read as ‘0’

bit 5-0 TRISC<5:0>: PORTC Tri-State Control bits
1 = PORTC pin configured as an input (tri-stated)
0 = PORTC pin configured as an output

REGISTER 14-11: LATC: PORTC DATA LATCH REGISTER

U-0 U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
— — LATC5 LATC4 LATC3 LATC2 LATC1 LATC0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 Unimplemented: Read as ‘0’

bit 5-0 LATC<5:0>: PORTC Output Latch Value bits((1)

Note 1: Writes to PORTC are actually written to corresponding LATC register. Reads from PORTC register returns
actual I/O pin values.

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REGISTER 14-12: ANSELC: PORTC ANALOG SELECT REGISTER

U-0 U-0 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1
— — ANSC5 ANSC4 ANSC3 ANSC2 ANSC1 ANSC0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 Unimplemented: Read as ‘0’

bit 5-0 ANSC<5:0>: Analog Select between Analog or Digital Function on Pins RC<5:0>, respectively(1)
1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled.
0 = Digital I/O. Pin is assigned to port or digital special function.

Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to
allow external control of the voltage on the pin.

REGISTER 14-13: WPUC: WEAK PULL-UP PORTC REGISTER

U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— — WPUC5 WPUC4 WPUC3 WPUC2 WPUC1 WPUC0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 Unimplemented: Read as ‘0’

bit 5-0 WPUC<5:0>: Weak Pull-up Register bits
1 = Pull-up enabled
0 = Pull-up disabled

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REGISTER 14-14: ODCONC: PORTC OPEN-DRAIN CONTROL REGISTER

U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— — ODCC5 ODCC4 ODCC3 ODCC2 ODCC1 ODCC0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 Unimplemented: Read as ‘0’

bit 5-0 ODCC<5:0>: PORTC Open-Drain Enable bits
For RC<5:0> pins, respectively
1 = Port pin operates as open-drain drive (sink current only)
0 = Port pin operates as standard push-pull drive (source and sink current)

REGISTER 14-15: SLRCONC: PORTC SLEW RATE CONTROL REGISTER

U-0 U-0 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1
— — SLRC5 SLRC4 SLRC3 SLRC2 SLRC1 SLRC0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 Unimplemented: Read as ‘0’

bit 5-0 SLRC<5:0>: PORTC Slew Rate Enable bits
For RC<5:0> pins, respectively
1 = Port pin slew rate is limited
0 = Port pin slews at maximum rate

REGISTER 14-16: INLVLC: PORTC INPUT LEVEL CONTROL REGISTER

U-0 U-0 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1
— — INLVLC5 INLVLC4 INLVLC3 INLVLC2 INLVLC1 INLVLC0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 Unimplemented: Read as ‘0’

bit 5-0 INLVLC<5:0>: PORTC Input Level Select bits
For RC<5:0> pins, respectively
1 = ST input used for PORT reads and interrupt-on-change
0 = TTL input used for PORT reads and interrupt-on-change

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TABLE 14-3: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC

Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
on Page
PORTC — — RC5 RC4 RC3 RC2 RC1 RC0 181
TRISC — — TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 181
LATC — — LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 181
ANSELC — — ANSC5 ANSC4 ANSC3 ANSC2 ANSC1 ANSC0 182
WPUC — — WPUC5 WPUC4 WPUC3 WPUC2 WPUC1 WPUC0 182
ODCONC — — ODCC5 ODCC4 ODCC3 ODCC2 ODCC1 ODCC0 183
SLRCONC — — SLRC5 SLRC4 SLRC3 SLRC2 SLRC1 SLRC0 183
INLVLC — — INLVLC5 INLVLC4 INLVLC3 INLVLC2 INLVLC1 INLVLC0 183
Legend: – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTC.

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15.0 PERIPHERAL PIN SELECT
(PPS) MODULE
The Peripheral Pin Select (PPS) module connects
peripheral inputs and outputs to the device I/O pins.
Only digital signals are included in the selections.
All analog inputs and outputs remain fixed to their
assigned pins. Input and output selections are
independent as shown in the simplified block diagram
Figure 15-1.

FIGURE 15-1: SIMPLIFIED PPS BLOCK DIAGRAM

PPS Outputs
RA0PPS
PPS Inputs

abcPPS RA0
RA0
Peripheral abc

RxyPPS

Rxy

Peripheral xyz
RC7(1) RC7PPS(1)

xyzPPS RC7(1)

Note: Not available on 14-Pin devices.

15.1 PPS Inputs 15.2 PPS Outputs

Each peripheral has a PPS register with which the Each I/O pin has a PPS register with which the pin
inputs to the peripheral are selected. Inputs include the output source is selected. With few exceptions, the port
device pins. TRIS control associated with that pin retains control
Although every peripheral has its own PPS input over the pin output driver. Peripherals that control the
selection register, the selections are identical for every pin output driver as part of the peripheral operation will
peripheral as shown in Register 15-1. override the TRIS control as needed. These
peripherals are (See Section 15.3 “Bidirectional
Note: The notation “xxx” in the register name is Pins”):
a place holder for the peripheral identifier.
• EUSART (synchronous operation)
For example, CLC1PPS.
• MSSP (I2C)
Although every pin has its own PPS peripheral
selection register, the selections are identical for every
pin as shown in Register 15-2.
Note: The notation “Rxy” is a place holder for the
pin port and bit identifiers. For example, x
and y for PORTA bit 0 would be A and 0,
respectively, resulting in the pin PPS
output selection register RA0PPS.

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TABLE 15-1: PPS INPUT SIGNAL ROUTING OPTIONS (PIC16(L)F15313)
Remappable to Pins of
INPUT SIGNAL Default Location Reset Value PORTx
Input Register Name
NAME at POR (xxxPPS<4:0>) PIC16(L)F15313
PORTA
INT INTPPS RA2 00010 
T0CKI T0CKIPPS RA2 00010 
T1CKI T1CKIPSS RA5 00101 
T1G T1GPPS RA4 00100 
T2IN T2INPPS RA5 00101 
CCP1 CCP1PPS RA5 00101 
CCP2 CCP2PPS RA5 00101 
CWG1IN CWG1INPPS RA2 00010 
CLCIN0 CLCIN0PPS RA3 00011 
CLCIN1 CLCIN1PPS RA5 00101 
CLCIN2 CLCIN2PPS RA1 00001 
CLCIN3 CLCIN3PPS RA0 00000 
ADACT ADACTPPS RA5 00101 
SCK1/SCL1 SSP1CLKPPS RA1 00001 
SDI1/SDA1 SSP1DATPPS RA2 00010 
SS1 SSP1SS1PPS RA3 00011 
RX1/DT1 RX1PPS RA1 00001 
CK1 TX1PPS RA0 00000 

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TABLE 15-2: PPS INPUT SIGNAL ROUTING OPTIONS (PIC16(L)F15323)
Default Remappable to Pins of PORTx
INPUT SIGNAL Input Register Reset Value
Location at PIC16(L)F15323
NAME Name (xxxPPS<4:0>)
POR
PORTA PORTC
INT INTPPS RA2 00010  
T0CKI T0CKIPPS RA2 00010  
T1CKI T1CKIPSS RA5 00101  
T1G T1GPPS RA4 00100  
T2IN T2INPPS RA5 00101  
CCP1 CCP1PPS RC5 10101  
CCP2 CCP2PPS RC3 10011  
CWG1IN CWG1INPPS RA2 00010  
CLCIN0 CLCIN0PPS RC3 10011  
CLCIN1 CLCIN1PPS RC4 10100  
CLCIN2 CLCIN2PPS RC1 10001  
CLCIN3 CLCIN3PPS RA5 00101  
ADACT ADACTPPS RC2 10010  
SCK1/SCL1 SSP1CLKPPS RC0 10000  
SDI1/SDA1 SSP1DATPPS RC1 10001  
SS1 SSP1SS1PPS RC3 10011  
RX1/DT1 RX1DTPPS RC5 10101  
CK1 TX1CKPPS RC4 10100  

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TABLE 15-3: PPS INPUT REGISTER

VALUES
Desired Input Pin Value to Write to Register
RA0 0x00
RA1 0x01
RA2 0x02
RA3 0x03
RA4 0x04
RA5 0x05
RC0(1) 0x10
(1)
RC1 0x11
RC2(1) 0x12
RC3(1) 0x13
RC4(1) 0x14
(1)
RC5 0x15
Note 1: Present on PIC16(L)F15323 only.

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15.3 Bidirectional Pins 15.5 PPS Permanent Lock
PPS selections for peripherals with bidirectional The PPS can be permanently locked by setting the
signals on a single pin must be made so that the PPS PPS1WAY Configuration bit. When this bit is set, the
input and PPS output select the same pin. Peripherals PPSLOCKED bit can only be cleared and set one time
that have bidirectional signals include: after a device Reset. This allows for clearing the
• EUSART (synchronous operation) PPSLOCKED bit so that the input and output selections
can be made during initialization. When the
• MSSP (I2C)
PPSLOCKED bit is set after all selections have been
made, it will remain set and cannot be cleared until after
the next device Reset event.
Note: The I2C SCLx and SDAx functions can be
remapped through PPS. However, only
the RB1, RB2, RC3 and RC4 pins have 15.6 Operation During Sleep
the I2C and SMBus specific input buffers PPS input and output selections are unaffected by Sleep.
implemented (I2C mode disables INLVL
and sets thresholds that are specific for
I2C). If the SCLx or SDAx functions are
15.7 Effects of a Reset
mapped to some other pin (other than A device Power-on-Reset (POR) clears all PPS input
RB1, RB2, RC3 or RC4), the general and output selections to their default values (Permanent
purpose TTL or ST input buffers (as Lock Removed). All other Resets leave the selections
configured based on INLVL register unchanged. Default input selections are shown in
setting) will be used instead. In most Table 15-1 and Table 15-2.
applications, it is therefore recommended
only to map the SCLx and SDAx pin
functions to the RB1, RB2, RC3 or RC4
pins.

15.4 PPS Lock

The PPS includes a mode in which all input and output
selections can be locked to prevent inadvertent
changes. PPS selections are locked by setting the
PPSLOCKED bit of the PPSLOCK register. Setting and
clearing this bit requires a special sequence as an extra
precaution against inadvertent changes. Examples of
setting and clearing the PPSLOCKED bit are shown in
Example 15-1.

EXAMPLE 15-1: PPS LOCK/UNLOCK

SEQUENCE
; suspend interrupts
BCF INTCON,GIE
; BANKSEL PPSLOCK ; set bank
; required sequence, next 5 instructions
MOVLW 0x55
MOVWF PPSLOCK
MOVLW 0xAA
MOVWF PPSLOCK
; Set PPSLOCKED bit to disable writes or
; Clear PPSLOCKED bit to enable writes
BSF PPSLOCK,PPSLOCKED
; restore interrupts
BSF INTCON,GIE

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TABLE 15-4: PPS OUTPUT SIGNAL TABLE 15-5: PPS OUTPUT SIGNAL
ROUTING OPTIONS ROUTING OPTIONS
(PIC16(L)F15313) (PIC16(L)F15323)
Remappable to Remappable to Pins of
Pins of PORTx RxyPPS PORTx
Output Signal RxyPPS Register Output
Register
Name Value PIC16(L)F15313 Signal Name PIC16(L)F15323
Value
PORTA PORTA PORTC
CLKR 0x1B  CLKR 0x1B  
NCO1OUT 0x1A  NCO1OUT 0x1A  
TMR0 0x19  TMR0 0x19  
SDO1/SDA1 0x16  SDO1/SDA1 0x16  
SCK1/SCL1 0x15  SCK1/SCL1 0x15  
C1OUT 0x13  C2OUT 0x14  
DT1 0x10  C1OUT 0x13  
TX1/CK1 0x0F  DT1 0x10  
PWM6OUT 0x0E  TX1/CK1 0x0F  
PWM5OUT 0x0D  PWM6OUT 0x0E  
PWM4OUT 0x0C  PWM5OUT 0x0D  
PWM3OUT 0x0B  PWM4OUT 0x0C  
CCP2 0x0A  PWM3OUT 0x0B  
CCP1 0x09  CCP2 0x0A  
CWG1D 0x08  CCP1 0x09  
CWG1C 0x07  CWG1D 0x08  
CWG1B 0x06  CWG1C 0x07  
CWG1A 0x05  CWG1B 0x06  
CLC4OUT 0x04  CWG1A 0x05  
CLC3OUT 0x03  CLC4OUT 0x04  
CLC2OUT 0x02  CLC3OUT 0x03  
CLC1OUT 0x01  CLC2OUT 0x02  
CLC1OUT 0x01  

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15.8 Register Definitions: PPS Input Selection
REGISTER 15-1: xxxPPS: PERIPHERAL xxx INPUT SELECTION(1)
U-0 U-0 R/W-q/u R/W-q/u R/W/q/u R/W-q/u R/W-q/u R/W-q/u
— — xxxPPS<5:0>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = value depends on peripheral

bit 7-6 Unimplemented: Read as ‘0’

bit 5-0 xxxPPS<5:0>: Peripheral xxx Input Selection bits
See Table 15-1 and Table 15-2.

Note 1: The “xxx” in the register name “xxxPPS” represents the input signal function name, such as “INT”,
“T0CKI”, “RX”, etc. This register summary shown here is only a prototype of the array of actual registers,
as each input function has its own dedicated SFR (ex: INTPPS, T0CKIPPS, RXPPS, etc.).
2: Each specific input signal may only be mapped to a subset of these I/O pins, as shown in Table 15-1 and
Table 15-2. Attempting to map an input signal to a non-supported I/O pin will result in undefined behavior.
For example, the “INT” signal map be mapped to any PORTA or PORTB pin. Therefore, the INTPPS
register may be written with values from 0x00-0x0F (corresponding to RA0-RB7). Attempting to write 0x10
or higher to the INTPPS register is not supported and will result in undefined behavior.

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REGISTER 15-2: RxyPPS: PIN Rxy OUTPUT SOURCE SELECTION REGISTER

U-0 U-0 U-0 R/W-0/u R/W-0/u R/W-0/u R/W-0/u R/W-0/u
— — — RxyPPS<4:0>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-5 Unimplemented: Read as ‘0’

bit 4-0 RxyPPS<4:0>: Pin Rxy Output Source Selection bits
See Table 15-4 and Table 15-5.

Note 1: TRIS control is overridden by the peripheral as required.

REGISTER 15-3: PPSLOCK: PPS LOCK REGISTER

U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0/0
— — — — — — — PPSLOCKED
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-1 Unimplemented: Read as ‘0’

bit 0 PPSLOCKED: PPS Locked bit
1= PPS is locked. PPS selections can not be changed.
0= PPS is not locked. PPS selections can be changed.

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TABLE 15-6: SUMMARY OF REGISTERS ASSOCIATED WITH THE PPS MODULE

Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
on page
PPSLOCK — — — — — — — PPSLOCKED 192
INTPPS — — INTPPS<5:0> 191
T0CKIPPS — — T0CKIPPS<5:0> 191
T1CKIPPS — — T1CKIPPS<5:0> 191
T1GPPS — — T1GPPS<5:0> 191
T2INPPS T2INPPS<5:0> 191
CCP1PPS — — CCP1PPS<5:0> 191
CCP2PPS — — CCP2PPS<5:0> 191
CWG1PPS — — CWG1PPS<5:0> 191
SSP1CLKPPS — — SSP1CLKPPS<5:0> 191
SSP1DATPPS — — SSP1DATPPS<5:0> 191
SSP1SSPPS — — SSP1SSPPS<5:0> 191
RX1DTPPS — — RX1DTPPS<5:0> 191
TX1CKPPS — — TX1CKPPS<5:0> 191
CLCIN0PPS — — CLCIN0PPS<5:0> 191
CLCIN1PPS — — CLCIN1PPS<5:0> 191
CLCIN2PPS — — CLCIN2PPS<5:0> 191
CLCIN3PPS — — CLCIN3PPS<5:0> 191
ADACTPPS — — ADACTPPS<5:0> 191
RA0PPS — — — RA0PPS<4:0> 192
RA1PPS — — — RA1PPS<4:0> 192
RA2PPS — — — RA2PPS<4:0> 192
RA3PPS — — — RA3PPS<4:0> 192
RA4PPS — — — RA4PPS<4:0> 192
RA5PPS — — — RA5PPS<4:0> 192
RC0PPS(1) — — — RC0PPS<4:0> 192
(1)
RC1PPS — — — RC1PPS<4:0> 192
RC2PPS(1) — — — RC2PPS<4:0> 192
(1)
RC3PPS — — — RC3PPS<4:0> 192
RC4PPS(1) — — — RC4PPS<4:0> 192
RC5PPS(1) — — — RC5PPS<4:0> 192
RC6PPS(1) — — — RC6PPS<4:0> 192
(1)
RC7PPS — — — RC7PPS<4:0> 192
Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the PPS module.
Note 1: Present on PIC16(L)F15323 only.

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16.0 PERIPHERAL MODULE 16.2 Enabling a module
DISABLE When the register bit is cleared, the module is re-
The PIC16(L)F15313/23 provides the ability to disable enabled and will be in its Reset state; SFR data will
selected modules, placing them into the lowest reflect the POR Reset values.
possible Power mode. Depending on the module, it may take up to one full
For legacy reasons, all modules are ON by default instruction cycle for the module to become active.
following any Reset. There should be no interaction with the module
(e.g., writing to registers) for at least one instruction
after it has been re-enabled.
16.1 Disabling a Module
Disabling a module has the following effects: 16.3 Disabling a Module
• All clock and control inputs to the module are When a module is disabled, all the associated PPS
suspended; there are no logic transitions, and the selection registers (Registers xxxPPS Register 15-1,
module will not function. 15-2, and 15-3), are also disabled.
• The module is held in Reset:
- Writing to SFRs is disabled 16.4 System Clock Disable
- Reads return 00h
Setting SYSCMD (PMD0, Register 16-1) disables the
system clock (FOSC) distribution network to the
peripherals. Not all peripherals make use of SYSCLK,
so not all peripherals are affected. Refer to the specific
peripheral description to see if it will be affected by this
bit.

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REGISTER 16-1: PMD0: PMD CONTROL REGISTER 0
R/W-0/0 R/W-0/0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0
SYSCMD FVRMD — — — NVMMD CLKRMD IOCMD
7 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition

bit 7 SYSCMD: Disable Peripheral System Clock Network bit

See description in Section 16.4 “System Clock Disable”.
1 = System clock network disabled (a.k.a. FOSC)
0 = System clock network enabled
bit 6 FVRMD: Disable Fixed Voltage Reference (FVR) bit
1 = FVR module disabled
0 = FVR module enabled
bit 5-3 Unimplemented: Read as ‘0’
bit 2 NVMMD: NVM Module Disable bit(1)
1 = User memory reading and writing is disabled; NVMCON registers cannot be written; FSR access
to these locations returns zero.
0 = NVM module enabled
bit 1 CLKRMD: Disable Clock Reference CLKR bit
1 = CLKR module disabled
0 = CLKR module enabled
bit 0 IOCMD: Disable Interrupt-on-Change bit, All Ports
1 = IOC module(s) disabled
0 = IOC module(s) enabled

Note 1: When enabling NVM, a delay of up to 1 µs may be required before accessing data.

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REGISTER 16-2: PMD1: PMD CONTROL REGISTER 1
R/W-0/0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0
NCO1MD — — — — TMR2MD TMR1MD TMR0MD
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition

bit 7 NCO1MD: Disable Numerically Control Oscillator bit

1 = NCO1 module disabled
0 = NCO1 module enabled
bit 6-3 Unimplemented: Read as ‘0’
bit 2 TMR2MD: Disable Timer TMR2 bit
1 = Timer2 module disabled
0 = Timer2 module enabled
bit 1 TMR1MD: Disable Timer TMR1 bit
1 = Timer1 module disabled
0 = Timer1 module enabled
bit 0 TMR0MD: Disable Timer TMR0 bit
1 = Timer0 module disabled
0 = Timer0 module enabled

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REGISTER 16-3: PMD2: PMD CONTROL REGISTER 2
U-0 R/W-0/0 R/W-0/0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0
— DAC1MD ADCMD — — CMP2MD CMP1MD ZCDMD
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition

bit 7 Unimplemented: Read as ‘0’

bit 6 DAC1MD: Disable DAC1 bit
1 = DAC module disabled
0 = DAC module enabled
bit 5 ADCMD: Disable ADC bit
1 = ADC module disabled
0 = ADC module enabled
bit 4-3 Unimplemented: Read as ‘0’
bit 2 CMP2MD: Disable Comparator C2 bit(1)
1 = C2 module disabled
0 = C2 module enabled
bit 1 CMP1MD: Disable Comparator C1 bit
1 = C1 module disabled
0 = C1 module enabled
bit 0 ZCDMD: Disable ZCD bit
1 = ZCD module disabled
0 = ZCD module enabled

Note 1: Present only on PIC16(L)F15323.

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REGISTER 16-4: PMD3: PMD CONTROL REGISTER 3
U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— — PWM6MD PWM5MD PWM4MD PWM3MD CCP2MD CCP1MD
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition

bit 7-6 Unimplemented: Read as ‘0’

bit 5 PWM6MD: Disable Pulse-Width Modulator PWM6 bit
1 = PWM6 module disabled
0 = PWM6 module enabled
bit 4 PWM5MD: Disable Pulse-Width Modulator PWM5 bit
1 = PWM5 module disabled
0 = PWM5 module enabled
bit 3 PWM4MD: Disable Pulse-Width Modulator PWM4 bit
1 = PWM4 module disabled
0 = PWM4 module enabled
bit 2 PWM3MD: Disable Pulse-Width Modulator PWM3 bit
1 = PWM3 module disabled
0 = PWM3 module enabled
bit 1 CCP2MD: Disable CCP2 bit
1 = CCP2 module disabled
0 = CCP2 module enabled
bit 0 CCP1MD: Disable CCP1 bit
1 = CCP1 module disabled
0 = CCP1 module enabled

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REGISTER 16-5: PMD4: PMD CONTROL REGISTER 4
U-0 R/W-0/0 U-0 R/W-0/0 U-0 U-0 U-0 R/W-0/0
— UART1MD — MSSP1MD — — — CWG1MD
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition

bit 7 Unimplemented: Read as ‘0’

bit 6 UART1MD: Disable EUSART1 bit
1 = EUSART1 module disabled
0 = EUSART1 module enabled
bit 5 Unimplemented: Read as ‘0’
bit 4 MSSP1MD: Disable MSSP1 bit
1 = MSSP1 module disabled
0 = MSSP1 module enabled
bit 3-1 Unimplemented: Read as ‘0’
bit 0 CWG1MD: Disable CWG1 bit
1 = CWG1 module disabled
0 = CWG1 module enabled

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REGISTER 16-6: PMD5 – PMD CONTROL REGISTER 5
U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0
— — — CLC4MD CLC3MD CLC2MD CLC1MD —
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition

bit 7-5 Unimplemented: Read as ‘0’

bit 4 CLC4MD: Disable CLC4 bit
1 = CLC4 module disabled
0 = CLC4 module enabled
bit 3 CLC3MD: Disable CLC3 bit
1 = CLC3 module disabled
0 = CLC3 module enabled
bit 2 CLC2MD: Disable CLC2 bit
1 = CLC2 module disabled
0 = CLC2 module enabled
bit 1 CLC1MD: Disable CLC bit
1 = CLC1 module disabled
0 = CLC1 module enabled
bit 0 Unimplemented: Read as ‘0’

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TABLE 16-1: SUMMARY OF REGISTERS ASSOCIATED WITH THE PPS MODULE

Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
on page
PMD0 SYSCMD FVRMD — — — NVMMD CLKRMD IOCMD 195
PMD1 NCO1MD — — — — TMR2MD TMR1MD TMR0MD 196
PMD2 — DAC1MD ADCMD — — CMP2MD CMP1MD ZCDMD 197
PMD3 — — PWM6MD PWM5MD PWM4MD PWM3MD CCP2MD CCP1MD 198
PMD4 — UART1MD — MSSP1MD — — — CWG1MD 199
PMD5 — — — CLC4MD CLC3MD CLC2MD CLC1MD — 200
Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the PPS module.

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17.0 INTERRUPT-ON-CHANGE 17.3 Interrupt Flags
An interrupt can be generated by detecting a signal that The bits located in the IOCxF registers are status flags
has either a rising edge or a falling edge. Any individual that correspond to the interrupt-on-change pins of each
pin, or combination of pins, can be configured to port. If an expected edge is detected on an appropriately
generate an interrupt. The interrupt-on-change module enabled pin, then the status flag for that pin will be set,
has the following features: and an interrupt will be generated if the IOCIE bit is set.
The IOCIF bit of the PIR0 register reflects the status of
• Interrupt-on-Change enable (Master Switch)
all IOCxF bits.
• Individual pin configuration
• Rising and falling edge detection 17.3.1 CLEARING INTERRUPT FLAGS
• Individual pin interrupt flags The individual status flags, (IOCxF register bits), can be
Figure 17-1 is a block diagram of the IOC module. cleared by resetting them to zero. If another edge is
detected during this clearing operation, the associated
17.1 Enabling the Module status flag will be set at the end of the sequence,
regardless of the value actually being written.
To allow individual pins to generate an interrupt, the
In order to ensure that no detected edge is lost while
IOCIE bit of the PIE0 register must be set. If the IOCIE
clearing flags, only AND operations masking out known
bit is disabled, the edge detection on the pin will still
changed bits should be performed. The following
occur, but an interrupt will not be generated.
sequence is an example of what should be performed.

17.2 Individual Pin Configuration EXAMPLE 17-1: CLEARING INTERRUPT

For each pin, a rising edge detector and a falling edge FLAGS
detector are present. To enable a pin to detect a rising (PORTA EXAMPLE)
edge, the associated bit of the IOCxP register is set. To MOVLW 0xff
enable a pin to detect a falling edge, the associated bit XORWF IOCAF, W
of the IOCxN register is set. ANDWF IOCAF, F
A pin can be configured to detect rising and falling
edges simultaneously by setting the associated bits in
both of the IOCxP and IOCxN registers. 17.4 Operation in Sleep
The interrupt-on-change interrupt event will wake the
device from Sleep mode, if the IOCIE bit is set.

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FIGURE 17-1: INTERRUPT-ON-CHANGE BLOCK DIAGRAM (PORTA EXAMPLE)
Rev. 10-000037D
10/3/2016

IOCANx D Q

R Q4Q1
edge
detect

RAx

to data bus
data bus = S
IOCAPx D Q D Q IOCAFx
0 or 1

R
write IOCAFx
IOCIE
Q2
IOC interrupt
to CPU core
from all other
IOCnFx individual
pin detectors

Note 1: See Table 8-1 for BOR Active Conditions.

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17.5 Register Definitions: Interrupt-on-Change Control

REGISTER 17-1: IOCAP: INTERRUPT-ON-CHANGE PORTA POSITIVE EDGE REGISTER

U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
(1)
— — IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0(1)
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 Unimplemented: read as ‘0’

bit 5-0 IOCAP<5:0>: Interrupt-on-Change PORTA Positive Edge Enable bits
1 = Interrupt-on-Change enabled on the pin for a positive-going edge. IOCAFx bit and IOCIF flag will
be set upon detecting an edge.
0 = Interrupt-on-Change disabled for the associated pin.

REGISTER 17-2: IOCAN: INTERRUPT-ON-CHANGE PORTA NEGATIVE EDGE REGISTER

U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— — IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1(1) IOCAN0(1)
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 Unimplemented: read as ‘0’

bit 5-0 IOCAN<5:0>: Interrupt-on-Change PORTA Negative Edge Enable bits
1 = Interrupt-on-Change enabled on the pin for a negative-going edge. IOCAFx bit and IOCIF flag will
be set upon detecting an edge.
0 = Interrupt-on-Change disabled for the associated pin.

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REGISTER 17-3: IOCAF: INTERRUPT-ON-CHANGE PORTA FLAG REGISTER

U-0 U-0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0
(1)
— — IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0(1)
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared HS - Bit is set in hardware

bit 7-6 Unimplemented: read as ‘0’

bit 5-0 IOCAF<5:0>: Interrupt-on-Change PORTA Flag bits
1 = An enabled change was detected on the associated pin.
Set when IOCAPx = 1 and a rising edge was detected on RAx, or when IOCANx = 1 and a falling
edge was detected on RAx.
0 = No change was detected, or the user cleared the detected change.

Note 1: If the debugger is enabled, these bits are not available for use.

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REGISTER 17-4: IOCCP: INTERRUPT-ON-CHANGE PORTC POSITIVE EDGE REGISTER(1)

U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— — IOCCP5 IOCCP4 IOCCP3 IOCCP2 IOCCP1 IOCCP0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 Unimplemented: read as ‘0’

bit 5-0 IOCCP<5:0>: Interrupt-on-Change PORTC Positive Edge Enable bits
1 = Interrupt-on-Change enabled on the pin for a positive-going edge. IOCCFx bit and IOCIF flag will
be set upon detecting an edge.
0 = Interrupt-on-Change disabled for the associated pin
Note 1: Present only in PIC16(L)F15323.

REGISTER 17-5: IOCCN: INTERRUPT-ON-CHANGE PORTC NEGATIVE EDGE REGISTER(1)

U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— — IOCCN5 IOCCN4 IOCCN3 IOCCN2 IOCCN1 IOCCN0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 Unimplemented: read as ‘0’

bit 5-0 IOCCN<5:0>: Interrupt-on-Change PORTC Negative Edge Enable bits
1 = Interrupt-on-Change enabled on the pin for a negative-going edge. IOCCFx bit and IOCIF flag will
be set upon detecting an edge.
0 = Interrupt-on-Change disabled for the associated pin
Note 1: Present only in PIC16(L)F15323.

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REGISTER 17-6: IOCCF: INTERRUPT-ON-CHANGE PORTC FLAG REGISTER(1)

U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— — IOCCF5 IOCCF4 IOCCF3 IOCCF2 IOCCF1 IOCCF0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared HS - Bit is set in hardware

bit 7-0 IOCCF<7:0>: Interrupt-on-Change PORTC Flag bits

1 = An enabled change was detected on the associated pin
Set when IOCCPx = 1 and a rising edge was detected on RCx, or when IOCCNx = 1 and a falling
edge was detected on RCx.
0 = No change was detected, or the user cleared the detected change

Note 1: Present only on PIC16(L)F15323.

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TABLE 17-1: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPT-ON-CHANGE
Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
on Page
INTCON GIE PEIE — — — — — INTEDG 121
PIE0 — — TMR0IE IOCIE — — — INTE 122
IOCAP — — IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0 204
IOCAN — — IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0 204
IOCAF — — IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0 205
(1)
IOCCP — — IOCCP5 IOCCP4 IOCCP3 IOCCP2 IOCCP1 IOCCP0 206
IOCCN(1) — — IOCCN5 IOCCN4 IOCCN3 IOCCN2 IOCCN1 IOCCN0 206
IOCCF(1) — — IOCCF5 IOCCF4 IOCCF3 IOCCF2 IOCCF1 IOCCF0 207
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by interrupt-on-change.
Note 1: Present only in PIC16(L)F15323.

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18.0 FIXED VOLTAGE REFERENCE 18.1 Independent Gain Amplifiers
(FVR) The output of the FVR, which is connected to the ADC,
The Fixed Voltage Reference, or FVR, is a stable comparators, and DAC, is routed through two
voltage reference, independent of VDD, with 1.024V, independent programmable gain amplifiers. Each
2.048V or 4.096V selectable output levels. The output amplifier can be programmed for a gain of 1x, 2x or 4x,
of the FVR can be configured to supply a reference to produce the three possible voltage levels.
voltage to the following: The ADFVR<1:0> bits of the FVRCON register are
• ADC input channel used to enable and configure the gain amplifier settings
for the reference supplied to the ADC module.
• ADC positive reference
Reference Section 20.0 “Analog-to-Digital
• Comparator positive and negative input Converter (ADC) Module” for additional information.
• Digital-to-Analog Converter (DAC)
The CDAFVR<1:0> bits of the FVRCON register are used
The FVR can be enabled by setting the FVREN bit of to enable and configure the gain amplifier settings for the
the FVRCON register. reference supplied to the DAC and comparator module.
Reference Section 21.0 “5-Bit Digital-to-Analog
Converter (DAC1) Module” and Section 23.0
Note: Fixed Voltage Reference output cannot “Comparator Module” for additional information.
exceed VDD.
18.2 FVR Stabilization Period
When the Fixed Voltage Reference module is enabled,
it requires time for the reference and amplifier circuits
to stabilize.
FVRRDY is an indicator of the reference being ready.
In the case of an LF device, or a device on which the
BOR is enabled in the Configuration Word settings,
then the FVRRDY bit will be high prior to setting
FVREN as those module require the reference voltage.

FIGURE 18-1: VOLTAGE REFERENCE BLOCK DIAGRAM

Rev. 10-000053D
9/15/2016

2
ADFVR<1:0>

1x
2x ADC FVR Buffer
4x

2
CDAFVR<1:0>

1x
Comparator and DAC
2x
4x FVR Buffer

FVREN

Voltage
FVRRDY (Note 1)
Reference

Note 1: FVRRDY is always ‘1’.

2: Any peripheral requiring the Fixed Reference (See Table 18-1).

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 PIC16(L)F15313/23
18.3 Register Definitions: FVR Control

REGISTER 18-1: FVRCON: FIXED VOLTAGE REFERENCE CONTROL REGISTER

R/W-0/0 R-q/q R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
FVREN FVRRDY(1) TSEN (3)
TSRNG (3)
CDAFVR<1:0> ADFVR<1:0>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition

bit 7 FVREN: Fixed Voltage Reference Enable bit

1 = Fixed Voltage Reference is enabled
0 = Fixed Voltage Reference is disabled
bit 6 FVRRDY: Fixed Voltage Reference Ready Flag bit(1)
1 = Fixed Voltage Reference output is ready for use
0 = Fixed Voltage Reference output is not ready or not enabled
bit 5 TSEN: Temperature Indicator Enable bit(3)
1 = Temperature Indicator is enabled
0 = Temperature Indicator is disabled
bit 4 TSRNG: Temperature Indicator Range Selection bit(3)
1 = Temperature in High Range VOUT = 3VT
0 = Temperature in Low Range VOUT = 2VT
bit 3-2 CDAFVR<1:0>: Comparator FVR Buffer Gain Selection bits
11 = Comparator FVR Buffer Gain is 4x, (4.096V)(2)
10 = Comparator FVR Buffer Gain is 2x, (2.048V)(2)
01 = Comparator FVR Buffer Gain is 1x, (1.024V)
00 = Comparator FVR Buffer is off
bit 1-0 ADFVR<1:0>: ADC FVR Buffer Gain Selection bit
11 = ADC FVR Buffer Gain is 4x, (4.096V)(2)
10 = ADC FVR Buffer Gain is 2x, (2.048V)(2)
01 = ADC FVR Buffer Gain is 1x, (1.024V)
00 = ADC FVR Buffer is off

Note 1: FVRRDY is always ‘1’.

2: Fixed Voltage Reference output cannot exceed VDD.
3: See Section 19.0 “Temperature Indicator Module” for additional information.

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 PIC16(L)F15313/23
TABLE 18-1: SUMMARY OF REGISTERS ASSOCIATED WITH FIXED VOLTAGE REFERENCE
Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
on page
FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR<1:0> ADFVR<1:0> 210
ADCON0 CHS<5:0> GO/DONE ADON 223
ADCON1 ADFM ADCS<2:0> — — ADPREF<1:0> 224
DAC1CON0 DAC1EN — DAC1OE1 DAC1OE2 DAC1PSS<1:0> — DAC1NSS 232
Legend: – = unimplemented locations read as ‘0’. Shaded cells are not used with the Fixed Voltage Reference.

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 PIC16(L)F15313/23
19.0 TEMPERATURE INDICATOR The output of the circuit is measured using the internal
Analog-to-Digital Converter. A channel is reserved for
MODULE
the temperature circuit output. Refer to Section 20.0
This family of devices is equipped with a temperature “Analog-to-Digital Converter (ADC) Module” for
circuit designed to measure the operating temperature detailed information.
of the silicon die. The main purpose of the temperature The ON/OFF bit for the module is located in the
indicator module is to provide a temperature-depen- FVRCON register. See Section 18.0 “Fixed Voltage
dent voltage that can be measured by the Analog-to- Reference (FVR)” for more information. The circuit is
Digital Converter. enabled by setting the TSEN bit of the FVRCON
The circuit’s range of operating temperature falls register. When the module is disabled, the circuit draws
between -40°C and +125°C. The circuit may be used no current.
as a temperature threshold detector or a more accurate The circuit operates in either High or Low range. Refer
temperature indicator, depending on the level of to Section 19.5 “Temperature Indicator Range” for
calibration performed. A one-point calibration allows more details on the range settings.
the circuit to indicate a temperature closely surrounding
that point. A two-point calibration allows the circuit to
19.2 Estimation of Temperature
sense the entire range of temperature more accurately.
This section describes how the sensor voltage can be
19.1 Module Operation used to estimate the temperature of the module. To use
the sensor, the output voltage, VTSENSE, is measured
The temperature indicator module consists of a and the corresponding temperature is determined.
temperature-sensing circuit that provides a voltage to Equation 19-1 provides an estimate for the die
the device ADC. The analog voltage output, VTSENSE, temperature based on the VTSENSE value.
varies inversely to the device temperature. The output
of the temperature indicator is referred to as VOUT.
EQUATION 19-1: SENSOR TEMPERATURE
Figure 19-1 shows a simplified block diagram of the
temperature indicator module. T SENSE = V TSENSE   Mt  + T OFFSET

FIGURE 19-1: TEMPERATURE

INDICATOR BLOCK Where:
DIAGRAM Mt = 1/Mv, where Mv = sensor voltage sensitivity (V/°C).
TOFFSET is the temperature difference between the
Rev. 10-000069B
10/18/2016
theoretical temperature and the actual temperature.

VREF

TSEN

VOUT
To ADC
Temp. Indicator

TSRNG

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 PIC16(L)F15313/23
19.2.1 CALIBRATION 19.2.2 TEMPERATURE RESOLUTION
The resolution of the ADC reading, Ma (°C/count),
19.2.1.1 Single-Point Calibration
depends on both the ADC resolution N and the
Single-point calibration is performed by application reference voltage used for conversion, as shown in
software using Equation 19-1 and the assumed Mt. A Equation 19-2. It is recommended to use the smallest
reading of VTSENSE at a known temperature is taken, VREF value, such as 2.048 FVR reference voltage,
and the theoretical temperature is calculated by instead of VDD.
temporarily setting TOFFSET = 0. Then TOFFSET is
computed as the difference of the actual and calculated
temperatures. Finally, TOFFSET is stored in nonvolatile Note: Refer to Section 37.0 “Electrical
memory within the device, and is applied to future Specifications” for FVR reference
readings to gain a more accurate measurement. voltage accuracy.

19.2.1.2 Higher-Order Calibration EQUATION 19-2: TEMPERATURE

If the application requires more precise temperature RESOLUTION (°C/LSb)
measurement, additional calibrations steps will be
necessary. For these applications, two-point or three- V REF
point calibration is recommended. N
-  Mt
Ma = -----------
2

V REF
Note 1: The TOFFSET value may be determined ------------
N
by the user with a temperature test. 2
Ma = ------------
2: Although the measurement range is Mv
-40°C to +125 °C due to the variations in
offset error, the single-point uncalibrated Where:
calculated TSENSE value may indicate a Mv = sensor voltage sensitivity (V/°C)
temperature from -140°C to +225°C VREF = Reference voltage of the ADC module (in Volts)
before the calibration offset is applied. N = Resolution of the ADC
3: The user must take into consideration
self-heating of the device at different
The typical Mv value for a single diode is
clock frequencies and output pin loading.
approximately -1.267 to -1.32 mV/C. The typical Mv
For package related thermal characteris-
value for a stack of two diodes (low range setting) is
tics information, refer to Section TABLE
approximately -2.533 mV/C. The typical Mv value for a
37-6: “Thermal Characteristics”.
stack of three diodes (high range setting) is approxi-
mately -3.8 mV/C.

19.3 ADC Acquisition Time

To ensure accurate temperature measurements, the
user must wait a minimum of 25 us for the ADC value
to settle, after the ADC input multiplexer is connected
to the temperature indicator output, before the
conversion is performed.

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 PIC16(L)F15313/23
19.4 Minimum Operating VDD 19.6 Device Information Area (DIA)
When the temperature circuit is operated in Low range,
Data
the device may be operated at any operating voltage During factory testing, internal ADC readings are taken
that is within specifications. When the temperature at a single temperature point within the operating range
circuit is operated in High range, the device operating of the device, and stored in the Data Information Area
voltage, VDD, must be high enough to ensure that the (DIA). Two readings are currently taken and stored in
temperature circuit is correctly biased. the DIA for each device. One with the low range setting
Table 19-1 shows the recommended minimum VDD vs. selected and one for the high range setting. Both
Range setting. readings are taken at the same temperature reference
point.
These single temperature point readings stored in the
TABLE 19-1: RECOMMENDED VDD vs.
DIA can be used to perform the single-point calibration
RANGE
as described in Section 19.2.1 “Calibration” by
Min.VDD, TSRNG = 1 Min. VDD, TSRNG = 0 solving Equation 19-1 for TOFFSET.
(High Range) (Low Range)
Note: Note that the lower temperature range
 2.5  1.8 (e.g., -40°C) will suffer in accuracy
because temperature conversion must
19.5 Temperature Indicator Range extrapolate below the reference points,
amplifying any measurement errors.
The temperature indicator circuit operates in either
High or Low range. The High range, selected by setting Refer to Section 6.3 “Analog-to-Digital Conversion
the TSRNG bit of the FVRCON register, provides a Data of the Temperature Sensor” for more
wider output voltage. This provides more resolution information on the temperature indicator data stored in
over the temperature range. High range requires a the DIA and how to access it.
higher-bias voltage to operate and thus, a higher VDD
is needed. The Low range is selected by clearing the
TSRNG bit of the FVRCON register. The Low range
generates a lower sensor voltage and thus, a lower
VDD voltage is needed to operate the circuit.
The output voltage of the sensor is the highest value at
-40°C and the lowest value at +125°C.
• High Range: The High range is used in
applications with the reference for the ADC,
VREF = 2.048V. This range may not be suitable for
battery-powered applications.
• Low Range: This mode is useful in applications in
which the VDD is too low for high-range operation.
The VDD in this mode can be as low as 1.8V. VDD
must, however, be at least 0.5V higher than the
maximum sensor voltage depending on the
expected low operating temperature.

TABLE 19-2: SUMMARY OF REGISTERS ASSOCIATED WITH THE TEMPERATURE INDICATOR

Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
on Page
FVRCON FVREN FVRRDY TSEN TSRNG CDFVR<1:0> ADFVR<1:0> 210
ADCON0 CHS<5:0> GO/DONE ADON 223
ADCON1 ADFM ADCS<2:0> — — ADPREF<1:0> 224
ADACT — — — ADACT<4:0> 225
ADRESH ADRESH<7:0> 226
ADRESL ADRESL<7:0> 226
Legend: Shaded cells are unused by the Temperature Indicator module.

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20.0 ANALOG-TO-DIGITAL The ADC voltage reference is software selectable to be
either internally generated or externally supplied.
CONVERTER (ADC) MODULE
The ADC can generate an interrupt upon completion of
The Analog-to-Digital Converter (ADC) allows a conversion. This interrupt can be used to wake-up the
conversion of an analog input signal to a 10-bit binary device from Sleep.
representation of that signal. This device uses analog
inputs, which are multiplexed into a single sample and
hold circuit. The output of the sample and hold is
connected to the input of the converter. The converter
generates a 10-bit binary result via successive
approximation and stores the conversion result into the
ADC result registers (ADRESH:ADRESL register pair).
Figure 20-1 shows the block diagram of the ADC.

FIGURE 20-1: ADC BLOCK DIAGRAM

VDD ADPREF Rev. 10-000033A

7/30/2013

Positive
VDD Reference
Select

VREF+ pin

VSS ADCS<2:0>
AN0
ANa VRNEG VRPOS
External .
Channel FOSC/n Fosc
. Divider FOSC
Inputs ADC
ADC_clk
. sampled Clock
ANz input Select FRC
FRC
Temp Indicator
Internal
Channel DACx_output ADC CLOCK SOURCE
Inputs
FVR_buffer1 ADC
Sample Circuit
CHS<4:0>
ADFM
set bit ADIF

10
complete 10-bit Result
Write to bit
GO/DONE
GO/DONE Q1 16
start
Q4
ADRESH ADRESL
Q2 Enable

Trigger Select
TRIGSEL<3:0> ADON
. . . VSS
Trigger Sources

AUTO CONVERSION
TRIGGER

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20.1 ADC Configuration 20.1.3 ADC VOLTAGE REFERENCE
When configuring and using the ADC the following The ADPREF<1:0> bits of the ADCON1 register
functions must be considered: provides control of the positive voltage reference. The
positive voltage reference can be:
• Port configuration
• VREF+ pin
• Channel selection
• VDD
• ADC voltage reference selection
• FVR 2.048V
• ADC conversion clock source
• FVR 4.096V (Not available on LF devices)
• Interrupt control
• Result formatting The ADPREF bit of the ADCON1 register provides
control of the negative voltage reference. The negative
20.1.1 PORT CONFIGURATION voltage reference can be:
The ADC can be used to convert both analog and • VREF- pin
digital signals. When converting analog signals, the I/O • VSS
pin will be configured for analog by setting the See Section 18.0 “Fixed Voltage Reference (FVR)”
associated TRIS and ANSEL bits. Refer to for more details on the Fixed Voltage Reference.
Section 14.0 “I/O Ports” for more information.
Note: Analog voltages on any pin that is defined 20.1.4 CONVERSION CLOCK
as a digital input may cause the input The source of the conversion clock is software
buffer to conduct excess current. selectable via the ADCS<2:0> bits of the ADCON1
register. There are seven possible clock options:
20.1.2 CHANNEL SELECTION • FOSC/2
There are several channel selections available: • FOSC/4
• Six Port A channels • FOSC/8
• Six Port C channels (PIC16(L)F15323 only) • FOSC/16
• Temperature Indicator • FOSC/32
• DAC output • FOSC/64
• Fixed Voltage Reference (FVR) • ADCRC (dedicated RC oscillator)
• AVSS (Ground) The time to complete one bit conversion is defined as
The CHS<5:0> bits of the ADCON0 register TAD. One full 10-bit conversion requires 11.5 TAD
(Register 20-1) determine which channel is connected periods as shown in Figure 20-2.
to the sample and hold circuit. For correct conversion, the appropriate TAD specification
When changing channels, a delay is required before must be met. Refer to Table 37-13 for more information.
starting the next conversion. Refer to Section 20.2 Table 20-1 gives examples of appropriate ADC clock
“ADC Operation” for more information. selections.
Note: Unless using the ADCRC, any changes in
the system clock frequency will change
Note: It is recommended that when switching
the ADC clock frequency, which may
from an ADC channel of a higher voltage
adversely affect the ADC result.
to a channel of a lower voltage, that the
user selects the VSS channel before con-
necting to the channel with the lower volt-
age. If the ADC does not have a dedicated
VSS input channel, the VSS selection
(DAC1R<4:0> = b’00000’) through the
DAC output channel can be used. If the
DAC is in use, a free input channel can be
connected to VSS, and can be used in
place of the DAC.

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TABLE 20-1: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES
ADC Clock Period (TAD) Device Frequency (FOSC)

ADC
ADCS<2:0> 32 MHz 20 MHz 16 MHz 8 MHz 4 MHz 1 MHz
Clock Source
FOSC/2 000 62.5ns(2) 100 ns(2) 125 ns(2) 250 ns(2) 500 ns(2) 2.0 s
FOSC/4 100 125 ns(2) 200 ns(2) 250 ns(2) 500 ns(2) 1.0 s 4.0 s
FOSC/8 001 0.5 s(2) 400 ns(2) 0.5 s(2) 1.0 s 2.0 s 8.0 s(3)
FOSC/16 101 800 ns 800 ns 1.0 s 2.0 s 4.0 s 16.0 s(3)
FOSC/32 010 1.0 s 1.6 s 2.0 s 4.0 s 8.0 s(3) 32.0 s(2)
FOSC/64 110 2.0 s 3.2 s 4.0 s 8.0 s(3) 16.0 s(2) 64.0 s(2)
ADCRC x11 1.0-6.0 s(1,4) 1.0-6.0 s(1,4) 1.0-6.0 s(1,4) 1.0-6.0 s(1,4) 1.0-6.0 s(1,4) 1.0-6.0 s(1,4)
Legend: Shaded cells are outside of recommended range.
Note 1: See TAD parameter for ADCRC source typical TAD value.
2: These values violate the required TAD time.
3: Outside the recommended TAD time.
4: The ADC clock period (TAD) and total ADC conversion time can be minimized when the ADC clock is derived
from the system clock FOSC. However, the ADCRC oscillator source must be used when conversions are to be
performed with the device in Sleep mode.

FIGURE 20-2: ANALOG-TO-DIGITAL CONVERSION TAD CYCLES

Rev. 10-000035A
7/30/2013

TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11

b9 b8 b7 b6 b5 b4 b3 b2 b1 b0

THCD
Conversion Starts
TACQ On the following cycle:
Holding capacitor disconnected
from analog input (THCD).
ADRESH:ADRESL is loaded,
GO bit is cleared,
Set GO bit ADIF bit is set,
holding capacitor is reconnected to analog input.
Enable ADC (ADON bit)
and
Select channel (ACS bits)

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 PIC16(L)F15313/23
20.1.5 INTERRUPTS 20.1.6 RESULT FORMATTING
The ADC module allows for the ability to generate an The 10-bit ADC conversion result can be supplied in
interrupt upon completion of an Analog-to-Digital two formats, left justified or right justified. The ADFM bit
conversion. The ADC Interrupt Flag is the ADIF bit in of the ADCON1 register controls the output format.
the PIR1 register. The ADC Interrupt Enable is the Figure 20-3 shows the two output formats.
ADIE bit in the PIE1 register. The ADIF bit must be
cleared in software.
Note 1: The ADIF bit is set at the completion of
every conversion, regardless of whether
or not the ADC interrupt is enabled.
2: The ADC operates during Sleep only
when the ADCRC oscillator is selected.
This interrupt can be generated while the device is
operating or while in Sleep. If the device is in Sleep, the
interrupt will wake-up the device. Upon waking from
Sleep, the next instruction following the SLEEP
instruction is always executed. If the user is attempting
to wake-up from Sleep and resume in-line code
execution, the ADIE bit of the PIE1 register and the
PEIE bit of the INTCON register must both be set and
the GIE bit of the INTCON register must be cleared. If
all three of these bits are set, the execution will switch
to the Interrupt Service Routine (ISR).

FIGURE 20-3: 10-BIT ADC CONVERSION RESULT FORMAT

Rev. 10-000 054A
12/21/201 6

ADRESH ADRESL

(ADFM = 0) MSb LSb

bit 7 bit 0 bit 7 bit 0

10-bit ADC Result Unimplemented: Read as ‘0’

(ADFM = 1) MSb LSb

bit 7 bit 0 bit 7 bit 0

Unimplemented: Read as ‘0’ 10-bit ADC Result

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20.2 ADC Operation 20.2.3 ADC OPERATION DURING SLEEP
The ADC module can operate during Sleep. This
20.2.1 STARTING A CONVERSION requires the ADC clock source to be set to the ADCRC
To enable the ADC module, the ADON bit of the option. When the ADCRC oscillator source is selected,
ADCON0 register must be set to a ‘1’. Setting the the ADC waits one additional instruction before starting
GO/DONE bit of the ADCON0 register to a ‘1’ will start the conversion. This allows the SLEEP instruction to be
the Analog-to-Digital conversion. executed, which can reduce system noise during the
conversion. If the ADC interrupt is enabled, the device
Note: The GO/DONE bit will not be set in the
will wake-up from Sleep when the conversion
same instruction that turns on the ADC.
completes. If the ADC interrupt is disabled, the ADC
Refer to Section 20.2.5 “ADC Conver-
module is turned off after the conversion completes,
sion Procedure”.
although the ADON bit remains set.
20.2.2 COMPLETION OF A CONVERSION When the ADC clock source is something other than
ADCRC, a SLEEP instruction causes the present
When the conversion is complete, the ADC module will: conversion to be aborted and the ADC module is
• Clear the GO/DONE bit turned off, although the ADON bit remains set.
• Set the ADIF Interrupt Flag bit
20.2.4 AUTO-CONVERSION TRIGGER
• Update the ADRESH and ADRESL registers with
new conversion result The Auto-conversion Trigger allows periodic ADC
measurements without software intervention. When a
rising edge of the selected source occurs, the
Note: A device Reset forces all registers to their GO/DONE bit is set by hardware.
Reset state. Thus, the ADC module is The Auto-conversion Trigger source is selected with
turned off and any pending conversion is the ADACT<4:0> bits of the ADACT register.
terminated.
Using the Auto-conversion Trigger does not assure
proper ADC timing. It is the user’s responsibility to
ensure that the ADC timing requirements are met.
See Table 20-2 for auto-conversion sources.

TABLE 20-2: ADC AUTO-CONVERSION

TABLE
ADACT SOURCE/
DESCRIPTION
VALUE PERIPHERAL

0x00 Disabled External Trigger Disabled

0x01 ADACTPPS Pin Selected by ADACTPPS
0x02 TMR0 Timer0 overflow condition
0x03 TMR1 Timer1 overflow condition
Match between Timer2 postscaled
0x04 TMR2
value and PR2
0x05 CCP1 CCP1 output
0x06 CCP2 CCP2 output
0x07 PWM3 PWM3 output
0x08 PWM4 PWM4 output
0x09 PWM5 PWM5 output
0x0A PWM6 PWM6 output
0x0B NCO1 NCO1 output
0x0C C1OUT Comparator C1 output
0x0D C2OUT Comparator C2 output
0x0E IOCIF Interrupt-on change flag trigger
0x0F CLC1 CLC1 output
0x10 CLC2 CLC2 output
0x11 CLC3 CLC3 output
0x12 CLC4 CLC4 output
0x13-0xFF Reserved Reserved, do not use

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20.2.5 ADC CONVERSION PROCEDURE EXAMPLE 20-1: ADC CONVERSION
This is an example procedure for using the ADC to ;This code block configures the ADC
perform an Analog-to-Digital conversion: ;for polling, Vdd and Vss references, ADCRC
;oscillator and AN0 input.
1. Configure Port: ;
;Conversion start & polling for completion ;
• Disable pin output driver (Refer to the TRIS are included.
register) ;
• Configure pin as analog (Refer to the ANSEL BANKSEL ADCON1 ;
MOVLW B’11110000’ ;Right justify, ADCRC
register) ;oscillator
2. Configure the ADC module: MOVWF ADCON1 ;Vdd and Vss Vref
BANKSEL TRISA ;
• Select ADC conversion clock BSF TRISA,0 ;Set RA0 to input
• Select voltage reference BANKSEL ANSELA ;
BSF ANSELA,0 ;Set RA0 to analog
• Select ADC input channel BANKSEL ADCON0 ;
MOVLW B’00000001’ ;Select channel AN0
• Turn on ADC module MOVWF ADCON0 ;Turn ADC On
3. Configure ADC interrupt (optional): CALL SampleTime ;Acquisiton delay
BSF ADCON0,ADGO ;Start conversion
• Clear ADC interrupt flag BTFSC ADCON0,ADGO ;Is conversion done?
• Enable ADC interrupt GOTO $-1 ;No, test again
BANKSEL ADRESH ;
• Enable peripheral interrupt MOVF ADRESH,W ;Read upper 2 bits
• Enable global interrupt(1) MOVWF RESULTHI ;store in GPR space
BANKSEL ADRESL ;
4. Wait the required acquisition time(2). MOVF ADRESL,W ;Read lower 8 bits
5. Start conversion by setting the GO/DONE bit. MOVWF RESULTLO ;Store in GPR space

6. Wait for ADC conversion to complete by one of

the following:
• Polling the GO/DONE bit
• Waiting for the ADC interrupt
7. Read ADC Result.
8. Clear the ADC interrupt flag (required if interrupt
is enabled).

Note 1: The global interrupt can be disabled if the

user is attempting to wake-up from Sleep
and resume in-line code execution.
2: Refer to Section 20.3 “ADC Acquisi-
tion Requirements”.

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 PIC16(L)F15313/23
20.3 ADC Acquisition Requirements source impedance is decreased, the acquisition time
may be decreased. After the analog input channel is
For the ADC to meet its specified accuracy, the charge selected (or changed), an ADC acquisition must be
holding capacitor (CHOLD) must be allowed to fully done before the conversion can be started. To calculate
charge to the input channel voltage level. The Analog the minimum acquisition time, Equation 20-1 may be
Input model is shown in Figure 20-4. The source used. This equation assumes that 1/2 LSb error is used
impedance (RS) and the internal sampling switch (RSS) (1024 steps for the ADC). The 1/2 LSb error is the
impedance directly affect the time required to charge maximum error allowed for the ADC to meet its
the capacitor CHOLD. The sampling switch (RSS) specified resolution.
impedance varies over the device voltage (VDD), refer
to Figure 20-4. The maximum recommended
impedance for analog sources is 10 k. As the

EQUATION 20-1: ACQUISITION TIME EXAMPLE

Assumptions: Temperature = 50°C and external impedance of 10k  5.0V V DD

T ACQ = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient
= T AMP + T C + T COFF
= 2µs + T C +   Temperature - 25°C   0.05µs/°C  

The value for TC can be approximated with the following equations:

V AP P LI ED  1 – -------------------------- = V CHOLD
1
;[1] VCHOLD charged to within 1/2 lsb
 n+1 
2 –1
–TC
 ----------
RC
V AP P LI ED  1 – e  = V CHOLD ;[2] VCHOLD charge response to VAPPLIED
 
– Tc
 ---------
V AP P LI ED  1 – e  = V A PP LIE D  1 – -------------------------- ;combining [1] and [2]
RC 1
  n+1 
2 –1

Note: Where n = number of bits of the ADC.

Solving for TC:

T C = – C HOLD  R IC + R SS + R S  ln(1/2047)
= – 10pF  1k  + 7k  + 10k   ln(0.0004885)
= 1.37 µs
Therefore:
T A CQ = 2µs + 1.37 +   50°C- 25°C   0.05µs/°C  
= 4.62µs

Note 1: The VAPPLIED has no effect on the equation, since it cancels itself out.
2: The charge holding capacitor (CHOLD) is not discharged after each conversion.
3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin
leakage specification.

 2017 Microchip Technology Inc. Preliminary DS40001897A-page 221

 PIC16(L)F15313/23
FIGURE 20-4: ANALOG INPUT MODEL

Rev. 10-000070A
8/23/2016

VDD
Sampling
Analog switch
VT § 0.6V SS
RS Input pin RIC ” 1K RSS

ILEAKAGE(1) CHOLD = 10 pF
VA CPIN VT § 0.6V
5pF
Ref-

6V
Legend: CHOLD = Sample/Hold Capacitance 5V
CPIN = Input Capacitance VDD 4V RSS
3V
ILEAKAGE = Leakage Current at the pin due to varies injunctions 2V
RIC = Interconnect Resistance
RSS = Resistance of Sampling switch
SS = Sampling Switch 5 6 7 8 9 10 11
VT = Threshold Voltage Sampling Switch
RS = Source Resistance (kŸ )

Note 1: See Refer to Section 37.0 “Electrical Specifications”.

FIGURE 20-5: ADC TRANSFER FUNCTION

Full-Scale Range

3FFh
3FEh
3FDh
3FCh
ADC Output Code

3FBh

03h
02h
01h
00h
Analog Input Voltage
0.5 LSB 1.5 LSB

Ref- Zero-Scale
Transition Full-Scale
Transition Ref+

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 PIC16(L)F15313/23
20.4 Register Definitions: ADC Control
REGISTER 20-1: ADCON0: ADC CONTROL REGISTER 0
R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
CHS<5:0> GO/DONE ADON
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-2 CHS<5:0>: Analog Channel Select bits

111111 = FVR Buffer 2 reference voltage(2)
111110 = FVR 1Buffer 1 reference voltage(2)
111101 = DAC1 output voltage(1)
111100 = Temperature sensor output(3)
111011 = AVSS (Analog Ground)
010111 = Reserved
010110 = Reserved
010101 = RC5(4)
010100 = RC4(4)
010011 = RC3(4)
010010 = RC2(4)
010001 = RC1(4)
010000 = RC0(4)
001111 = Reserved
•
•
•
000110 = Reserved
000101 = RA5(5)
000100 = RA4(5)
000011 = RA3
000010 = RA2
000001 = RA1
000000 = RA0
bit 1 GO/DONE: ADC Conversion Status bit
1 = ADC conversion cycle in progress. Setting this bit starts an ADC conversion cycle.
This bit is automatically cleared by hardware when the ADC conversion has completed.
0 = ADC conversion completed/not in progress
bit 0 ADON: ADC Enable bit
1 = ADC is enabled
0 = ADC is disabled and consumes no operating current

Note 1: See Section 21.0 “5-Bit Digital-to-Analog Converter (DAC1) Module” for more information.
2: See Section 18.0 “Fixed Voltage Reference (FVR)” for more information.
3: See Section 19.0 “Temperature Indicator Module” for more information.
4: Present only on the PIC16(L)F15323.
5: The analog functionality on the channels RA4 and RA5 is disabled when the system clock source is an external oscillator.

 2017 Microchip Technology Inc. Preliminary DS40001897A-page 223

 PIC16(L)F15313/23

REGISTER 20-2: ADCON1: ADC CONTROL REGISTER 1

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 R/W-0/0 R/W-0/0
ADFM ADCS<2:0> — — ADPREF<1:0>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 ADFM: ADC Result Format Select bit

1 = Right justified. Six Most Significant bits of ADRESH are set to ‘0’ when the conversion result is
loaded.
0 = Left justified. Six Least Significant bits of ADRESL are set to ‘0’ when the conversion result is
loaded.
bit 6-4 ADCS<2:0>: ADC Conversion Clock Select bits
111 = ADCRC (dedicated RC oscillator)
110 = FOSC/64
101 = FOSC/16
100 = FOSC/4
011 = ADCRC (dedicated RC oscillator)
010 = FOSC/32
001 = FOSC/8
000 = FOSC/2
bit 3-2 Unimplemented: Read as ‘0’
bit 1-0 ADPREF<1:0>: ADC Positive Voltage Reference Configuration bits
11 = VREF+ is connected to internal Fixed Voltage Reference (FVR) module(1)
10 = VREF+ is connected to external VREF+ pin(1)
01 = Reserved
00 = VREF+ is connected to VDD

Note 1: When selecting the VREF+ pin as the source of the positive reference, be aware that a minimum voltage
specification exists. See Table 37-14 for details.

 2017 Microchip Technology Inc. Preliminary DS40001897A-page 224

 PIC16(L)F15313/23

REGISTER 20-3: ADACT: A/D AUTO-CONVERSION TRIGGER

U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— — — ADACT<4:0>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-5 Unimplemented: Read as ‘0’

bit 4-0 ADACT<4:0>: Auto-Conversion Trigger Selection bits(1) (see Table 20-2)
Note 1: This is a rising edge sensitive input for all sources.

 2017 Microchip Technology Inc. Preliminary DS40001897A-page 225

 PIC16(L)F15313/23

REGISTER 20-4: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 0

R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
ADRES<9:2>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-0 ADRES<9:2>: ADC Result Register bits

Upper eight bits of 10-bit conversion result

REGISTER 20-5: ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 0

R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
ADRES<1:0> — — — — — —
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 ADRES<1:0>: ADC Result Register bits

Lower two bits of 10-bit conversion result
bit 5-0 Reserved: Do not use.

 2017 Microchip Technology Inc. Preliminary DS40001897A-page 226

 PIC16(L)F15313/23

REGISTER 20-6: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 1

R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
— — — — — — ADRES<9:8>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-2 Reserved: Do not use.

bit 1-0 ADRES<9:8>: ADC Result Register bits
Upper two bits of 10-bit conversion result

REGISTER 20-7: ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 1

R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
ADRES<7:0>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-0 ADRES<7:0>: ADC Result Register bits

Lower eight bits of 10-bit conversion result

 2017 Microchip Technology Inc. Preliminary DS40001897A-page 227

 PIC16(L)F15313/23

TABLE 20-3: SUMMARY OF REGISTERS ASSOCIATED WITH ADC

Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
on Page
INTCON GIE PEIE — — — — — INTEDG 121
PIE1 OSFIE CSWIE — — — — — ADIE 123
PIR1 OSFIF CSWIF — — — — — ADIF 131
TRISA — — TRISA5 TRISA4 — TRISA2 TRISA1 TRISA0 175
ANSELC(1) — — ANSC5 ANSC4 ANSC3 ANSC2 ANSC1 ANSC0 182

ADCON0 CHS<5:0> GO/DONE ADON 223

ADCON1 ADFM ADCS<2:0> — — ADPREF<1:0> 224
ADACT — — — ADACT<4:0> 225
ADRESH ADRESH<7:0> 226
ADRESL ADRESL<7:0> 226
FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR<1:0> ADFVR<1:0> 210
DAC1CON1 — — — DAC1R<4:0> 232
OSCSTAT1 EXTOR HFOR MFOR LFOR SOR ADOR — PLLR 112
Legend: — = unimplemented read as ‘0’. Shaded cells are not used for the ADC module.
Note 1: Present on PIC16(L)F15323PIC16(L)F15323 only.

 2017 Microchip Technology Inc. Preliminary DS40001897A-page 228

 PIC16(L)F15313/23
21.0 5-BIT DIGITAL-TO-ANALOG 21.1 Output Voltage Selection
CONVERTER (DAC1) MODULE The DAC has 32 voltage level ranges. The 32 levels
The Digital-to-Analog Converter supplies a variable are set with the DAC1R<4:0> bits of the DAC1CON1
voltage reference, ratiometric with the input source, register.
with 32 selectable output levels. The DAC output voltage is determined by Equation 21-1:
The input of the DAC can be connected to:
• External VREF pins
• VDD supply voltage
• FVR (Fixed Voltage Reference)
The output of the DAC can be configured to supply a
reference voltage to the following:
• Comparator positive input
• ADC input channel
• DAC1OUT pin
The Digital-to-Analog Converter (DAC) is enabled by
setting the DAC1EN bit of the DAC1CON0 register.

EQUATION 21-1: DAC OUTPUT VOLTAGE

 DAC1R  4:0 
V = V –V  ----------------------------------- +  V 
OUT  SOURCE+ SOURCE- 5  SOURCE-
2
V = V or V REF+ or FV R
SOURCE+ DD

V
SOURCE- = SS or V REF-
V

21.2 Ratiometric Output Level

The DAC output value is derived using a resistor ladder
with each end of the ladder tied to a positive and
negative voltage reference input source. If the voltage
of either input source fluctuates, a similar fluctuation will
result in the DAC output value.
The value of the individual resistors within the ladder
can be found in Table 37-15.

21.3 DAC Voltage Reference Output

The DAC voltage can be output to the DAC1OUT1/2
pins by setting the DAC1OE1/2 bits of the DAC1CON0
register, respectively. Selecting the DAC reference
voltage for output on the DAC1OUT1/2 pins
automatically overrides the digital output buffer and
digital input threshold detector functions, disables the
weak pull-up, and disables the current-controlled drive
function of that pin. Reading the DAC1OUT1/2 pin
when it has been configured for DAC reference voltage
output will always return a ‘0’.
Due to the limited current drive capability, a buffer must
be used on the DAC voltage reference output for
external connections to the DAC1OUT1/2 pins.
Figure 21-2 shows an example buffering technique.

 2017 Microchip Technology Inc. Preliminary DS40001897A-page 229

 PIC16(L)F15313/23
FIGURE 21-1: DIGITAL-TO-ANALOG CONVERTER BLOCK DIAGRAM
Rev. 10-000026G
12/15/2016

Reserved 11
VSOURCE+ DACR<4:0>
FVR Buffer 10 5
VREF+ 01 R

VDD 00

R
DACPSS

32-to-1 MUX
32 DACx_output
To Peripherals
Steps
DACEN
R

R DACxOUT1(1)

DACOE1
R
DACxOUT2(1)

VREF- 1 VSOURCE- DACOE2

VSS 0

DACNSS
Note 1: The unbuffered DACx_output is provided on the DACxOUT pin(s).

FIGURE 21-2: VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE

PIC® MCU

DAC
R
Module
+
Voltage DAC1OUT Buffered DAC Output
–
Reference
Output
Impedance

 2017 Microchip Technology Inc. Preliminary DS40001897A-page 230

 PIC16(L)F15313/23
21.4 Operation During Sleep
The DAC continues to function during Sleep. When the
device wakes up from Sleep through an interrupt or a
Watchdog Timer time-out, the contents of the
DAC1CON0 register are not affected.

21.5 Effects of a Reset

A device Reset affects the following:
• DAC is disabled.
• DAC output voltage is removed from the
DAC1OUT1/2 pins.
• The DAC1R<4:0> range select bits are cleared.

 2017 Microchip Technology Inc. Preliminary DS40001897A-page 231

 PIC16(L)F15313/23
21.6 Register Definitions: DAC Control

REGISTER 21-1: DAC1CON0: VOLTAGE REFERENCE CONTROL REGISTER 0

R/W-0/0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0
DAC1EN — DAC1OE1 DAC1OE2 DAC1PSS<1:0> — DAC1NSS
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 DAC1EN: DAC1 Enable bit

1 = DAC is enabled
0 = DAC is disabled
bit 6 Unimplemented: Read as ‘0’
bit 5 DAC1OE1: DAC1 Voltage Output 1 Enable bit
1 = DAC voltage level is an output on the DAC1OUT1 pin
0 = DAC voltage level is disconnected from the DAC1OUT1 pin
bit 4 DAC1OE2: DAC1 Voltage Output 1 Enable bit
1 = DAC voltage level is an output on the DAC1OUT2 pin
0 = DAC voltage level is disconnected from the DAC1OUT2 pin
bit 3-2 DAC1PSS<1:0>: DAC1 Positive Source Select bits
11 = Reserved, do not use
10 = FVR output
01 = VREF+ pin
00 = VDD
bit 1 Unimplemented: Read as ‘0’
bit 0 DAC1NSS: Read as ‘0’

REGISTER 21-2: DAC1CON1: VOLTAGE REFERENCE CONTROL REGISTER 1

U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— — — DAC1R<4:0>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-5 Unimplemented: Read as ‘0’

bit 4-0 DAC1R<4:0>: DAC1 Voltage Output Select bits
VOUT = (VSRC+ - VSRC-)*(DAC1R<4:0>/32) + VSRC

 2017 Microchip Technology Inc. Preliminary DS40001897A-page 232

 PIC16(L)F15313/23
TABLE 21-1: SUMMARY OF REGISTERS ASSOCIATED WITH THE DAC1 MODULE
Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
on page
DAC1CON0 DAC1EN — DAC1OE1 DAC1OE2 DAC1PSS<1:0> — DAC1NSS 232
DAC1CON1 — — — DAC1R<4:0> 232
CM1PSEL — — — — — PCH<2:0> 252
CM2PSEL(1) — — — — — PCH<2:0> 252
Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used with the DAC module.
Note 1: Present on PIC16(L)F15323 only.

 2017 Microchip Technology Inc. Preliminary DS40001897A-page 233

 PIC16(L)F15313/23
22.0 NUMERICALLY CONTROLLED
OSCILLATOR (NCO) MODULE
The Numerically Controlled Oscillator (NCO) module is
a timer that uses overflow from the addition of an
increment value to divide the input frequency. The
advantage of the addition method over simple counter
driven timer is that the output frequency resolution
does not vary with the divider value. The NCO is most
useful for application that requires frequency accuracy
and fine resolution at a fixed duty cycle.
Features of the NCO include:
• 20-bit Increment Function
• Fixed Duty Cycle mode (FDC) mode
• Pulse Frequency (PF) mode
• Output Pulse Width Control
• Multiple Clock Input Sources
• Output Polarity Control
• Interrupt Capability
Figure 22-1 is a simplified block diagram of the NCO
module.

 2017 Microchip Technology Inc. Preliminary DS40001897A-page 234

 FIGURE 22-1: NUMERICALLY CONTROLLED OSCILLATOR MODULE SIMPLIFIED BLOCK DIAGRAM
 2017 Microchip Technology Inc.

NCOxINCU NCOxINCH NCOxINCL Rev. 10-000028D

3/24/2017
20
(1)
INCBUFU INCBUFH INCBUFL
20
20
1111

NCO_overflow Adder
20
NCOx Clock
NCOx_clk
Sources NCOxACCU NCOxACCH NCOxACCL
20
See
NCOxCLK
Register NCO_interrupt set bit
Fixed Duty NCOxIF
0000
Cycle Mode
Preliminary

Circuitry

NxCKS<3:0> D Q D Q 0 TRIS bit

4

NCOxOUT
_ 1
Q

NxPFM NxPOL

PIC16(L)F15313/23
NCOx_out
To Peripherals

EN S Q

_ NxOUT
Ripple
R Q
Counter

Pulse
R Frequency
3
DS40001897A-page 235

Mode Circuitry
NxPWS<2:0>

Note 1: The increment registers are double-buffered to allow for value changes to be made without first disabling the NCO module. The full increment value is loaded into the buffer registers on the
second rising edge of the NCOx_clk signal that occurs immediately after a write to NCOxINCL register. The buffers are not user-accessible and are shown here for reference.
 PIC16(L)F15313/23
22.1 NCO OPERATION
The NCO operates by repeatedly adding a fixed value to
an accumulator. Additions occur at the input clock rate.
The accumulator will overflow with a carry periodically,
which is the raw NCO output (NCO_overflow). This
effectively reduces the input clock by the ratio of the
addition value to the maximum accumulator value. See
Equation 22-1.
The NCO output can be further modified by stretching
the pulse or toggling a flip-flop. The modified NCO
output is then distributed internally to other peripherals
and can be optionally output to a pin. The accumulator
overflow also generates an interrupt (NCO_overflow).
The NCO period changes in discrete steps to create an
average frequency.

EQUATION 22-1: NCO OVERFLOW FREQUENCY

NCO Clock Frequency  Increment Value

F OVERFLOW = ---------------------------------------------------------------------------------------------------------------
20
-
2

22.1.1 NCO CLOCK SOURCES 22.1.4 INCREMENT REGISTERS

Clock sources available to the NCO include: The increment value is stored in three registers making
• HFINTOSC up a 20-bit incrementer. In order of LSB to MSB they
• FOSC are:
• LC1_out • NCO1INCL
• LC2_out • NCO1INCH
• LC3_out • NCO1INCU
• LC4_out
• MFINTOSC (500 kHz) When the NCO module is enabled, the NCO1INCU and
• MFINTOSC (32 kHz) NCO1INCH registers should be written first, then the
• CLKR NCO1INCL register. Writing to the NCO1INCL register
initiates the increment buffer registers to be loaded
The NCO clock source is selected by configuring the simultaneously on the second rising edge of the
N1CKS<2:0> bits in the NCO1CLK register. NCO_clk signal.
22.1.2 ACCUMULATOR The registers are readable and writable. The increment
registers are double-buffered to allow value changes to
The accumulator is a 20-bit register. Read and write
be made without first disabling the NCO module.
access to the accumulator is available through three
registers: When the NCO module is disabled, the increment
buffers are loaded immediately after a write to the
• NCO1ACCL
increment registers.
• NCO1ACCH
• NCO1ACCU
Note: The increment buffer registers are not user-
22.1.3 ADDER accessible.
The NCO Adder is a full adder, which operates
synchronously from the source clock. The addition of
the previous result and the increment value replaces
the accumulator value on the rising edge of each input
clock.

 2017 Microchip Technology Inc. Preliminary DS40001897A-page 236

 PIC16(L)F15313/23
22.2 FIXED DUTY CYCLE MODE 22.5 Interrupts
In Fixed Duty Cycle (FDC) mode, every time the When the accumulator overflows (NCO_overflow), the
accumulator overflows (NCO_overflow), the output is NCO Interrupt Flag bit, NCO1IF, of the PIR7 register is
toggled at a frequency rate half of the FOVERFLOW. This set. To enable the interrupt event (NCO_interrupt), the
provides a 50% duty cycle, provided that the increment following bits must be set:
value remains constant. For more information, see • N1EN bit of the NCO1CON register
Figure 22-2. • NCO1IE bit of the PIE7 register
The FDC mode is selected by clearing the N1PFM bit • PEIE bit of the INTCON register
in the NCO1CON register. • GIE bit of the INTCON register
The interrupt must be cleared by software by clearing
22.3 PULSE FREQUENCY MODE the NCO1IF bit in the Interrupt Service Routine.
In Pulse Frequency (PF) mode, every time the
Accumulator overflows, the output becomes active for 22.6 Effects of a Reset
one or more clock periods. Once the clock period All of the NCO registers are cleared to zero as the
expires, the output returns to an inactive state. This result of a Reset.
provides a pulsed output. The output becomes active
on the rising clock edge immediately following the
overflow event. For more information, see Figure 22-2.
22.7 Operation in Sleep
The value of the active and inactive states depends on The NCO module operates independently from the
the polarity bit, N1POL in the NCO1CON register. system clock and will continue to run during Sleep,
provided that the clock source selected remains active.
The PF mode is selected by setting the N1PFM bit in
the NCO1CON register. The HFINTOSC remains active during Sleep when the
NCO module is enabled and the HFINTOSC is
22.3.1 OUTPUT PULSE WIDTH CONTROL selected as the clock source, regardless of the system
clock source selected.
When operating in PF mode, the active state of the out-
put can vary in width by multiple clock periods. Various In other words, if the HFINTOSC is simultaneously
pulse widths are selected with the N1PWS<2:0> bits in selected as the system clock and the NCO clock
the NCO1CLK register. source, when the NCO is enabled, the CPU will go idle
during Sleep, but the NCO will continue to operate and
When the selected pulse width is greater than the
the HFINTOSC will remain active.
Accumulator overflow time frame, then NCO1 output
does not toggle. This will have a direct effect on the Sleep mode current.

22.4 OUTPUT POLARITY CONTROL

The last stage in the NCO module is the output polarity.
The N1POL bit in the NCO1CON register selects the
output polarity. Changing the polarity while the
interrupts are enabled will cause an interrupt for the
resulting output transition.
The NCO output signal (NCO1_out) is available to the
following peripherals:
• CLC
• CWG
• Timer1
• Timer2
• CLKR

 2017 Microchip Technology Inc. Preliminary DS40001897A-page 237

 FIGURE 22-2: FDC OUTPUT MODE OPERATION DIAGRAM
 2017 Microchip Technology Inc.

Rev. 10-000029A
11/7/2013

NCOx
Clock
Source

NCOx
Increment 4000h 4000h 4000h
Value

NCOx
Accumulator 00000h 04000h 08000h FC000h 00000h 04000h 08000h FC000h 00000h 04000h 08000h
Value
Preliminary

NCO_overflow

NCO_interrupt

PIC16(L)F15313/23
NCOx Output
FDC Mode

NCOx Output
PF Mode
DS40001897A-page 238

NCOxPWS =
000

NCOx Output
PF Mode
NCOxPWS =
001
 PIC16(L)F15313/23
22.8 NCO Control Registers

REGISTER 22-1: NCO1CON: NCO CONTROL REGISTER

R/W-0/0 U-0 R-0/0 R/W-0/0 U-0 U-0 U-0 R/W-0/0
N1EN — N1OUT N1POL — — — N1PFM
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 N1EN: NCO1 Enable bit

1 = NCO1 module is enabled
0 = NCO1 module is disabled
bit 6 Unimplemented: Read as ‘0’
bit 5 N1OUT: NCO1 Output bit
Displays the current output value of the NCO1 module.
bit 4 N1POL: NCO1 Polarity bit
1 = NCO1 output signal is inverted
0 = NCO1 output signal is not inverted
bit 3-1 Unimplemented: Read as ‘0’
bit 0 N1PFM: NCO1 Pulse Frequency Mode bit
1 = NCO1 operates in Pulse Frequency mode
0 = NCO1 operates in Fixed Duty Cycle mode, divide by 2

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REGISTER 22-2: NCO1CLK: NCO1 INPUT CLOCK CONTROL REGISTER
R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
N1PWS<2:0>(1,2) — N1CKS<3:0>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-5 N1PWS<2:0>: NCO1 Output Pulse Width Select bits(1)

111 = NCO1 output is active for 128 input clock periods
110 = NCO1 output is active for 64 input clock periods
101 = NCO1 output is active for 32 input clock periods
100 = NCO1 output is active for 16 input clock periods
011 = NCO1 output is active for 8 input clock periods
010 = NCO1 output is active for 4 input clock periods
001 = NCO1 output is active for 2 input clock periods
000 = NCO1 output is active for 1 input clock period
bit 4 Unimplemented: Read as ‘0’
bit 3-0 N1CKS<3:0>: NCO1 Clock Source Select bits
1011-1111 = Reserved
1010 = LC4_out
1001 = LC3_out
1000 = LC2_out
0111 = LC1_out
0110 = CLKR
0101 = Reserved
0100 = MFINTOSC (32 kHz)
0011 = MFINTOSC (500 kHz)
0010 = LFINTOSC
0001 = HFINTOSC
0000 = FOSC

Note 1: N1PWS applies only when operating in Pulse Frequency mode.

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REGISTER 22-3: NCO1ACCL: NCO1 ACCUMULATOR REGISTER – LOW BYTE
R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
NCO1ACC<7:0>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-0 NCO1ACC<7:0>: NCO1 Accumulator, Low Byte

REGISTER 22-4: NCO1ACCH: NCO1 ACCUMULATOR REGISTER – HIGH BYTE

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
NCO1ACC<15:8>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-0 NOC1ACC<15:8>: NCO1 Accumulator, High Byte

REGISTER 22-5: NCO1ACCU: NCO1 ACCUMULATOR REGISTER – UPPER BYTE(1)

U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— — — — NCO1ACC<19:16>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-4 Unimplemented: Read as ‘0’

bit 3-0 NCO1ACC<19:16>: NCO1 Accumulator, Upper Byte

Note 1: The accumulator spans registers NCO1ACCU:NCO1ACCH: NCO1ACCL. The 24 bits are reserved but
not all are used.This register updates in real-time, asynchronously to the CPU; there is no provision to
guarantee atomic access to this 24-bit space using an 8-bit bus. Writing to this register while the module is
operating will produce undefined results.

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REGISTER 22-6: NCO1INCL: NCO1 INCREMENT REGISTER – LOW BYTE(1,2)
R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-1/1
NCO1INC<7:0>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-0 NCO1INC<7:0>: NCO1 Increment, Low Byte

Note 1: The logical increment spans NCO1INCU:NCO1INCH:NCO1INCL.

2: DDSINC is double-buffered as INCBUF; INCBUF is updated on the next falling edge of NCOCLK after
writing to NCO1INCL; NCO1INCU and NCO1INCH should be written prior to writing NCO1INCL.

REGISTER 22-7: NCO1INCH: NCO1 INCREMENT REGISTER – HIGH BYTE(1)

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
NCO1INC<15:8>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-0 NCO1INC<15:8>: NCO1 Increment, High Byte

Note 1: The logical increment spans NCO1INCU:NCO1INCH:NCO1INCL.

REGISTER 22-8: NCO1INCU: NCO1 INCREMENT REGISTER – UPPER BYTE(1)

U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— — — — NCO1INC<19:16>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-4 Unimplemented: Read as ‘0’

bit 3-0 NCO1INC<19:16>: NCO1 Increment, Upper Byte

Note 1: The logical increment spans NCO1INCU:NCO1INCH:NCO1INCL.

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TABLE 22-1: SUMMARY OF REGISTERS ASSOCIATED WITH NCO

Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
on Page

INTCON GIE PEIE ― ― ― ― ― INTEDG 121

PIR7 — — NVMIF NCO1IF — — — CWG1IF 137

PIE7 — — NVMIE NCO1IE — — — CWG1IE 129

NCO1CON N1EN ― N1OUT N1POL ― ― ― N1PFM 239
NCO1CLK N1PWS<2:0> ― N1CKS<3:0> 240
NCO1ACCL NCO1ACC<7:0> 241
NCO1ACCH NCO1ACC<15:8> 241
NCO1ACCU ― ― ― ― NCO1ACC<19:16> 241
NCO1INCL NCO1INC<7:0> 242
NCO1INCH NCO1INC<15:8> 242
NCO1INCU ― ― ― ― NCO1AINC<19:16> 242
RxyPPS ― ― ― RxyPPS<4:0> 192
Legend: — = unimplemented read as ‘0’. Shaded cells are not used for NCO module.

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 PIC16(L)F15313/23
23.0 COMPARATOR MODULE FIGURE 23-1: SINGLE COMPARATOR
Comparators are used to interface analog circuits to a
digital circuit by comparing two analog voltages and VIN+ +
providing a digital indication of their relative magnitudes. Output
VIN- –
Comparators are very useful mixed signal building
blocks because they provide analog functionality
independent of program execution. The analog
comparator module includes the following features:
• Programmable input selection VIN-
VIN+
• Selectable voltage reference
• Programmable output polarity
• Rising/falling output edge interrupts
• CWG1 Auto-shutdown source
Output
23.1 Comparator Overview
A single comparator is shown in Figure 23-1 along with
Note: The black areas of the output of the
the relationship between the analog input levels and
comparator represents the uncertainty
the digital output. When the analog voltage at VIN+ is
due to input offsets and response time.
less than the analog voltage at VIN-, the output of the
comparator is a digital low level. When the analog
voltage at VIN+ is greater than the analog voltage at
VIN-, the output of the comparator is a digital high level.
The comparators available are shown in Table 23-1.

TABLE 23-1: AVAILABLE COMPARATORS

Device C1 C2
PIC16(L)F15313 ●
PIC16(L)F15323 ● ●

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FIGURE 23-2: COMPARATOR MODULE SIMPLIFIED BLOCK DIAGRAM

Rev. 10-000027K
11/20/2015

3 (1)
CxNCH<2:0> CxON
Interrupt CxINTP
Rising
Edge set bit
CxIN0- 000 CxIF
Interrupt CxINTN
CxIN1- 001
Falling
CxIN2- 010 CxON(1) Edge

CxIN3- 011 CxVN

- D Q
CxOUT
Reserved 100
Cx MCxOUT
Reserved 101 CxVP
FVR_buffer2 110
+ Q1

111 CxSP CxHYS CxPOL

CxOUT_sync to
peripherals
CxSYNC
CxIN0+ 000
TRIS bit
CxIN1+ 001 0

Reserved 010 PPS CxOUT

D Q 1
Reserved 011
Reserved 100 RxyPPS
(From Timer1 Module) T1CLK
DAC_output 101
FVR_buffer2 110
111

CxPCH<2:0> CxON(1)
2

Note 1: When CxON = 0, all multiplexer inputs are disconnected and the Comparator will produce a ‘0’ at the output.

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23.2 Comparator Control 23.2.3 COMPARATOR OUTPUT POLARITY
Each comparator has two control registers: CMxCON0 Inverting the output of the comparator is functionally
and CMxCON1. equivalent to swapping the comparator inputs. The
polarity of the comparator output can be inverted by
The CMxCON0 register (see Register 23-1) contains setting the CxPOL bit of the CMxCON0 register.
Control and Status bits for the following: Clearing the CxPOL bit results in a non-inverted output.
• Enable Table 23-2 shows the output state versus input
• Output conditions, including polarity control.
• Output polarity
• Hysteresis enable
TABLE 23-2: COMPARATOR OUTPUT
• Timer1 output synchronization STATE VS. INPUT
The CMxCON1 register (see Register 23-2) contains CONDITIONS
Control bits for the following:
Input Condition CxPOL CxOUT
• Interrupt on positive/negative edge enables
CxVN > CxVP 0 0
• The CMxNSEL and CMxPSEL (Register 23-3 and
Register 23-4) contain control bits for the CxVN < CxVP 0 1
following: CxVN > CxVP 1 1
- Positive input channel selection CxVN < CxVP 1 0
- Negative input channel selection

23.2.1 COMPARATOR ENABLE

Setting the CxON bit of the CMxCON0 register enables
the comparator for operation. Clearing the CxON bit
disables the comparator resulting in minimum current
consumption.

23.2.2 COMPARATOR OUTPUT

The output of the comparator can be monitored by
reading either the CxOUT bit of the CMxCON0 register
or the MCxOUT bit of the CMOUT register.
The comparator output can also be routed to an
external pin through the RxyPPS register
(Register 15-2). The corresponding TRIS bit must be
clear to enable the pin as an output.
Note 1: The internal output of the comparator is
latched with each instruction cycle.
Unless otherwise specified, external out-
puts are not latched.

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23.3 Comparator Hysteresis The associated interrupt flag bit, CxIF bit of the PIR2
register, must be cleared in software. If another edge is
A selectable amount of separation voltage can be detected while this flag is being cleared, the flag will still
added to the input pins of each comparator to provide a be set at the end of the sequence.
hysteresis function to the overall operation. Hysteresis
is enabled by setting the CxHYS bit of the CMxCON0
register.
Note: Although a comparator is disabled, an
See Comparator Specifications in Table 37-14 for more interrupt can be generated by changing
information. the output polarity with the CxPOL bit of
the CMxCON0 register, or by switching
23.4 Timer1 Gate Operation the comparator on or off with the CxON bit
of the CMxCON0 register.
The output resulting from a comparator operation can
be used as a source for gate control of Timer1. See
Section 26.5 “Timer Gate” for more information. This 23.6 Comparator Positive Input
feature is useful for timing the duration or interval of an Selection
analog event.
Configuring the CxPCH<2:0> bits of the CMxPSEL
It is recommended that the comparator output be register directs an internal voltage reference or an
synchronized to Timer1. This ensures that Timer1 does analog pin to the noninverting input of the comparator:
not increment while a change in the comparator is
occurring. • CxIN0+ analog pin
• DAC output
23.4.1 COMPARATOR OUTPUT • FVR (Fixed Voltage Reference)
SYNCHRONIZATION • VSS (Ground)
The output from a comparator can be synchronized See Section 18.0 “Fixed Voltage Reference (FVR)”
with Timer1 by setting the CxSYNC bit of the for more information on the Fixed Voltage Reference
CMxCON0 register. module.
Once enabled, the comparator output is latched on the See Section 21.0 “5-Bit Digital-to-Analog Converter
falling edge of the Timer1 source clock. If a prescaler is (DAC1) Module” for more information on the DAC
used with Timer1, the comparator output is latched after input signal.
the prescaling function. To prevent a race condition, the
Any time the comparator is disabled (CxON = 0), all
comparator output is latched on the falling edge of the
comparator inputs are disabled.
Timer1 clock source and Timer1 increments on the
rising edge of its clock source. See the Comparator
Block Diagram (Figure 23-2) and the Timer1 Block 23.7 Comparator Negative Input
Diagram (Figure 26-1) for more information. Selection
The CxNCH<2:0> bits of the CMxCON1 register direct
23.5 Comparator Interrupt an analog input pin and internal reference voltage or
An interrupt can be generated upon a change in the analog ground to the inverting input of the comparator:
output value of the comparator for each comparator, a • CxIN- pin
rising edge detector and a falling edge detector are • FVR (Fixed Voltage Reference)
present.
• Analog Ground
When either edge detector is triggered and its associ-
ated enable bit is set (CxINTP and/or CxINTN bits of
the CMxCON1 register), the Corresponding Interrupt
Note: To use CxINy+ and CxINy- pins as analog
Flag bit (CxIF bit of the PIR2 register) will be set.
input, the appropriate bits must be set in
To enable the interrupt, you must set the following bits: the ANSEL register and the correspond-
• CxON, CxPOL and CxSP bits of the CMxCON0 ing TRIS bits must also be set to disable
register the output drivers.
• CxIE bit of the PIE2 register
• CxINTP bit of the CMxCON1 register (for a rising
edge detection)
• CxINTN bit of the CMxCON1 register (for a falling
edge detection)
• PEIE and GIE bits of the INTCON register

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23.8 Comparator Response Time 23.9 Analog Input Connection
The comparator output is indeterminate for a period of
Considerations
time after the change of an input source or the selection A simplified circuit for an analog input is shown in
of a new reference voltage. This period is referred to as Figure 23-3. Since the analog input pins share their
the response time. The response time of the comparator connection with a digital input, they have reverse
differs from the settling time of the voltage reference. biased ESD protection diodes to VDD and VSS. The
Therefore, both of these times must be considered when analog input, therefore, must be between VSS and VDD.
determining the total response time to a comparator If the input voltage deviates from this range by more
input change. See the Comparator and Voltage than 0.6V in either direction, one of the diodes is
Reference Specifications in Table 37-14 for more forward biased and a latch-up may occur.
details.
A maximum source impedance of 10 k is recommended
for the analog sources. Also, any external component
connected to an analog input pin, such as a capacitor or
a Zener diode, should have very little leakage current to
minimize inaccuracies introduced.

Note 1: When reading a PORT register, all pins

configured as analog inputs will read as a
‘0’. Pins configured as digital inputs will
convert as an analog input, according to
the input specification.
2: Analog levels on any pin defined as a
digital input, may cause the input buffer to
consume more current than is specified.

FIGURE 23-3: ANALOG INPUT MODEL

VDD
Analog
Input
pin VT  0.6V RIC
Rs < 10K
To Comparator

CPIN ILEAKAGE(1)
VA VT  0.6V
5 pF

Vss

Legend: CPIN = Input Capacitance

ILEAKAGE = Leakage Current at the pin due to various junctions
RIC = Interconnect Resistance
RS = Source Impedance
VA = Analog Voltage
VT = Threshold Voltage

Note 1: See I/O Ports in Table 37-4.

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23.10 CWG1 Auto-shutdown Source
The output of the comparator module can be used as
an auto-shutdown source for the CWG1 module. When
the output of the comparator is active and the
corresponding ASxE is enabled, the CWG operation
will be suspended immediately (see Section 30.10
“Auto-Shutdown”).

23.11 Operation in Sleep Mode

The comparator module can operate during Sleep. The
comparator clock source is based on the Timer1 clock
source. If the Timer1 clock source is either the system
clock (FOSC) or the instruction clock (FOSC/4), Timer1
will not operate during Sleep, and synchronized
comparator outputs will not operate.
A comparator interrupt will wake the device from Sleep.
The CxIE bits of the PIE2 register must be set to enable
comparator interrupts.

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23.12 Register Definitions: Comparator Control

REGISTER 23-1: CMxCON0: COMPARATOR Cx CONTROL REGISTER 0

R/W-0/0 R-0/0 U-0 R/W-0/0 U-0 U-0 R/W-0/0 R/W-0/0
ON OUT — POL — — HYS SYNC
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 ON: Comparator Enable bit

1 = Comparator is enabled
0 = Comparator is disabled and consumes no active power
bit 6 OUT: Comparator Output bit
If CxPOL = 1 (inverted polarity):
1 = CxVP < CxVN
0 = CxVP > CxVN
If CxPOL = 0 (noninverted polarity):
1 = CxVP > CxVN
0 = CxVP < CxVN
bit 5 Unimplemented: Read as ‘0’
bit 4 POL: Comparator Output Polarity Select bit
1 = Comparator output is inverted
0 = Comparator output is not inverted
bit 3-2 Unimplemented: Read as ‘0’
bit 1 HYS: Comparator Hysteresis Enable bit
1 = Comparator hysteresis enabled
0 = Comparator hysteresis disabled
bit 0 SYNC: Comparator Output Synchronous Mode bit
1 = Comparator output to Timer1 and I/O pin is synchronous to changes on Timer1 clock source.
Output updated on the falling edge of Timer1 clock source.
0 = Comparator output to Timer1 and I/O pin is asynchronous

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REGISTER 23-2: CMxCON1: COMPARATOR Cx CONTROL REGISTER 1

U-0 U-0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0
— — — — — — INTP INTN
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-2 Unimplemented: Read as ‘0’

bit 1 INTP: Comparator Interrupt on Positive-Going Edge Enable bits
1 = The CxIF interrupt flag will be set upon a positive-going edge of the CxOUT bit
0 = No interrupt flag will be set on a positive-going edge of the CxOUT bit
bit 0 INTN: Comparator Interrupt on Negative-Going Edge Enable bits
1 = The CxIF interrupt flag will be set upon a negative-going edge of the CxOUT bit
0 = No interrupt flag will be set on a negative-going edge of the CxOUT bit

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REGISTER 23-3: CMxNSEL: COMPARATOR Cx NEGATIVE INPUT SELECT REGISTER

U-0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0
— — — — — NCH<2:0>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-3 Unimplemented: Read as ‘0’

bit 2-0 NCH<2:0>: Comparator Negative Input Channel Select bits
111 = CxVN connects to AVSS
110 = CxVN connects to FVR Buffer 2
101 = CxVN unconnected
100 = CxVN unconnected
011 = CxVN connects to CxIN3- pin
010 = CxVN connects to CxIN2- pin
001 = CxVN connects to CxIN1- pin
000 = CxVN connects to CxIN0- pin

REGISTER 23-4: CMxPSEL: COMPARATOR Cx POSITIVE INPUT SELECT REGISTER

U-0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0
— — — — — PCH<2:0>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-3 Unimplemented: Read as ‘0’

bit 2-0 PCH<2:0>: Comparator Positive Input Channel Select bits
111 = CxVP connects to AVSS
110 = CxVP connects to FVR Buffer 2
101 = CxVP connects to DAC output
100 = CxVP unconnected
011 = CxVP unconnected
010 = CxVP unconnected
001 = CxVP connects to CxIN1+ pin
000 = CxVP connects to CxIN0+ pin

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REGISTER 23-5: CMOUT: COMPARATOR OUTPUT REGISTER

U-0 U-0 U-0 U-0 U-0 U-0 R-0/0 R-0/0
— — — — — — MC2OUT MC1OUT
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-2 Unimplemented: Read as ‘0’

bit 1 MC2OUT: Mirror Copy of C2OUT bit
bit 0 MC1OUT: Mirror Copy of C1OUT bit

TABLE 23-3: SUMMARY OF REGISTERS ASSOCIATED WITH COMPARATOR MODULE

Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
on Page

CMxCON0 ON OUT — POL — — HYS SYNC 250

CMxCON1 — — — — — — INTP INTN 251
CMOUT — — — — — — MC2OUT MC1OUT 253
FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR<1:0> ADFVR<1:0> 210
DAC1CON0 DAC1EN — DAC1OE1 DAC1OE2 DAC1PSS<1:0> — DAC1NSS 232
DAC1CON1 — — — DAC1R<4:0> 232
INTCON GIE PEIE — INTEDG 121
PIE2 — ZCDIE — — — — C2IE C1IE 124
PIR2 — ZCDIF — — — — C2IF C1IF 132
RxyPPS ― ― ― RxyPPS<4:0> 192
CLCINxPPS — — CLCIN0PPS<5:0> 191
T1GPPS ― ― T1GPPS<5:0> 191
Legend: — = unimplemented location, read as ‘0’. Shaded cells are unused by the comparator module.

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 PIC16(L)F15313/23
24.0 ZERO-CROSS DETECTION 24.1 External Resistor Selection
(ZCD) MODULE The ZCD module requires a current limiting resistor in
The ZCD module detects when an A/C signal crosses series with the external voltage source. The impedance
through the ground potential. The actual zero crossing and rating of this resistor depends on the external
threshold is the zero crossing reference voltage, source peak voltage. Select a resistor value that will drop
VCPINV, which is typically 0.75V above ground. all of the peak voltage when the current through the
resistor is nominally 300 A. Refer to Equation 24-1 and
The connection to the signal to be detected is through Figure 24-1. Make sure that the ZCD I/O pin internal
a series current limiting resistor. The module applies a weak pull-up is disabled so it does not interfere with the
current source or sink to the ZCD pin to maintain a current source and sink.
constant voltage on the pin, thereby preventing the pin
voltage from forward biasing the ESD protection
EQUATION 24-1: EXTERNAL RESISTOR
diodes. When the applied voltage is greater than the
reference voltage, the module sinks current. When the
V PEAK
applied voltage is less than the reference voltage, the R SERIES = ----------------
-
–4
module sources current. The current source and sink 3 10
action keeps the pin voltage constant over the full
range of the applied voltage. The ZCD module is
shown in the simplified block diagram Figure 24-2.
FIGURE 24-1: EXTERNAL VOLTAGE
The ZCD module is useful when monitoring an A/C
waveform for, but not limited to, the following purposes: VMAXPEAK
• A/C period measurement VPEAK VMINPEAK
• Accurate long term time measurement
• Dimmer phase delayed drive
VCPINV
• Low EMI cycle switching

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 PIC16(L)F15313/23
FIGURE 24-2: SIMPLIFIED ZCD BLOCK DIAGRAM

VPULLUP Rev. 10-000194D

6/10/2016

optional

VDD RPULLUP

- ZCDxIN RSERIES

External
Zcpinv + RPULLDOWN voltage
source

optional

ZCD Output for other modules

ZCDxPOL

ZCDxOUT pin

Interrupt
det
ZCDxINTP Set
ZCDxIF
ZCDxINTN flag
Interrupt
det

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24.2 ZCD Logic Output 24.5 Correcting for VCPINV offset
The ZCD module includes a Status bit, which can be The actual voltage at which the ZCD switches is the
read to determine whether the current source or sink is reference voltage at the noninverting input of the ZCD
active. The OUT bit of the ZCDxCON register is set op amp. For external voltage source waveforms other
when the current sink is active, and cleared when the than square waves, this voltage offset from zero
current source is active. The OUT bit is affected by the causes the zero-cross event to occur either too early or
polarity even if the module is disabled. too late.

24.3 ZCD Logic Polarity 24.5.1 CORRECTION BY AC COUPLING

When the external voltage source is sinusoidal then the
The POL bit of the ZCDxCON register inverts the
effects of the VCPINV offset can be eliminated by isolat-
ZCDxOUT bit relative to the current source and sink
ing the external voltage source from the ZCD pin with a
output. When the POL bit is set, a OUT high indicates
capacitor in addition to the voltage reducing resistor.
that the current source is active, and a low output
The capacitor will cause a phase shift resulting in the
indicates that the current sink is active.
ZCD output switch in advance of the actual zero cross-
The POL bit affects the ZCD interrupts. See Section ing event. The phase shift will be the same for both ris-
24.4 “ZCD Interrupts”. ing and falling zero crossings, which can be
compensated for by either delaying the CPU response
24.4 ZCD Interrupts to the ZCD switch by a timer or other means, or select-
ing a capacitor value large enough that the phase shift
An interrupt will be generated upon a change in the is negligible.
ZCD logic output when the appropriate interrupt
enables are set. A rising edge detector and a falling To determine the series resistor and capacitor values
edge detector are present in the ZCD for this purpose. for this configuration, start by computing the imped-
ance, Z, to obtain a peak current of 300 uA. Next, arbi-
The ZCDIF bit of the PIR2 register will be set when trarily select a suitably large non-polar capacitor and
either edge detector is triggered and its associated compute its reactance, Xc, at the external voltage
enable bit is set. The INTP enables rising edge inter- source frequency. Finally, compute the series resistor,
rupts and the INTN bit enables falling edge interrupts. capacitor peak voltage, and phase shift by the formulas
Both are located in the ZCDxCON register. shown in Equation 24-2.
To fully enable the interrupt, the following bits must be set:
• ZCDIE bit of the PIE2 register EQUATION 24-2: R-C CALCULATIONS
• INTP bit of the ZCDxCON register VPEAK = external voltage source peak voltage
(for a rising edge detection) f = external voltage source frequency
• INTN bit of the ZCDxCON register
C = series capacitor
(for a falling edge detection)
• PEIE and GIE bits of the INTCON register R = series resistor

Changing the POL bit can cause an interrupt, VC = Peak capacitor voltage
regardless of the level of the EN bit.  = Capacitor induced zero crossing phase advance
The ZCDIF bit of the PIR2 register must be cleared in in radians
software as part of the interrupt service. If another edge T = Time ZC event occurs before actual zero
is detected while this flag is being cleared, the flag will crossing
still be set at the end of the sequence.
Z = VPEAK/3x10-4
Xc = 1/(2fC)
R =  (Z2 - Xc2)
VC = Xc(3x10-4)
 = Tan-1(Xc/R)
T = /(2f)

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EXAMPLE 24-1: This offset time can be compensated for by adding a
pull-up or pull-down biasing resistor to the ZCD pin. A
VRMS = 120 pull-up resistor is used when the external voltage
VPEAK =VRMS*  source is varying relative to VSS. A pull-down resistor is
f = 60 Hz used when the voltage is varying relative to VDD. The
resistor adds a bias to the ZCD pin so that the target
C = 0.1 uF external voltage source must go to zero to pull the pin
Z = VPEAK/3x10-4 = 169.7/(3x10-4) = 565.7 kOhms voltage to the VCPINV switching voltage. The pull-up or
pull-down value can be determined with the equation
Xc = 1/(2fC) = 1/(2*60*1*10-7) = 26.53 kOhms
shown in Equation 24-4.
R =  (Z2 - Xc2) = 565.1 kOhms (computed)
R = 560 kOhms (used) EQUATION 24-4: ZCD PULL-UP/DOWN
ZR =  (R2 + Xc2) = 560.6 kOhms (using actual resis-
tor)
IPEAK = VPEAK/ ZR = 302.7*10-6 When External Signal is relative to Vss:
VC = Xc* IPEAK = 8.0 V
 = Tan-1(Xc/R) = 0.047 radians
R SERIES  V PULLUP – V cpinv 
R PULLUP = ------------------------------------------------------------------------
T = /(2f) = 125.6 us
V cpinv
When External Signal is relative to VDD:
·
24.5.2 CORRECTION BY OFFSET  R PULLDOWN = R SERIES   Vcpinv 
--------------------------------------------------
CURRENT   V DD – Vcpinv  
When the waveform is varying relative to VSS, then the
zero cross is detected too early as the waveform falls
and too late as the waveform rises. When the
waveform is varying relative to VDD, then the zero cross 24.6 Handling VPEAK variations
is detected too late as the waveform rises and too early
as the waveform falls. The actual offset time can be If the peak amplitude of the external voltage is
determined for sinusoidal waveforms with the expected to vary, the series resistor must be selected
corresponding equations shown in Equation 24-3. to keep the ZCD current source and sink below the
design maximum range of ± 600 A and above a
EQUATION 24-3: ZCD EVENT OFFSET reasonable minimum range. A general rule of thumb is
that the maximum peak voltage can be no more than
When External Voltage Source is relative to Vss: six times the minimum peak voltage. To ensure that the
maximum current does not exceed ± 600 A and the
minimum is at least ± 100 A, compute the series
asin  ------------------
Vcpinv
 V PEAK  resistance as shown in Equation 24-5. The
T OFFSET = ---------------------------------- compensating pull-up for this series resistance can be
2  Freq determined with Equation 24-4 because the pull-up
value is not dependent from the peak voltage.
When External Voltage Source is relative to VDD:
EQUATION 24-5: SERIES R FOR V RANGE

asin  --------------------------------
V DD – Vcpinv
V PEAK V MAXPEAK + V MINPEAK
R SERIES = ---------------------------------------------------------
T OFFSET = ------------------------------------------------- 7 10
–4
2  Freq

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24.7 Operation During Sleep
The ZCD current sources and interrupts are unaffected
by Sleep.

24.8 Effects of a Reset

The ZCD circuit can be configured to default to the active
or inactive state on Power-on-Reset (POR). When the
ZCDDIS Configuration bit is cleared, the ZCD circuit will
be active at POR. When the ZCD Configuration bit is set,
the EN bit of the ZCDxCON register must be set to
enable the ZCD module.

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24.9 Register Definitions: ZCD Control

REGISTER 24-1: ZCDCON: ZERO-CROSS DETECTION CONTROL REGISTER

R/W-q/q U-0 R-x/x R/W-0/0 U-0 U-0 R/W-0/0 R/W-0/0
SEN — OUT POL — — INTP INTN
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = value depends on Configuration bits

bit 7 SEN: Zero-Cross Detection Enable bit

1 = Zero-cross detect is enabled. ZCD pin is forced to output to source and sink current.
0 = Zero-cross detect is disabled. ZCD pin operates according to PPS and TRIS controls.
bit 6 Unimplemented: Read as ‘0’
bit 5 OUT: Zero-Cross Detection Logic Level bit
POL bit = 1:
1 = ZCD pin is sourcing current
0 = ZCD pin is sinking current
POL bit = 0:
1 = ZCD pin is sinking current
0 = ZCD pin is sourcing current
bit 4 POL: Zero-Cross Detection Logic Output Polarity bit
1 = ZCD logic output is inverted
0 = ZCD logic output is not inverted
bit 3-2 Unimplemented: Read as ‘0’
bit 1 INTP: Zero-Cross Positive Edge Interrupt Enable bit
1 = ZCDIF bit is set on low-to-high ZCDx_output transition
0 = ZCDIF bit is unaffected by low-to-high ZCDx_output transition
bit 0 INTN: Zero-Cross Negative Edge Interrupt Enable bit
1 = ZCDIF bit is set on high-to-low ZCDx_output transition
0 = ZCDIF bit is unaffected by high-to-low ZCDx_output transition

TABLE 24-1: SUMMARY OF REGISTERS ASSOCIATED WITH THE ZCD MODULE

Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
on page

PIE3 — — RC1IE TX1IE — — BCL1IE SSP1IE 125

PIR3 — — RC1IF TX1IF — — BCL1IF SSP1IF 133
ZCDxCON EN — OUT POL — — INTP INTN 259
Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the ZCD module.

TABLE 24-2: SUMMARY OF CONFIGURATION WORD WITH THE ZCD MODULE

Register
Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0
on Page

13:8 — — DEBUG STVREN PPS1WAY ZCDDIS BORV —

CONFIG2 77
7:0 BOREN <1:0> LPBOREN — — — PWRTE MCLRE
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by the ZCD module.

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25.0 TIMER0 MODULE The value of TMR0L is compared to that of the Period
buffer, a copy of TMR0H, on each clock cycle. When
The Timer0 module is an 8/16-bit timer/counter with the the two values match, the following events happen:
following features:
• TMR0_out goes high for one prescaled clock
• 16-bit timer/counter period
• 8-bit timer/counter with programmable period • TMR0L is reset
• Synchronous or asynchronous operation • The contents of TMR0H are copied to the period
• Selectable clock sources buffer
• Programmable prescaler (independent of
In 8-bit mode, the TMR0L and TMR0H registers are
Watchdog Timer)
both directly readable and writable. The TMR0L
• Programmable postscaler
register is cleared on any device Reset, while the
• Operation during Sleep mode
TMR0H register initializes at FFh.
• Interrupt on match or overflow
• Output on I/O pin (via PPS) or to other peripherals Both the prescaler and postscaler counters are cleared
on the following events:
25.1 Timer0 Operation • A write to the TMR0L register
• A write to either the T0CON0 or T0CON1
Timer0 can operate as either an 8-bit timer/counter or registers
a 16-bit timer/counter. The mode is selected with the • Any device Reset – Power-on Reset (POR),
T016BIT bit of the T0CON register. MCLR Reset, Watchdog Timer Reset (WDTR) or
• Brown-out Reset (BOR)
25.1.1 16-BIT MODE
In normal operation, TMR0 increments on the rising 25.1.3 COUNTER MODE
edge of the clock source. A 15-bit prescaler on the In Counter mode, the prescaler is normally disabled by
clock input gives several prescale options (see setting the T0CKPS bits of the T0CON1 register to
prescaler control bits, T0CKPS<3:0> in the T0CON1 ‘0000’. Each rising edge of the clock input (or the
register). output of the prescaler if the prescaler is used)
increments the counter by ‘1’.
25.1.1.1 Timer0 Reads and Writes in 16-Bit
Mode 25.1.4 TIMER MODE
TMR0H is not the actual high byte of Timer0 in 16-bit In Timer mode, the Timer0 module will increment every
mode. It is actually a buffered version of the real high instruction cycle as long as there is a valid clock signal
byte of Timer0, which is neither directly readable nor and the T0CKPS bits of the T0CON1 register
writable (see Figure 25-1). TMR0H is updated with the (Register 25-2) are set to ‘0000’. When a prescaler is
contents of the high byte of Timer0 during a read of added, the timer will increment at the rate based on the
TMR0L. This provides the ability to read all 16 bits of prescaler value.
Timer0 without having to verify that the read of the high
and low byte was valid, due to a rollover between 25.1.5 ASYNCHRONOUS MODE
successive reads of the high and low byte. When the T0ASYNC bit of the T0CON1 register is set
Similarly, a write to the high byte of Timer0 must also (T0ASYNC = ‘1’), the counter increments with each
take place through the TMR0H Buffer register. The high rising edge of the input source (or output of the
byte is updated with the contents of TMR0H when a prescaler, if used). Asynchronous mode allows the
write occurs to TMR0L. This allows all 16 bits of Timer0 counter to continue operation during Sleep mode
to be updated at once. provided that the clock also continues to operate during
Sleep.
25.1.2 8-BIT MODE
In normal operation, TMR0 increments on the rising 25.1.6 SYNCHRONOUS MODE
edge of the clock source. A 15-bit prescaler on the When the T0ASYNC bit of the T0CON1 register is clear
clock input gives several prescale options (see (T0ASYNC = 0), the counter clock is synchronized to
prescaler control bits, T0CKPS<3:0> in the T0CON1 the system oscillator (FOSC/4). When operating in
register). Synchronous mode, the counter clock frequency
cannot exceed FOSC/4.

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25.2 Clock Source Selection 25.5 Operation during Sleep
The T0CS<2:0> bits of the T0CON1 register are used When operating synchronously, Timer0 will halt. When
to select the clock source for Timer0. Register 25-2 operating asynchronously, Timer0 will continue to
displays the clock source selections. increment and wake the device from Sleep (if Timer0
interrupts are enabled) provided that the input clock
25.2.1 INTERNAL CLOCK SOURCE source is active.
When the internal clock source is selected, Timer0
operates as a timer and will increment on multiples of 25.6 Timer0 Interrupts
the clock source, as determined by the Timer0
The Timer0 interrupt flag bit (TMR0IF) is set when
prescaler.
either of the following conditions occur:
25.2.2 EXTERNAL CLOCK SOURCE • 8-bit TMR0L matches the TMR0H value
When an external clock source is selected, Timer0 can • 16-bit TMR0 rolls over from ‘FFFFh’
operate as either a timer or a counter. Timer0 will When the postscaler bits (T0OUTPS<3:0>) are set to
increment on multiples of the rising edge of the external 1:1 operation (no division), the T0IF flag bit will be set
clock source, as determined by the Timer0 prescaler. with every TMR0 match or rollover. In general, the
TMR0IF flag bit will be set every T0OUTPS +1 matches
25.3 Programmable Prescaler or rollovers.
If Timer0 interrupts are enabled (TMR0IE bit of the
A software programmable prescaler is available for
PIE0 register = 1), the CPU will be interrupted and the
exclusive use with Timer0. There are 16 prescaler
device may wake from sleep (see Section 25.2 “Clock
options for Timer0 ranging in powers of two from 1:1 to
Source Selection” for more details).
1:32768. The prescaler values are selected using the
T0CKPS<3:0> bits of the T0CON1 register.
25.7 Timer0 Output
The prescaler is not directly readable or writable.
Clearing the prescaler register can be done by writing The Timer0 output can be routed to any I/O pin via the
to the TMR0L register or the T0CON1 register. RxyPPS output selection register (see Section 15.0
“Peripheral Pin Select (PPS) Module” for additional
25.4 Programmable Postscaler information). The Timer0 output can also be used by
other peripherals, such as the Auto-conversion Trigger
A software programmable postscaler (output divider) is of the Analog-to-Digital Converter. Finally, the Timer0
available for exclusive use with Timer0. There are 16 output can be monitored through software via the
postscaler options for Timer0 ranging from 1:1 to 1:16. Timer0 output bit (T0OUT) of the T0CON0 register
The postscaler values are selected using the (Register 25-1).
T0OUTPS<3:0> bits of the T0CON0 register.
TMR0_out will be one postscaled clock period when a
The postscaler is not directly readable or writable. match occurs between TMR0L and TMR0H in 8-bit
Clearing the postscaler register can be done by writing mode, or when TMR0 rolls over in 16-bit mode. The
to the TMR0L register or the T0CON0 register. In the Timer0 output is a 50% duty cycle that toggles on each
16-bit mode, if the postscaler option is selected to a TMR0_out rising clock edge.
ratio other than 1:1, the reload of the TMR0H and
TMR0L registers is not possible inside the Interrupt
Service Routine. The timer period must be calculated
with the prescaler and postscaler factors selected.

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FIGURE 25-1: BLOCK DIAGRAM OF TIMER0

Rev. 10-000017G
4/6/2017

CLC1 111
Reserved 110
MFINTOSC 101 T0CKPS<3:0> TMR0 Peripherals
LFINTOSC 100 body T0OUTPS<3:0> T0IF
Prescaler 1
HFINTOSC 011 IN OUT Postscaler T0_out
SYNC 0
FOSC/4 010
PPS 001 FOSC/4 T016BIT TMR0
T0ASYNC D Q PPS
000
T0CKIPPS CK Q RxyPPS

T0CS<2:0>

8-bit TMR0 Body Diagram (T016BIT = 0) 16-bit TMR0 Body Diagram (T016BIT = 1)

Clear IN TMR0 High OUT

IN TMR0L R TMR0L Byte

Read TMR0L
COMPARATOR OUT
Write TMR0L
T0_match 8
8 TMR0H
TMR0 High
Byte
Latch 8
Enable
TMR0H
8
Internal Data Bus

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REGISTER 25-1: T0CON0: TIMER0 CONTROL REGISTER 0
R/W-0/0 U-0 R-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
T0EN — T0OUT T016BIT T0OUTPS<3:0>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 T0EN: Timer0 Enable bit

1 = The module is enabled and operating
0 = The module is disabled and in the lowest power mode
bit 6 Unimplemented: Read as ‘0’
bit 5 T0OUT: Timer0 Output bit (read-only)
Timer0 output bit
bit 4 T016BIT: Timer0 Operating as 16-bit Timer Select bit
1 = Timer0 is a 16-bit timer
0 = Timer0 is an 8-bit timer
bit 3-0 T0OUTPS<3:0>: Timer0 output postscaler (divider) select bits
1111 = 1:16 Postscaler
1110 = 1:15 Postscaler
1101 = 1:14 Postscaler
1100 = 1:13 Postscaler
1011 = 1:12 Postscaler
1010 = 1:11 Postscaler
1001 = 1:10 Postscaler
1000 = 1:9 Postscaler
0111 = 1:8 Postscaler
0110 = 1:7 Postscaler
0101 = 1:6 Postscaler
0100 = 1:5 Postscaler
0011 = 1:4 Postscaler
0010 = 1:3 Postscaler
0001 = 1:2 Postscaler
0000 = 1:1 Postscaler

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REGISTER 25-2: T0CON1: TIMER0 CONTROL REGISTER 1
R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
T0CS<2:0> T0ASYNC T0CKPS<3:0>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-5 T0CS<2:0>: Timer0 Clock Source select bits

111 = LC1_out
110 = Reserved
101 = MFINTOSC (500 kHz)
100 = LFINTOSC
011 = HFINTOSC
010 = FOSC/4
001 = T0CKIPPS (Inverted)
000 = T0CKIPPS (True)
bit 4 T0ASYNC: TMR0 Input Asynchronization Enable bit
1 = The input to the TMR0 counter is not synchronized to system clocks
0 = The input to the TMR0 counter is synchronized to FOSC/4
bit 3-0 T0CKPS<3:0>: Prescaler Rate Select bit
1111 = 1:32768
1110 = 1:16384
1101 = 1:8192
1100 = 1:4096
1011 = 1:2048
1010 = 1:1024
1001 = 1:512
1000 = 1:256
0111 = 1:128
0110 = 1:64
0101 = 1:32
0100 = 1:16
0011 = 1:8
0010 = 1:4
0001 = 1:2
0000 = 1:1

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TABLE 25-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0

Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
on Page

TMR0L Holding Register for the Least Significant Byte of the 16-bit TMR0 Register 260*
TMR0H Holding Register for the Most Significant Byte of the 16-bit TMR0 Register 260*
T0CON0 T0EN ― T0OUT T016BIT T0OUTPS<3:0> 263
T0CON1 T0CS<2:0> T0ASYNC T0CKPS<3:0> 264
T0CKIPPS ― ― T0CKIPPS<5:0> 191
TMR0PPS ― ― TMR0PPS<5:0> 191
T1GCON GE GPOL GTM GSPM GGO/DONE GVAL — — 275
INTCON GIE PEIE ― ― ― ― ― INTEDG 121
PIR0 ― ― TMR0IF IOCIF ― ― ― INTF 130
PIE0 ― ― TMR0IE IOCIE ― ― ― INTE 122
Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by the Timer0 module.
* Page with Register information.

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26.0 TIMER1 MODULE WITH GATE • Wake-up on overflow (external clock,
Asynchronous mode only)
CONTROL
• Time base for the Capture/Compare function
The Timer1 module is 16-bit timer/counters with the • Auto-conversion Trigger (with CCP)
following features:
• Selectable Gate Source Polarity
• 16-bit timer/counter register pair (TMR1H:TMR1L) • Gate Toggle mode
• Programmable internal or external clock source • Gate Single-Pulse mode
• 2-bit prescaler • Gate Value Status
• Clock source for optional comparator • Gate Event Interrupt
synchronization
Figure 26-1 is a block diagram of the Timer1 module.
• Multiple Timer1 gate (count enable) sources
• Interrupt on overflow This device has one instance of Timer1 type modules.

FIGURE 26-1: TIMER1 BLOCK DIAGRAM

TMRxGATE<4:0> Rev. 10-000018J
8/15/2016

4
TxGPPS
TxGSPM
PPS 00000

1
0 Single Pulse D Q TxGVAL
NOTE (5) 0
11111
1 Acq. Control
Q1
D Q

TxGPOL TxGGO/DONE
CK Q
TMRxON Interrupt
set bit
R
TxGTM det TMRxGIF

TMRxGE
set flag bit
TMRxIF
TMRxON
EN
(2) To Comparators (6)
TMRx
Tx_overflow Synchronized Clock Input
TMRxH TMRxL Q D 0
1
TxCLK
TxSYNC

TMRxCLK<3:0>
4
TxCKIPPS
(1)
PPS 0000

Prescaler
Synchronize(3)
1,2,4,8
(4)
Note det
1111
2
Fosc/2
TxCKPS<1:0> Internal Sleep
Clock Input
Note 1: ST Buffer is high speed type when using TxCKIPPS.
2: TMRx register increments on rising edge.
3: Synchronize does not operate while in Sleep.
4: See Register 26-3 for Clock source selections.
5: See Register 26-4 for GATE source selections.
6: Synchronized comparator output should not be used in conjunction with synchronized input clock.

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26.1 Timer1 Operation 26.2 Clock Source Selection
The Timer1 modules are 16-bit incrementing counters The T1CLK register is used to select the clock source for
which are accessed through the TMR1H:TMR1L the timer. Register 26-3 shows the possible clock
register pairs. Writes to TMR1H or TMR1L directly sources that may be selected to make the timer
update the counter. increment.
When used with an internal clock source, the module is
26.2.1 INTERNAL CLOCK SOURCE
a timer and increments on every instruction cycle.
When used with an external clock source, the module When the internal clock source FOSC is selected, the
can be used as either a timer or counter and incre- TMR1H:TMR1L register pair will increment on multiples
ments on every selected edge of the external source. of FOSC as determined by the respective Timer1
prescaler.
The timer is enabled by configuring the TMR1ON and
GE bits in the T1CON and T1GCON registers, When the FOSC internal clock source is selected, the
respectively. Table 26-1 displays the Timer1 enable timer register value will increment by four counts every
selections. instruction clock cycle. Due to this condition, a 2 LSB
error in resolution will occur when reading the
TMR1H:TMR1L value. To utilize the full resolution of the
TABLE 26-1: TIMER1 ENABLE timer in this mode, an asynchronous input signal must
SELECTIONS be used to gate the timer clock input.
Timer1 Out of the total timer gate signal sources, the following
TMR1ON TMR1GE
Operation subset of sources can be asynchronous and may be
1 1 Count Enabled useful for this purpose:
1 0 Always On • CLC4 output
0 1 Off • CLC3 output
• CLC2 output
0 0 Off
• CLC1 output
• Zero-Cross Detect output
• Comparator2 output
• Comparator1 output
• TxG PPS remappable input pin

26.2.2 EXTERNAL CLOCK SOURCE

When the timer is enabled and the external clock input
source (ex: T1CKI PPS remappable input) is selected as
the clock source, the timer will increment on the rising
edge of the external clock input.
When using an external clock source, the timer can be
configured to run synchronously or asynchronously, as
described in Section 26.4 “Timer Operation in
Asynchronous Counter Mode”.

Note: In Counter mode, a falling edge must be

registered by the counter prior to the first
incrementing rising edge after any one or
more of the following conditions:
• The timer is first enabled after POR
• Firmware writes to TMR1H or TMR1L
• The timer is disabled
• The timer is re-enabled (e.g.,
TMR1ON-->1) when the T1CKI
signal is currently logic low.

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26.3 Timer Prescaler 26.4.1 READING AND WRITING TIMER1 IN
ASYNCHRONOUS COUNTER
Timer1 has four prescaler options allowing 1, 2, 4 or 8
MODE
divisions of the clock input. The CKPS bits of the
T1CON register control the prescale counter. The Reading TMR1H or TMR1L while the timer is running
prescale counter is not directly readable or writable; from an external asynchronous clock will ensure a valid
however, the prescaler counter is cleared upon a write to read (taken care of in hardware). However, the user
TMR1H or TMR1L. should keep in mind that reading the 16-bit timer in two
8-bit values itself, poses certain problems, since the
26.4 Timer Operation in Asynchronous timer may overflow between the reads.
Counter Mode For writes, it is recommended that the user simply stop
the timer and write the desired values. A write
If the control bit SYNC of the T1CON register is set, the contention may occur by writing to the timer registers,
external clock input is not synchronized. The timer while the register is incrementing. This may produce an
increments asynchronously to the internal phase unpredictable value in the TMR1H:TMR1L register pair.
clocks. If the external clock source is selected then the
timer will continue to run during Sleep and can
26.5 Timer Gate
generate an interrupt on overflow, which will wake-up
the processor. However, special precautions in Timer1 can be configured to count freely or the count
software are needed to read/write the timer (see can be enabled and disabled using the time gate
Section 26.4.1 “Reading and Writing Timer1 in circuitry. This is also referred to as Timer Gate Enable.
Asynchronous Counter Mode”).
The timer gate can also be driven by multiple select-
Note: When switching from synchronous to able sources.
asynchronous operation, it is possible to
skip an increment. When switching from 26.5.1 TIMER GATE ENABLE
asynchronous to synchronous operation, The Timer Gate Enable mode is enabled by setting the
it is possible to produce an additional GE bit of the T1GCON register. The polarity of the
increment. Timer Gate Enable mode is configured using the GPOL
bit of the T1GCON register.
When Timer Gate Enable signal is enabled, the timer
will increment on the rising edge of the Timer1 clock
source. When Timer Gate Enable signal is disabled,
the timer always increments, regardless of the GE bit.
See Figure 26-3 for timing details.

TABLE 26-2: TIMER GATE ENABLE

SELECTIONS
T1CLK T1GPOL T1G Timer Operation
 1 1 Counts
 1 0 Holds Count
 0 1 Holds Count
 0 0 Counts

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26.5.2 TIMER GATE SOURCE SELECTION 26.5.4 TIMER1 GATE SINGLE-PULSE
One of the several different external or internal signal MODE
sources may be chosen to gate the timer and allow the When Timer1 Gate Single-Pulse mode is enabled, it is
timer to increment. The gate input signal source can be possible to capture a single-pulse gate event. Timer1
selected based on the T1GATE register setting. See the Gate Single-Pulse mode is first enabled by setting the
T1GATE register (Register 26-4) description for a GSPM bit in the T1GCON register. Next, the
complete list of the available gate sources. The polarity GGO/DONE bit in the T1GCON register must be set.
for each available source is also selectable. Polarity The timer will be fully enabled on the next incrementing
selection is controlled by the GPOL bit of the T1GCON edge. On the next trailing edge of the pulse, the
register. GGO/DONE bit will automatically be cleared. No other
gate events will be allowed to increment the timer until
26.5.2.1 T1G Pin Gate Operation the GGO/DONE bit is once again set in software. See
The T1G pin is one source for the timer gate control. It Figure 26-5 for timing details.
can be used to supply an external source to the time If the Single-Pulse Gate mode is disabled by clearing the
gate circuitry. GSPM bit in the T1GCON register, the GGO/DONE bit
should also be cleared.
26.5.2.2 Timer0 Overflow Gate Operation
Enabling the Toggle mode and the Single-Pulse mode
When Timer0 overflows, or a period register match simultaneously will permit both sections to work
condition occurs (in 8-bit mode), a low-to-high pulse will together. This allows the cycle times on the timer gate
automatically be generated and internally supplied to source to be measured. See Figure 26-6 for timing
the Timer1 gate circuitry. details.
26.5.2.3 Comparator C1 Gate Operation 26.5.5 TIMER1 GATE VALUE STATUS
The output resulting from a Comparator 1 operation can When Timer1 Gate Value Status is utilized, it is possible
be selected as a source for the timer gate control. The to read the most current level of the gate control value.
Comparator 1 output can be synchronized to the timer The value is stored in the GVAL bit in the T1GCON reg-
clock or left asynchronous. For more information see ister. The GVAL bit is valid even when the timer gate is
Section 23.4.1 “Comparator Output not enabled (GE bit is cleared).
Synchronization”.
26.5.6 TIMER1 GATE EVENT INTERRUPT
26.5.2.4 Comparator C2 Gate Operation
When Timer1 Gate Event Interrupt is enabled, it is
The output resulting from a Comparator 2 operation possible to generate an interrupt upon the completion
can be selected as a source for the timer gate control. of a gate event. When the falling edge of GVAL occurs,
The Comparator 2 output can be synchronized to the the TMR1GIF flag bit in the PIR5 register will be set. If
timer clock or left asynchronous. For more information the TMR1GIE bit in the PIE5 register is set, then an
see Section 23.4.1 “Comparator Output interrupt will be recognized.
Synchronization”.
The TMR1GIF flag bit operates even when the timer
26.5.3 TIMER1 GATE TOGGLE MODE gate is not enabled (TMR1GE bit is cleared).
When Timer1 Gate Toggle mode is enabled, it is possi-
ble to measure the full-cycle length of a timer gate sig-
nal, as opposed to the duration of a single level pulse.
The timer gate source is routed through a flip-flop that
changes state on every incrementing edge of the
signal. See Figure 26-4 for timing details.
Timer1 Gate Toggle mode is enabled by setting the
GTM bit of the T1GCON register. When the GTM bit is
cleared, the flip-flop is cleared and held clear. This is
necessary in order to control which edge is measured.
Note: Enabling Toggle mode at the same time
as changing the gate polarity may result in
indeterminate operation.

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26.6 Timer1 Interrupts 26.8 CCP Capture/Compare Time Base
The timer register pair (TMR1H:TMR1L) increments to The CCP modules use the TMR1H:TMR1L register
FFFFh and rolls over to 0000h. When the timer rolls pair as the time base when operating in Capture or
over, the respective timer interrupt flag bit of the PIR5 Compare mode.
register is set. To enable the interrupt on rollover, you In Capture mode, the value in the TMR1H:TMR1L
must set these bits: register pair is copied into the CCPRxH:CCPRxL
• ON bit of the T1CON register register pair on a configured event.
• TMR1IE bit of the PIE4 register In Compare mode, an event is triggered when the value
• PEIE bit of the INTCON register CCPRxH:CCPRxL register pair matches the value in
• GIE bit of the INTCON register the TMR1H:TMR1L register pair. This event can be an
Auto-conversion Trigger.
The interrupt is cleared by clearing the TMR1IF bit in
the Interrupt Service Routine. For more information, see Section 28.0
“Capture/Compare/PWM Modules”.

Note: To avoid immediate interrupt vectoring, 26.9 CCP Auto-Conversion Trigger

the TMR1H:TMR1L register pair should When any of the CCP’s are configured to trigger an
be preloaded with a value that is not immi- auto-conversion, the trigger will clear the
nently about to rollover, and the TMR1IF TMR1H:TMR1L register pair. This auto-conversion
flag should be cleared prior to enabling does not cause a timer interrupt. The CCP module may
the timer interrupts. still be configured to generate a CCP interrupt.
In this mode of operation, the CCPRxH:CCPRxL
26.7 Timer1 Operation During Sleep register pair becomes the period register for Timer1.
Timer1 can only operate during Sleep when setup in The timer should be synchronized and FOSC/4 should
Asynchronous Counter mode. In this mode, an external be selected as the clock source in order to utilize the
crystal or clock source can be used to increment the Auto-conversion Trigger. Asynchronous operation of
counter. To set up the timer to wake the device: the timer can cause an Auto-conversion Trigger to be
• ON bit of the T1CON register must be set missed.
• TMR1IE bit of the PIE4 register must be set In the event that a write to TMR1H or TMR1L coincides
• PEIE bit of the INTCON register must be set with an Auto-conversion Trigger from the CCP, the
write will take precedence.
• SYNC bit of the T1CON register must be set
• CS bits of the T1CLK register must be configured For more information, see Section 28.2.4 “Compare
During Sleep”.
• The timer clock source must be enabled and
continue operation during sleep.
The device will wake-up on an overflow and execute
the next instructions. If the GIE bit of the INTCON
register is set, the device will call the Interrupt Service
Routine.

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FIGURE 26-2: TIMER1 INCREMENTING EDGE

TxCKI = 1
when the timer is
enabled

TxCKI = 0
when the timer is
enabled

Note 1: Arrows indicate counter increments.

2: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock.

FIGURE 26-3: TIMER1 GATE ENABLE MODE

TMRxGE

TxGPOL

Selected
gate input

TxCKI

TxGVAL

TMRxH:TMRxL N N+1 N+2 N+3 N+4

Count

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FIGURE 26-4: TIMER1 GATE TOGGLE MODE

TMRxGE

TxGPOL

TxGTM

Selected
gate input
TxCKI

TxGVAL

TMRxH:TMRxL N N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8

Count

FIGURE 26-5: TIMER1 GATE SINGLE-PULSE MODE

TMRxGE

TxGPOL

TxGSPM
Cleared by hardware on
TxGGO/ Set by software falling edge of TxGVAL
DONE
Counting enabled on
rising edge of selected source
Selected gate
source

TxCKI

TxGVAL

TMRxH:TMRxL N N+1 N+2

Count
Cleared by
TMRxGIF Cleared by software Set by hardware on software
falling edge of TxGVAL

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FIGURE 26-6: TIMER1 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE

TMRxGE

TxGPOL

TxGSPM

TxGTM

Cleared by hardware on
TxGGO/ Set by software falling edge of TxGVAL
DONE Counting enabled on
rising edge of selected source
Selected gate
source

TxCKI

TxGVAL

TMRxH:TMRxL N N+1 N+2 N+3 N+4

Count
Set by hardware on Cleared by
TMRxGIF Cleared by software falling edge of TxGVAL software

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26.10 Register Definitions: Timer1 Control

REGISTER 26-1: T1CON: TIMER1 CONTROL REGISTER

U-0 U-0 R/W-0/u R/W-0/u U-0 R/W-0/u R/W-0/u R/W-0/u
— — CKPS<1:0> — SYNC RD16 ON
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 Unimplemented: Read as ‘0’

bit 5-4 CKPS<1:0>: Timer1 Input Clock Prescale Select bits
11 = 1:8 Prescale value
10 = 1:4 Prescale value
01 = 1:2 Prescale value
00 = 1:1 Prescale value
bit 3 Unimplemented: Read as ‘0’
bit 2 SYNC: Timer1 Synchronization Control bit
When TMR1CLK = FOSC or FOSC/4
This bit is ignored. The timer uses the internal clock and no additional synchronization is performed.
ELSE
0 = Synchronize external clock input with system clock
1 = Do not synchronize external clock input
bit 1 RD16: 16-bit Read/Write Mode Enable bit
0 = Enables register read/write of Timer1 in two 8-bit operation
1 = Enables register read/write of Timer1 in one 16-bit operation
bit 0 ON: Timer1 On bit
1 = Enables Timer1
0 = Stops Timer1 and clears Timer1 gate flip-flop

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REGISTER 26-2: T1GCON: TIMER1 GATE CONTROL REGISTER

R/W-0/u R/W-0/u R/W-0/u R/W-0/u R/W/HC-0/u R-x/x U-0 U-0
GE GPOL GTM GSPM GGO/DONE GVAL — —
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared HC = Bit is cleared by hardware

bit 7 GE: Timer1 Gate Enable bit

If ON = 0:
This bit is ignored
If ON = 1:
1 = Timer1 counting is controlled by the Timer1 gate function
0 = Timer1 is always counting
bit 6 GPOL: Timer1 Gate Polarity bit
1 = Timer1 gate is active-high (Timer1 counts when gate is high)
0 = Timer1 gate is active-low (Timer1 counts when gate is low)
bit 5 GTM: Timer1 Gate Toggle Mode bit
1 = Timer1 Gate Toggle mode is enabled
0 = Timer1 Gate Toggle mode is disabled and toggle flip-flop is cleared
Timer1 gate flip-flop toggles on every rising edge.
bit 4 GSPM: Timer1 Gate Single-Pulse Mode bit
1 = Timer1 Gate Single-Pulse mode is enabled
0 = Timer1 Gate Single-Pulse mode is disabled
bit 3 GGO/DONE: Timer1 Gate Single-Pulse Acquisition Status bit
1 = Timer1 gate single-pulse acquisition is ready, waiting for an edge
0 = Timer1 gate single-pulse acquisition has completed or has not been started
This bit is automatically cleared when GSPM is cleared
bit 2 GVAL: Timer1 Gate Value Status bit
Indicates the current state of the Timer1 gate that could be provided to TMR1H:TMR1L
Unaffected by Timer1 Gate Enable (GE)
bit 1-0 Unimplemented: Read as ‘0’

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REGISTER 26-3: T1CLK TIMER1 CLOCK SELECT REGISTER

U-0 U-0 U-0 U-0 R/W-0/u R/W-0/u R/W-0/u R/W-0/u
— — — — CS<3:0>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared HC = Bit is cleared by hardware

bit 7-4 Unimplemented: Read as ‘0’

bit 3-0 CS<3:0>: Timer1 Clock Select bits
1111 = Reserved
1110 = Reserved
1101 = LC4_out
1100 = LC3_out
1011 = LC2_out
1010 = LC1_out
1001 = Timer0 overflow output
1000 = CLKR output
0111 = Reserved
0110 = MFINTOSC (32 kHz)
0101 = MFINTOSC (500 kHz)
0100 = LFINTOSC
0011 = HFINTOSC
0010 = FOSC
0001 = FOSC/4
0000 = T1CKIPPS

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REGISTER 26-4: T1GATE TIMER1 GATE SELECT REGISTER

U-0 U-0 U-0 R/W-0/u R/W-0/u R/W-0/u R/W-0/u R/W-0/u
— — — GSS<4:0>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared HC = Bit is cleared by hardware

bit 7-5 Unimplemented: Read as ‘0’

bit 4-0 GSS<4:0>: Timer1 Gate Select bits
11111-10001 = Reserved
10000 = LC4_out
01111 = LC3_out
01110 = LC2_out
01101 = LC1_out
00100 = ZCD1_output
01011 = C2OUT_sync
01010 = C1OUT_sync
01001 = NCO1_out
01000 = PWM6_out
00111 = PWM5_out
00110 = PWM4_out
00101 = PWM3_out
00100 = CCP2_out
00011 = CCP1_out
00010 = TMR2_postscaled
00001 = Timer0 overflow output
00000 = T1GPPS

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TABLE 26-3: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1

Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
on Page

INTCON GIE PEIE ― ― ― ― ― INTEDG 121

PIE4 — — — — — — TMR2IE TMR1IE 126
PIR4 — — — — — — TMR2IF TMR1IF 134
T1CON — — CKPS<1:0> — SYNC RD16 ON 274
T1GCON GE GPOL GTM GSPM GGO/DONE GVAL — — 275
T1GATE — — — GSS<4:0> 277
T1CLK — — — — CS<3:0> 276
TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register 266*
TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register 266*
T1CKIPPS ― ― T1CKIPPS<5:0> 191
T1GPPS ― ― T1GPPS<5:0> 191
CCPxCON CCPxEN CCPxOE CCPxOUT CCPxFMT CCPxMODE<3:0> 306
CLCxSELy ― ― ― LCxDyS<4:0> 352
ADACT ― ― ― ADACT<4:0> 225
Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used with the Timer1 modules.
* Page with register information.

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27.0 TIMER2 MODULE WITH • Selectable external hardware timer Resets
HARDWARE LIMIT TIMER (HLT) • Programmable prescaler (1:1 to 1:128)
• Programmable postscaler (1:1 to 1:16)
The Timer2 module is an 8-bit timer that can operate as
• Selectable synchronous/asynchronous operation
free-running period counters or in conjunction with
external signals that control start, run, freeze, and reset • Alternate clock sources
operation in One-Shot and Monostable modes of • Interrupt-on-period
operation. Sophisticated waveform control such as • Three modes of operation:
pulse density modulation are possible by combining the - Free Running Period
operation of this timer with other internal peripherals - One-shot
such as the comparators and CCP modules. Features
- Monostable
of the timer include:
See Figure 27-1 for a block diagram of Timer2. See
• 8-bit timer register
Figure 27-2 for the clock source block diagram.
• 8-bit period register

FIGURE 27-1: TIMER2 BLOCK DIAGRAM

RSEL <:0> Rev. 10-000168C
9/10/2015

INPPS
TxIN PPS MODE<4:0> MODE<3>

Edge Detector reset

External
TMRx_ers Level Detector CCP_pset(1)
Reset
(2) Mode Control
Sources (2 clock Sync)

enable MODE<4:3>=01
Clear ON
MODE<4:1>=1011 D Q

CPOL
TMRx_clk Prescaler 0
R
T[7MR
Set flag bit
3 Sync 1 TMRxIF

CKPS<2:0> Fosc/4 PSYNC TMRx_postscaled

Comparator Postscaler

4
ON Sync
(2 Clocks)
1
7[PR OUTPS<3:0>
0

CSYNC

Note 1: Signal to the CCP to trigger the PWM pulse.

2: See Register 27-4 for external Reset sources.

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FIGURE 27-2: TIMER2 CLOCK SOURCE the output postscaler counter. When the postscaler
BLOCK DIAGRAM count equals the value in the OUTPS<4:0> bits of the
TMRxCON1 register, a one TMR2_clk period wide pulse
TxCLKCON Rev. 10-000 169B
occurs on the TMR2_postscaled output, and the
5/29/201 4
postscaler count is cleared.
TXINPPS
TXIN PPS 27.1.2 ONE-SHOT MODE
The One-Shot mode is identical to the Free Running
Period mode except that the ON bit is cleared and the
timer is stopped when TMR2 matches T2PR and will
Timer Clock Sources TMR2_clk not restart until the T2ON bit is cycled off and on.
(See Table 27-2) Postscaler OUTPS<4:0> values other than 0 are
meaningless in this mode because the timer is stopped
at the first period event and the postscaler is reset
when the timer is restarted.

27.1.3 MONOSTABLE MODE

Monostable modes are similar to One-Shot modes
except that the ON bit is not cleared and the timer can
be restarted by an external Reset event.
27.1 Timer2 Operation
Timer2 operates in three major modes: 27.2 Timer2 Output
• Free Running Period The Timer2 module’s primary output is TMR2_posts-
• One-shot caled, which pulses for a single TMR2_clk period when
• Monostable the postscaler counter matches the value in the
Within each mode there are several options for starting, OUTPS bits of the TMR2CON register. The T2PR post-
stopping, and reset. Table 27-1 lists the options. scaler is incremented each time the TMR2 value
matches the T2PR value. This signal can be selected
In all modes, the TMR2 count register is incremented as an input to several other input modules:
on the rising edge of the clock signal from the program-
mable prescaler. When TMR2 equals T2PR, a high • The ADC module, as an Auto-conversion Trigger
level is output to the postscaler counter. TMR2 is • COG, as an auto-shutdown source
cleared on the next clock input. In addition, the Timer2 is also used by the CCP module
An external signal from hardware can also be config- for pulse generation in PWM mode. Both the actual
ured to gate the timer operation or force a TMR2 count TMR2 value as well as other internal signals are sent to
Reset. In Gate modes the counter stops when the gate the CCP module to properly clock both the period and
is disabled and resumes when the gate is enabled. In pulse width of the PWM signal. See Section 28.0
Reset modes the TMR2 count is reset on either the “Capture/Compare/PWM Modules” for more details
level or edge from the external source. on setting up Timer2 for use with the CCP, as well as
the timing diagrams in Section 27.5 “Operation
The TMR2 and T2PR registers are both directly read-
Examples” for examples of how the varying Timer2
able and writable. The TMR2 register is cleared and the
modes affect CCP PWM output.
T2PR register initializes to FFh on any device Reset.
Both the prescaler and postscaler counters are cleared
on the following events: 27.3 External Reset Sources
• a write to the TMR2 register In addition to the clock source, the Timer2 also takes in
• a write to the T2CON register an external Reset source. This external Reset source
is selected for Timer2 with the T2RST register. This
• any device Reset
source can control starting and stopping of the timer, as
• External Reset Source event that resets the timer. well as resetting the timer, depending on which mode
Note: TMR2 is not cleared when T2CON is the timer is in. The mode of the timer is controlled by
written. the MODE<4:0> bits of the TMRxHLT register.
Edge-Triggered modes require six Timer clock periods
27.1.1 FREE RUNNING PERIOD MODE between external triggers. Level-Triggered modes
require the triggering level to be at least three Timer
The value of TMR2 is compared to that of the Period
clock periods long. External triggers are ignored while
register, T2PR, on each TMR2_clk cycle. When the two
in Debug Freeze mode.
values match, the comparator resets the value of TMR2
to 00h on the next rising TMR2_clk edge and increments

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TABLE 27-1: TIMER2 OPERATING MODES

MODE<4:0> Output Timer Control
Mode Operation
<4:3> <2:0> Operation Start Reset Stop
000 Software gate (Figure 27-4) ON = 1 — ON = 0
Hardware gate, active-high ON = 1 and — ON = 0 or
001 Period
(Figure 27-5) TMRx_ers = 1 TMRx_ers = 0
Pulse
ON = 1 and — ON = 0 or
010 Hardware gate, active-low
TMRx_ers = 0 TMRx_ers = 1
Free 011 Rising or falling edge Reset TMRx_ers ↕
Running 00
Period 100 Period Rising edge Reset (Figure 27-6) TMRx_ers ↑ ON = 0
101 Pulse Falling edge Reset TMRx_ers ↓
with ON = 1 ON = 0 or
110 Hardware Low level Reset TMRx_ers = 0
TMRx_ers = 0
Reset
High level Reset (Figure 27-7) ON = 0 or
111 TMRx_ers = 1
TMRx_ers = 1
000 One-shot Software start (Figure 27-8) ON = 1 —
ON = 1 and
001 Rising edge start (Figure 27-9) —
Edge TMRx_ers ↑
triggered ON = 1 and
010 Falling edge start —
start TMRx_ers ↓
(Note 1) ON = 1 and ON = 0
011 Any edge start — or
TMRx_ers ↕
Next clock
One-shot 01 Rising edge start and ON = 1 and
100 TMRx_ers ↑ after
Edge Rising edge Reset (Figure 27-10) TMRx_ers ↑ TMRx = PRx
triggered Falling edge start and ON = 1 and (Note 2)
101 start TMRx_ers ↓
Falling edge Reset TMRx_ers ↓
and
hardware Rising edge start and ON = 1 and
110 TMRx_ers = 0
Reset Low level Reset (Figure 27-11) TMRx_ers ↑
(Note 1) Falling edge start and ON = 1 and
111 TMRx_ers = 1
High level Reset TMRx_ers ↓
000 Reserved
Rising edge start ON = 1 and ON = 0
001 —
Edge (Figure 27-12) TMRx_ers ↑ or
Mono-stable triggered ON = 1 and Next clock
010 Falling edge start —
start TMRx_ers ↓ after
(Note 1) ON = 1 and TMRx = PRx
011 Any edge start — (Note 3)
TMRx_ers ↕
Reserved 10 100 Reserved
Reserved 101 Reserved
Level High level start and ON = 1 and
110 TMRx_ers = 0
triggered Low level Reset (Figure 27-13) TMRx_ers = 1
ON = 0 or
start
One-shot Held in Reset
and Low level start & ON = 1 and
111 TMRx_ers = 1 (Note 2)
hardware High level Reset TMRx_ers = 0
Reset
Reserved 11 xxx Reserved
Note 1: If ON = 0 then an edge is required to restart the timer after ON = 1.
2: When TMRx = PRx then the next clock clears ON and stops TMRx at 00h.
3: When TMRx = PRx then the next clock stops TMRx at 00h but does not clear ON.

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 PIC16(L)F15313/23
27.4 Timer2 Interrupt
Timer2 can also generate a device interrupt. The
interrupt is generated when the postscaler counter
matches one of 16 postscale options (from 1:1 through
1:16), which are selected with the postscaler control
bits, OUTPS<3:0> of the T2CON register. The interrupt
is enabled by setting the TMR2IE interrupt enable bit of
the PIE4 register. Interrupt timing is illustrated in
Figure 27-3.

FIGURE 27-3: TIMER2 PRESCALER, POSTSCALER, AND INTERRUPT TIMING DIAGRAM

Rev. 10-000205A
4/7/2016

CKPS 0b010

PRx 1

OUTPS 0b0001

TMRx_clk

TMRx 0 1 0 1 0 1 0

TMRx_postscaled

(1) (2) (1)

TMRxIF

Note 1: Setting the interrupt flag is synchronized with the instruction clock.
Synchronization may take as many as 2 instruction cycles
2: Cleared by software.

27.5 Operation Examples 27.5.1 SOFTWARE GATE MODE

Unless otherwise specified, the following notes apply to This mode corresponds to legacy Timer2 operation.
the following timing diagrams: The timer increments with each clock input when
ON = 1 and does not increment when ON = 0. When
- Both the prescaler and postscaler are set to the TMRx count equals the PRx period count the timer
1:1 (both the CKPS and OUTPS bits in the resets on the next clock and continues counting from 0.
TxCON register are cleared). Operation with the ON bit software controlled is illus-
- The diagrams illustrate any clock except trated in Figure 27-4. With PRx = 5, the counter
Fosc/4 and show clock-sync delays of at advances until TMRx = 5, and goes to zero with the
least two full cycles for both ON and next clock.
Timer2_ers. When using Fosc/4, the
clock-sync delay is at least one instruction
period for Timer2_ers; ON applies in the next
instruction period.
- The PWM Duty Cycle and PWM output are
illustrated assuming that the timer is used for
the PWM function of the CCP module as
described in Section 28.0 “Capture/Com-
pare/PWM Modules”. The signals are not a
part of the Timer2 module.

 2017 Microchip Technology Inc. Preliminary DS40001897A-page 282

 PIC16(L)F15313/23
FIGURE 27-4: SOFTWARE GATE MODE TIMING DIAGRAM (MODE = 00000)
Rev. 10-000195B
5/30/2014

MODE 0b00000

TMRx_clk

Instruction(1) BSF BCF BSF

ON

PRx 5

TMRx 0 1 2 3 4 5 0 1 2 3 4 5 0 1 2 3 4 5 0 1

TMRx_postscaled

PWM Duty
3
Cycle

PWM Output

Note 1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to
set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input.

 2017 Microchip Technology Inc. Preliminary DS40001897A-page 283

 PIC16(L)F15313/23
27.5.2 HARDWARE GATE MODE When MODE<4:0> = 00001 then the timer is stopped
when the external signal is high. When
The Hardware Gate modes operate the same as the
MODE<4:0> = 00010 then the timer is stopped when
Software Gate mode except the TMRx_ers external
the external signal is low.
signal gates the timer. When used with the CCP the
gating extends the PWM period. If the timer is stopped Figure 27-5 illustrates the Hardware Gating mode for
when the PWM output is high then the duty cycle is also MODE<4:0> = 00001 in which a high input level starts
extended. the counter.

FIGURE 27-5: HARDWARE GATE MODE TIMING DIAGRAM (MODE = 00001)

Rev. 10-000 196B
5/30/201 4

MODE 0b00001

TMRx_clk

TMRx_ers

PRx 5

TMRx 0 1 2 3 4 5 0 1 2 3 4 5 0 1

TMRx_postscaled

PWM Duty
3
Cycle

PWM Output

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 PIC16(L)F15313/23
27.5.3 EDGE-TRIGGERED HARDWARE When the timer is used in conjunction with the CCP in
LIMIT MODE PWM mode then an early Reset shortens the period
and restarts the PWM pulse after a two clock delay.
In Hardware Limit mode the timer can be reset by the
Refer to Figure 27-6.
TMRx_ers external signal before the timer reaches the
period count. Three types of Resets are possible:
• Reset on rising or falling edge
(MODE<4:0>= 00011)
• Reset on rising edge (MODE<4:0> = 00100)
• Reset on falling edge (MODE<4:0> = 00101)

FIGURE 27-6: EDGE-TRIGGERED HARDWARE LIMIT MODE TIMING DIAGRAM

(MODE = 00100)
Rev. 10-000 197B
5/30/201 4

MODE 0b00100

TMRx_clk

PRx 5

Instruction(1) BSF BCF BSF

ON

TMRx_ers

TMRx 0 1 2 0 1 2 3 4 5 0 1 2 3 4 5 0 1

TMRx_postscaled

PWM Duty
3
Cycle

PWM Output

Note 1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to
set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input.

 2017 Microchip Technology Inc. Preliminary DS40001897A-page 285

 PIC16(L)F15313/23
27.5.4 LEVEL-TRIGGERED HARDWARE When the CCP uses the timer as the PWM time base
LIMIT MODE then the PWM output will be set high when the timer
starts counting and then set low only when the timer
In the Level-Triggered Hardware Limit Timer modes the
count matches the CCPRx value. The timer is reset
counter is reset by high or low levels of the external
when either the timer count matches the PRx value or
signal TMRx_ers, as shown in Figure 27-7. Selecting
two clock periods after the external Reset signal goes
MODE<4:0> = 00110 will cause the timer to reset on a
true and stays true.
low level external signal. Selecting
MODE<4:0> = 00111 will cause the timer to reset on a The timer starts counting, and the PWM output is set
high level external signal. In the example, the counter high, on either the clock following the PRx match or two
is reset while TMRx_ers = 1. ON is controlled by BSF clocks after the external Reset signal relinquishes the
and BCF instructions. When ON = 0 the external signal Reset. The PWM output will remain high until the timer
is ignored. counts up to match the CCPRx pulse width value. If the
external Reset signal goes true while the PWM output
is high then the PWM output will remain high until the
Reset signal is released allowing the timer to count up
to match the CCPRx value.

FIGURE 27-7: LEVEL-TRIGGERED HARDWARE LIMIT MODE TIMING DIAGRAM

(MODE = 00111)
Rev. 10-000198B
5/30/2014

MODE 0b00111

TMRx_clk

PRx 5

Instruction(1) BSF BCF BSF

ON

TMRx_ers

TMRx 0 1 2 0 1 2 3 4 5 0 0 1 2 3 4 5 0

TMRx_postscaled

PWM Duty
3
Cycle

PWM Output

Note 1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to
set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input.

 2017 Microchip Technology Inc. Preliminary DS40001897A-page 286

 PIC16(L)F15313/23
27.5.5 SOFTWARE START ONE-SHOT When One-Shot mode is used in conjunction with the
MODE CCP PWM operation the PWM pulse drive starts
concurrent with setting the ON bit. Clearing the ON bit
In One-Shot mode the timer resets and the ON bit is
while the PWM drive is active will extend the PWM
cleared when the timer value matches the PRx period
drive. The PWM drive will terminate when the timer
value. The ON bit must be set by software to start
value matches the CCPRx pulse width value. The
another timer cycle. Setting MODE<4:0> = 01000
PWM drive will remain off until software sets the ON bit
selects One-Shot mode which is illustrated in
to start another cycle. If software clears the ON bit after
Figure 27-8. In the example, ON is controlled by BSF
the CCPRx match but before the PRx match then the
and BCF instructions. In the first case, a BSF instruc-
PWM drive will be extended by the length of time the
tion sets ON and the counter runs to completion and
ON bit remains cleared. Another timing cycle can only
clears ON. In the second case, a BSF instruction starts
be initiated by setting the ON bit after it has been
the cycle, BCF/BSF instructions turn the counter off
cleared by a PRx period count match.
and on during the cycle, and then it runs to completion.

FIGURE 27-8: SOFTWARE START ONE-SHOT MODE TIMING DIAGRAM (MODE = 01000)
Rev. 10-000199B
4/7/2016

MODE 0b01000

TMRx_clk

PRx 5

Instruction(1) BSF BSF BCF BSF

ON

TMRx 0 1 2 3 4 5 0 1 2 3 4 5 0

TMRx_postscaled

PWM Duty
3
Cycle

PWM Output

Note 1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions
executed by the CPU to set or clear the ON bit of TxCON. CPU
execution is asynchronous to the timer clock input.

 2017 Microchip Technology Inc. Preliminary DS40001897A-page 287

 PIC16(L)F15313/23
27.5.6 EDGE-TRIGGERED ONE-SHOT If the timer is halted by clearing the ON bit then another
MODE TMRx_ers edge is required after the ON bit is set to
resume counting. Figure 27-9 illustrates operation in
The Edge-Triggered One-Shot modes start the timer the rising edge One-Shot mode.
on an edge from the external signal input, after the ON
When Edge-Triggered One-Shot mode is used in con-
bit is set, and clear the ON bit when the timer matches
junction with the CCP then the edge-trigger will activate
the PRx period value. The following edges will start the the PWM drive and the PWM drive will deactivate when
timer: the timer matches the CCPRx pulse width value and
• Rising edge (MODE<4:0> = 01001) stay deactivated when the timer halts at the PRx period
• Falling edge (MODE<4:0> = 01010) count match.
• Rising or Falling edge (MODE<4:0> = 01011)

FIGURE 27-9: EDGE-TRIGGERED ONE-SHOT MODE TIMING DIAGRAM (MODE = 01001)

Rev. 10-000200B
5/19/2016

MODE 0b01001

TMRx_clk

PRx 5

Instruction(1) BSF BSF BCF

ON

TMRx_ers

TMRx 0 1 2 3 4 5 0 1 2

CCP_pset

TMRx_postscaled

PWM Duty
3
Cycle

PWM Output

Note 1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to
set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input.

 2017 Microchip Technology Inc. Preliminary DS40001897A-page 288

 27.5.7 EDGE-TRIGGERED HARDWARE LIMIT ONE-SHOT The timer resets and clears the ON bit when the timer value matches the PRx
 2017 Microchip Technology Inc.

MODE period value. External signal edges will have no effect until after software sets
the ON bit. Figure 27-10 illustrates the rising edge hardware limit one-shot
In Edge-Triggered Hardware Limit One-Shot modes the timer starts on the first operation.
external signal edge after the ON bit is set and resets on all subsequent edges.
When this mode is used in conjunction with the CCP then the first starting edge
Only the first edge after the ON bit is set is needed to start the timer. The
trigger, and all subsequent Reset edges, will activate the PWM drive. The PWM
counter will resume counting automatically two clocks after all subsequent drive will deactivate when the timer matches the CCPRx pulse-width value and
external Reset edges. Edge triggers are as follows: stay deactivated until the timer halts at the PRx period match unless an external
• Rising edge start and Reset (MODE<4:0> = 01100) signal edge resets the timer before the match occurs.
• Falling edge start and Reset (MODE<4:0> = 01101)

FIGURE 27-10: EDGE-TRIGGERED HARDWARE LIMIT ONE-SHOT MODE TIMING DIAGRAM (MODE = 01100)

Rev. 10-000201B
4/7/2016

MODE 0b01100

TMRx_clk
Preliminary

PRx 5

Instruction(1) BSF BSF

ON

PIC16(L)F15313/23
TMRx_ers

TMRx 0 1 2 3 4 5 0 1 2 0 1 2 3 4 5 0

TMRx_postscaled

PWM Duty
3
Cycle
DS40001897A-page 289

PWM Output

Note 1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to
set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input.
 27.5.8 LEVEL RESET, EDGE-TRIGGERED HARDWARE LIMIT When the timer count matches the PRx period count, the timer is reset and the
 2017 Microchip Technology Inc.

ONE-SHOT MODES ON bit is cleared. When the ON bit is cleared by either a PRx match or by soft-
ware control a new external signal edge is required after the ON bit is set to start
In Level -Triggered One-Shot mode the timer count is reset on the external the counter.
signal level and starts counting on the rising/falling edge of the transition from
When Level-Triggered Reset One-Shot mode is used in conjunction with the
Reset level to the active level while the ON bit is set. Reset levels are selected
CCP PWM operation the PWM drive goes active with the external signal edge
as follows: that starts the timer. The PWM drive goes inactive when the timer count equals
• Low Reset level (MODE<4:0> = 01110) the CCPRx pulse width count. The PWM drive does not go active when the
• High Reset level (MODE<4:0> = 01111) timer count clears at the PRx period count match.

FIGURE 27-11: LOW LEVEL RESET, EDGE-TRIGGERED HARDWARE LIMIT ONE-SHOT MODE TIMING DIAGRAM (MODE = 01110)
Rev. 10-000202B
4/7/2016

MODE 0b01110

TMRx_clk

PRx 5
Preliminary

Instruction(1) BSF BSF

ON

TMRx_ers

PIC16(L)F15313/23
TMRx 0 1 2 3 4 5 0 1 0 1 2 3 4 5 0

TMRx_postscaled

PWM Duty
3
Cycle

PWM Output
DS40001897A-page 290

Note 1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to
set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input.
 27.5.9 EDGE-TRIGGERED MONOSTABLE MODES When an Edge-Triggered Monostable mode is used in conjunction with the
 2017 Microchip Technology Inc.

CCP PWM operation the PWM drive goes active with the external Reset signal
The Edge-Triggered Monostable modes start the timer on an edge from the
edge that starts the timer, but will not go active when the timer matches the PRx
external Reset signal input, after the ON bit is set, and stop incrementing the
value. While the timer is incrementing, additional edges on the external Reset
timer when the timer matches the PRx period value. The following edges will
signal will not affect the CCP PWM.
start the timer:
• Rising edge (MODE<4:0> = 10001)
• Falling edge (MODE<4:0> = 10010)
• Rising or Falling edge (MODE<4:0> = 10011)

FIGURE 27-12: RISING EDGE-TRIGGERED MONOSTABLE MODE TIMING DIAGRAM (MODE = 10001)
Rev. 10-000203A
4/7/2016

MODE 0b10001

TMRx_clk

PRx 5
Preliminary

Instruction(1) BSF BCF BSF BCF BSF

ON

TMRx_ers

PIC16(L)F15313/23
TMRx 0 1 2 3 4 5 0 1 2 3 4 5 0 1 2 3 4 5 0

TMRx_postscaled

PWM Duty
3
Cycle

PWM Output
DS40001897A-page 291

Note 1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to
set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input.
 27.5.10 LEVEL-TRIGGERED HARDWARE LIMIT ONE-SHOT When the timer count matches the PRx period count, the timer is reset and the
 2017 Microchip Technology Inc.

MODES ON bit is cleared. When the ON bit is cleared by either a PRx match or by soft-
ware control the timer will stay in Reset until both the ON bit is set and the exter-
The Level-Triggered Hardware Limit One-Shot modes hold the timer in Reset
nal signal is not at the Reset level.
on an external Reset level and start counting when both the ON bit is set and
the external signal is not at the Reset level. If one of either the external signal When Level-Triggered Hardware Limit One-Shot modes are used in conjunc-
is not in Reset or the ON bit is set then the other signal being set/made active tion with the CCP PWM operation the PWM drive goes active with either the
will start the timer. Reset levels are selected as follows: external signal edge or the setting of the ON bit, whichever of the two starts the
timer.
• Low Reset level (MODE<4:0> = 10110)
• High Reset level (MODE<4:0> = 10111)

FIGURE 27-13: LEVEL-TRIGGERED HARDWARE LIMIT ONE-SHOT MODE TIMING DIAGRAM (MODE = 10110)
Rev. 10-000204A
4/7/2016

MODE 0b10110

TMR2_clk
Preliminary

PRx 5

Instruction(1) BSF BSF BCF BSF

ON

PIC16(L)F15313/23
TMR2_ers

TMRx 0 1 2 3 4 5 0 1 2 3 0 1 2 3 4 5 0

TMR2_postscaled

PWM Duty
‘D3
Cycle

PWM Output
DS40001897A-page 292

Note 1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to
set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input.
 PIC16(L)F15313/23
27.6 Timer2 Operation During Sleep
When PSYNC = 1, Timer2 cannot be operated while
the processor is in Sleep mode. The contents of the
TMR2 and T2PR registers will remain unchanged while
processor is in Sleep mode.
When PSYNC = 0, Timer2 will operate in Sleep as long
as the clock source selected is also still running.
Selecting the LFINTOSC, MFINTOSC, or HFINTOSC
oscillator as the timer clock source will keep the
selected oscillator running during Sleep.

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 PIC16(L)F15313/23
27.7 Register Definitions: Timer2 Control

REGISTER 27-1: T2CLKCON: TIMER2 CLOCK SELECTION REGISTER

U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— — — — CS<3:0>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-4 Unimplemented: Read as ‘0’

bit 3-0 CS<3:0>: Timer2 Clock Select bits
1111 = Reserved
1110 = LC4_out
1101 = LC3_out
1100 = LC2_out
1011 = LC1_out
1010 = ZCD1_output
1001 = NCO1_out
1000 = CLKR
0111 = Reserved
0110 = MFINTOSC (31.25 kHz)
0101 = MFINTOSC (500 kHz)
0100 = LFINTOSC
0011 = HFINTOSC (32 MHz)
0010 = FOSC
0001 = FOSC/4
0000 = T2CKIPPS

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 PIC16(L)F15313/23

REGISTER 27-2: T2CON: TIMER2 CONTROL REGISTER

R/W/HC-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
(1)
ON CKPS<2:0> OUTPS<3:0>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared HC = Bit is cleared by hardware

bit 7 ON: Timerx On bit

1 = Timerx is on
0 = Timerx is off: all counters and state machines are reset
bit 6-4 CKPS<2:0>: Timer2-type Clock Prescale Select bits
111 = 1:128 Prescaler
110 = 1:64 Prescaler
101 = 1:32 Prescaler
100 = 1:16 Prescaler
011 = 1:8 Prescaler
010 = 1:4 Prescaler
001 = 1:2 Prescaler
000 = 1:1 Prescaler
bit 3-0 OUTPS<3:0>: Timerx Output Postscaler Select bits
1111 = 1:16 Postscaler
1110 = 1:15 Postscaler
1101 = 1:14 Postscaler
1100 = 1:13 Postscaler
1011 = 1:12 Postscaler
1010 = 1:11 Postscaler
1001 = 1:10 Postscaler
1000 = 1:9 Postscaler
0111 = 1:8 Postscaler
0110 = 1:7 Postscaler
0101 = 1:6 Postscaler
0100 = 1:5 Postscaler
0011 = 1:4 Postscaler
0010 = 1:3 Postscaler
0001 = 1:2 Postscaler
0000 = 1:1 Postscaler

Note 1: In certain modes, the ON bit will be auto-cleared by hardware. See Section 27.5 “Operation Examples”.

 2017 Microchip Technology Inc. Preliminary DS40001897A-page 295

 PIC16(L)F15313/23

REGISTER 27-3: T2HLT: TIMERx HARDWARE LIMIT CONTROL REGISTER

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
PSYNC(1, 2) CKPOL(3) CKSYNC(4, 5) MODE<4:0>(6, 7)
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 PSYNC: Timerx Prescaler Synchronization Enable bit(1, 2)

1 = TMRx Prescaler Output is synchronized to Fosc/4
0 = TMRx Prescaler Output is not synchronized to Fosc/4
bit 6 CKPOL: Timerx Clock Polarity Selection bit(3)
1 = Falling edge of input clock clocks timer/prescaler
0 = Rising edge of input clock clocks timer/prescaler
bit 5 CKSYNC: Timerx Clock Synchronization Enable bit(4, 5)
1 = ON register bit is synchronized to TMR2_clk input
0 = ON register bit is not synchronized to TMR2_clk input
bit 4-0 MODE<4:0>: Timerx Control Mode Selection bits(6, 7)
See Table 27-1.

Note 1: Setting this bit ensures that reading TMRx will return a valid value.
2: When this bit is ‘1’, Timer2 cannot operate in Sleep mode.
3: CKPOL should not be changed while ON = 1.
4: Setting this bit ensures glitch-free operation when the ON is enabled or disabled.
5: When this bit is set then the timer operation will be delayed by two TMRx input clocks after the ON bit is set.
6: Unless otherwise indicated, all modes start upon ON = 1 and stop upon ON = 0 (stops occur without affecting the value
of TMRx).
7: When TMRx = PRx, the next clock clears TMRx, regardless of the operating mode.

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 PIC16(L)F15313/23

REGISTER 27-4: T2RST: TIMER2 EXTERNAL RESET SIGNAL SELECTION REGISTER

U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— — — — RSEL<3:0>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-4 Unimplemented: Read as ‘0’

bit 3-0 RSEL<3:0>: Timer2 External Reset Signal Source Selection bits
1111 = Reserved
1101 = LC4_out
1100 = LC3_out
1011 = LC2_out
1010 = LC1_out
1001 = ZCD1_output
1000 = C2OUT_sync(1)
0111 = C1OUT_sync
0110 = PWM6_out
0101 = PWM5_out
0100 = PWM4_out
0011 = PWM3_out
0010 = CCP2_out
0001 = CCP1_out
0000 = T2INPPS

Note 1: Present on PIC16(L)F15323 only. Reserved for the PIC16(L)F15313.

 2017 Microchip Technology Inc. Preliminary DS40001897A-page 297

 PIC16(L)F15313/23
TABLE 27-2: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER2
Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
on Page
CCP1CON EN — OUT FMT MODE<3:0> 306
CCP2CON EN — OUT FMT MODE<3:0> 306
INTCON GIE PEIE — — — — — INTEDG 121
PIE1 OSFIE CSWIE — — — — ― ADIE 123
PIR1 OSFIF CSWIF — — — — — ADIF 131
PR2 Timer2 Module Period Register 280*
TMR2 Holding Register for the 8-bit TMR2 Register 280*
T2CON ON CKPS<2:0> OUTPS<3:0> 295
T2CLKCON — — — — CS<3:0> 294
T2RST — — — — RSEL<3:0> 297
T2HLT PSYNC CKPOL CKSYNC MODE<4:0> 296
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for Timer2 module.
* Page provides register information.

 2017 Microchip Technology Inc. Preliminary DS40001897A-page 298

 PIC16(L)F15313/23
28.0 CAPTURE/COMPARE/PWM
MODULES
The Capture/Compare/PWM module is a peripheral
that allows the user to time and control different events,
and to generate Pulse-Width Modulation (PWM)
signals. In Capture mode, the peripheral allows the
timing of the duration of an event. The Compare mode
allows the user to trigger an external event when a
predetermined amount of time has expired. The PWM
mode can generate Pulse-Width Modulated signals of
varying frequency and duty cycle.
The Capture/Compare/PWM modules available are
shown in Table 28-1.

TABLE 28-1: AVAILABLE CCP MODULES

Device CCP1 CCP2
PIC16(L)F15313/23 ● ●
The Capture and Compare functions are identical for all
CCP modules.
Note 1: In devices with more than one CCP
module, it is very important to pay close
attention to the register names used. A
number placed after the module acronym
is used to distinguish between separate
modules. For example, the CCP1CON
and CCP2CON control the same
operational aspects of two completely
different CCP modules.
2: Throughout this section, generic
references to a CCP module in any of its
operating modes may be interpreted as
being equally applicable to CCPx module.
Register names, module signals, I/O pins,
and bit names may use the generic
designator ‘x’ to indicate the use of a
numeral to distinguish a particular module,
when required.

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 PIC16(L)F15313/23
28.1 Capture Mode Figure 28-1 shows a simplified diagram of the capture
operation.
Capture mode makes use of the 16-bit Timer1
resource. When an event occurs on the capture 28.1.1 CAPTURE SOURCES
source, the 16-bit CCPRxH:CCPRxL register pair
In Capture mode, the CCPx pin should be configured
captures and stores the 16-bit value of the
as an input by setting the associated TRIS control bit.
TMR1H:TMR1L register pair, respectively. An event is
defined as one of the following and is configured by the Note: If the CCPx pin is configured as an output,
CCPxMODE<3:0> bits of the CCPxCON register: a write to the port can cause a capture
• Every falling edge condition.
• Every rising edge The capture source is selected by configuring the
• Every 4th rising edge CCPxCTS<2:0> bits of the CCPxCAP register. The
following sources can be selected:
• Every 16th rising edge
• CCPxPPS input
When a capture is made, the Interrupt Request Flag bit
• C1OUT_sync
CCPxIF of the PIR6 register is set. The interrupt flag
• C2OUT_sync
must be cleared in software. If another capture occurs
• IOC_interrupt
before the value in the CCPRxH, CCPRxL register pair
• LC1_out
is read, the old captured value is overwritten by the new
• LC2_out
captured value.
• LC3_out
• LC4_out

FIGURE 28-1: CAPTURE MODE OPERATION BLOCK DIAGRAM

Rev. 10-000158F
9/1/2015
RxyPPS
CCPx
CTS<2:0>

TRIS Control
LC4_out 111
LC3_out 110 CCPRxH CCPRxL
LC2_out 101 16
set CCPxIF
LC1_out 100 Prescaler and
IOC_interrupt 011 1,4,16 Edge Detect
16
C2OUT_sync 010
C1OUT_sync 001 MODE <3:0> TMR1H TMR1L
CCPx PPS 000

CCPxPPS

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28.1.2 TIMER1 MODE RESOURCE 28.1.5 CAPTURE DURING SLEEP
Timer1 must be running in Timer mode or Synchronized Capture mode depends upon the Timer1 module for
Counter mode for the CCP module to use the capture proper operation. There are two options for driving the
feature. In Asynchronous Counter mode, the capture Timer1 module in Capture mode. It can be driven by the
operation may not work. instruction clock (FOSC/4), or by an external clock source.
See Section 26.0 “Timer1 Module with Gate When Timer1 is clocked by FOSC/4, Timer1 will not
Control” for more information on configuring Timer1. increment during Sleep. When the device wakes from
Sleep, Timer1 will continue from its previous state.
28.1.3 SOFTWARE INTERRUPT MODE
Capture mode will operate during Sleep when Timer1
When the Capture mode is changed, a false capture is clocked by an external clock source.
interrupt may be generated. The user should keep the
CCPxIE interrupt enable bit of the PIE6 register clear to 28.2 Compare Mode
avoid false interrupts. Additionally, the user should
clear the CCPxIF interrupt flag bit of the PIR6 register Compare mode makes use of the 16-bit Timer1
following any change in Operating mode. resource. The 16-bit value of the CCPRxH:CCPRxL
register pair is constantly compared against the 16-bit
Note: Clocking Timer1 from the system clock value of the TMR1H:TMR1L register pair. When a
(FOSC) should not be used in Capture match occurs, one of the following events can occur:
mode. In order for Capture mode to
recognize the trigger event on the CCPx • Toggle the CCPx output
pin, Timer1 must be clocked from the • Set the CCPx output
instruction clock (FOSC/4). • Clear the CCPx output
• Generate an Auto-conversion Trigger
28.1.4 CCP PRESCALER • Generate a Software Interrupt
There are four prescaler settings specified by the The action on the pin is based on the value of the
CCPxMODE<3:0> bits of the CCPxCON register. CCPxMODE<3:0> control bits of the CCPxCON
Whenever the CCP module is turned off, or the CCP register. At the same time, the interrupt flag CCPxIF bit
module is not in Capture mode, the prescaler counter is set, and an ADC conversion can be triggered, if
is cleared. Any Reset will clear the prescaler counter. selected.
Switching from one capture prescaler to another does not All Compare modes can generate an interrupt and
clear the prescaler and may generate a false interrupt. To trigger and ADC conversion.
avoid this unexpected operation, turn the module off by
clearing the CCPxCON register before changing the Figure 28-2 shows a simplified diagram of the compare
prescaler. Example 28-1 demonstrates the code to operation.
perform this function.
FIGURE 28-2: COMPARE MODE
EXAMPLE 28-1: CHANGING BETWEEN OPERATION BLOCK
CAPTURE PRESCALERS DIAGRAM
BANKSEL CCPxCON ;Set Bank bits to point CCPxMODE<3:0>
;to CCPxCON Mode Select
CLRF CCPxCON ;Turn CCP module off
MOVLW NEW_CAPT_PS ;Load the W reg with Set CCPxIF Interrupt Flag
;the new prescaler (PIR6)
CCPx 4
;move value and CCP ON Pin CCPRxH CCPRxL
MOVWF CCPxCON ;Load CCPxCON with this
Q S
;value Output Comparator
R Logic Match

TMR1H TMR1L
TRIS
Output Enable

Auto-conversion Trigger

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28.2.1 CCPX PIN CONFIGURATION 28.3 PWM Overview
The software must configure the CCPx pin as an output Pulse-Width Modulation (PWM) is a scheme that
by clearing the associated TRIS bit and defining the provides power to a load by switching quickly between
appropriate output pin through the RxyPPS registers. fully on and fully off states. The PWM signal resembles
See Section 15.0 “Peripheral Pin Select (PPS) a square wave where the high portion of the signal is
Module” for more details. considered the on state and the low portion of the signal
The CCP output can also be used as an input for other is considered the off state. The high portion, also known
peripherals. as the pulse width, can vary in time and is defined in
steps. A larger number of steps applied, which
lengthens the pulse width, also supplies more power to
Note: Clearing the CCPxCON register will force the load. Lowering the number of steps applied, which
the CCPx compare output latch to the shortens the pulse width, supplies less power. The
default low level. This is not the PORT I/O PWM period is defined as the duration of one complete
data latch. cycle or the total amount of on and off time combined.
PWM resolution defines the maximum number of steps
28.2.2 TIMER1 MODE RESOURCE
that can be present in a single PWM period. A higher
In Compare mode, Timer1 must be running in either resolution allows for more precise control of the pulse
Timer mode or Synchronized Counter mode. The width time and in turn the power that is applied to the
compare operation may not work in Asynchronous load.
Counter mode.
The term duty cycle describes the proportion of the on
See Section 26.0 “Timer1 Module with Gate Control” time to the off time and is expressed in percentages,
for more information on configuring Timer1. where 0% is fully off and 100% is fully on. A lower duty
cycle corresponds to less power applied and a higher
Note: Clocking Timer1 from the system clock
duty cycle corresponds to more power applied.
(FOSC) should not be used in Compare
mode. In order for Compare mode to Figure 28-3 shows a typical waveform of the PWM
recognize the trigger event on the CCPx signal.
pin, TImer1 must be clocked from the
instruction clock (FOSC/4) or from an 28.3.1 STANDARD PWM OPERATION
external clock source. The standard PWM mode generates a Pulse-Width
Modulation (PWM) signal on the CCPx pin with up to
28.2.3 AUTO-CONVERSION TRIGGER ten bits of resolution. The period, duty cycle, and
All CCPx modes set the CCP interrupt flag (CCPxIF). resolution are controlled by the following registers:
When this flag is set and a match occurs, an • PR2 registers
Auto-conversion Trigger can take place if the CCP • T2CON registers
module is selected as the conversion trigger source.
• CCPRxL registers
Refer to Section 20.2.4 “Auto-Conversion Trigger” • CCPxCON registers
for more information.
Figure 28-4 shows a simplified block diagram of PWM
Note: Removing the match condition by operation.
changing the contents of the CCPRxH
and CCPRxL register pair, between the
clock edge that generates the Note: The corresponding TRIS bit must be
Auto-conversion Trigger and the clock cleared to enable the PWM output on the
edge that generates the Timer1 Reset, will CCPx pin.
preclude the Reset from occurring
FIGURE 28-3: CCP PWM OUTPUT SIGNAL
28.2.4 COMPARE DURING SLEEP
Since FOSC is shut down during Sleep mode, the Period
Compare mode will not function properly during Sleep,
unless the timer is running. The device will wake on Pulse Width
TMR2 = PR2
interrupt (if enabled).
TMR2 = CCPRxH:CCPRxL

TMR2 = 0

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FIGURE 28-4: SIMPLIFIED PWM BLOCK DIAGRAM
Rev. 10-000 157C

Duty cycle registers 9/5/201 4

CCPRxH CCPRxL
CCPx_out
To Peripherals
set CCPIF
10-bit Latch(2)
(Not accessible by user)

Comparator R Q PPS CCPx

S RxyPPS
TMR2 Module TRIS Control

R
TMR2 (1)

ERS logic
Comparator CCPx_pset

PR2

28.3.2 SETUP FOR PWM OPERATION 6. Enable PWM output pin:

The following steps should be taken when configuring • Wait until the Timer overflows and the
the CCP module for standard PWM operation: TMR2IF bit of the PIR4 register is set. See
Note below.
1. Use the desired output pin RxyPPS control to
• Enable the CCPx pin output driver by
select CCPx as the source and disable the
clearing the associated TRIS bit.
CCPx pin output driver by setting the associated
TRIS bit. Note: In order to send a complete duty cycle and
2. Load the PR2 register with the PWM period period on the first PWM output, the above
value. steps must be included in the setup
sequence. If it is not critical to start with a
3. Configure the CCP module for the PWM mode
complete PWM signal on the first output,
by loading the CCPxCON register with the
then step 6 may be ignored.
appropriate values.
4. Load the CCPRxL register, and the CCPRxH
28.3.3 CCP/PWM CLOCK SELECTION
register with the PWM duty cycle value and
configure the CCPxFMT bit of the CCPxCON The PIC16(L)F15313/23 allows each individual CCP
register to set the proper register alignment. and PWM module to select the timer source that
5. Configure and start Timer2: controls the module. Each module has an independent
selection.
• Clear the TMR2IF interrupt flag bit of the
PIR4 register. See Note below.
• Configure the CKPS bits of the T2CON
register with the Timer prescale value.
• Enable the Timer by setting the Timer2 ON
bit of the T2CON register.

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28.3.4 TIMER2 TIMER RESOURCE FIGURE 28-5: PWM 10-BIT ALIGNMENT
This device has a newer version of the Timer2 module Rev. 10-000 160A

that has many new modes, which allow for greater 12/9/201 3

customization and control of the PWM signals than on CCPRxH CCPRxL

older parts. Refer to Section 27.5 “Operation 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 FMT = 0
Examples” for examples of PWM signal generation
using the different modes of Timer2. The CCP CCPRxH CCPRxL
operation requires that the timer used as the PWM time FMT = 1 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
base has the FOSC/4 clock source selected

28.3.5 PWM PERIOD 10-bit Duty Cycle

The PWM period is specified by the PR2 register of 9 8 7 6 5 4 3 2 1 0
Timer2. The PWM period can be calculated using the
formula of Equation 28-1.

EQUATION 28-1: PWM PERIOD EQUATION 28-2: PULSE WIDTH

PWM Period =   PR2  + 1   4  T OSC  Pulse Width =  CCPRxH:CCPRxL register pair  

(TMR2 Prescale Value) T OSC  (TMR2 Prescale Value)

Note 1: TOSC = 1/FOSC

EQUATION 28-3: DUTY CYCLE RATIO
When TMR2 is equal to PR2, the following three events
occur on the next increment cycle:
 CCPRxH:CCPRxL register pair 
• TMR2 is cleared Duty Cycle Ratio = ----------------------------------------------------------------------------------
4  PR2 + 1 
• The CCPx pin is set. (Exception: If the PWM duty
cycle = 0%, the pin will not be set.)
CCPRxH:CCPRxL register pair are used to double
• The PWM duty cycle is transferred from the
buffer the PWM duty cycle. This double buffering
CCPRxL/H register pair into a 10-bit buffer.
provides for glitchless PWM operation.

Note: The Timer postscaler (see Section 27.4 The 8-bit timer TMR2 register is concatenated with
“Timer2 Interrupt”) is not used in the either the 2-bit internal system clock (FOSC), or two bits
determination of the PWM frequency. of the prescaler, to create the 10-bit time base. The
system clock is used if the Timer2 prescaler is set to 1:1.
28.3.6 PWM DUTY CYCLE When the 10-bit time base matches the
The PWM duty cycle is specified by writing a 10-bit CCPRxH:CCPRxL register pair, then the CCPx pin is
value to the CCPRxH:CCPRxL register pair. The cleared (see Figure 28-4).
alignment of the 10-bit value is determined by the
CCPRxFMT bit of the CCPxCON register (see 28.3.7 PWM RESOLUTION
Figure 28-5). The CCPRxH:CCPRxL register pair can The resolution determines the number of available duty
be written to at any time; however the duty cycle value cycles for a given period. For example, a 10-bit resolution
is not latched into the 10-bit buffer until after a match will result in 1024 discrete duty cycles, whereas an 8-bit
between PR2 and TMR2. resolution will result in 256 discrete duty cycles.
Equation 28-2 is used to calculate the PWM pulse The maximum PWM resolution is ten bits when PR2 is
width. 255. The resolution is a function of the PR2 register
Equation 28-3 is used to calculate the PWM duty cycle value as shown by Equation 28-4.
ratio.
EQUATION 28-4: PWM RESOLUTION

log  4  PR2 + 1  
Resolution = ------------------------------------------ bits
log  2 

Note: If the pulse width value is greater than the

period the assigned PWM pin(s) will
remain unchanged.

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TABLE 28-2: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 20 MHz)
PWM Frequency 1.22 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz
Timer Prescale 16 4 1 1 1 1
PR2 Value 0xFF 0xFF 0xFF 0x3F 0x1F 0x17
Maximum Resolution (bits) 10 10 10 8 7 6.6

TABLE 28-3: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 8 MHz)

PWM Frequency 1.22 kHz 4.90 kHz 19.61 kHz 76.92 kHz 153.85 kHz 200.0 kHz
Timer Prescale 16 4 1 1 1 1
PR2 Value 0x65 0x65 0x65 0x19 0x0C 0x09
Maximum Resolution (bits) 8 8 8 6 5 5

28.3.8 OPERATION IN SLEEP MODE

In Sleep mode, the TMR2 register will not increment
and the state of the module will not change. If the CCPx
pin is driving a value, it will continue to drive that value.
When the device wakes up, TMR2 will continue from its
previous state.

28.3.9 CHANGES IN SYSTEM CLOCK

FREQUENCY
The PWM frequency is derived from the system clock
frequency. Any changes in the system clock frequency
will result in changes to the PWM frequency. See
Section 9.0 “Oscillator Module (with Fail-Safe
Clock Monitor)” for additional details.

28.3.10 EFFECTS OF RESET

Any Reset will force all ports to Input mode and the
CCP registers to their Reset states.

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28.4 Register Definitions: CCP Control
Long bit name prefixes for the CCP peripherals are
shown in Section 1.1 “Register and Bit Naming
Conventions”.
TABLE 28-4: LONG BIT NAMES PREFIXES
FOR CCP PERIPHERALS
Peripheral Bit Name Prefix
CCP1 CCP1
CCP2 CCP2

REGISTER 28-1: CCPxCON: CCPx CONTROL REGISTER

R/W-0/0 U-0 R-x R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
EN — OUT FMT MODE<3:0>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Reset
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 EN: CCPx Module Enable bit

1 = CCPx is enabled
0 = CCPx is disabled
bit 6 Unimplemented: Read as ‘0’
bit 5 OUT: CCPx Output Data bit (read-only)
bit 4 FMT: CCPW (Pulse Width) Alignment bit
MODE = Capture mode
Unused
MODE = Compare mode
Unused
MODE = PWM mode
1 = Left-aligned format
0 = Right-aligned format

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REGISTER 28-1: CCPxCON: CCPx CONTROL REGISTER (CONTINUED)
bit 3-0 MODE<3:0>: CCPx Mode Select bits(1)
1111 - 1100 = PWM mode (Timer2 as the timer source)
1110 = Reserved
1101 = Reserved
1100 = Reserved

1011 = Compare mode: output will pulse 0-1-0; Clears TMR1

1010 = Compare mode: output will pulse 0-1-0
1001 = Compare mode: clear output on compare match
1000 = Compare mode: set output on compare match

0111 = Capture mode: every 16th rising edge of CCPx input

0110 = Capture mode: every 4th rising edge of CCPx input
0101 = Capture mode: every rising edge of CCPx input
0100 = Capture mode: every falling edge of CCPx input

0011 = Capture mode: every edge of CCPx input

0010 = Compare mode: toggle output on match
0001 = Compare mode: toggle output on match; clear TMR1
0000 = Capture/Compare/PWM off (resets CCPx module)

Note 1: All modes will set the CCPxIF bit, and will trigger an ADC conversion if CCPx is selected as the ADC
trigger source.

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REGISTER 28-2: CCPxCAP: CAPTURE INPUT SELECTION REGISTER
U-0 U-0 U-0 U-0 U-0 R/W-0/x R/W-0/x R/W-0/x
— — — — — CTS<2:0>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Reset
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-3 Unimplemented: Read as ‘0’

bit 2-0 CTS<2:0>: Capture Trigger Input Selection bits

CTS CCP1.capture CCP2.capture

111 LC4_out
110 LC3_out
101 LC2_out
100 LC1_out
011 IOC_interrupt
010 C2OUT
001 C1OUT
000 CCP1PPS CCP2PPS

REGISTER 28-3: CCPRxL REGISTER: CCPx REGISTER LOW BYTE

R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x
CCPRx<7:0>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Reset
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-0 CCPxMODE = Capture mode

CCPRxL<7:0>: Capture value of TMR1L
CCPxMODE = Compare mode
CCPRxL<7:0>: LS Byte compared to TMR1L
CCPxMODE = PWM modes when CCPxFMT = 0:
CCPRxL<7:0>: Pulse-width Least Significant eight bits
CCPxMODE = PWM modes when CCPxFMT = 1:
CCPRxL<7:6>: Pulse-width Least Significant two bits
CCPRxL<5:0>: Not used.

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REGISTER 28-4: CCPRxH REGISTER: CCPx REGISTER HIGH BYTE
R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x
CCPRx<15:8>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Reset
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-0 CCPxMODE = Capture mode

CCPRxH<7:0>: Captured value of TMR1H
CCPxMODE = Compare mode
CCPRxH<7:0>: MS Byte compared to TMR1H
CCPxMODE = PWM modes when CCPxFMT = 0:
CCPRxH<7:2>: Not used
CCPRxH<1:0>: Pulse-width Most Significant two bits
CCPxMODE = PWM modes when CCPxFMT = 1:
CCPRxH<7:0>: Pulse-width Most Significant eight bits

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TABLE 28-5: SUMMARY OF REGISTERS ASSOCIATED WITH CCPx

Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
on Page
INTCON GIE PEIE — — — — — INTEDG 121
PIR4 — — — — — — TMR2IF TMR1IF 134
PIE4 — — — — — — TMR2IE TMR1IE 126
CCP1CON EN — OUT FMT MODE<3:0> 306
CCP1CAP — — — — — CTS<2:0> 308
CCPR1L Capture/Compare/PWM Register 1 (LSB) 308
CCPR1H Capture/Compare/PWM Register 1 (MSB) 309
CCP2CON EN — OUT FMT MODE<3:0> 306
CCP2CAP — — — — — CTS<2:0> 308
CCPR2L Capture/Compare/PWM Register 1 (LSB) 308
CCPR2H Capture/Compare/PWM Register 1 (MSB) 308
CCP1PPS — — CCP1PPS<5:0> 191
CCP2PPS — — CCP2PPS<5:0> 191
RxyPPS — — — RxyPPS<4:0> 192
ADACT — — — ADACT<4:0> 225
CLCxSELy — — — LCxDyS<4:0> 352
CWG1ISM — — — — IS<3:0> 341
Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by the CCP module.

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29.0 PULSE-WIDTH MODULATION FIGURE 29-1: PWM OUTPUT
(PWM)
Q1 Q2 Q3 Q4 Rev. 10-000023C
8/26/2015

The PWMx modules generate Pulse-Width Modulated

(PWM) signals of varying frequency and duty cycle.
FOSC
In addition to the CCP modules, the
PIC16(L)F15313/23 devices contain four 10-bit PWM
Pulse Width
modules (PWM3, PWM4, PWM5 and PWM6). The PWM
PWM modules reproduce the PWM capability of the TMRx = 0
(1)

CCP modules.
(1)
TMRx = PWMxDC

Note: The PWM3/4/5/6 modules are four (1)

TMRx = PRx
instances of the same PWM module
design. Throughout this section, the lower
Note 1: Timer dependent on PWMTMRS register settings.
case ‘x’ in register and bit names is a
generic reference to the PWM module
number (which should be substituted with
3, or 4, or, 5 or 6 during code
development). For example, the control
register is generically described in this
chapter as PWMxCON, but the actual
device registers are PWM3CON,
PWM4CON, PWM5CON and
PWM6CON. Similarly, the PWMxEN bit
represents the PWM3EN, PWM4EN,
PWM5EN and PWM6EN bits.
Pulse-Width Modulation (PWM) is a scheme that
provides power to a load by switching quickly between
fully on and fully off states. The PWM signal resembles
a square wave where the high portion of the signal is
considered the ‘on’ state (pulse width), and the low
portion of the signal is considered the ‘off’ state. The
term duty cycle describes the proportion of the ‘on’ time
to the ‘off’ time and is expressed in percentages, where
0% is fully off and 100% is fully on. A lower duty cycle
corresponds to less power applied and a higher duty
cycle corresponds to more power applied. The PWM
period is defined as the duration of one complete cycle
or the total amount of on and off time combined.
PWM resolution defines the maximum number of steps
that can be present in a single PWM period. A higher
resolution allows for more precise control of the pulse
width time and, in turn, the power that is applied to the
load.
Figure 29-1 shows a typical waveform of the PWM
signal.

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29.1 Standard PWM Mode
The standard PWM mode generates a Pulse-Width
Modulation (PWM) signal on the PWMx pin with up to
ten bits of resolution. The period, duty cycle, and
resolution are controlled by the following registers:
• TMR2 register
• PR2 register
• PWMxCON registers
• PWMxDCH registers
• PWMxDCL registers
Figure 29-2 shows a simplified block diagram of PWM
operation.
If PWMPOL = 0, the default state of the output is ‘0‘. If
PWMPOL = 1, the default state is ‘1’. If PWMEN = 0,
the output will be the default state.

Note: The corresponding TRIS bit must be

cleared to enable the PWM output on the
PWMx pin

FIGURE 29-2: SIMPLIFIED PWM BLOCK DIAGRAM

Rev. 10-000022B
9/24/2014

Duty cycle registers PWMxDCL<7:6>

PWMxDCH

PWMx_out
To Peripherals
10-bit Latch
(Not visible to user)

Comparator R Q
0
PPS PWMx
1
S Q
TMR2 Module
R PWMxPOL RxyPPS TRIS Control
TMR2 (1)

Comparator
T2_match

PR2

Note 1: 8-bit timer is concatenated with two bits generated by Fosc or two bits of the internal prescaler to
create 10-bit time-base.

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 PIC16(L)F15313/23
29.1.1 PWM CLOCK SELECTION 29.1.4 PWM DUTY CYCLE
The PIC16(L)F15313/23 allows each individual CCP The PWM duty cycle is specified by writing a 10-bit
and PWM module to select the timer source that con- value to the PWMxDC register. The PWMxDCH
trols the module. Each module has an independent contains the eight MSbs and the PWMxDCL<7:6> bits
selection. contain the two LSbs.
The PWMDC register is double-buffered and can be
29.1.2 USING THE TMR2 WITH THE PWM
updated at any time. This double buffering is essential
MODULE for glitch-free PWM operation. New values take effect
This device has a newer version of the TMR2 module when TMR2 = PR2. Note that PWMDC is left-justified.
that has many new modes, which allow for greater The 8-bit timer TMR2 register is concatenated with
customization and control of the PWM signals than on either the 2-bit internal system clock (FOSC), or two
older parts. Refer to Section 27.5 “Operation bits of the prescaler, to create the 10-bit time base. The
Examples” for examples of PWM signal generation system clock is used if the Timer2 prescaler is set to
using the different modes of Timer2. 1:1.
Equation 29-2 is used to calculate the PWM pulse
Note: PWM operation requires that the timer width.
used as the PWM time base has the Equation 29-3 is used to calculate the PWM duty cycle
FOSC/4 clock source selected. ratio.

29.1.3 PWM PERIOD EQUATION 29-2: PULSE WIDTH

Referring to Figure 29-1, the PWM output has a period
and a pulse width. The frequency of the PWM is the Pulse Widthൌሺܹܲ‫ܥܦݔܯ‬ሻ  ή ܱܶܵ‫ ܥ‬ή
inverse of the period (1/period). ሺܶ‫݁ݑ݈ܸ݈ܽ݁ܽܿݏ݁ݎܲʹܴܯ‬ሻ

The PWM period is specified by writing to the PR2

register. The PWM period can be calculated using the
EQUATION 29-3: DUTY CYCLE RATIO
following formula:
ሺܹܲ‫ܥܦݔܯ‬ሻ
‫ ݋݅ݐܴ݈ܽ݁ܿݕܥݕݐݑܦ‬ൌ  
EQUATION 29-1: PWM PERIOD Ͷሺܴܲʹ ൅ ͳሻ

ܹܲ‫ ݀݋݅ݎ݁ܲܯ‬ൌ  ሾሺܴܲʹሻ  ൅ ͳሿ  ή Ͷ ή ܱܶܵ‫ܥ‬

ή  ሺܶ‫݁ݑ݈ܸ݈ܽ݁ܽܿݏ݁ݎܲʹܴܯ‬ሻ 29.1.5 PWM RESOLUTION
The resolution determines the number of available duty
Note 1: TOSC = 1/FOSC cycles for a given period. For example, a 10-bit
resolution will result in 1024 discrete duty cycles,
When TMR2 is equal to PR2, the following three events whereas an 8-bit resolution will result in 256 discrete
occur on the next increment cycle: duty cycles.
• TMR2 is cleared The maximum PWM resolution is ten bits when PR2 is
• The PWMx pin is set (Exception: If the PWM duty 255. The resolution is a function of the PR2 register
cycle = 0%, the pin will not be set.) value as shown by Equation 29-4.
• The PWM pulse width is latched from PWMxDC.
EQUATION 29-4: PWM RESOLUTION
Note: If the pulse width value is greater than the log  4  PR2 + 1  
period the assigned PWM pin(s) will Resolution = ------------------------------------------ bits
log  2 
remain unchanged.

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 PIC16(L)F15313/23
29.1.6 OPERATION IN SLEEP MODE 29.1.8 EFFECTS OF RESET
In Sleep mode, the TMR2 register will not increment Any Reset will force all ports to Input mode and the
and the state of the module will not change. If the PWMx registers to their Reset states.
PWMx pin is driving a value, it will continue to drive that
value. When the device wakes up, TMR2 will continue
from its previous state.

29.1.7 CHANGES IN SYSTEM CLOCK

FREQUENCY
The PWM frequency is derived from the system clock
frequency. Any changes in the system clock frequency
will result in changes to the PWM frequency. See
Section 9.0 “Oscillator Module (with Fail-Safe
Clock Monitor)” for additional details.

TABLE 29-1: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 20 MHz)

PWM Frequency 1.22 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz
Timer Prescale 16 4 1 1 1 1
PR2 Value 0xFF 0xFF 0xFF 0x3F 0x1F 0x17
Maximum Resolution (bits) 10 10 10 8 7 6.6

TABLE 29-2: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 8 MHz)

PWM Frequency 1.22 kHz 4.90 kHz 19.61 kHz 76.92 kHz 153.85 kHz 200.0 kHz
Timer Prescale 16 4 1 1 1 1
PR2 Value 0xFF 0xFF 0xFF 0x3F 0x1F 0x17
Maximum Resolution (bits) 10 10 10 8 7 6.6

29.1.9 SETUP FOR PWM OPERATION 6. Wait until the TMR2IF is set.
The following steps should be taken when configuring 7. When the TMR2IF flag bit is set:
the module for using the PWMx outputs: • Clear the associated TRIS bit(s) to enable the out-
put driver.
1. Disable the PWMx pin output driver(s) by setting
• Route the signal to the desired pin by configuring
the associated TRIS bit(s).
the RxyPPS register.
2. Configure the PWM output polarity by • Enable the PWMx module by setting the
configuring the PWMxPOL bit of the PWMxCON PWMxEN bit of the PWMxCON register.
register.
In order to send a complete duty cycle and period on
3. Load the PR2 register with the PWM period value,
the first PWM output, the above steps must be followed
as determined by Equation 29-1.
in the order given. If it is not critical to start with a
4. Load the PWMxDCH register and bits <7:6> of complete PWM signal, then the PWM module can be
the PWMxDCL register with the PWM duty cycle enabled during Step 2 by setting the PWMxEN bit of
value, as determined by Equation 29-2. the PWMxCON register.
5. Configure and start Timer2:
• Clear the TMR2IF interrupt flag bit of the PIR4
register.
• Select the Timer2 prescale value by configuring
the CKPS<2:0> bits of the T2CON register.
• Enable Timer2 by setting the Timer2 ON bit of the
T2CON register.

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 PIC16(L)F15313/23
29.2 Register Definitions: PWM Control

REGISTER 29-1: PWMxCON: PWM CONTROL REGISTER

R/W-0/0 U-0 R-0 R/W-0/0 U-0 U-0 U-0 U-0
PWMxEN — PWMxOUT PWMxPOL — — — —
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 PWMxEN: PWM Module Enable bit

1 = PWM module is enabled
0 = PWM module is disabled
bit 6 Unimplemented: Read as ‘0’
bit 5 PWMxOUT: PWM Module Output Level when Bit is Read
bit 4 PWMxPOL: PWMx Output Polarity Select bit
1 = PWM output is active-low
0 = PWM output is active-high
bit 3-0 Unimplemented: Read as ‘0’

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 PIC16(L)F15313/23

REGISTER 29-2: PWMxDCH: PWM DUTY CYCLE HIGH BITS

R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
PWMxDC<9:2>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-0 PWMxDC<9:2>: PWM Duty Cycle Most Significant bits

These bits are the MSbs of the PWM duty cycle. The two LSbs are found in PWMxDCL Register.

REGISTER 29-3: PWMxDCL: PWM DUTY CYCLE LOW BITS

R/W-x/u R/W-x/u U-0 U-0 U-0 U-0 U-0 U-0
PWMxDC<1:0> — — — — — —
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 PWMxDC<1:0>: PWM Duty Cycle Least Significant bits

These bits are the LSbs of the PWM duty cycle. The MSbs are found in PWMxDCH Register.
bit 5-0 Unimplemented: Read as ‘0’

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 PIC16(L)F15313/23

TABLE 29-3: SUMMARY OF REGISTERS ASSOCIATED WITH PWMx

Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
on Page
T2CON ON CKPS<2:0> OUTPS<3:0> 295
T2TMR Holding Register for the 8-bit TMR2 Register 280*
T2PR TMR2 Period Register 280*
RxyPPS ― ― — RxyPPS<4:0> 192
CWG1ISM — — — — IS<3:0> 341
CLCxSELy — — LCxDyS<5:0> 352
TRISA — — TRISA5 TRISA4 — TRISA2 TRISA1 TRISA0 175
TRISC(1) — — TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 181
Legend: - = Unimplemented locations, read as ‘0’. Shaded cells are not used by the PWMx module.
* Page with Register information.
Note 1: Present on PIC16(L)F15323 only.

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 PIC16(L)F15313/23
30.0 COMPLEMENTARY WAVEFORM 30.1 Fundamental Operation
GENERATOR (CWG) MODULE The CWG module can operate in six different modes,
The Complementary Waveform Generator (CWG) as specified by MODE of the CWG1CON0 register:
produces half-bridge, full-bridge, and steering of PWM • Half-Bridge mode (Figure 30-9)
waveforms. It is backwards compatible with previous • Push-Pull mode (Figure 30-2)
ECCP functions. - Full-Bridge mode, Forward (Figure 30-3)
The CWG has the following features: - Full-Bridge mode, Reverse (Figure 30-3)
• Six operating modes: • Steering mode (Figure 30-10)
- Synchronous Steering mode • Synchronous Steering mode (Figure 30-11)
- Asynchronous Steering mode It may be necessary to guard against the possibility of
- Full-Bridge mode, Forward circuit faults or a feedback event arriving too late or not
- Full-Bridge mode, Reverse at all. In this case, the active drive must be terminated
- Half-Bridge mode before the Fault condition causes damage. Thus, all
output modes support auto-shutdown, which is covered
- Push-Pull mode
in 30.10 “Auto-Shutdown”.
• Output polarity control
• Output steering 30.1.1 HALF-BRIDGE MODE
- Synchronized to rising event In Half-Bridge mode, two output signals are generated
- Immediate effect as true and inverted versions of the input as illustrated
• Independent 6-bit rising and falling event dead- in Figure 30-9. A non-overlap (dead-band) time is
band timers inserted between the two outputs as described in
- Clocked dead band Section 30.5 “Dead-Band Control”.
- Independent rising and falling dead-band The unused outputs CWG1C and CWG1D drive similar
enables signals, with polarity independently controlled by the
• Auto-shutdown control with: POLC and POLD bits of the CWG1CON1 register,
respectively.
- Selectable shutdown sources
- Auto-restart enable
- Auto-shutdown pin override control
The CWG modules available are shown in Table 30-1.

TABLE 30-1: AVAILABLE CWG MODULES

Device CWG1
PIC16(L)F15313/23 ●

 2017 Microchip Technology Inc. Preliminary DS40001897A-page 318

 FIGURE 30-1: SIMPLIFIED CWG BLOCK DIAGRAM (HALF-BRIDGE MODE)
 2017 Microchip Technology Inc.

Rev. 10-000166B
8/29/2014

CWG_data

Rising Deadband Block

See clock CWG_dataA
CWGxISM signal_out
Register signal_in CWG_dataC
Preliminary

D Q

CWGxISM<3:0>
E Q
R
Falling Deadband Block
clock CWG_dataB
signal_out
signal_in CWG_dataD

PIC16(L)F15313/23
EN
SHUTDOWN

HFINTOSC 1
FOSC 0

CWGxCLK<0>
DS40001897A-page 319
 PIC16(L)F15313/23
30.1.2 PUSH-PULL MODE
In Push-Pull mode, two output signals are generated,
alternating copies of the input as illustrated in
Figure 30-2. This alternation creates the push-pull
effect required for driving some transformer-based
power supply designs.
The push-pull sequencer is reset whenever EN = 0 or
if an auto-shutdown event occurs. The sequencer is
clocked by the first input pulse, and the first output
appears on CWG1A.
The unused outputs CWG1C and CWG1D drive copies
of CWG1A and CWG1B, respectively, but with polarity
controlled by the POLC and POLD bits of the
CWG1CON1 register, respectively.

30.1.3 FULL-BRIDGE MODES

In Forward and Reverse Full-Bridge modes, three out-
puts drive static values while the fourth is modulated by
the input data signal. In Forward Full-Bridge mode,
CWG1A is driven to its active state, CWG1B and
CWG1C are driven to their inactive state, and CWG1D
is modulated by the input signal. In Reverse Full-Bridge
mode, CWG1C is driven to its active state, CWG1A and
CWG1D are driven to their inactive states, and CWG1B
is modulated by the input signal. In Full-Bridge mode,
the dead-band period is used when there is a switch
from forward to reverse or vice-versa. This dead-band
control is described in Section 30.5 “Dead-Band Con-
trol”, with additional details in Section 30.6 “Rising
Edge and Reverse Dead Band” and Section
30.7 “Falling Edge and Forward Dead Band”.
The mode selection may be toggled between forward
and reverse toggling the MODE<0> bit of the
CWG1CON0 while keeping MODE<2:1> static, without
disabling the CWG module.

 2017 Microchip Technology Inc. Preliminary DS40001897A-page 320

 FIGURE 30-2: SIMPLIFIED CWG BLOCK DIAGRAM (PUSH-PULL MODE)
 2017 Microchip Technology Inc.

Rev. 10-000167B
8/29/2014

CWG_data

See
CWGxISM
Register D Q

CWG_dataA
Q CWG_dataC
R

CWG_dataB
D Q
CWG_dataD
CWGxISM<3:0>
Preliminary

E Q
R

EN
SHUTDOWN

PIC16(L)F15313/23
DS40001897A-page 321
 FIGURE 30-3: SIMPLIFIED CWG BLOCK DIAGRAM (FORWARD AND REVERSE FULL-BRIDGE MODES)
 2017 Microchip Technology Inc.

Rev. 10-000165B
8/29/2014

MODE0 Reverse Deadband Block

clock
signal_out
See signal_in
CWGxISM
Register
CWG_dataA

D Q CWG_dataB

D Q
Q CWG_dataC
CWGxISM<3:0>
E Q CWG_dataD
Preliminary

R
clock
signal_out
signal_in
Forward Deadband Block
EN CWG_data
SHUTDOWN

PIC16(L)F15313/23
HFINTOSC 1
FOSC 0

CWGxCLK<0>
DS40001897A-page 322
 PIC16(L)F15313/23
30.1.4 STEERING MODES
In Steering modes, the data input can be steered to any
or all of the four CWG output pins. In Synchronous
Steering mode, changes to steering selection registers
take effect on the next rising input.
In Non-Synchronous mode, steering takes effect on the
next instruction cycle. Additional details are provided in
Section 30.9 “CWG Steering Mode”.

FIGURE 30-4: SIMPLIFIED CWG BLOCK DIAGRAM (OUTPUT STEERING MODES)

Rev. 10-000164B
8/26/2015

See
CWGxISM CWG_dataA
Register
CWG_dataB
CWG_data

CWG_dataC
CWG_dataD
D Q

CWGxISM <3:0>
E Q
R

EN
SHUTDOWN

30.2 Clock Source

The CWG module allows the following clock sources to
be selected:
• Fosc (system clock)
• HFINTOSC (16 MHz only)
The clock sources are selected using the CS bit of the
CWG1CLKCON register.

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30.3 Selectable Input Sources 30.4 Output Control
The CWG generates the output waveforms from the 30.4.1 POLARITY CONTROL
input sources in Table 30-2.
The polarity of each CWG output can be selected
independently. When the output polarity bit is set, the
TABLE 30-2: SELECTABLE INPUT
corresponding output is active-high. Clearing the
SOURCES
output polarity bit configures the corresponding output
Source Peripheral Signal Name as active-low. However, polarity does not affect the
override levels. Output polarity is selected with the
CWG input PPS pin CWG1IN PPS
POLx bits of the CWG1CON1. Auto-shutdown and
CCP1 CCP1_out steering options are unaffected by polarity.
CCP2 CCP2_out
PWM3 PWM3_out
PWM4 PWM4_out
PWM5 PWM5_out
PWM6 PWM6_out
NCO NCO1_out
Comparator C1 C1OUT_sync
Comparator C2 C2OUT_sync
CLC1 LC1_out
CLC2 LC2_out
CLC3 LC3_out
CLC4 LC4_out
The input sources are selected using the CWG1ISM
register.

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 PIC16(L)F15313/23
FIGURE 30-5: CWG OUTPUT BLOCK DIAGRAM

Rev. 10-000171B
9/24/2014

LSAC<1:0>

‘1’ 11 RxyPPS
TRIS Control
‘0’ 10
1
CWG_dataA High Z 01 PPS CWGxA
1 0
POLA 00
OVRA 0

STRA(1)

LSBD<1:0>

‘1’ 11 RxyPPS
TRIS Control
‘0’ 10
1
CWG_dataB High Z 01 PPS CWGxB
1 0
POLB 00
OVRB 0

STRB(1)

LSAC<1:0>

‘1’ 11 RxyPPS
TRIS Control
‘0’ 10
1
CWG_dataC High Z 01 PPS CWGxC
1 0
POLC 00
OVRC 0

STRC(1)

LSBD<1:0>

‘1’ 11 RxyPPS
TRIS Control
‘0’ 10
1
CWG_dataD High Z 01 PPS CWGxD
1 0
POLD 00
OVRD 0

STRD(1)

CWG_shutdown

Note 1: STRx is held to 1 in all modes other than Output Steering Mode.

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 PIC16(L)F15313/23
30.5 Dead-Band Control 30.6 Rising Edge and Reverse Dead
The dead-band control provides non-overlapping PWM
Band
signals to prevent shoot-through current in PWM CWG1DBR controls the rising edge dead-band time at
switches. Dead-band operation is employed for Half- the leading edge of CWG1A (Half-Bridge mode) or the
Bridge and Full-Bridge modes. The CWG contains two leading edge of CWG1B (Full-Bridge mode). The
6-bit dead-band counters. One is used for the rising CWG1DBR value is double-buffered. When EN = 0,
edge of the input source control in Half-Bridge mode or the CWG1DBR register is loaded immediately when
for reverse dead-band Full-Bridge mode. The other is CWG1DBR is written. When EN = 1, then software
used for the falling edge of the input source control in must set the LD bit of the CWG1CON0 register, and the
Half-Bridge mode or for forward dead band in Full- buffer will be loaded at the next falling edge of the CWG
Bridge mode. input signal. If the input source signal is not present for
Dead band is timed by counting CWG clock periods enough time for the count to be completed, no output
from zero up to the value in the rising or falling dead- will be seen on the respective output.
band counter registers. See CWG1DBR and
CWG1DBF registers, respectively. 30.7 Falling Edge and Forward Dead
Band
30.5.1 DEAD-BAND FUNCTIONALITY IN
HALF-BRIDGE MODE CWG1DBF controls the dead-band time at the leading
In Half-Bridge mode, the dead-band counters dictate edge of CWG1B (Half-Bridge mode) or the leading
the delay between the falling edge of the normal output edge of CWG1D (Full-Bridge mode). The CWG1DBF
and the rising edge of the inverted output. This can be value is double-buffered. When EN = 0, the
seen in Figure 30-9. CWG1DBF register is loaded immediately when
CWG1DBF is written. When EN = 1 then software
30.5.2 DEAD-BAND FUNCTIONALITY IN must set the LD bit of the CWG1CON0 register, and
FULL-BRIDGE MODE the buffer will be loaded at the next falling edge of the
In Full-Bridge mode, the dead-band counters are used CWG input signal. If the input source signal is not
when undergoing a direction change. The MODE<0> present for enough time for the count to be completed,
bit of the CWG1CON0 register can be set or cleared no output will be seen on the respective output.
while the CWG is running, allowing for changes from
Refer to Figure 30-6 and Figure 30-7 for examples.
Forward to Reverse mode. The CWG1A and CWG1C
signals will change upon the first rising input edge
following a direction change, but the modulated signals
(CWG1B or CWG1D, depending on the direction of the
change) will experience a delay dictated by the dead-
band counters. This is demonstrated in Figure 30-3.

 2017 Microchip Technology Inc. Preliminary DS40001897A-page 326

 FIGURE 30-6: DEAD-BAND OPERATION CWG1DBR = 0X01, CWG1DBF = 0X02
 2017 Microchip Technology Inc.

cwg_clock

Input Source

CWG1A

CWG1B
Preliminary

FIGURE 30-7: DEAD-BAND OPERATION, CWG1DBR = 0X03, CWG1DBF = 0X04, SOURCE SHORTER THAN DEAD BAND

PIC16(L)F15313/23
cwg_clock

Input Source

CWG1A

CWG1B

source shorter than dead band

DS40001897A-page 327
 PIC16(L)F15313/23
30.8 Dead-Band Uncertainty EQUATION 30-1: DEAD-BAND
UNCERTAINTY
When the rising and falling edges of the input source
are asynchronous to the CWG clock, it creates uncer-
tainty in the dead-band time delay. The maximum 1
TDEADBAND_UNCERTAINTY = -----------------------------
uncertainty is equal to one CWG clock period. Refer to Fcwg_clock
Equation 30-1 for more details.
Example:
FCWG_CLOCK = 16 MHz

Therefore:
1
TDEADBAND_UNCERTAINTY = -----------------------------
Fcwg_clock

1
= ------------------
16MHz

= 62.5ns

FIGURE 30-8: EXAMPLE OF PWM DIRECTION CHANGE

MODE0

CWG1A

CWG1B

CWG1C

CWG1D

No delay CWG1DBR No delay CWG1DBF

CWG1_data

Note 1: WGPOL{ABCD} = 0
2: The direction bit MODE<0> (Register 30-1) can be written any time during the PWM cycle, and takes effect at the
next rising CWG1_data.
3: When changing directions, CWG1A and CWG1C switch at rising CWG1_data; modulated CWG1B and CWG1D
are held inactive for the dead band duration shown; dead band affects only the first pulse after the direction change.

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 PIC16(L)F15313/23
FIGURE 30-9: CWG HALF-BRIDGE MODE OPERATION

CWG1_clock

CWG1A
CWG1C
Rising Event Dead Band Rising Event D
Falling Event Dead Band Falling Event Dead Band
CWG1B
CWG1D

CWG1_data
Note: CWG1_rising_src = CCP1_out, CWG1_falling_src = ~CCP1_out

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 PIC16(L)F15313/23
30.9 CWG Steering Mode 30.9.1 STEERING SYNCHRONIZATION
In Steering mode (MODE = 00x), the CWG allows any Changing the MODE bits allows for two modes of
combination of the CWG1x pins to be the modulated steering, synchronous and asynchronous.
signal. The same signal can be simultaneously avail- When MODE = 000, the steering event is asynchro-
able on multiple pins, or a fixed-value output can be nous and will happen at the end of the instruction that
presented. writes to STRx (that is, immediately). In this case, the
When the respective STRx bit of CWG1OCON0 is ‘0’, output signal at the output pin may be an incomplete
the corresponding pin is held at the level defined. When waveform. This can be useful for immediately removing
the respective STRx bit of CWG1OCON0 is ‘1’, the pin a signal from the pin.
is driven by the input data signal. The user can assign When MODE = 001, the steering update is synchro-
the input data signal to one, two, three, or all four output nous and occurs at the beginning of the next rising
pins. edge of the input data signal. In this case, steering the
The POLx bits of the CWG1CON1 register control the output on/off will always produce a complete waveform.
signal polarity only when STRx = 1. Figure 30-10 and Figure 30-11 illustrate the timing of
The CWG auto-shutdown operation also applies in asynchronous and synchronous steering, respectively.
Steering modes as described in Section 30.10 “Auto-
Shutdown”. An auto-shutdown event will only affect
pins that have STRx = 1.

FIGURE 30-10: EXAMPLE OF ASYNCHRONOUS STEERING EVENT (MODE<2:0> = 000)

Rising Event

CWG1_data
(Rising and Falling Source)

STR<D:A>

CWG1<D:A> OVR<D:A> OVR<D:A> Data

follows CWG1_data

FIGURE 30-11: EXAMPLE OF STEERING EVENT (MODE<2:0> = 001)

CWG1_data
(Rising and Falling Source)

STR<D:A>

CWG1<D:A> OVR<D:A> Data OVR<D:A> Data

follows CWG1_data

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 PIC16(L)F15313/23
30.10 Auto-Shutdown 30.11 Operation During Sleep
Auto-shutdown is a method to immediately override the The CWG module operates independently from the
CWG output levels with specific overrides that allow for system clock and will continue to run during Sleep,
safe shutdown of the circuit. The shutdown state can be provided that the clock and input sources selected
either cleared automatically or held until cleared by remain active.
software. The auto-shutdown circuit is illustrated in The HFINTOSC remains active during Sleep when all
Figure 30-12. the following conditions are met:
30.10.1 SHUTDOWN • CWG module is enabled
The shutdown state can be entered by either of the • Input source is active
following two methods: • HFINTOSC is selected as the clock source,
regardless of the system clock source selected.
• Software generated
• External Input In other words, if the HFINTOSC is simultaneously
selected as the system clock and the CWG clock
30.10.1.1 Software Generated Shutdown source, when the CWG is enabled and the input source
is active, then the CPU will go idle during Sleep, but the
Setting the SHUTDOWN bit of the CWG1AS0 register HFINTOSC will remain active and the CWG will con-
will force the CWG into the shutdown state. tinue to operate. This will have a direct effect on the
When the auto-restart is disabled, the shutdown state Sleep mode current.
will persist as long as the SHUTDOWN bit is set.
When auto-restart is enabled, the SHUTDOWN bit will
clear automatically and resume operation on the next
rising edge event.

30.10.2 EXTERNAL INPUT SOURCE

External shutdown inputs provide the fastest way to
safely suspend CWG operation in the event of a Fault
condition. When any of the selected shutdown inputs
goes active, the CWG outputs will immediately go to the
selected override levels without software delay. Several
input sources can be selected to cause a shutdown con-
dition. All input sources are active-low. The sources are:
• Comparator C1OUT_sync
• Comparator C2OUT_sync
• Timer2 – TMR2_postscaled
• CWG1IN input pin
Shutdown inputs are selected using the CWG1AS1
register (Register 30-6).
Note: Shutdown inputs are level sensitive, not
edge sensitive. The shutdown state can-
not be cleared, except by disabling auto-
shutdown, as long as the shutdown input
level persists.

 2017 Microchip Technology Inc. Preliminary DS40001897A-page 331

 FIGURE 30-12: CWG SHUTDOWN BLOCK DIAGRAM
 2017 Microchip Technology Inc.

Write ‘1’ to Rev. 10-000172F

3/14/2017
SHUTDOWN bit

PPS
INAS
CWGxINPPS
C1OUT_sync
C1AS

C2OUT_sync
C2AS

TMR2_postscaled SHUTDOWN S
S Q
TMR2AS
D Q CWG_shutdown
REN FREEZE
R
Write ‘0’ to
SHUTDOWN bit
CWG_data CK
Preliminary

PIC16(L)F15313/23
DS40001897A-page 332
 PIC16(L)F15313/23
30.12 Configuring the CWG 30.12.2 AUTO-SHUTDOWN RESTART
The following steps illustrate how to properly configure After an auto-shutdown event has occurred, there are
the CWG. two ways to resume operation:

1. Ensure that the TRIS control bits corresponding • Software controlled

to the desired CWG pins for your application are • Auto-restart
set so that the pins are configured as inputs. The restart method is selected with the REN bit of the
2. Clear the EN bit, if not already cleared. CWG1CON2 register. Waveforms of software con-
3. Set desired mode of operation with the MODE trolled and automatic restarts are shown in Figure 30-13
bits. and Figure 30-14.
4. Set desired dead-band times, if applicable to
mode, with the CWG1DBR and CWG1DBF 30.12.2.1 Software Controlled Restart
registers. When the REN bit of the CWG1AS0 register is cleared,
5. Setup the following controls in the CWG1AS0 the CWG must be restarted after an auto-shutdown
and CWG1AS1 registers. event by software. Clearing the shutdown state
requires all selected shutdown inputs to be low, other-
a. Select the desired shutdown source.
wise the SHUTDOWN bit will remain set. The overrides
b. Select both output overrides to the desired will remain in effect until the first rising edge event after
levels (this is necessary even if not using auto- the SHUTDOWN bit is cleared. The CWG will then
shutdown because start-up will be from a shut- resume operation.
down state).
c. Set which pins will be affected by auto-shut- 30.12.2.2 Auto-Restart
down with the CWG1AS1 register. When the REN bit of the CWG1CON2 register is set,
d. Set the SHUTDOWN bit and clear the REN bit. the CWG will restart from the auto-shutdown state
automatically. The SHUTDOWN bit will clear automati-
6. Select the desired input source using the cally when all shutdown sources go low. The overrides
CWG1ISM register. will remain in effect until the first rising edge event after
7. Configure the following controls. the SHUTDOWN bit is cleared. The CWG will then
a. Select desired clock source using the resume operation.
CWG1CLKCON register.
b. Select the desired output polarities using the
CWG1CON1 register.
c. Set the output enables for the desired outputs.
8. Set the EN bit.
9. Clear TRIS control bits corresponding to the
desired output pins to configure these pins as
outputs.
10. If auto-restart is to be used, set the REN bit and
the SHUTDOWN bit will be cleared automati-
cally. Otherwise, clear the SHUTDOWN bit to
start the CWG.

30.12.1 PIN OVERRIDE LEVELS

The levels driven to the output pins, while the shutdown
input is true, are controlled by the LSBD and LSAC bits
of the CWG1AS0 register. LSBD<1:0> controls the
CWG1B and D override levels and LSAC<1:0> controls
the CWG1A and C override levels. The control bit logic
level corresponds to the output logic drive level while in
the shutdown state. The polarity control does not affect
the override level.

 2017 Microchip Technology Inc. Preliminary DS40001897A-page 333

 FIGURE 30-13: SHUTDOWN FUNCTIONALITY, AUTO-RESTART DISABLED (REN = 0, LSAC = 01, LSBD = 01)
 2017 Microchip Technology Inc.

Shutdown Event Ceases REN Cleared by Software

CWG Input
Source

Shutdown Source

SHUTDOWN

CWG1A Tri-State (No Pulse)

CWG1C

CWG1B Tri-State (No Pulse)

CWG1D
No Shutdown
Shutdown Output Resumes
Preliminary

FIGURE 30-14: SHUTDOWN FUNCTIONALITY, AUTO-RESTART ENABLED (REN = 1, LSAC = 01, LSBD = 01)

Shutdown Event Ceases REN auto-cleared by hardware

PIC16(L)F15313/23
CWG Input
Source

Shutdown Source

SHUTDOWN

CWG1A Tri-State (No Pulse)

DS40001897A-page 334

CWG1C

CWG1B Tri-State (No Pulse)

CWG1D
No Shutdown
Shutdown Output Resumes
 PIC16(L)F15313/23
30.13 Register Definitions: CWG Control
Long bit name prefixes for the CWG peripherals are
shown in Section 1.1 “Register and Bit Naming
Conventions”.

REGISTER 30-1: CWG1CON0: CWG1 CONTROL REGISTER 0

R/W-0/0 R/W/HC-0/0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0
EN LD(1) — — — MODE<2:0>
bit 7 bit 0

Legend:
HC = Bit is cleared by hardware HS = Bit is set by hardware
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition

bit 7 EN: CWG1 Enable bit

1 = Module is enabled
0 = Module is disabled
bit 6 LD: CWG1 Load Buffer bits(1)
1 = Buffers to be loaded on the next rising/falling event
0 = Buffers not loaded
bit 5-3 Unimplemented: Read as ‘0’
bit 2-0 MODE<2:0>: CWG1 Mode bits
111 = Reserved
110 = Reserved
101 = CWG outputs operate in Push-Pull mode
100 = CWG outputs operate in Half-Bridge mode
011 = CWG outputs operate in Reverse Full-Bridge mode
010 = CWG outputs operate in Forward Full-Bridge mode
001 = CWG outputs operate in Synchronous Steering mode
000 = CWG outputs operate in Steering mode

Note 1: This bit can only be set after EN = 1 and cannot be set in the same instruction that EN is set.

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REGISTER 30-2: CWG1CON1: CWG1 CONTROL REGISTER 1

U-0 U-0 R-x U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— — IN — POLD POLC POLB POLA
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition

bit 7-6 Unimplemented: Read as ‘0’

bit 5 IN: CWG Input Value bit
bit 4 Unimplemented: Read as ‘0’
bit 3 POLD: CWG1D Output Polarity bit
1 = Signal output is inverted polarity
0 = Signal output is normal polarity
bit 2 POLC: CWG1C Output Polarity bit
1 = Signal output is inverted polarity
0 = Signal output is normal polarity
bit 1 POLB: CWG1B Output Polarity bit
1 = Signal output is inverted polarity
0 = Signal output is normal polarity
bit 0 POLA: CWG1A Output Polarity bit
1 = Signal output is inverted polarity
0 = Signal output is normal polarity

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 PIC16(L)F15313/23

REGISTER 30-3: CWG1DBR: CWG1 RISING DEAD-BAND COUNTER REGISTER

U-0 U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
— — DBR<5:0>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition

bit 7-6 Unimplemented: Read as ‘0’

bit 5-0 DBR<5:0>: Rising Event Dead-Band Value for Counter bits

REGISTER 30-4: CWG1DBF: CWG1 FALLING DEAD-BAND COUNTER REGISTER

U-0 U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
— — DBF<5:0>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition

bit 7-6 Unimplemented: Read as ‘0’

bit 5-0 DBF<5:0>: Falling Event Dead-Band Value for Counter bits

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 PIC16(L)F15313/23

REGISTER 30-5: CWG1AS0: CWG1 AUTO-SHUTDOWN CONTROL REGISTER 0

R/W/HS-0/0 R/W-0/0 R/W-0/0 R/W-1/1 R/W-0/0 R/W-1/1 U-0 U-0
(1, 2)
SHUTDOWN REN LSBD<1:0> LSAC<1:0> — —
bit 7 bit 0

Legend:
HC = Bit is cleared by hardware HS = Bit is set by hardware
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition

bit 7 SHUTDOWN: Auto-Shutdown Event Status bit(1, 2)

1 = An Auto-Shutdown state is in effect
0 = No Auto-shutdown event has occurred
bit 6 REN: Auto-Restart Enable bit
1 = Auto-restart enabled
0 = Auto-restart disabled
bit 5-4 LSBD<1:0>: CWG1B and CWG1D Auto-Shutdown State Control bits
11 =A logic ‘1’ is placed on CWG1B/D when an auto-shutdown event is present
10 =A logic ‘0’ is placed on CWG1B/D when an auto-shutdown event is present
01 =Pin is tri-stated on CWG1B/D when an auto-shutdown event is present
00 =The inactive state of the pin, including polarity, is placed on CWG1B/D after the required dead-
band interval
bit 3-2 LSAC<1:0>: CWG1A and CWG1C Auto-Shutdown State Control bits
11 =A logic ‘1’ is placed on CWG1A/C when an auto-shutdown event is present
10 =A logic ‘0’ is placed on CWG1A/C when an auto-shutdown event is present
01 =Pin is tri-stated on CWG1A/C when an auto-shutdown event is present
00 =The inactive state of the pin, including polarity, is placed on CWG1A/C after the required dead-
band interval
bit 1-0 Unimplemented: Read as ‘0’

Note 1: This bit may be written while EN = 0 (CWG1CON0 register) to place the outputs into the shutdown
configuration.
2: The outputs will remain in auto-shutdown state until the next rising edge of the input signal after this bit is
cleared.

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 PIC16(L)F15313/23

REGISTER 30-6: CWG1AS1: CWG1 AUTO-SHUTDOWN CONTROL REGISTER 1

U-1 U-1 U-1 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— — — AS4E AS3E AS2E AS1E AS0E
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition

bit 7-5 Unimplemented: Read as ‘0’

bit 4 AS4E: CLC2 Output bit
1 = LC2_out shut-down is enabled
0 = LC2_out shut-down is disabled
bit 3 AS3E: Comparator C2 Output bit
1 = C2 output shut-down is enabled
0 = C2 output shut-down is disabled
bit 2 AS2E: Comparator C1 Output bit
1 = C1 output shut-down is enabled
0 = C1 output shut-down is disabled
bit 2 AS1E: TMR2 Postscale Output bit
1 = TMR2 Postscale shut-down is enabled
0 = TMR2 Postscale shut-down is disabled
bit 0 AS0E: CWG1 Input Pin bit
1 = Input pin selected by CWG1PPS shut-down is enabled
0 = Input pin selected by CWG1PPS shut-down is disabled

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 PIC16(L)F15313/23

REGISTER 30-7: CWG1STR: CWG1 STEERING CONTROL REGISTER(1)

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
OVRD OVRC OVRB OVRA STRD(2) STRC(2) STRB(2) STRA(2)
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition

bit 7 OVRD: Steering Data D bit

bit 6 OVRC: Steering Data C bit
bit 5 OVRB: Steering Data B bit
bit 4 OVRA: Steering Data A bit
bit 3 STRD: Steering Enable D bit(2)
1 = CWG1D output has the CWG1_data waveform with polarity control from POLD bit
0 = CWG1D output is assigned the value of OVRD bit
bit 2 STRC: Steering Enable C bit(2)
1 = CWG1C output has the CWG1_data waveform with polarity control from POLC bit
0 = CWG1C output is assigned the value of OVRC bit
bit 1 STRB: Steering Enable B bit(2)
1 = CWG1B output has the CWG1_data waveform with polarity control from POLB bit
0 = CWG1B output is assigned the value of OVRB bit
bit 0 STRA: Steering Enable A bit(2)
1 = CWG1A output has the CWG1_data waveform with polarity control from POLA bit
0 = CWG1A output is assigned the value of OVRA bit

Note 1: The bits in this register apply only when MODE<2:0> = 00x.
2: This bit is effectively double-buffered when MODE<2:0> = 001.

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 PIC16(L)F15313/23

REGISTER 30-8: CWG1CLK: CWG1 CLOCK SELECTION REGISTER

U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0/0
— — — — — — — CS
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition

bit 7-1 Unimplemented: Read as ‘0’

bit 0 CS: CWG1 Clock Selection bit
1 = HFINTOSC 16 MHz is selected
0 = FOSC is selected

REGISTER 30-9: CWG1ISM: CWG1 INPUT SELECTION REGISTER

U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— — — — IS<3:0>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition

bit 7-4 Unimplemented: Read as ‘0’

bit 3-0 IS<3:0>: CWG1 Input Selection bits
1111 = Reserved. No channel connected.
1110 = Reserved. No channel connected.
1101 = LC4_out
1100 = LC3_out
1011 = LC2_out
1010 = LC1_out
1001 = Comparator C2 out(1)
1000 = Comparator C1 out
0111 = NCO1 output
0110 = PWM6_out
0101 = PWM5_out
0100 = PWM4_out
0011 = PWM3_out
0010 = CCP2_out
0001 = CCP1_out
0000 = CWG11CLK

Note 1: Present on PIC16(L)F15323 only.

 2017 Microchip Technology Inc. Preliminary DS40001897A-page 341

 PIC16(L)F15313/23
TABLE 30-3: SUMMARY OF REGISTERS ASSOCIATED WITH CWG
Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
on Page

CWG1CLKCON — — — — — — — CS 341
CWG1ISM — — — — IS<3:0> 341
CWG1DBR — — DBR<5:0> 337
CWG1DBF — — DBF<5:0> 337
CWG1CON0 EN LD — — — MODE<2:0> 340
CWG1CON1 — — IN — POLD POLC POLB POLA 336
CWG1AS0 SHUTDOWN REN LSBD<1:0> LSAC<1:0> — — 338
CWG1AS1 — — — AS4E AS3E AS2E AS1E AS0E 339
CWG1STR OVRD OVRC OVRB OVRA STRD STRC STRB STRA 340
Legend: – = unimplemented locations read as ‘0’. Shaded cells are not used by CWG.

 2017 Microchip Technology Inc. Preliminary DS40001897A-page 342

 PIC16(L)F15313/23
31.0 CONFIGURABLE LOGIC CELL Refer to Figure 31-1 for a simplified diagram showing
signal flow through the CLCx.
(CLC)
Possible configurations include:
The Configurable Logic Cell (CLCx) module provides
programmable logic that operates outside the speed • Combinatorial Logic
limitations of software execution. The logic cell selects - AND
from 40 input signals and, through the use of - NAND
configurable gates, reduces the inputs to four logic - AND-OR
lines that drive one of eight selectable single-output - AND-OR-INVERT
logic functions.
- OR-XOR
Input sources are a combination of the following: - OR-XNOR
• I/O pins • Latches
• Internal clocks - S-R
• Peripherals - Clocked D with Set and Reset
• Register bits - Transparent D with Set and Reset
The output can be directed internally to peripherals and - Clocked J-K with Reset
to an output pin.
The CLC modules available are shown in Table 31-1.

TABLE 31-1: AVAILABLE CLC MODULES

Device CLC1 CLC2 CLC3 CLC4
PIC16(L)F15313/23 ● ● ● ●

Note: The CLC1, CLC2, CLC3 and CLC4 are

four separate module instances of the
same CLC module design. Throughout
this section, the lower case ‘x’ in register
and bit names is a generic reference to
the CLC number (which should be substi-
tuted with 1, 2, 3, or 4 during code devel-
opment). For example, the control register
is generically described in this chapter as
CLCxCON, but the actual device registers
are CLC1CON, CLC2CON, CLC3CON
and CLC4CON. Similarly, the LCxEN bit
represents the LC1EN, LC2EN, LC3EN
and LC4EN bits.

 2017 Microchip Technology Inc. Preliminary DS40001897A-page 343

 PIC16(L)F15313/23
FIGURE 31-1: CLCx SIMPLIFIED BLOCK DIAGRAM

Rev. 10-000025H
11/9/2016

OUT
D Q
CLCxOUT

Q1
LCx_in[0]
LCx_in[1] CLCx_out
to Peripherals
LCx_in[2]
Input Data Selection Gates(1)

. lcxg1
EN
CLCxPPS

. lcxg2

lcxg3
Logic
Function
(2)
lcxq
PPS CLCx

. lcxg4
POL TRIS

LCx_in[n-2] MODE<2:0> Interrupt

LCx_in[n-1] det
LCx_in[n]
INTP
set bit
INTN CLCxIF
Interrupt
det

Note 1: See Figure 31-2: Input Data Selection and Gating.

2: See Figure 31-3: Programmable Logic Functions.

 2017 Microchip Technology Inc. Preliminary DS40001897A-page 344

 PIC16(L)F15313/23
31.1 CLCx Setup TABLE 31-2: CLCx DATA INPUT SELECTION
Programming the CLCx module is performed by LCxDyS<4:0>
CLCx Input Source
Value
configuring the four stages in the logic signal flow. The
four stages are: 101000 to 111111 [40+] Reserved
100111 [39] CWG1B output
• Data selection
100110 [38] CWG1A output
• Data gating
100101 [37] Reserved
• Logic function selection 100100 [36] Reserved
• Output polarity 100011 [35] MSSP1 SCK output
Each stage is setup at run time by writing to the corre- 100010 [34] MSSP1 SDO output
sponding CLCx Special Function Registers. This has 100001 [33] Reserved
the added advantage of permitting logic reconfiguration 100000 [32] Reserved
on-the-fly during program execution. 011111 [31] EUSART1 (TX/CK) output
011110 [30] EUSART1 (DT) output
31.1.1 DATA SELECTION
011101 [29] CLC4 output
There are 40 signals available as inputs to the 011100 [28] CLC3 output
configurable logic. Four 40-input multiplexers are used 011011 [27] CLC2 output
to select the inputs to pass on to the next stage.
011010 [26] CLC1 output
Data selection is through four multiplexers as indicated 011001 [25] IOCIF
on the left side of Figure 31-2. Data inputs in the figure 011000 [24] ZCD output
are identified by a generic numbered input name. 010111 [23] C2OUT(1)
Table 31-2 correlates the generic input name to the 010110 [22] C1OUT
actual signal for each CLC module. The column labeled 010101 [21] NCO1 output
‘LCxDyS<4:0> Value’ indicates the MUX selection code 010100 [20] PWM6 output
for the selected data input. LCxDyS is an abbreviation to 010011 [19] PWM5 output
identify specific multiplexers: LCxD1S<4:0> through
010010 [18] PWM4 output
LCxD4S<4:0>.
010001 [17] PWM3 output
Data inputs are selected with CLCxSEL0 through 010000 [16] CCP2 output
CLCxSEL3 registers (Register 31-3 through 001111 [15] CCP1 output
Register 31-6).
001110 [14] Timer2 overflow
001101 [13] Timer1 overflow
001100 [12] Timer0 overflow
001011 [11] CLKR
001010 [10] ADCRC
001001 [9] Reserved
001000 [8] MFINTOSC (32 kHz)
000111 [7] MFINTOSC (500 kHz)
000110 [6] LFINTOSC
000101 [5] HFINTOSC
000100 [4] FOSC
000011 [3] CLCIN3PPS
000010 [2] CLCIN2PPS
000001 [1] CLCIN1PPS
Note 1: Present on PIC16(L)F15323 only.

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 PIC16(L)F15313/23
31.1.2 DATA GATING Data gating is indicated in the right side of Figure 31-2.
Only one gate is shown in detail. The remaining three
Outputs from the input multiplexers are directed to the
gates are configured identically with the exception that
desired logic function input through the data gating
the data enables correspond to the enables for that
stage. Each data gate can direct any combination of the
gate.
four selected inputs.
Note: Data gating is undefined at power-up. 31.1.3 LOGIC FUNCTION
The gate stage is more than just signal direction. The There are eight available logic functions including:
gate can be configured to direct each input signal as • AND-OR
inverted or non-inverted data. The output of each gate • OR-XOR
can be inverted before going on to the logic function
• AND
stage.
• S-R Latch
The gating is in essence a 1-to-4 input
• D Flip-Flop with Set and Reset
AND/NAND/OR/NOR gate. When every input is
inverted and the output is inverted, the gate is an OR of • D Flip-Flop with Reset
all enabled data inputs. When the inputs and output are • J-K Flip-Flop with Reset
not inverted, the gate is an AND or all enabled inputs. • Transparent Latch with Set and Reset
Table 31-3 summarizes the basic logic that can be Logic functions are shown in Figure 31-2. Each logic
obtained in gate 1 by using the gate logic select bits. function has four inputs and one output. The four inputs
The table shows the logic of four input variables, but are the four data gate outputs of the previous stage.
The output is fed to the inversion stage and from there
each gate can be configured to use less than four. If
to other peripherals, an output pin, and back to the
no inputs are selected, the output will be zero or one,
CLCx itself.
depending on the gate output polarity bit.
31.1.4 OUTPUT POLARITY
TABLE 31-3: DATA GATING LOGIC
The last stage in the Configurable Logic Cell is the
CLCxGLSy LCxGyPOL Gate Logic output polarity. Setting the LCxPOL bit of the CLCxPOL
0x55 1 4-input AND register inverts the output signal from the logic stage.
Changing the polarity while the interrupts are enabled
0x55 0 4-input NAND will cause an interrupt for the resulting output transition.
0xAA 1 4-input NOR
0xAA 0 4-input OR
0x00 0 Logic 0
0x00 1 Logic 1
It is possible (but not recommended) to select both the
true and negated values of an input. When this is done,
the gate output is zero, regardless of the other inputs,
but may emit logic glitches (transient-induced pulses).
If the output of the channel must be zero or one, the
recommended method is to set all gate bits to zero and
use the gate polarity bit to set the desired level.
Data gating is configured with the logic gate select
registers as follows:
• Gate 1: CLCxGLS0 (Register 31-7)
• Gate 2: CLCxGLS1 (Register 31-8)
• Gate 3: CLCxGLS2 (Register 31-9)
• Gate 4: CLCxGLS3 (Register 31-10)
Register number suffixes are different than the gate
numbers because other variations of this module have
multiple gate selections in the same register.

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 PIC16(L)F15313/23
31.2 CLCx Interrupts 31.6 CLCx Setup Steps
An interrupt will be generated upon a change in the The following steps should be followed when setting up
output value of the CLCx when the appropriate interrupt the CLCx:
enables are set. A rising edge detector and a falling • Disable CLCx by clearing the LCxEN bit.
edge detector are present in each CLC for this purpose.
• Select desired inputs using CLCxSEL0 through
The CLCxIF bit of the associated PIR5 register will be CLCxSEL3 registers (See Table 31-2).
set when either edge detector is triggered and its asso- • Clear any associated ANSEL bits.
ciated enable bit is set. The LCxINTP enables rising
• Enable the chosen inputs through the four gates
edge interrupts and the LCxINTN bit enables falling
using CLCxGLS0, CLCxGLS1, CLCxGLS2, and
edge interrupts. Both are located in the CLCxCON
CLCxGLS3 registers.
register.
• Select the gate output polarities with the
To fully enable the interrupt, set the following bits: LCxGyPOL bits of the CLCxPOL register.
• CLCxIE bit of the PIE5 register • Select the desired logic function with the
• LCxINTP bit of the CLCxCON register (for a rising LCxMODE<2:0> bits of the CLCxCON register.
edge detection) • Select the desired polarity of the logic output with
• LCxINTN bit of the CLCxCON register (for a the LCxPOL bit of the CLCxPOL register. (This
falling edge detection) step may be combined with the previous gate out-
• PEIE and GIE bits of the INTCON register put polarity step).
• If driving a device pin, set the desired pin PPS
The CLCxIF bit of the PIR5 register, must be cleared in
control register and also clear the TRIS bit
software as part of the interrupt service. If another edge
corresponding to that output.
is detected while this flag is being cleared, the flag will
still be set at the end of the sequence. • If interrupts are desired, configure the following
bits:
31.3 Output Mirror Copies - Set the LCxINTP bit in the CLCxCON register
for rising event.
Mirror copies of all LCxCON output bits are contained - Set the LCxINTN bit in the CLCxCON
in the CLCxDATA register. Reading this register reads register for falling event.
the outputs of all CLCs simultaneously. This prevents
- Set the CLCxIE bit of the PIE5 register.
any reading skew introduced by testing or reading the
LCxOUT bits in the individual CLCxCON registers. - Set the GIE and PEIE bits of the INTCON
register.
31.4 Effects of a Reset • Enable the CLCx by setting the LCxEN bit of the
CLCxCON register.
The CLCxCON register is cleared to zero as the result
of a Reset. All other selection and gating values remain
unchanged.

31.5 Operation During Sleep

The CLC module operates independently from the
system clock and will continue to run during Sleep,
provided that the input sources selected remain active.
The HFINTOSC remains active during Sleep when the
CLC module is enabled and the HFINTOSC is
selected as an input source, regardless of the system
clock source selected.
In other words, if the HFINTOSC is simultaneously
selected as the system clock and as a CLC input
source, when the CLC is enabled, the CPU will go idle
during Sleep, but the CLC will continue to operate and
the HFINTOSC will remain active.
This will have a direct effect on the Sleep mode current.

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FIGURE 31-2: INPUT DATA SELECTION AND GATING

Data Selection
LCx_in
Data GATE 1

lcxd1T LCxD1G1T

lcxd1N LCxD1G1N
LCx_in
LCxD2G1T
LCxD1S<5:0>

LCxD2G1N lcxg1
LCx_in
LCxD3G1T
LCxG1POL
lcxd2T
LCxD3G1N
lcxd2N
LCxD4G1T
LCx_in

LCxD2S<5:0> LCxD4G1N

LCx_in
Data GATE 2
lcxg2
lcxd3T
(Same as Data GATE 1)
lcxd3N
Data GATE 3
LCx_in
lcxg3
LCxD3S<5:0>
(Same as Data GATE 1)

LCx_in Data GATE 4

lcxg4

lcxd4T (Same as Data GATE 1)

lcxd4N

LCx_in

LCxD4S<5:0>

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FIGURE 31-3: PROGRAMMABLE LOGIC FUNCTIONS
Rev. 10-000122A
5/18/2016

AND-OR OR-XOR

lcxg1 lcxg1

lcxg2 lcxg2
lcxq lcxq
lcxg3 lcxg3

lcxg4 lcxg4

LCxMODE<2:0> = 000 LCxMODE<2:0> = 001

4-input AND S-R Latch

lcxg1 lcxg1
S Q lcxq
lcxg2
lcxg2
lcxq
lcxg3
lcxg3
R
lcxg4 lcxg4

LCxMODE<2:0> = 010 LCxMODE<2:0> = 011

1-Input D Flip-Flop with S and R 2-Input D Flip-Flop with R
lcxg4
S
lcxg4
lcxg2 D Q lcxq D Q lcxq
lcxg2

lcxg1 R
lcxg1 R
lcxg3 lcxg3

LCxMODE<2:0> = 100 LCxMODE<2:0> = 101

J-K Flip-Flop with R 1-Input Transparent Latch with S and R
lcxg4
lcxg2 J Q lcxq S
lcxg2 D Q lcxq
lcxg1
lcxg4 K
R
lcxg3 LE
R
lcxg3
lcxg1

LCxMODE<2:0> = 110 LCxMODE<2:0> = 111

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31.7 Register Definitions: CLC Control

REGISTER 31-1: CLCxCON: CONFIGURABLE LOGIC CELL CONTROL REGISTER

R/W-0/0 U-0 R-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
LCxEN — LCxOUT LCxINTP LCxINTN LCxMODE<2:0>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 LCxEN: Configurable Logic Cell Enable bit

1 = Configurable logic cell is enabled and mixing input signals
0 = Configurable logic cell is disabled and has logic zero output
bit 6 Unimplemented: Read as ‘0’
bit 5 LCxOUT: Configurable Logic Cell Data Output bit
Read-only: logic cell output data, after LCPOL; sampled from CLCxOUT
bit 4 LCxINTP: Configurable Logic Cell Positive Edge Going Interrupt Enable bit
1 = CLCxIF will be set when a rising edge occurs on CLCxOUT
0 = CLCxIF will not be set
bit 3 LCxINTN: Configurable Logic Cell Negative Edge Going Interrupt Enable bit
1 = CLCxIF will be set when a falling edge occurs on CLCxOUT
0 = CLCxIF will not be set
bit 2-0 LCxMODE<2:0>: Configurable Logic Cell Functional Mode bits
111 = Cell is 1-input transparent latch with S and R
110 = Cell is J-K flip-flop with R
101 = Cell is 2-input D flip-flop with R
100 = Cell is 1-input D flip-flop with S and R
011 = Cell is S-R latch
010 = Cell is 4-input AND
001 = Cell is OR-XOR
000 = Cell is AND-OR

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REGISTER 31-2: CLCxPOL: SIGNAL POLARITY CONTROL REGISTER

R/W-0/0 U-0 U-0 U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u
LCxPOL — — — LCxG4POL LCxG3POL LCxG2POL LCxG1POL
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 LCxPOL: CLCxOUT Output Polarity Control bit

1 = The output of the logic cell is inverted
0 = The output of the logic cell is not inverted
bit 6-4 Unimplemented: Read as ‘0’
bit 3 LCxG4POL: Gate 3 Output Polarity Control bit
1 = The output of gate 3 is inverted when applied to the logic cell
0 = The output of gate 3 is not inverted
bit 2 LCxG3POL: Gate 2 Output Polarity Control bit
1 = The output of gate 2 is inverted when applied to the logic cell
0 = The output of gate 2 is not inverted
bit 1 LCxG2POL: Gate 1 Output Polarity Control bit
1 = The output of gate 1 is inverted when applied to the logic cell
0 = The output of gate 1 is not inverted
bit 0 LCxG1POL: Gate 0 Output Polarity Control bit
1 = The output of gate 0 is inverted when applied to the logic cell
0 = The output of gate 0 is not inverted

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REGISTER 31-3: CLCxSEL0: GENERIC CLCx DATA 0 SELECT REGISTER

U-0 U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
— — LCxD1S<5:0>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 Unimplemented: Read as ‘0’

bit 5-0 LCxD1S<5:0>: CLCx Data1 Input Selection bits
See Table 31-2.

REGISTER 31-4: CLCxSEL1: GENERIC CLCx DATA 1 SELECT REGISTER

U-0 U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
— — LCxD2S<5:0>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 Unimplemented: Read as ‘0’

bit 5-0 LCxD2S<5:0>: CLCx Data 2 Input Selection bits
See Table 31-2.

REGISTER 31-5: CLCxSEL2: GENERIC CLCx DATA 2 SELECT REGISTER

U-0 U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
— — LCxD3S<5:0>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 Unimplemented: Read as ‘0’

bit 5-0 LCxD3S<5:0>: CLCx Data 3 Input Selection bits
See Table 31-2.

REGISTER 31-6: CLCxSEL3: GENERIC CLCx DATA 3 SELECT REGISTER

U-0 U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
— — LCxD4S<5:0>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 Unimplemented: Read as ‘0’

bit 5-0 LCxD4S<5:0>: CLCx Data 4 Input Selection bits
See Table 31-2.

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REGISTER 31-7: CLCxGLS0: GATE 0 LOGIC SELECT REGISTER

R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
LCxG1D4T LCxG1D4N LCxG1D3T LCxG1D3N LCxG1D2T LCxG1D2N LCxG1D1T LCxG1D1N
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 LCxG1D4T: Gate 0 Data 4 True (non-inverted) bit

1 = CLCIN3 (true) is gated into CLCx Gate 0
0 = CLCIN3 (true) is not gated into CLCx Gate 0
bit 6 LCxG1D4N: Gate 0 Data 4 Negated (inverted) bit
1 = CLCIN3 (inverted) is gated into CLCx Gate 0
0 = CLCIN3 (inverted) is not gated into CLCx Gate 0
bit 5 LCxG1D3T: Gate 0 Data 3 True (non-inverted) bit
1 = CLCIN2 (true) is gated into CLCx Gate 0
0 = CLCIN2 (true) is not gated into CLCx Gate 0
bit 4 LCxG1D3N: Gate 0 Data 3 Negated (inverted) bit
1 = CLCIN2 (inverted) is gated into CLCx Gate 0
0 = CLCIN2 (inverted) is not gated into CLCx Gate 0
bit 3 LCxG1D2T: Gate 0 Data 2 True (non-inverted) bit
1 = CLCIN1 (true) is gated into CLCx Gate 0
0 = CLCIN1 (true) is not gated into l CLCx Gate 0
bit 2 LCxG1D2N: Gate 0 Data 2 Negated (inverted) bit
1 = CLCIN1 (inverted) is gated into CLCx Gate 0
0 = CLCIN1 (inverted) is not gated into CLCx Gate 0
bit 1 LCxG1D1T: Gate 0 Data 1 True (non-inverted) bit
1 = CLCIN0 (true) is gated into CLCx Gate 0
0 = CLCIN0 (true) is not gated into CLCx Gate 0
bit 0 LCxG1D1N: Gate 0 Data 1 Negated (inverted) bit
1 = CLCIN0 (inverted) is gated into CLCx Gate 0
0 = CLCIN0 (inverted) is not gated into CLCx Gate 0

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REGISTER 31-8: CLCxGLS1: GATE 1 LOGIC SELECT REGISTER

R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
LCxG2D4T LCxG2D4N LCxG2D3T LCxG2D3N LCxG2D2T LCxG2D2N LCxG2D1T LCxG2D1N
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 LCxG2D4T: Gate 1 Data 4 True (non-inverted) bit

1 = CLCIN3 (true) is gated into CLCx Gate 1
0 = CLCIN3 (true) is not gated into CLCx Gate 1
bit 6 LCxG2D4N: Gate 1 Data 4 Negated (inverted) bit
1 = CLCIN3 (inverted) is gated into CLCx Gate 1
0 = CLCIN3 (inverted) is not gated into CLCx Gate 1
bit 5 LCxG2D3T: Gate 1 Data 3 True (non-inverted) bit
1 = CLCIN2 (true) is gated into CLCx Gate 1
0 = CLCIN2 (true) is not gated into CLCx Gate 1
bit 4 LCxG2D3N: Gate 1 Data 3 Negated (inverted) bit
1 = CLCIN2 (inverted) is gated into CLCx Gate 1
0 = CLCIN2 (inverted) is not gated into CLCx Gate 1
bit 3 LCxG2D2T: Gate 1 Data 2 True (non-inverted) bit
1 = CLCIN1 (true) is gated into CLCx Gate 1
0 = CLCIN1 (true) is not gated into CLCx Gate 1
bit 2 LCxG2D2N: Gate 1 Data 2 Negated (inverted) bit
1 = CLCIN1 (inverted) is gated into CLCx Gate 1
0 = CLCIN1 (inverted) is not gated into CLCx Gate 1
bit 1 LCxG2D1T: Gate 1 Data 1 True (non-inverted) bit
1 = CLCIN0 (true) is gated into CLCx Gate 1
0 = CLCIN0 (true) is not gated into CLCx Gate1
bit 0 LCxG2D1N: Gate 1 Data 1 Negated (inverted) bit
1 = CLCIN0 (inverted) is gated into CLCx Gate 1
0 = CLCIN0 (inverted) is not gated into CLCx Gate 1

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REGISTER 31-9: CLCxGLS2: GATE 2 LOGIC SELECT REGISTER

R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
LCxG3D4T LCxG3D4N LCxG3D3T LCxG3D3N LCxG3D2T LCxG3D2N LCxG3D1T LCxG3D1N
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 LCxG3D4T: Gate 2 Data 4 True (non-inverted) bit

1 = CLCIN3 (true) is gated into CLCx Gate 2
0 = CLCIN3 (true) is not gated into CLCx Gate 2
bit 6 LCxG3D4N: Gate 2 Data 4 Negated (inverted) bit
1 = CLCIN3 (inverted) is gated into CLCx Gate 2
0 = CLCIN3 (inverted) is not gated into CLCx Gate 2
bit 5 LCxG3D3T: Gate 2 Data 3 True (non-inverted) bit
1 = CLCIN2 (true) is gated into CLCx Gate 2
0 = CLCIN2 (true) is not gated into CLCx Gate 2
bit 4 LCxG3D3N: Gate 2 Data 3 Negated (inverted) bit
1 = CLCIN2 (inverted) is gated into CLCx Gate 2
0 = CLCIN2 (inverted) is not gated into CLCx Gate 2
bit 3 LCxG3D2T: Gate 2 Data 2 True (non-inverted) bit
1 = CLCIN1 (true) is gated into CLCx Gate 2
0 = CLCIN1 (true) is not gated into CLCx Gate 2
bit 2 LCxG3D2N: Gate 2 Data 2 Negated (inverted) bit
1 = CLCIN1 (inverted) is gated into CLCx Gate 2
0 = CLCIN1 (inverted) is not gated into CLCx Gate 2
bit 1 LCxG3D1T: Gate 2 Data 1 True (non-inverted) bit
1 = CLCIN0 (true) is gated into CLCx Gate 2
0 = CLCIN0 (true) is not gated into CLCx Gate 2
bit 0 LCxG3D1N: Gate 2 Data 1 Negated (inverted) bit
1 = CLCIN0 (inverted) is gated into CLCx Gate 2
0 = CLCIN0 (inverted) is not gated into CLCx Gate 2

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REGISTER 31-10: CLCxGLS3: GATE 3 LOGIC SELECT REGISTER

R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
LCxG4D4T LCxG4D4N LCxG4D3T LCxG4D3N LCxG4D2T LCxG4D2N LCxG4D1T LCxG4D1N
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 LCxG4D4T: Gate 3 Data 4 True (non-inverted) bit

1 = CLCIN3 (true) is gated into CLCx Gate 3
0 = CLCIN3 (true) is not gated into CLCx Gate 3
bit 6 LCxG4D4N: Gate 3 Data 4 Negated (inverted) bit
1 = CLCIN3 (inverted) is gated into CLCx Gate 3
0 = CLCIN3 (inverted) is not gated into CLCx Gate 3
bit 5 LCxG4D3T: Gate 3 Data 3 True (non-inverted) bit
1 = CLCIN2 (true) is gated into CLCx Gate 3
0 = CLCIN2 (true) is not gated into CLCx Gate 3
bit 4 LCxG4D3N: Gate 3 Data 3 Negated (inverted) bit
1 = CLCIN2 (inverted) is gated into CLCx Gate 3
0 = CLCIN2 (inverted) is not gated into CLCx Gate 3
bit 3 LCxG4D2T: Gate 3 Data 2 True (non-inverted) bit
1 = CLCIN1 (true) is gated into CLCx Gate 3
0 = CLCIN1 (true) is not gated into CLCx Gate 3
bit 2 LCxG4D2N: Gate 3 Data 2 Negated (inverted) bit
1 = CLCIN1 (inverted) is gated into CLCx Gate 3
0 = CLCIN1 (inverted) is not gated into CLCx Gate 3
bit 1 LCxG4D1T: Gate 4 Data 1 True (non-inverted) bit
1 = CLCIN0 (true) is gated into CLCx Gate 3
0 = CLCIN0 (true) is not gated into CLCx Gate 3
bit 0 LCxG4D1N: Gate 3 Data 1 Negated (inverted) bit
1 = CLCIN0 (inverted) is gated into CLCx Gate 3
0 = CLCIN0 (inverted) is not gated into CLCx Gate 3

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REGISTER 31-11: CLCDATA: CLC DATA OUTPUT

U-0 U-0 U-0 U-0 R-0 R-0 R-0 R-0
— — — — MLC4OUT MLC3OUT MLC2OUT MLC1OUT
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-4 Unimplemented: Read as ‘0’

bit 3 MLC4OUT: Mirror copy of LC4OUT bit
bit 2 MLC3OUT: Mirror copy of LC3OUT bit
bit 1 MLC2OUT: Mirror copy of LC2OUT bit
bit 0 MLC1OUT: Mirror copy of LC1OUT bit

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TABLE 31-4: SUMMARY OF REGISTERS ASSOCIATED WITH CLCx

Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
on Page

INTCON GIE PEIE ― ― ― ― ― INTEDG 121

PIR5 CLC4IF CLC3IF CLC2IF CLC1IF — — — TMR1GIF 135

PIE5 CLC4IE CLC4IE CLC2IE CLC1IE — — — TMR1GIE 127

CLC1CON LC1EN ― LC1OUT LC1INTP LC1INTN LC1MODE<2:0> 350

CLC1POL LC1POL ― ― ― LC1G4POL LC1G3POL LC1G2POL LC1G1POL 351

CLC1SEL0 ― ― LC1D1S<5:0> 352

CLC1SEL1 ― ― LC1D2S<5:0> 352

CLC1SEL2 ― ― LC1D3S<5:0> 352

CLC1SEL3 ― ― LC1D4S<5:0> 352

CLC1GLS0 ― ― LC1G1D3T LC1G1D3N LC1G1D2T LC1G1D2N LC1G1D1T LC1G1D1N 353

CLC1GLS1 ― ― LC1G2D3T LC1G2D3N LC1G2D2T LC1G2D2N LC1G2D1T LC1G2D1N 354

CLC1GLS2 ― ― LC1G3D3T LC1G3D3N LC1G3D2T LC1G3D2N LC1G3D1T LC1G3D1N 355

CLC1GLS3 ― ― LC1G4D3T LC1G4D3N LC1G4D2T LC1G4D2N LC1G4D1T LC1G4D1N 356

CLC2CON LC2EN ― LC2OUT LC2INTP LC2INTN LC2MODE<2:0> 350

CLC2POL LC2POL ― ― ― LC2G4POL LC2G3POL LC2G2POL LC2G1POL 351

CLC2SEL0 ― ― LC2D1S<5:0> 352

CLC2SEL1 ― ― LC2D2S<5:0> 352

CLC2SEL2 ― ― LC2D3S<5:0> 352

CLC2SEL3 ― ― LC2D4S<5:0> 352

CLC2GLS0 ― ― LC2G1D3T LC2G1D3N LC2G1D2T LC2G1D2N LC2G1D1T LC2G1D1N 353

CLC2GLS1 ― ― LC2G2D3T LC2G2D3N LC2G2D2T LC2G2D2N LC2G2D1T LC2G2D1N 354

CLC2GLS2 ― ― LC2G3D3T LC2G3D3N LC2G3D2T LC2G3D2N LC2G3D1T LC2G3D1N 355

CLC2GLS3 ― ― LC2G4D3T LC2G4D3N LC2G4D2T LC2G4D2N LC2G4D1T LC2G4D1N 356

CLC3CON LC3EN ― LC3OUT LC3INTP LC3INTN LC3MODE<2:0> 350

CLC3POL LC3POL ― ― ― LC3G4POL LC3G3POL LC3G2POL LC3G1POL 351

CLC3SEL0 ― ― LC3D1S<5:0> 352

CLC3SEL1 ― ― LC3D2S<5:0> 352

CLC3SEL2 ― ― LC3D3S<5:0> 352

CLC3SEL3 ― ― LC3D4S<5:0> 352

CLC3GLS0 ― ― LC3G1D3T LC3G1D3N LC3G1D2T LC3G1D2N LC3G1D1T LC3G1D1N 353

CLC3GLS1 ― ― LC3G2D3T LC3G2D3N LC3G2D2T LC3G2D2N LC3G2D1T LC3G2D1N 354

CLC3GLS2 ― ― LC3G3D3T LC3G3D3N LC3G3D2T LC3G3D2N LC3G3D1T LC3G3D1N 355

CLC3GLS3 ― ― LC3G4D3T LC3G4D3N LC3G4D2T LC3G4D2N LC3G4D1T LC3G4D1N 356

CLC4CON LC4EN ― LC4OUT LC4INTP LC4INTN LC4MODE<2:0> 350

CLC4POL LC4POL ― ― ― LC4G4POL LC4G3POL LC4G2POL LC4G1POL 351

CLC4SEL0 ― ― LC4D1S<5:0> 352

CLC4SEL1 ― ― LC4D2S<5:0> 352

CLC4SEL2 ― ― LC4D3S<5:0> 352

CLC4SEL3 ― ― LC4D4S<5:0> 352

CLC4GLS0 ― ― LC4G1D3T LC4G1D3N LC4G1D2T LC4G1D2N LC4G1D1T LC4G1D1N 353

Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the CLCx modules.

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TABLE 31-4: SUMMARY OF REGISTERS ASSOCIATED WITH CLCx (continued)

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

CLC4GLS1 ― ― LC4G2D3T LC4G2D3N LC4G2D2T LC4G2D2N LC4G2D1T LC4G2D1N 354

CLC4GLS2 ― ― LC4G3D3T LC4G3D3N LC4G3D2T LC4G3D2N LC4G3D1T LC4G3D1N 355

CLC4GLS3 ― ― LC4G4D3T LC4G4D3N LC4G4D2T LC4G4D2N LC4G4D1T LC4G4D1N 356

CLCIN0PPS ― ― CLCIN0PPS<5:0> 191

CLCIN1PPS ― ― CLCIN1PPS<5:0> 191

CLCIN2PPS ― ― CLCIN2PPS<5:0> 191

CLCIN3PPS ― ― CLCIN3PPS<5:0> 191

Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the CLCx modules.

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32.0 MASTER SYNCHRONOUS
SERIAL PORT (MSSP1)
MODULE
32.1 MSSP Module Overview
The Master Synchronous Serial Port (MSSP) module is
a serial interface useful for communicating with other
peripheral or microcontroller devices. These peripheral
devices may be serial EEPROMs, shift registers,
display drivers, A/D converters, etc. The MSSP module
can operate in one of two modes:
• Serial Peripheral Interface (SPI)
• Inter-Integrated Circuit (I2C)
The SPI interface supports the following modes and
features:
• Master mode
• Slave mode
• Clock Parity
• Slave Select Synchronization (Slave mode only)
• Daisy-chain connection of slave devices
Figure 32-1 is a block diagram of the SPI interface
module.

FIGURE 32-1: MSSP BLOCK DIAGRAM (SPI MODE)

Data Bus
Read Write

SSP1BUF Reg

SSPDATPPS
SDI
PPS SSPSR Reg
SDO bit 0 Shift
Clock
PPS

RxyPPS

SS SS Control 2 (CKP, CKE)

PPS Enable Clock Select

Edge
SSPSSPPS Select

SSPCLKPPS(2) SSPM<3:0>

SCK PPS
4
( T2_match
2
)
Edge Prescaler TOSC
PPS Select 4, 16, 64

TRIS bit RxyPPS(1) Baud Rate

Generator
(SSP1ADD)
Note 1: Output selection for master mode.
2: Input selection for slave mode.

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The I2C interface supports the following modes and • Clock stretching
features: • Bus collision detection
• Master mode • General call address matching
• Slave mode • Address masking
• Byte NACKing (Slave mode) • Selectable SDA hold times
• Limited multi-master support Figure 32-2 is a block diagram of the I2C interface
• 7-bit and 10-bit addressing module in Master mode. Figure 32-3 is a diagram of the
• Start and Stop interrupts I2C interface module in Slave mode.
• Interrupt masking

FIGURE 32-2: MSSP BLOCK DIAGRAM (I2C MASTER MODE)

Internal
data bus [SSPM<3:0>]
SSPDATPPS(1) Read Write
SDA
SDA in
PPS SSP1BUF Baud Rate
Generator
(SSP1ADD)
Shift
RxyPPS(1) Clock

Clock arbitrate/BCOL detect

SSPSR

Clock Cntl

(Hold off clock source)

PPS MSb LSb
Receive Enable (RCEN)

Start bit, Stop bit,

Acknowledge
(2)
SSPCLKPPS Generate (SSP1CON2)
SCL
PPS

PPS

Start bit detect,

RxyPPS(2) Stop bit detect
Write collision detect Set/Reset: S, P, SSP1STAT, WCOL, SSPOV
SCL in
Clock arbitration Reset SEN, PEN (SSP1CON2)
State counter for Set SSP1IF, BCL1IF
Bus Collision end of XMIT/RCV
Address Match detect

Note 1: SDA pin selections must be the same for input and output.
2: SCL pin selections must be the same for input and output.

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FIGURE 32-3: MSSP BLOCK DIAGRAM (I2C SLAVE MODE)

Internal
Data Bus

Read Write

SSPCLKPPS(2) SSP1BUF Reg

SCL
PPS
Shift
Clock
Clock
PPS Stretching SSPSR Reg
MSb LSb
RxyPPS(2)

SSP1MSK Reg
(1)
SSPDATPPS
SDA Match Detect Addr Match
PPS
SSP1ADD Reg
PPS
Start and Set, Reset
RxyPPS(1) Stop bit Detect S, P bits
(SSP1STAT Reg)

Note 1: SDA pin selections must be the same for input and output.
2: SCL pin selections must be the same for input and output.

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32.2 SPI Mode Overview During each SPI clock cycle, a full-duplex data
transmission occurs. This means that while the master
The Serial Peripheral Interface (SPI) bus is a device is sending out the MSb from its shift register (on
synchronous serial data communication bus that its SDO pin) and the slave device is reading this bit and
operates in Full-Duplex mode. Devices communicate saving it as the LSb of its shift register, that the slave
in a master/slave environment where the master device device is also sending out the MSb from its shift register
initiates the communication. A slave device is (on its SDO pin) and the master device is reading this
controlled through a Chip Select known as Slave bit and saving it as the LSb of its shift register.
Select.
After eight bits have been shifted out, the master and
The SPI bus specifies four signal connections: slave have exchanged register values.
• Serial Clock (SCK) If there is more data to exchange, the shift registers are
• Serial Data Out (SDO) loaded with new data and the process repeats itself.
• Serial Data In (SDI) Whether the data is meaningful or not (dummy data),
• Slave Select (SS) depends on the application software. This leads to
Figure 32-1 shows the block diagram of the MSSP three scenarios for data transmission:
module when operating in SPI mode. • Master sends useful data and slave sends dummy
The SPI bus operates with a single master device and data.
one or more slave devices. When multiple slave • Master sends useful data and slave sends useful
devices are used, an independent Slave Select data.
connection is required from the master device to each • Master sends dummy data and slave sends useful
slave device. data.
Figure 32-4 shows a typical connection between a Transmissions may involve any number of clock
master device and multiple slave devices. cycles. When there is no more data to be transmitted,
The master selects only one slave at a time. Most slave the master stops sending the clock signal and it
devices have tri-state outputs so their output signal deselects the slave.
appears disconnected from the bus when they are not Every slave device connected to the bus that has not
selected. been selected through its slave select line must disre-
Transmissions involve two shift registers, eight bits in gard the clock and transmission signals and must not
size, one in the master and one in the slave. Data is transmit out any data of its own.
always shifted out one bit at a time, with the Most
Significant bit (MSb) shifted out first. At the same time,
a new Least Significant bit (LSb) is shifted into the
same register.
Figure 32-5 shows a typical connection between two
processors configured as master and slave devices.
Data is shifted out of both shift registers on the
programmed clock edge and latched on the opposite
edge of the clock.
The master device transmits information out on its SDO
output pin which is connected to, and received by, the
slave’s SDI input pin. The slave device transmits infor-
mation out on its SDO output pin, which is connected
to, and received by, the master’s SDI input pin.
To begin communication, the master device first sends
out the clock signal. Both the master and the slave
devices should be configured for the same clock polar-
ity.
The master device starts a transmission by sending out
the MSb from its shift register. The slave device reads
this bit from that same line and saves it into the LSb
position of its shift register.

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FIGURE 32-4: SPI MASTER AND MULTIPLE SLAVE CONNECTION

SCK SCK
SPI Master
SDO SDI SPI Slave
SDI SDO #1
General I/O SS
General I/O
General I/O SCK
SDI SPI Slave
SDO #2
SS

SCK
SDI SPI Slave
SDO #3
SS

32.2.1 SPI MODE REGISTERS

The MSSP module has five registers for SPI mode
operation. These are:
• MSSP STATUS register (SSP1STAT)
• MSSP Control register 1 (SSP1CON1)
• MSSP Control register 3 (SSP1CON3)
• MSSP Data Buffer register (SSP1BUF)
• MSSP Address register (SSP1ADD)
• MSSP Shift register (SSP1SR)
(Not directly accessible)
SSP1CON1 and SSP1STAT are the control and status
registers in SPI mode operation. The SSP1CON1
register is readable and writable. The lower six bits of
the SSP1STAT are read-only. The upper two bits of the
SSP1STAT are read/write.
In one SPI master mode, SSP1ADD can be loaded
with a value used in the Baud Rate Generator. More
information on the Baud Rate Generator is available in
Section 32.7 “Baud Rate Generator”.
SSP1SR is the shift register used for shifting data in
and out. SSP1BUF provides indirect access to the
SSP1SR register. SSP1BUF is the buffer register to
which data bytes are written, and from which data
bytes are read.
In receive operations, SSP1SR and SSP1BUF
together create a buffered receiver. When SSP1SR
receives a complete byte, it is transferred to SSP1BUF
and the SSP1IF interrupt is set.
During transmission, the SSP1BUF is not buffered. A
write to SSP1BUF will write to both SSP1BUF and
SSP1SR.

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32.2.2 SPI MODE OPERATION The MSSP consists of a transmit/receive shift register
(SSP1SR) and a buffer register (SSP1BUF). The
When initializing the SPI, several options need to be SSP1SR shifts the data in and out of the device, MSb first.
specified. This is done by programming the appropriate The SSP1BUF holds the data that was written to the
control bits (SSP1CON1<3:0> and SSP1STAT<7:6>). SSP1SR until the received data is ready. Once the eight
These control bits allow the following to be specified: bits of data have been received, that byte is moved to the
• Master mode (SCK is the clock output) SSP1BUF register. Then, the Buffer Full Detect bit, BF of
• Slave mode (SCK is the clock input) the SSP1STAT register, and the interrupt flag bit, SSP1IF,
• Clock Polarity (Idle state of SCK) are set. Any write to the SSP1BUF register during
transmission/reception of data will be ignored and the
• Data Input Sample Phase (middle or end of data
write collision detect bit WCOL of the SSP1CON1
output time)
register, will be set. User software must clear the WCOL
• Clock Edge (output data on rising/falling edge of bit to allow the following write(s) to the SSP1BUF register
SCK) to complete successfully.
• Clock Rate (Master mode only)
When the application software is expecting to receive
• Slave Select mode (Slave mode only) valid data, the SSP1BUF should be read before the next
To enable the serial port, SSP Enable bit, SSPEN of the byte of data to transfer is written to the SSP1BUF. The
SSP1CON1 register, must be set. To reset or reconfig- Buffer Full bit, BF of the SSP1STAT register, indicates
ure SPI mode, clear the SSPEN bit, re-initialize the when SSP1BUF has been loaded with the received data
SSP1CONx registers and then set the SSPEN bit. This (transmission is complete). When the SSP1BUF is read,
configures the SDI, SDO, SCK and SS pins as serial port the BF bit is cleared. This data may be irrelevant if the
pins. For the pins to behave as the serial port function, SPI is only a transmitter. Generally, the MSSP interrupt
some must have their data direction bits (in the TRISx is used to determine when the transmission/reception
register) appropriately programmed as follows: has completed. If the interrupt method is not going to be
used, then software polling can be done to ensure that a
• SDI must have corresponding TRIS bit set
write collision does not occur.
• SDO must have corresponding TRIS bit cleared
The SSP1SR is not directly readable or writable and
• SCK (Master mode) must have corresponding
can only be accessed by addressing the SSP1BUF
TRIS bit cleared
register.
• SCK (Slave mode) must have corresponding
TRIS bit set
• SS must have corresponding TRIS bit set
Any serial port function that is not desired may be
overridden by programming the corresponding data
direction (TRIS) register to the opposite value.

FIGURE 32-5: SPI MASTER/SLAVE CONNECTION

SPI Master SSPM<3:0> = 00xx SPI Slave SSPM<3:0> = 010x

= 1010
SDO SDI

Serial Input Buffer Serial Input Buffer

(SSP1BUF) (SSP1BUF)

Shift Register SDI SDO Shift Register

(SSP1SR) (SSP1SR)
MSb LSb MSb LSb
Serial Clock
SCK SCK

Slave Select
General I/O SS
Processor 1 (optional) Processor 2

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32.2.3 SPI MASTER MODE The clock polarity is selected by appropriately
programming the CKP bit of the SSP1CON1 register
The master can initiate the data transfer at any time
and the CKE bit of the SSP1STAT register. This then,
because it controls the SCK line. The master
would give waveforms for SPI communication as
determines when the slave (Processor 2, Figure 32-5)
shown in Figure 32-6, Figure 32-8, Figure 32-9 and
is to broadcast data by the software protocol.
Figure 32-10, where the MSB is transmitted first. In
In Master mode, the data is transmitted/received as Master mode, the SPI clock rate (bit rate) is user
soon as the SSP1BUF register is written to. If the SPI programmable to be one of the following:
is only going to receive, the SDO output could be
• FOSC/4 (or TCY)
disabled (programmed as an input). The SSP1SR
register will continue to shift in the signal present on the • FOSC/16 (or 4 * TCY)
SDI pin at the programmed clock rate. As each byte is • FOSC/64 (or 16 * TCY)
received, it will be loaded into the SSP1BUF register as • Timer2 output/2
if a normal received byte (interrupts and Status bits • FOSC/(4 * (SSP1ADD + 1))
appropriately set).
Figure 32-6 shows the waveforms for Master mode.
When the CKE bit is set, the SDO data is valid before
there is a clock edge on SCK. The change of the input
sample is shown based on the state of the SMP bit. The
time when the SSP1BUF is loaded with the received
data is shown.

FIGURE 32-6: SPI MODE WAVEFORM (MASTER MODE)

Write to
SSP1BUF

SCK
(CKP = 0
CKE = 0)

SCK
(CKP = 1
CKE = 0)
4 Clock
SCK Modes
(CKP = 0
CKE = 1)

SCK
(CKP = 1
CKE = 1)

SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

(CKE = 0)

SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

(CKE = 1)
SDI
(SMP = 0) bit 7 bit 0
Input
Sample
(SMP = 0)
SDI
(SMP = 1) bit 0
bit 7

Input
Sample
(SMP = 1)
SSP1IF

SSP1SR to
SSP1BUF

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32.2.4 SPI SLAVE MODE 32.2.5 SLAVE SELECT
In Slave mode, the data is transmitted and received as SYNCHRONIZATION
external clock pulses appear on SCK. When the last The Slave Select can also be used to synchronize
bit is latched, the SSP1IF interrupt flag bit is set. communication. The Slave Select line is held high until
Before enabling the module in SPI Slave mode, the clock the master device is ready to communicate. When the
line must match the proper Idle state. The clock line can Slave Select line is pulled low, the slave knows that a
be observed by reading the SCK pin. The Idle state is new transmission is starting.
determined by the CKP bit of the SSP1CON1 register. If the slave fails to receive the communication properly,
While in Slave mode, the external clock is supplied by it will be reset at the end of the transmission, when the
the external clock source on the SCK pin. This external Slave Select line returns to a high state. The slave is
clock must meet the minimum high and low times as then ready to receive a new transmission when the
specified in the electrical specifications. Slave Select line is pulled low again. If the Slave Select
line is not used, there is a risk that the slave will
While in Sleep mode, the slave can transmit/receive
eventually become out of sync with the master. If the
data. The shift register is clocked from the SCK pin
slave misses a bit, it will always be one bit off in future
input and when a byte is received, the device will
transmissions. Use of the Slave Select line allows the
generate an interrupt. If enabled, the device will
slave and master to align themselves at the beginning
wake-up from Sleep.
of each transmission.
32.2.4.1 Daisy-Chain Configuration The SS pin allows a Synchronous Slave mode. The
SPI must be in Slave mode with SS pin control enabled
The SPI bus can sometimes be connected in a
(SSP1CON1<3:0> = 0100).
daisy-chain configuration. The first slave output is
connected to the second slave input, the second slave When the SS pin is low, transmission and reception are
output is connected to the third slave input, and so on. enabled and the SDO pin is driven.
The final slave output is connected to the master input. When the SS pin goes high, the SDO pin is no longer
Each slave sends out, during a second group of clock driven, even if in the middle of a transmitted byte and
pulses, an exact copy of what was received during the becomes a floating output. External pull-up/pull-down
first group of clock pulses. The whole chain acts as resistors may be desirable depending on the applica-
one large communication shift register. The tion.
daisy-chain feature only requires a single Slave Select
line from the master device. Note 1: When the SPI is in Slave mode with SS pin
control enabled (SSP1CON1<3:0> =
Figure 32-7 shows the block diagram of a typical
0100), the SPI module will reset if the SS
daisy-chain connection when operating in SPI mode.
pin is set to VDD.
In a daisy-chain configuration, only the most recent
2: When the SPI is used in Slave mode with
byte on the bus is required by the slave. Setting the
CKE set; the user must enable SS pin
BOEN bit of the SSP1CON3 register will enable writes
control.
to the SSP1BUF register, even if the previous byte has
not been read. This allows the software to ignore data 3: While operated in SPI Slave mode the
that may not apply to it. SMP bit of the SSP1STAT register must
remain clear.
When the SPI module resets, the bit counter is forced
to ‘0’. This can be done by either forcing the SS pin to
a high level or clearing the SSPEN bit.

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FIGURE 32-7: SPI DAISY-CHAIN CONNECTION

SCK SCK
SPI Master
SDO SDI SPI Slave
SDI SDO #1
General I/O SS

SCK
SDI SPI Slave
SDO #2
SS

SCK
SDI SPI Slave
SDO #3
SS

FIGURE 32-8: SLAVE SELECT SYNCHRONOUS WAVEFORM

SS

SCK
(CKP = 0
CKE = 0)

SCK
(CKP = 1
CKE = 0)

Write to
SSP1BUF
Shift register SSP1SR
and bit count are reset
SSP1BUF to
SSP1SR

SDO bit 7 bit 6 bit 7 bit 6 bit 0

SDI bit 0
bit 7 bit 7
Input
Sample

SSP1IF
Interrupt
Flag

SSP1SR to
SSP1BUF

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FIGURE 32-9: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0)

SS
Optional

SCK
(CKP = 0
CKE = 0)

SCK
(CKP = 1
CKE = 0)
Write to
SSP1BUF
Valid
SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

SDI
bit 7 bit 0
Input
Sample

SSP1IF
Interrupt
Flag
SSP1SR to
SSP1BUF

Write Collision
detection active

FIGURE 32-10: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1)

SS
Not Optional

SCK
(CKP = 0
CKE = 1)

SCK
(CKP = 1
CKE = 1)
Write to
SSP1BUF
Valid
SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

SDI
bit 7 bit 0
Input
Sample

SSP1IF
Interrupt
Flag

SSP1SR to
SSP1BUF

Write Collision
detection active

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32.2.6 SPI OPERATION IN SLEEP MODE This is followed by a single Read/Write bit, which deter-
mines whether the master intends to transmit to or
In SPI Master mode, module clocks may be operating receive data from the slave device.
at a different speed than when in Full-Power mode; in
the case of the Sleep mode, all clocks are halted. If the requested slave exists on the bus, it will respond
with an Acknowledge bit, otherwise known as an ACK.
In SPI Master mode, when the Sleep mode is selected, The master then continues in either Transmit mode or
all module clocks are halted and the Receive mode and the slave continues in the comple-
transmission/reception will remain in that state until the ment, either in Receive mode or Transmit mode,
device wakes. After the device returns to Run mode, respectively.
the module will resume transmitting and receiving data.
In SPI Slave mode, the SPI Transmit/Receive Shift FIGURE 32-11: I2C MASTER/
register operates asynchronously to the device. This SLAVE CONNECTION
allows the device to be placed in Sleep mode and data
to be shifted into the SPI Transmit/Receive Shift
register. When all eight bits have been received, the VDD
MSSP interrupt flag bit will be set and if enabled, will
wake the device. SCL SCL
32.3 I2C MODE OVERVIEW VDD
Master Slave
The Inter-Integrated Circuit (I2C)
bus is a multi-master
serial data communication bus. Devices communicate SDA SDA
in a master/slave environment where the master
devices initiate the communication. A slave device is
controlled through addressing.
The I2C bus specifies two signal connections: The Acknowledge bit (ACK) is an active-low signal,
which holds the SDA line low to indicate to the transmit-
• Serial Clock (SCL)
ter that the slave device has received the transmitted
• Serial Data (SDA) data and is ready to receive more.
Figure 32-11 shows the block diagram of the MSSP The transition of a data bit is always performed while
module when operating in I2C mode. the SCL line is held low. Transitions that occur while the
Both the SCL and SDA connections are bidirectional SCL line is held high are used to indicate Start and Stop
open-drain lines, each requiring pull-up resistors for the bits.
supply voltage. Pulling the line to ground is considered On the last byte of data communicated, the master
a logical zero and letting the line float is considered a device may end the transmission by sending a Stop bit.
logical one. If the master device is in Receive mode, it sends the
Figure 32-11 shows a typical connection between two Stop bit in place of the last ACK bit. A Stop bit is
processors configured as master and slave devices. indicated by a low-to-high transition of the SDA line
The I2C bus can operate with one or more master while the SCL line is held high.
devices and one or more slave devices. In some cases, the master may want to maintain
There are four potential modes of operation for a given control of the bus and re-initiate another transmission.
If so, the master device may send another Start bit in
device:
place of the Stop bit.
• Master Transmit mode
(master is transmitting data to a slave)
• Master Receive mode
(master is receiving data from a slave)
• Slave Transmit mode
(slave is transmitting data to a master)
• Slave Receive mode
(slave is receiving data from the master)
To begin communication, a master device starts out in
Master Transmit mode. The master device sends out a
Start bit followed by the address byte of the slave it
intends to communicate with.

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32.3.1 CLOCK STRETCHING 32.4 I2C MODE OPERATION
When a slave device has not completed processing
All MSSP I2C communication is byte oriented and
data, it can delay the transfer of more data through the
shifted out MSb first. Six SFR registers and two
process of clock stretching. An addressed slave device
interrupt flags interface the module with the PIC®
may hold the SCL clock line low after receiving or send-
microcontroller and user software. Two pins, SDA and
ing a bit, indicating that it is not yet ready to continue.
SCL, are exercised by the module to communicate
The master that is communicating with the slave will
with other external I2C devices.
attempt to raise the SCL line in order to transfer the
next bit, but will detect that the clock line has not yet 32.4.1 BYTE FORMAT
been released. Because the SCL connection is
open-drain, the slave has the ability to hold that line low All communication in I2C is done in 9-bit segments. A
until it is ready to continue communicating. byte is sent from a master to a slave or vice-versa, fol-
lowed by an Acknowledge bit sent back. After the
Clock stretching allows receivers that cannot keep up eighth falling edge of the SCL line, the device output-
with a transmitter to control the flow of incoming data. ting data on the SDA changes that pin to an input and
reads in an acknowledge value on the next clock
32.3.2 ARBITRATION
pulse.
Each master device must monitor the bus for Start and
The clock signal, SCL, is provided by the master. Data
Stop bits. If the device detects that the bus is busy, it
is valid to change while the SCL signal is low, and
cannot begin a new message until the bus returns to an
sampled on the rising edge of the clock. Changes on
Idle state.
the SDA line while the SCL line is high define special
However, two master devices may try to initiate a trans- conditions on the bus, explained below.
mission on or about the same time. When this occurs,
the process of arbitration begins. Each transmitter 32.4.2 DEFINITION OF I2C TERMINOLOGY
checks the level of the SDA data line and compares it There is language and terminology in the description
to the level that it expects to find. The first transmitter to of I2C communication that have definitions specific to
observe that the two levels do not match, loses arbitra- I2C. That word usage is defined below and may be
tion, and must stop transmitting on the SDA line. used in the rest of this document without explanation.
For example, if one transmitter holds the SDA line to a This table was adapted from the Philips I2C
logical one (lets it float) and a second transmitter holds specification.
it to a logical zero (pulls it low), the result is that the
SDA line will be low. The first transmitter then observes 32.4.3 SDA AND SCL PINS
that the level of the line is different than expected and Selection of any I2C mode with the SSPEN bit set,
concludes that another transmitter is communicating. forces the SCL and SDA pins to be open-drain. These
The first transmitter to notice this difference is the one pins should be set by the user to inputs by setting the
that loses arbitration and must stop driving the SDA appropriate TRIS bits.
line. If this transmitter is also a master device, it also
Note 1: Any device pin can be selected for SDA
must stop driving the SCL line. It then can monitor the
and SCL functions with the PPS periph-
lines for a Stop condition before trying to reissue its
eral. These functions are bidirectional.
transmission. In the meantime, the other device that
The SDA input is selected with the
has not noticed any difference between the expected
SSPDATPPS registers. The SCL input is
and actual levels on the SDA line continues with its
selected with the SSPCLKPPS registers.
original transmission.
Outputs are selected with the RxyPPS
Slave Transmit mode can also be arbitrated, when a registers. It is the user’s responsibility to
master addresses multiple slaves, but this is less make the selections so that both the input
common. and the output for each function is on the
same pin.

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 PIC16(L)F15313/23
32.4.4 SDA HOLD TIME 32.4.5 START CONDITION

The hold time of the SDA pin is selected by the SDAHT The I2C specification defines a Start condition as a
bit of the SSP1CON3 register. Hold time is the time transition of SDA from a high to a low state while SCL
SDA is held valid after the falling edge of SCL. Setting line is high. A Start condition is always generated by
the SDAHT bit selects a longer 300 ns minimum hold the master and signifies the transition of the bus from
time and may help on buses with large capacitance. an Idle to an active state. Figure 32-12 shows wave
forms for Start and Stop conditions.
TABLE 32-1: I2C BUS TERMS
32.4.6 STOP CONDITION
TERM Description
A Stop condition is a transition of the SDA line from
Transmitter The device which shifts data out low-to-high state while the SCL line is high.
onto the bus.
Receiver The device which shifts data in Note: At least one SCL low time must appear
from the bus. before a Stop is valid, therefore, if the SDA
line goes low then high again while the SCL
Master The device that initiates a transfer,
line stays high, only the Start condition is
generates clock signals and termi-
detected.
nates a transfer.
Slave The device addressed by the 32.4.7 RESTART CONDITION
master.
Multi-master A bus with more than one device A Restart is valid any time that a Stop would be valid.
that can initiate data transfers. A master can issue a Restart if it wishes to hold the
bus after terminating the current transfer. A Restart
Arbitration Procedure to ensure that only one
has the same effect on the slave that a Start would,
master at a time controls the bus.
resetting all slave logic and preparing it to clock in an
Winning arbitration ensures that
address. The master may want to address the same or
the message is not corrupted.
another slave. Figure 32-13 shows the wave form for a
Synchronization Procedure to synchronize the Restart condition.
clocks of two or more devices on
the bus. In 10-bit Addressing Slave mode a Restart is required
for the master to clock data out of the addressed
Idle No master is controlling the bus,
slave. Once a slave has been fully addressed, match-
and both SDA and SCL lines are
ing both high and low address bytes, the master can
high.
issue a Restart and the high address byte with the
Active Any time one or more master R/W bit set. The slave logic will then hold the clock
devices are controlling the bus. and prepare to clock out data.
Addressed Slave device that has received a
Slave matching address and is actively 32.4.8 START/STOP CONDITION INTERRUPT
being clocked by a master. MASKING
Matching Address byte that is clocked into a The SCIE and PCIE bits of the SSP1CON3 register
Address slave that matches the value can enable the generation of an interrupt in Slave
stored in SSP1ADD. modes that do not typically support this function. Slave
Write Request Slave receives a matching modes where interrupt on Start and Stop detect are
address with R/W bit clear, and is already enabled, these bits will have no effect.
ready to clock in data.
Read Request Master sends an address byte with
the R/W bit set, indicating that it
wishes to clock data out of the
Slave. This data is the next and all
following bytes until a Restart or
Stop.
Clock Stretching When a device on the bus hold
SCL low to stall communication.
Bus Collision Any time the SDA line is sampled
low by the module while it is out-
putting and expected high state.

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 PIC16(L)F15313/23
FIGURE 32-12: I2C START AND STOP CONDITIONS

SDA

SCL
S P
Change of Change of
Data Allowed Data Allowed
Start Stop
Condition Condition

FIGURE 32-13: I2C RESTART CONDITION

Sr

Change of Change of
Data Allowed Data Allowed
Restart
Condition

32.4.9 ACKNOWLEDGE SEQUENCE Slave software, when the AHEN and DHEN bits are
set, allow the user to set the ACK value sent back to
The 9th SCL pulse for any transferred byte in I2C is the transmitter. The ACKDT bit of the SSP1CON2
dedicated as an Acknowledge. It allows receiving register is set/cleared to determine the response.
devices to respond back to the transmitter by pulling
the SDA line low. The transmitter must release control There are certain conditions where an ACK will not be
of the line during this time to shift in the response. The sent by the slave. If the BF bit of the SSP1STAT
Acknowledge (ACK) is an active-low signal, pulling the register or the SSPOV bit of the SSP1CON1 register
SDA line low indicates to the transmitter that the are set when a byte is received.
device has received the transmitted data and is ready When the module is addressed, after the eighth falling
to receive more. edge of SCL on the bus, the ACKTIM bit of the
The result of an ACK is placed in the ACKSTAT bit of SSP1CON3 register is set. The ACKTIM bit indicates
the SSP1CON2 register. the acknowledge time of the active bus. The ACKTIM
Status bit is only active when the AHEN bit or DHEN
bit is enabled.

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 PIC16(L)F15313/23
32.5 I2C SLAVE MODE OPERATION 32.5.2 SLAVE RECEPTION

The MSSP Slave mode operates in one of four modes When the R/W bit of a matching received address byte
selected by the SSPM bits of SSP1CON1 register. The is clear, the R/W bit of the SSP1STAT register is
modes can be divided into 7-bit and 10-bit Addressing cleared. The received address is loaded into the
mode. 10-bit Addressing modes operate the same as SSP1BUF register and acknowledged.
7-bit with some additional overhead for handling the When the overflow condition exists for a received
larger addresses. address, then not Acknowledge is given. An overflow
Modes with Start and Stop bit interrupts operate the condition is defined as either bit BF of the SSP1STAT
same as the other modes with SSP1IF additionally register is set, or bit SSPOV of the SSP1CON1 register
getting set upon detection of a Start, Restart, or Stop is set. The BOEN bit of the SSP1CON3 register
condition. modifies this operation. For more information see
Register 32-4.
32.5.1 SLAVE MODE ADDRESSES
An MSSP interrupt is generated for each transferred
The SSP1ADD register (Register 32-6) contains the data byte. Flag bit, SSP1IF, must be cleared by
Slave mode address. The first byte received after a software.
Start or Restart condition is compared against the When the SEN bit of the SSP1CON2 register is set,
value stored in this register. If the byte matches, the SCL will be held low (clock stretch) following each
value is loaded into the SSP1BUF register and an received byte. The clock must be released by setting
interrupt is generated. If the value does not match, the the CKP bit of the SSP1CON1 register.
module goes idle and no indication is given to the
software that anything happened. 32.5.2.1 7-bit Addressing Reception
The SSP Mask register (Register 32-5) affects the This section describes a standard sequence of events
address matching process. See Section 32.5.9 “SSP for the MSSP module configured as an I2C slave in
Mask Register” for more information. 7-bit Addressing mode. Figure 32-14 and Figure 32-15
is used as a visual reference for this description.
32.5.1.1 I2C Slave 7-bit Addressing Mode
This is a step by step process of what typically must
In 7-bit Addressing mode, the LSb of the received data be done to accomplish I2C communication.
byte is ignored when determining if there is an address
1. Start bit detected.
match.
2. S bit of SSP1STAT is set; SSP1IF is set if
32.5.1.2 I2C Slave 10-bit Addressing Mode interrupt on Start detect is enabled.
In 10-bit Addressing mode, the first received byte is 3. Matching address with R/W bit clear is received.
compared to the binary value of ‘1 1 1 1 0 A9 A8 0’. A9 4. The slave pulls SDA low sending an ACK to the
and A8 are the two MSb’s of the 10-bit address and master, and sets SSP1IF bit.
stored in bits 2 and 1 of the SSP1ADD register. 5. Software clears the SSP1IF bit.
After the acknowledge of the high byte the UA bit is set 6. Software reads received address from
and SCL is held low until the user updates SSP1ADD SSP1BUF clearing the BF flag.
with the low address. The low address byte is clocked 7. If SEN = 1; Slave software sets CKP bit to
in and all eight bits are compared to the low address release the SCL line.
value in SSP1ADD. Even if there is not an address 8. The master clocks out a data byte.
match; SSP1IF and UA are set, and SCL is held low 9. Slave drives SDA low sending an ACK to the
until SSP1ADD is updated to receive a high byte master, and sets SSP1IF bit.
again. When SSP1ADD is updated the UA bit is
10. Software clears SSP1IF.
cleared. This ensures the module is ready to receive
the high address byte on the next communication. 11. Software reads the received byte from
SSP1BUF clearing BF.
A high and low address match as a write request is
12. Steps 8-12 are repeated for all received bytes
required at the start of all 10-bit addressing communi-
from the master.
cation. A transmission can be initiated by issuing a
Restart once the slave is addressed, and clocking in 13. Master sends Stop condition, setting P bit of
the high address with the R/W bit set. The slave SSP1STAT, and the bus goes idle.
hardware will then acknowledge the read request and
prepare to clock out data. This is only valid for a slave
after it has received a complete high and low address
byte match.

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 PIC16(L)F15313/23
32.5.2.2 7-bit Reception with AHEN and DHEN

Slave device reception with AHEN and DHEN set

operate the same as without these options with extra
interrupts and clock stretching added after the eighth
falling edge of SCL. These additional interrupts allows
time for the slave software to decide whether it wants
to ACK the receive address or data byte.
This list describes the steps that need to be taken by
slave software to use these options for I2C
communication. Figure 32-16 displays a module using
both address and data holding. Figure 32-17 includes
the operation with the SEN bit of the SSP1CON2
register set.
1. S bit of SSP1STAT is set; SSP1IF is set if
interrupt on Start detect is enabled.
2. Matching address with R/W bit clear is clocked
in. SSP1IF is set and CKP cleared after the
eighth falling edge of SCL.
3. Slave clears the SSP1IF.
4. Slave can look at the ACKTIM bit of the
SSP1CON3 register to determine if the SSP1IF
was after or before the ACK.
5. Slave reads the address value from SSP1BUF,
clearing the BF flag.
6. Slave sets ACK value clocked out to the master
by setting ACKDT.
7. Slave releases the clock by setting CKP.
8. SSP1IF is set after an ACK, not after a NACK.
9. If SEN = 1 the slave hardware will stretch the
clock after the ACK.
10. Slave clears SSP1IF.

Note: SSP1IF is still set after the ninth falling edge

of SCL even if there is no clock stretching
and BF has been cleared. Only if NACK is
sent to master is SSP1IF not set
11. SSP1IF set and CKP cleared after eighth falling
edge of SCL for a received data byte.
12. Slave looks at ACKTIM bit of SSP1CON3 to
determine the source of the interrupt.
13. Slave reads the received data from SSP1BUF
clearing BF.
14. Steps 7-14 are the same for each received data
byte.
15. Communication is ended by either the slave
sending an ACK = 1, or the master sending a
Stop condition. If a Stop is sent and Interrupt on
Stop Detect is disabled, the slave will only know
by polling the P bit of the SSP1STAT register.

 2017 Microchip Technology Inc. Preliminary DS40001897A-page 375

 FIGURE 32-14: I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 0, DHEN = 0)
 2017 Microchip Technology Inc.

Bus Master sends

Stop condition
From Slave to Master

Receiving Address Receiving Data Receiving Data ACK = 1

SDA
A7 A6 A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0

SCL
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S P
Preliminary

SSP1IF
SSP1IF set on 9th
Cleared by software Cleared by software falling edge of
SCL

PIC16(L)F15313/23
BF
First byte
SSP1BUF is read of data is
available
in SSP1BUF
SSPOV

SSPOV set because

SSP1BUF is still full.
ACK is not sent.
DS40001897A-page 376
 FIGURE 32-15: I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 0, DHEN = 0)
 2017 Microchip Technology Inc.

Bus Master sends

Stop condition

Receive Address Receive Data Receive Data ACK

SDA A7 A6 A5 A4 A3 A2 A1 R/W=0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0

SCL S 1 2 3 4 5 6 7 8 9 SEN 1 2 3 4 5 6 7 8 9 SEN 1 2 3 4 5 6 7 8 9 P

Clock is held low until CKP is set to ‘1’

Preliminary

SSP1IF

SSP1IF set on 9th

Cleared by software Cleared by software falling edge of SCL

BF
First byte

PIC16(L)F15313/23
of data is
SSP1BUF is read available
in SSP1BUF
SSPOV

SSPOV set because

SSP1BUF is still full.
ACK is not sent.
CKP

SCL is not held

CKP is written to ‘1’ in software, CKP is written to ‘1’ in software,
DS40001897A-page 377

low because
releasing SCL releasing SCL
ACK= 1
 FIGURE 32-16: I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 1, DHEN = 1)
 2017 Microchip Technology Inc.

Master Releases SDA Master sends

to slave for ACK sequence Stop condition

SDA Receiving Address Receiving Data ACK Received Data ACK=1

A7 A6 A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

SCL
S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P

SSP1IF
If AHEN = 1: SSP1IF is set on
SSP1IF is set 9th falling edge of Cleared by software No interrupt
SCL, after ACK after not ACK
BF from Slave
Preliminary

Address is
read from Data is read from SSP1BUF
ACKDT SSP1BUF

Slave software
clears ACKDT to Slave software
ACK the received sets ACKDT to
CKP byte not ACK

PIC16(L)F15313/23
When AHEN = 1:
When DHEN = 1: CKP set by software,
CKP is cleared by hardware
CKP is cleared by SCL is released
and SCL is stretched hardware on 8th falling
edge of SCL
ACKTIM

ACKTIM set by hardware ACKTIM cleared by ACKTIM set by hardware

on 8th falling edge of SCL hardware in 9th on 8th falling edge of SCL
rising edge of SCL
DS40001897A-page 378

P
 FIGURE 32-17: I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 1, DHEN = 1)
 2017 Microchip Technology Inc.

Master sends
Stop condition
Master releases
R/W = 0 SDA to slave for ACK sequence
Receiving Address Receive Data Receive Data ACK
SDA ACK
A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0

SCL
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P
S

SSP1IF
Cleared by software No interrupt after
if not ACK
from Slave
Preliminary

BF
Received
address is loaded into Received data is SSP1BUF can be
SSP1BUF available on SSP1BUF read any time before
next byte is loaded
ACKDT

Slave software clears

Slave sends
ACKDT to ACK not ACK
the received byte

PIC16(L)F15313/23
CKP
When AHEN = 1; When DHEN = 1; CKP is not cleared
on the 8th falling edge on the 8th falling edge Set by software, if not ACK
of SCL of an address of SCL of a received release SCL
byte, CKP is cleared data byte, CKP is cleared

ACKTIM

ACKTIM is set by hardware ACKTIM is cleared by hardware

on 8th falling edge of SCL on 9th rising edge of SCL
DS40001897A-page 379

P
 PIC16(L)F15313/23
32.5.3 SLAVE TRANSMISSION 32.5.3.2 7-bit Transmission
When the R/W bit of the incoming address byte is set A master device can transmit a read request to a
and an address match occurs, the R/W bit of the slave, and then clock data out of the slave. The list
SSP1STAT register is set. The received address is below outlines what software for a slave will need to
loaded into the SSP1BUF register, and an ACK pulse do to accomplish a standard transmission.
is sent by the slave on the ninth bit. Figure 32-18 can be used as a reference to this list.
Following the ACK, slave hardware clears the CKP bit 1. Master sends a Start condition on SDA and
and the SCL pin is held low (see Section 32.5.6 SCL.
“Clock Stretching” for more detail). By stretching the 2. S bit of SSP1STAT is set; SSP1IF is set if
clock, the master will be unable to assert another clock interrupt on Start detect is enabled.
pulse until the slave is done preparing the transmit 3. Matching address with R/W bit set is received by
data. the Slave setting SSP1IF bit.
The transmit data must be loaded into the SSP1BUF 4. Slave hardware generates an ACK and sets
register which also loads the SSP1SR register. Then SSP1IF.
the SCL pin should be released by setting the CKP bit 5. SSP1IF bit is cleared by user.
of the SSP1CON1 register. The eight data bits are
6. Software reads the received address from
shifted out on the falling edge of the SCL input. This
SSP1BUF, clearing BF.
ensures that the SDA signal is valid during the SCL
high time. 7. R/W is set so CKP was automatically cleared
after the ACK.
The ACK pulse from the master-receiver is latched on
8. The slave software loads the transmit data into
the rising edge of the ninth SCL input pulse. This ACK
SSP1BUF.
value is copied to the ACKSTAT bit of the SSP1CON2
register. If ACKSTAT is set (not ACK), then the data 9. CKP bit is set releasing SCL, allowing the
transfer is complete. In this case, when the not ACK is master to clock the data out of the slave.
latched by the slave, the slave goes idle and waits for 10. SSP1IF is set after the ACK response from the
another occurrence of the Start bit. If the SDA line was master is loaded into the ACKSTAT register.
low (ACK), the next transmit data must be loaded into 11. SSP1IF bit is cleared.
the SSP1BUF register. Again, the SCL pin must be 12. The slave software checks the ACKSTAT bit to
released by setting bit CKP. see if the master wants to clock out more data.
An MSSP interrupt is generated for each data transfer Note 1: If the master ACKs the clock will be
byte. The SSP1IF bit must be cleared by software and stretched.
the SSP1STAT register is used to determine the status
of the byte. The SSP1IF bit is set on the falling edge of 2: ACKSTAT is the only bit updated on the
the ninth clock pulse. rising edge of SCL (9th) rather than the
falling.
32.5.3.1 Slave Mode Bus Collision 13. Steps 9-13 are repeated for each transmitted
A slave receives a read request and begins shifting byte.
data out on the SDA line. If a bus collision is detected 14. If the master sends a not ACK; the clock is not
and the SBCDE bit of the SSP1CON3 register is set, held, but SSP1IF is still set.
the BCL1IF bit of the PIR3 register is set. Once a bus 15. The master sends a Restart condition or a Stop.
collision is detected, the slave goes idle and waits to be
16. The slave is no longer addressed.
addressed again. User software can use the BCL1IF bit
to handle a slave bus collision.

 2017 Microchip Technology Inc. Preliminary DS40001897A-page 380

 FIGURE 32-18: I2C SLAVE, 7-BIT ADDRESS, TRANSMISSION (AHEN = 0)
 2017 Microchip Technology Inc.

Master sends
Stop condition

Receiving Address Automatic Transmitting Data Automatic Transmitting Data ACK

R/W = 1
SDA A7 A6 A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0

SCL
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S P

SSP1IF

Cleared by software

BF
BF is automatically
Received address Data to transmit is cleared after 8th falling
is read from SSP1BUF loaded into SSP1BUF edge of SCL
Preliminary

CKP
When R/W is set CKP is not
SCL is always held for not
held low after 9th SCL Set by software ACK
falling edge
ACKSTAT

PIC16(L)F15313/23
Masters not ACK
is copied to
ACKSTAT
R/W
R/W is copied from the
matching address byte
D/A

Indicates an address
has been received
DS40001897A-page 381

P
 PIC16(L)F15313/23
32.5.3.3 7-bit Transmission with Address
Hold Enabled
Setting the AHEN bit of the SSP1CON3 register
enables additional clock stretching and interrupt
generation after the eighth falling edge of a received
matching address. Once a matching address has
been clocked in, CKP is cleared and the SSP1IF
interrupt is set.
Figure 32-19 displays a standard waveform of a 7-bit
address slave transmission with AHEN enabled.
1. Bus starts Idle.
2. Master sends Start condition; the S bit of
SSP1STAT is set; SSP1IF is set if interrupt on
Start detect is enabled.
3. Master sends matching address with R/W bit
set. After the eighth falling edge of the SCL line
the CKP bit is cleared and SSP1IF interrupt is
generated.
4. Slave software clears SSP1IF.
5. Slave software reads ACKTIM bit of SSP1CON3
register, and R/W and D/A of the SSP1STAT
register to determine the source of the interrupt.
6. Slave reads the address value from the
SSP1BUF register clearing the BF bit.
7. Slave software decides from this information if it
wishes to ACK or not ACK and sets the ACKDT
bit of the SSP1CON2 register accordingly.
8. Slave sets the CKP bit releasing SCL.
9. Master clocks in the ACK value from the slave.
10. Slave hardware automatically clears the CKP bit
and sets SSP1IF after the ACK if the R/W bit is
set.
11. Slave software clears SSP1IF.
12. Slave loads value to transmit to the master into
SSP1BUF setting the BF bit.
Note: SSP1BUF cannot be loaded until after the
ACK.
13. Slave sets the CKP bit releasing the clock.
14. Master clocks out the data from the slave and
sends an ACK value on the ninth SCL pulse.
15. Slave hardware copies the ACK value into the
ACKSTAT bit of the SSP1CON2 register.
16. Steps 10-15 are repeated for each byte transmit-
ted to the master from the slave.
17. If the master sends a not ACK the slave
releases the bus allowing the master to send a
Stop and end the communication.
Note: Master must send a not ACK on the last
byte to ensure that the slave releases the
SCL line to receive a Stop.

 2017 Microchip Technology Inc. Preliminary DS40001897A-page 382

 FIGURE 32-19: I2C SLAVE, 7-BIT ADDRESS, TRANSMISSION (AHEN = 1)
 2017 Microchip Technology Inc.

Master sends
Master releases SDA Stop condition
to slave for ACK sequence
Receiving Address R/W = 1 Automatic Transmitting Data
Automatic Transmitting Data ACK
SDA ACK ACK
A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

SCL
S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
P

SSP1IF
Cleared by software

BF BF is automatically
Received address Data to transmit is cleared after 8th falling
is read from SSP1BUF loaded into SSP1BUF edge of SCL
Preliminary

ACKDT

Slave clears
ACKDT to ACK
address

ACKSTAT
Master’s ACK

PIC16(L)F15313/23
response is copied
to SSP1STAT
CKP
When AHEN = 1; CKP not cleared
CKP is cleared by hardware When R/W = 1; Set by software, after not ACK
after receiving matching CKP is always releases SCL
address. cleared after ACK

ACKTIM
ACKTIM is set on 8th falling ACKTIM is cleared
edge of SCL on 9th rising edge of SCL
DS40001897A-page 383

R/W

D/A
 PIC16(L)F15313/23
32.5.4 SLAVE MODE 10-BIT ADDRESS 32.5.5 10-BIT ADDRESSING WITH ADDRESS OR
RECEPTION DATA HOLD

This section describes a standard sequence of events Reception using 10-bit addressing with AHEN or
for the MSSP module configured as an I2C slave in DHEN set is the same as with 7-bit modes. The only
10-bit Addressing mode. difference is the need to update the SSP1ADD register
Figure 32-20 is used as a visual reference for this using the UA bit. All functionality, specifically when the
description. CKP bit is cleared and SCL line is held low are the
same. Figure 32-21 can be used as a reference of a
This is a step by step process of what must be done by slave in 10-bit addressing with AHEN set.
slave software to accomplish I2C communication.
Figure 32-22 shows a standard waveform for a slave
1. Bus starts Idle. transmitter in 10-bit Addressing mode.
2. Master sends Start condition; S bit of
SSP1STAT is set; SSP1IF is set if interrupt on
Start detect is enabled.
3. Master sends matching high address with R/W
bit clear; UA bit of the SSP1STAT register is set.
4. Slave sends ACK and SSP1IF is set.
5. Software clears the SSP1IF bit.
6. Software reads received address from
SSP1BUF clearing the BF flag.
7. Slave loads low address into SSP1ADD,
releasing SCL.
8. Master sends matching low address byte to the
slave; UA bit is set.
Note: Updates to the SSP1ADD register are not
allowed until after the ACK sequence.

9. Slave sends ACK and SSP1IF is set.

Note: If the low address does not match, SSP1IF
and UA are still set so that the slave
software can set SSP1ADD back to the high
address. BF is not set because there is no
match. CKP is unaffected.
10. Slave clears SSP1IF.
11. Slave reads the received matching address
from SSP1BUF clearing BF.
12. Slave loads high address into SSP1ADD.
13. Master clocks a data byte to the slave and
clocks out the slaves ACK on the ninth SCL
pulse; SSP1IF is set.
14. If SEN bit of SSP1CON2 is set, CKP is cleared
by hardware and the clock is stretched.
15. Slave clears SSP1IF.
16. Slave reads the received byte from SSP1BUF
clearing BF.
17. If SEN is set the slave sets CKP to release the
SCL.
18. Steps 13-17 repeat for each received byte.
19. Master sends Stop to end the transmission.

 2017 Microchip Technology Inc. Preliminary DS40001897A-page 384

 FIGURE 32-20: I2C SLAVE, 10-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 0, DHEN = 0)
 2017 Microchip Technology Inc.

Master sends
Stop condition

Receive First Address Byte Receive Second Address Byte Receive Data Receive Data
SDA
1 1 1 1
0 A9 A8 ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK

SCL
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P
S
SCL is held low
while CKP = 0

SSP1IF
Set by hardware Cleared by software
Preliminary

on 9th falling edge

BF
If address matches Receive address is Data is read
SSP1ADD it is loaded into read from SSP1BUF from SSP1BUF
SSP1BUF

PIC16(L)F15313/23
UA
When UA = 1; Software updates SSP1ADD
SCL is held low and releases SCL

CKP

When SEN = 1; Set by software,

DS40001897A-page 385

CKP is cleared after releasing SCL

9th falling edge of received byte
 FIGURE 32-21: I2C SLAVE, 10-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 1, DHEN = 0)
 2017 Microchip Technology Inc.

Receive First Address Byte R/W = 0 Receive Second Address Byte Receive Data Receive Data
SDA 1 1 1 1 0 A9 A8 ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5

SCL S 1 2 3 4 5 6 7 8 9 UA 1 2 3 4 5 6 7 8 9 UA 1 2 3 4 5 6 7 8 9 1 2

SSP1IF
Set by hardware Cleared by software Cleared by software
on 9th falling edge

BF
Preliminary

SSP1BUF can be Received data

read anytime before is read from
the next received byte SSP1BUF
ACKDT
Slave software clears
ACKDT to ACK

PIC16(L)F15313/23
the received byte

UA

Update to SSP1ADD is Update of SSP1ADD,

not allowed until 9th
clears UA and releases
falling edge of SCL
SCL

CKP If when AHEN = 1;

on the 8th falling edge
DS40001897A-page 386

Set CKP with software

of SCL of an address releases SCL
byte, CKP is cleared
ACKTIM
ACKTIM is set by hardware
on 8th falling edge of SCL
 FIGURE 32-22: I2C SLAVE, 10-BIT ADDRESS, TRANSMISSION (SEN = 0, AHEN = 0, DHEN = 0)
 2017 Microchip Technology Inc.

Master sends
Master sends Stop condition
Restart event Master sends
not ACK

Receiving Address R/W = 0 Receiving Second Address Byte Receive First Address Byte Transmitting Data Byte ACK = 1
SDA 1 1 1 1 0 A9 A8 ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK 1 1 1 1 0 A9 A8 ACK D7 D6 D5 D4 D3 D2 D1 D0

SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P
S
Sr

SSP1IF

Set by hardware Cleared by software Set by hardware

Preliminary

BF

SSP1BUF loaded Received address is Data to transmit is

with received address read from SSP1BUF loaded into SSP1BUF
UA
High address is loaded
UA indicates SSP1ADD After SSP1ADD is back into SSP1ADD

PIC16(L)F15313/23
must be updated updated, UA is cleared
CKP and SCL is released

When R/W = 1; Set by software

ACKSTAT CKP is cleared on releases SCL
9th falling edge of SCL

Masters not ACK

is copied
R/W
R/W is copied from the
matching address byte
DS40001897A-page 387

D/A

Indicates an address
has been received
 PIC16(L)F15313/23
32.5.6 CLOCK STRETCHING 32.5.6.3 Byte NACKing
Clock stretching occurs when a device on the bus When AHEN bit of SSP1CON3 is set; CKP is cleared
holds the SCL line low, effectively pausing communi- by hardware after the eighth falling edge of SCL for a
cation. The slave may stretch the clock to allow more received matching address byte. When DHEN bit of
time to handle data or prepare a response for the SSP1CON3 is set; CKP is cleared after the eighth fall-
master device. A master device is not concerned with ing edge of SCL for received data.
stretching as anytime it is active on the bus and not Stretching after the eighth falling edge of SCL allows
transferring data it is stretching. Any stretching done the slave to look at the received address or data and
by a slave is invisible to the master software and decide if it wants to ACK the received data.
handled by the hardware that generates SCL.
The CKP bit of the SSP1CON1 register is used to 32.5.7 CLOCK SYNCHRONIZATION AND THE
control stretching in software. Any time the CKP bit is CKP BIT
cleared, the module will wait for the SCL line to go low Any time the CKP bit is cleared, the module will wait
and then hold it. Setting CKP will release SCL and for the SCL line to go low and then hold it. However,
allow more communication. clearing the CKP bit will not assert the SCL output low
32.5.6.1 Normal Clock Stretching until the SCL output is already sampled low. There-
fore, the CKP bit will not assert the SCL line until an
Following an ACK if the R/W bit of SSP1STAT is set, a external I2C master device has already asserted the
read request, the slave hardware will clear CKP. This SCL line. The SCL output will remain low until the CKP
allows the slave time to update SSP1BUF with data to bit is set and all other devices on the I2C bus have
transfer to the master. If the SEN bit of SSP1CON2 is released SCL. This ensures that a write to the CKP bit
set, the slave hardware will always stretch the clock will not violate the minimum high time requirement for
after the ACK sequence. Once the slave is ready; CKP SCL (see Figure 32-23).
is set by software and communication resumes.

32.5.6.2 10-bit Addressing Mode

In 10-bit Addressing mode, when the UA bit is set the

clock is always stretched. This is the only time the SCL
is stretched without CKP being cleared. SCL is
released immediately after a write to SSP1ADD.

FIGURE 32-23: CLOCK SYNCHRONIZATION TIMING

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

SDA DX DX ‚ – 1

SCL

Master device
CKP asserts clock

Master device
releases clock
WR
SSP1CON1

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 PIC16(L)F15313/23
32.5.8 GENERAL CALL ADDRESS SUPPORT In 10-bit Address mode, the UA bit will not be set on
the reception of the general call address. The slave
The addressing procedure for the I2C bus is such that will prepare to receive the second byte as data, just as
the first byte after the Start condition usually deter- it would in 7-bit mode.
mines which device will be the slave addressed by the
master device. The exception is the general call If the AHEN bit of the SSP1CON3 register is set, just
address which can address all devices. When this as with any other address reception, the slave hard-
address is used, all devices should, in theory, respond ware will stretch the clock after the eighth falling edge
with an acknowledge. of SCL. The slave must then set its ACKDT value and
release the clock with communication progressing as it
The general call address is a reserved address in the would normally.
I2C protocol, defined as address 0x00. When the
GCEN bit of the SSP1CON2 register is set, the slave
module will automatically ACK the reception of this
address regardless of the value stored in SSP1ADD.
After the slave clocks in an address of all zeros with
the R/W bit clear, an interrupt is generated and slave
software can read SSP1BUF and respond.
Figure 32-24 shows a general call reception
sequence.

FIGURE 32-24: SLAVE MODE GENERAL CALL ADDRESS SEQUENCE

Address is compared to General Call Address
after ACK, set interrupt

R/W = 0 Receiving Data ACK

General Call Address ACK D7
SDA D6 D5 D4 D3 D2 D1 D0

SCL
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S

SSP1IF

BF (SSP1STAT<0>)

Cleared by software
SSP1BUF is read
GCEN (SSP1CON2<7>)
’1’

32.5.9 SSP MASK REGISTER This register is reset to all ‘1’s upon any Reset
condition and, therefore, has no effect on standard
An SSP Mask (SSP1MSK) register (Register 32-5) is SSP operation until written with a mask value.
available in I2C Slave mode as a mask for the value
held in the SSP1SR register during an address The SSP Mask register is active during:
comparison operation. A zero (‘0’) bit in the SSP1MSK • 7-bit Address mode: address compare of A<7:1>.
register has the effect of making the corresponding bit • 10-bit Address mode: address compare of A<7:0>
of the received address a “don’t care”. only. The SSP mask has no effect during the
reception of the first (high) byte of the address.

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 PIC16(L)F15313/23
32.6 I2C Master Mode 32.6.1 I2C MASTER MODE OPERATION

Master mode is enabled by setting and clearing the The master device generates all of the serial clock
appropriate SSPM bits in the SSP1CON1 register and pulses and the Start and Stop conditions. A transfer is
by setting the SSPEN bit. In Master mode, the SDA and ended with a Stop condition or with a Repeated Start
SCK pins must be configured as inputs. The MSSP condition. Since the Repeated Start condition is also
peripheral hardware will override the output driver TRIS the beginning of the next serial transfer, the I2C bus will
controls when necessary to drive the pins low. not be released.
Master mode of operation is supported by interrupt In Master Transmitter mode, serial data is output
generation on the detection of the Start and Stop through SDA, while SCL outputs the serial clock. The
conditions. The Stop (P) and Start (S) bits are cleared first byte transmitted contains the slave address of the
from a Reset or when the MSSP module is disabled. receiving device (7 bits) and the Read/Write (R/W) bit.
Control of the I 2C bus may be taken when the P bit is In this case, the R/W bit will be logic ‘0’. Serial data is
set, or the bus is Idle. transmitted eight bits at a time. After each byte is
transmitted, an Acknowledge bit is received. Start and
In Firmware Controlled Master mode, user code
Stop conditions are output to indicate the beginning
conducts all I 2C bus operations based on Start and
and the end of a serial transfer.
Stop bit condition detection. Start and Stop condition
detection is the only active circuitry in this mode. All In Master Receive mode, the first byte transmitted
other communication is done by the user software contains the slave address of the transmitting device
directly manipulating the SDA and SCL lines. (7 bits) and the R/W bit. In this case, the R/W bit will be
logic ‘1’. Thus, the first byte transmitted is a 7-bit slave
The following events will cause the SSP Interrupt Flag address followed by a ‘1’ to indicate the receive bit.
bit, SSP1IF, to be set (SSP interrupt, if enabled): Serial data is received via SDA, while SCL outputs the
• Start condition generated serial clock. Serial data is received eight bits at a time.
• Stop condition generated After each byte is received, an Acknowledge bit is
transmitted. Start and Stop conditions indicate the
• Data transfer byte transmitted/received
beginning and end of transmission.
• Acknowledge transmitted/received
A Baud Rate Generator is used to set the clock
• Repeated Start generated
frequency output on SCL. See Section 32.7 “Baud
Note 1: The MSSP module, when configured in Rate Generator” for more detail.
I2C Master mode, does not allow queuing
of events. For instance, the user is not
allowed to initiate a Start condition and
immediately write the SSP1BUF register
to initiate transmission before the Start
condition is complete. In this case, the
SSP1BUF will not be written to and the
WCOL bit will be set, indicating that a
write to the SSP1BUF did not occur
2: When in Master mode, Start/Stop
detection is masked and an interrupt is
generated when the SEN/PEN bit is
cleared and the generation is complete.

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 PIC16(L)F15313/23
32.6.2 CLOCK ARBITRATION

Clock arbitration occurs when the master, during any

receive, transmit or Repeated Start/Stop condition,
releases the SCL pin (SCL allowed to float high). When
the SCL pin is allowed to float high, the Baud Rate
Generator (BRG) is suspended from counting until the
SCL pin is actually sampled high. When the SCL pin is
sampled high, the Baud Rate Generator is reloaded
with the contents of SSP1ADD<7:0> and begins count-
ing. This ensures that the SCL high time will always be
at least one BRG rollover count in the event that the
clock is held low by an external device (Figure 32-25).

FIGURE 32-25: BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION

SDA DX DX ‚ – 1

SCL deasserted but slave holds SCL allowed to transition high

SCL low (clock arbitration)
SCL

BRG decrements on
Q2 and Q4 cycles

BRG
03h 02h 01h 00h (hold off) 03h 02h
Value

SCL is sampled high, reload takes

place and BRG starts its count
BRG
Reload

32.6.3 WCOL STATUS FLAG

If the user writes the SSP1BUF when a Start, Restart,

Stop, Receive or Transmit sequence is in progress, the
WCOL is set and the contents of the buffer are
unchanged (the write does not occur). Any time the
WCOL bit is set it indicates that an action on SSP1BUF
was attempted while the module was not idle.
Note: Because queuing of events is not allowed,
writing to the lower five bits of SSP1CON2
is disabled until the Start condition is
complete.

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 PIC16(L)F15313/23
32.6.4 I2C MASTER MODE START
CONDITION TIMING Note 1: If at the beginning of the Start condition,
To initiate a Start condition (Figure 32-26), the user the SDA and SCL pins are already
sets the Start Enable bit, SEN bit of the SSP1CON2 sampled low, or if during the Start condi-
register. If the SDA and SCL pins are sampled high, tion, the SCL line is sampled low before
the Baud Rate Generator is reloaded with the contents the SDA line is driven low, a bus collision
of SSP1ADD<7:0> and starts its count. If SCL and occurs, the Bus Collision Interrupt Flag,
SDA are both sampled high when the Baud Rate Gen- BCLIF, is set, the Start condition is
erator times out (TBRG), the SDA pin is driven low. The aborted and the I2C module is reset into
action of the SDA being driven low while SCL is high is its Idle state.
the Start condition and causes the S bit of the 2: The Philips I2C specification states that a
SSP1STAT1 register to be set. Following this, the bus collision cannot occur on a Start.
Baud Rate Generator is reloaded with the contents of
SSP1ADD<7:0> and resumes its count. When the
Baud Rate Generator times out (TBRG), the SEN bit of
the SSP1CON2 register will be automatically cleared
by hardware; the Baud Rate Generator is suspended,
leaving the SDA line held low and the Start condition is
complete.

FIGURE 32-26: FIRST START BIT TIMING

Write to SEN bit occurs here Set S bit (SSP1STAT<3>)

At completion of Start bit,

SDA = 1,
SCL = 1 hardware clears SEN bit
and sets SSP1IF bit
TBRG TBRG Write to SSP1BUF occurs here
SDA 1st bit 2nd bit

TBRG
SCL
S
TBRG

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 PIC16(L)F15313/23
32.6.5 I2C MASTER MODE REPEATED cally cleared and the Baud Rate Generator will not be
START CONDITION TIMING reloaded, leaving the SDA pin held low. As soon as a
Start condition is detected on the SDA and SCL pins,
A Repeated Start condition (Figure 32-27) occurs when the S bit of the SSP1STAT register will be set. The
the RSEN bit of the SSP1CON2 register is pro- SSP1IF bit will not be set until the Baud Rate Generator
grammed high and the master state machine is no lon- has timed out.
ger active. When the RSEN bit is set, the SCL pin is
asserted low. When the SCL pin is sampled low, the Note 1: If RSEN is programmed while any other
Baud Rate Generator is loaded and begins counting. event is in progress, it will not take effect.
The SDA pin is released (brought high) for one Baud 2: A bus collision during the Repeated Start
Rate Generator count (TBRG). When the Baud Rate condition occurs if:
Generator times out, if SDA is sampled high, the SCL
pin will be deasserted (brought high). When SCL is • SDA is sampled low when SCL
sampled high, the Baud Rate Generator is reloaded goes from low-to-high.
and begins counting. SDA and SCL must be sampled • SCL goes low before SDA is
high for one TBRG. This action is then followed by asserted low. This may indicate
assertion of the SDA pin (SDA = 0) for one TBRG while that another master is attempting
SCL is high. SCL is asserted low. Following this, the to transmit a data ‘1’.
RSEN bit of the SSP1CON2 register will be automati-

FIGURE 32-27: REPEATED START CONDITION WAVEFORM

S bit set by hardware

Write to SSP1CON2
occurs here At completion of Start bit,
SDA = 1, SDA = 1,
hardware clears RSEN bit
SCL (no change) SCL = 1 and sets SSP1IF

TBRG TBRG TBRG

SDA 1st bit

Write to SSP1BUF occurs here

TBRG
SCL
Sr TBRG
Repeated Start

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 PIC16(L)F15313/23
32.6.6 I2C MASTER MODE TRANSMISSION 32.6.6.3 ACKSTAT Status Flag
Transmission of a data byte, a 7-bit address or the In Transmit mode, the ACKSTAT bit of the SSP1CON2
other half of a 10-bit address is accomplished by simply register is cleared when the slave has sent an Acknowl-
writing a value to the SSP1BUF register. This action will edge (ACK = 0) and is set when the slave does not
set the Buffer Full flag bit, BF, and allow the Baud Rate Acknowledge (ACK = 1). A slave sends an Acknowl-
Generator to begin counting and start the next trans- edge when it has recognized its address (including a
mission. Each bit of address/data will be shifted out general call), or when the slave has properly received
onto the SDA pin after the falling edge of SCL is its data.
asserted. SCL is held low for one Baud Rate Generator
32.6.6.4 Typical transmit sequence:
rollover count (TBRG). Data should be valid before SCL
is released high. When the SCL pin is released high, it 1. The user generates a Start condition by setting
is held that way for TBRG. The data on the SDA pin the SEN bit of the SSP1CON2 register.
must remain stable for that duration and some hold 2. SSP1IF is set by hardware on completion of the
time after the next falling edge of SCL. After the eighth Start.
bit is shifted out (the falling edge of the eighth clock),
3. SSP1IF is cleared by software.
the BF flag is cleared and the master releases SDA.
This allows the slave device being addressed to 4. The MSSP module will wait the required start
respond with an ACK bit during the ninth bit time if an time before any other operation takes place.
address match occurred, or if data was received prop- 5. The user loads the SSP1BUF with the slave
erly. The status of ACK is written into the ACKSTAT bit address to transmit.
on the rising edge of the ninth clock. If the master 6. Address is shifted out the SDA pin until all eight
receives an Acknowledge, the Acknowledge Status bit, bits are transmitted. Transmission begins as
ACKSTAT, is cleared. If not, the bit is set. After the ninth soon as SSP1BUF is written to.
clock, the SSP1IF bit is set and the master clock (Baud 7. The MSSP module shifts in the ACK bit from the
Rate Generator) is suspended until the next data byte slave device and writes its value into the
is loaded into the SSP1BUF, leaving SCL low and SDA ACKSTAT bit of the SSP1CON2 register.
unchanged (Figure 32-28). 8. The MSSP module generates an interrupt at the
After the write to the SSP1BUF, each bit of the address end of the ninth clock cycle by setting the
will be shifted out on the falling edge of SCL until all SSP1IF bit.
seven address bits and the R/W bit are completed. On 9. The user loads the SSP1BUF with eight bits of
the falling edge of the eighth clock, the master will data.
release the SDA pin, allowing the slave to respond with 10. Data is shifted out the SDA pin until all eight bits
an Acknowledge. On the falling edge of the ninth clock, are transmitted.
the master will sample the SDA pin to see if the address
11. The MSSP module shifts in the ACK bit from the
was recognized by a slave. The status of the ACK bit is
slave device and writes its value into the
loaded into the ACKSTAT Status bit of the SSP1CON2
ACKSTAT bit of the SSP1CON2 register.
register. Following the falling edge of the ninth clock
transmission of the address, the SSP1IF is set, the BF 12. Steps 8-11 are repeated for all transmitted data
flag is cleared and the Baud Rate Generator is turned bytes.
off until another write to the SSP1BUF takes place, 13. The user generates a Stop or Restart condition
holding SCL low and allowing SDA to float. by setting the PEN or RSEN bits of the
SSP1CON2 register. Interrupt is generated
32.6.6.1 BF Status Flag once the Stop/Restart condition is complete.
In Transmit mode, the BF bit of the SSP1STAT register
is set when the CPU writes to SSP1BUF and is cleared
when all eight bits are shifted out.

32.6.6.2 WCOL Status Flag

If the user writes the SSP1BUF when a transmit is
already in progress (i.e., SSP1SR is still shifting out a
data byte), the WCOL bit is set and the contents of the
buffer are unchanged (the write does not occur).
WCOL must be cleared by software before the next
transmission.

 2017 Microchip Technology Inc. Preliminary DS40001897A-page 394

 FIGURE 32-28: I2C MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS)
 2017 Microchip Technology Inc.

Write SSP1CON2<0> SEN = 1 ACKSTAT in

Start condition begins SSP1CON2 = 1
From slave, clear ACKSTAT bit SSP1CON2<6>
SEN = 0
Transmitting Data or Second Half
Transmit Address to Slave R/W = 0
of 10-bit Address ACK

SDA A7 A6 A5 A4 A3 A2 A1 ACK = 0 D7 D6 D5 D4 D3 D2 D1 D0

SSP1BUF written with 7-bit address and R/W

start transmit
SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S P
SCL held low
while CPU
responds to SSP1IF
Preliminary

SSP1IF
Cleared by software service routine
Cleared by software from SSP interrupt
Cleared by software

BF (SSP1STAT<0>)

PIC16(L)F15313/23
SSP1BUF written SSP1BUF is written by software
SEN

After Start condition, SEN cleared by hardware

PEN
DS40001897A-page 395

R/W
 PIC16(L)F15313/23
32.6.7 I2C MASTER MODE RECEPTION 32.6.7.4 Typical Receive Sequence:
Master mode reception (Figure 32-29) is enabled by 1. The user generates a Start condition by setting
programming the Receive Enable bit, RCEN bit of the the SEN bit of the SSP1CON2 register.
SSP1CON2 register. 2. SSP1IF is set by hardware on completion of the
Note: The MSSP module must be in an Idle Start.
state before the RCEN bit is set or the 3. SSP1IF is cleared by software.
RCEN bit will be disregarded. 4. User writes SSP1BUF with the slave address to
The Baud Rate Generator begins counting and on each transmit and the R/W bit set.
rollover, the state of the SCL pin changes 5. Address is shifted out the SDA pin until all eight
(high-to-low/low-to-high) and data is shifted into the bits are transmitted. Transmission begins as
SSP1SR. After the falling edge of the eighth clock, the soon as SSP1BUF is written to.
receive enable flag is automatically cleared, the 6. The MSSP module shifts in the ACK bit from the
contents of the SSP1SR are loaded into the SSP1BUF, slave device and writes its value into the
the BF flag bit is set, the SSP1IF flag bit is set and the ACKSTAT bit of the SSP1CON2 register.
Baud Rate Generator is suspended from counting, 7. The MSSP module generates an interrupt at the
holding SCL low. The MSSP is now in Idle state end of the ninth clock cycle by setting the
awaiting the next command. When the buffer is read by SSP1IF bit.
the CPU, the BF flag bit is automatically cleared. The 8. User sets the RCEN bit of the SSP1CON2
user can then send an Acknowledge bit at the end of register and the master clocks in a byte from the
reception by setting the Acknowledge Sequence slave.
Enable, ACKEN bit of the SSP1CON2 register.
9. After the eighth falling edge of SCL, SSP1IF and
32.6.7.1 BF Status Flag BF are set.
10. Master clears SSP1IF and reads the received
In receive operation, the BF bit is set when an address
byte from SSP1BUF, clears BF.
or data byte is loaded into SSP1BUF from SSP1SR. It
is cleared when the SSP1BUF register is read. 11. Master sets ACK value sent to slave in ACKDT
bit of the SSP1CON2 register and initiates the
32.6.7.2 SSPOV Status Flag ACK by setting the ACKEN bit.
In receive operation, the SSPOV bit is set when eight 12. Master’s ACK is clocked out to the slave and
bits are received into the SSP1SR and the BF flag bit is SSP1IF is set.
already set from a previous reception. 13. User clears SSP1IF.
14. Steps 8-13 are repeated for each received byte
32.6.7.3 WCOL Status Flag from the slave.
If the user writes the SSP1BUF when a receive is 15. Master sends a not ACK or Stop to end
already in progress (i.e., SSP1SR is still shifting in a communication.
data byte), the WCOL bit is set and the contents of the
buffer are unchanged (the write does not occur).

 2017 Microchip Technology Inc. Preliminary DS40001897A-page 396

 FIGURE 32-29: I2C MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS)
 2017 Microchip Technology Inc.

Write to SSP1CON2<4>
to start Ackno1wledge sequence
SDA = ACKDT (SSP1CON2<5>) = 0
Write to SSP1CON2<0>(SEN = 1),
begin Start condition ACK from Master Set ACKEN, start Acknowledge sequence
Master configured as a receiver SDA = ACKDT = 0 SDA = ACKDT = 1
SEN = 0 by programming SSP1CON2<3> (RCEN = 1)
PEN bit = 1
Write to SSP1BUF occurs here, RCEN cleared RCEN = 1, start RCEN cleared
ACK from Slave next receive automatically written here
start XMIT automatically
Transmit Address to Slave Receiving Data from Slave Receiving Data from Slave
SDA A7 A6 A5 A4 A3 A2 A1 R/W ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK

Bus master
ACK is not sent terminates
transfer
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
SCL S P
Data shifted in on falling edge of CLK Set SSP1IF at end
of receive Set SSP1IF interrupt
Set SSP1IF interrupt at end of Acknow-
Set SSP1IF interrupt ledge sequence
at end of receive
Preliminary

at end of Acknowledge
SSP1IF sequence

Set P bit
Cleared by software Cleared by software Cleared by software Cleared by software (SSP1STAT<4>)
SDA = 0, SCL = 1 Cleared in
while CPU software and SSP1IF
responds to SSP1IF

BF
(SSP1STAT<0>) Last bit is shifted into SSP1SR and

PIC16(L)F15313/23
contents are unloaded into SSP1BUF

SSPOV

SSPOV is set because

SSP1BUF is still full

ACKEN
DS40001897A-page 397

RCEN

Master configured as a receiver RCEN cleared ACK from Master RCEN cleared
by programming SSP1CON2<3> (RCEN = 1) automatically SDA = ACKDT = 0 automatically
 PIC16(L)F15313/23
32.6.8 ACKNOWLEDGE SEQUENCE 32.6.9 STOP CONDITION TIMING
TIMING A Stop bit is asserted on the SDA pin at the end of a
An Acknowledge sequence is enabled by setting the receive/transmit by setting the Stop Sequence Enable
Acknowledge Sequence Enable bit, ACKEN bit of the bit, PEN bit of the SSP1CON2 register. At the end of a
SSP1CON2 register. When this bit is set, the SCL pin is receive/transmit, the SCL line is held low after the
pulled low and the contents of the Acknowledge data bit falling edge of the ninth clock. When the PEN bit is set,
are presented on the SDA pin. If the user wishes to the master will assert the SDA line low. When the SDA
generate an Acknowledge, then the ACKDT bit should line is sampled low, the Baud Rate Generator is
be cleared. If not, the user should set the ACKDT bit reloaded and counts down to ‘0’. When the Baud Rate
before starting an Acknowledge sequence. The Baud Generator times out, the SCL pin will be brought high
Rate Generator then counts for one rollover period and one TBRG (Baud Rate Generator rollover count)
(TBRG) and the SCL pin is deasserted (pulled high). later, the SDA pin will be deasserted. When the SDA
When the SCL pin is sampled high (clock arbitration), pin is sampled high while SCL is high, the P bit of the
the Baud Rate Generator counts for TBRG. The SCL pin SSP1STAT register is set. A TBRG later, the PEN bit is
is then pulled low. Following this, the ACKEN bit is auto- cleared and the SSP1IF bit is set (Figure 32-31).
matically cleared, the Baud Rate Generator is turned off
and the MSSP module then goes into IDLE mode 32.6.9.1 WCOL Status Flag
(Figure 32-30). If the user writes the SSP1BUF when a Stop sequence
is in progress, then the WCOL bit is set and the
32.6.8.1 WCOL Status Flag contents of the buffer are unchanged (the write does
If the user writes the SSP1BUF when an Acknowledge not occur).
sequence is in progress, then WCOL bit is set and the
contents of the buffer are unchanged (the write does
not occur).
FIGURE 32-30: ACKNOWLEDGE SEQUENCE WAVEFORM
Acknowledge sequence starts here, ACKEN automatically cleared
write to SSP1CON2
ACKEN = 1, ACKDT = 0
TBRG TBRG
SDA D0 ACK

SCL 8 9

SSP1IF

Cleared in
SSP1IF set at software
the end of receive Cleared in
software SSP1IF set at the end
of Acknowledge sequence
Note: TBRG = one Baud Rate Generator period.

FIGURE 32-31: STOP CONDITION RECEIVE OR TRANSMIT MODE

Write to SSP1CON2, SCL = 1 for TBRG, followed by SDA = 1 for TBRG
set PEN after SDA sampled high. P bit (SSP1STAT<4>) is set.

Falling edge of PEN bit (SSP1CON2<2>) is cleared by

9th clock hardware and the SSP1IF bit is set
TBRG
SCL

SDA ACK

P
TBRG TBRG TBRG
SCL brought high after TBRG
SDA asserted low before rising edge of clock
to setup Stop condition

Note: TBRG = one Baud Rate Generator period.

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32.6.10 SLEEP OPERATION 32.6.13 MULTI -MASTER COMMUNICATION,
2
While in Sleep mode, the I C slave module can receive BUS COLLISION AND BUS
addresses or data and when an address match or ARBITRATION
complete byte transfer occurs, wake the processor Multi-Master mode support is achieved by bus arbitra-
from Sleep (if the MSSP interrupt is enabled). tion. When the master outputs address/data bits onto
the SDA pin, arbitration takes place when the master
32.6.11 EFFECTS OF A RESET outputs a ‘1’ on SDA, by letting SDA float high and
A Reset disables the MSSP module and terminates the another master asserts a ‘0’. When the SCL pin floats
current transfer. high, data should be stable. If the expected data on
SDA is a ‘1’ and the data sampled on the SDA pin is ‘0’,
32.6.12 MULTI-MASTER MODE then a bus collision has taken place. The master will set
In Multi-Master mode, the interrupt generation on the the Bus Collision Interrupt Flag, BCL1IF and reset the
detection of the Start and Stop conditions allows the I2C port to its Idle state (Figure 32-32).
determination of when the bus is free. The Stop (P) and If a transmit was in progress when the bus collision
Start (S) bits are cleared from a Reset or when the occurred, the transmission is halted, the BF flag is
MSSP module is disabled. Control of the I 2C bus may cleared, the SDA and SCL lines are deasserted and the
be taken when the P bit of the SSP1STAT register is SSP1BUF can be written to. When the user services
set, or the bus is Idle, with both the S and P bits clear. the bus collision Interrupt Service Routine and if the I2C
When the bus is busy, enabling the SSP interrupt will bus is free, the user can resume communication by
generate the interrupt when the Stop condition occurs. asserting a Start condition.
In multi-master operation, the SDA line must be If a Start, Repeated Start, Stop or Acknowledge
monitored for arbitration to see if the signal level is the condition was in progress when the bus collision
expected output level. This check is performed by occurred, the condition is aborted, the SDA and SCL
hardware with the result placed in the BCL1IF bit. lines are deasserted and the respective control bits in
The states where arbitration can be lost are: the SSP1CON2 register are cleared. When the user
services the bus collision Interrupt Service Routine and
• Address Transfer if the I2C bus is free, the user can resume
• Data Transfer communication by asserting a Start condition.
• A Start Condition The master will continue to monitor the SDA and SCL
• A Repeated Start Condition pins. If a Stop condition occurs, the SSP1IF bit will be set.
• An Acknowledge Condition A write to the SSP1BUF will start the transmission of
data at the first data bit, regardless of where the
transmitter left off when the bus collision occurred.
In Multi-Master mode, the interrupt generation on the
detection of Start and Stop conditions allows the
determination of when the bus is free. Control of the I2C
bus can be taken when the P bit is set in the SSP1STAT
register, or the bus is Idle and the S and P bits are
cleared.

FIGURE 32-32: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE

Sample SDA. While SCL is high,
Data changes SDA line pulled low data does not match what is driven
while SCL = 0 by another source by the master.
Bus collision has occurred.
SDA released
by master

SDA

SCL Set bus collision

interrupt (BCL1IF)

BCL1IF

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 PIC16(L)F15313/23
32.6.13.1 Bus Collision During a Start If the SDA pin is sampled low during this count, the
Condition BRG is reset and the SDA line is asserted early
(Figure 32-35). If, however, a ‘1’ is sampled on the SDA
During a Start condition, a bus collision occurs if:
pin, the SDA pin is asserted low at the end of the BRG
a) SDA or SCL are sampled low at the beginning of count. The Baud Rate Generator is then reloaded and
the Start condition (Figure 32-33). counts down to zero; if the SCL pin is sampled as ‘0’
b) SCL is sampled low before SDA is asserted low during this time, a bus collision does not occur. At the
(Figure 32-34). end of the BRG count, the SCL pin is asserted low.
During a Start condition, both the SDA and the SCL Note: The reason that bus collision is not a
pins are monitored. factor during a Start condition is that no
If the SDA pin is already low, or the SCL pin is already two bus masters can assert a Start condi-
low, then all of the following occur: tion at the exact same time. Therefore,
one master will always assert SDA before
• the Start condition is aborted,
the other. This condition does not cause a
• the BCL1IF flag is set and bus collision because the two masters
• the MSSP module is reset to its Idle state must be allowed to arbitrate the first
(Figure 32-33). address following the Start condition. If the
The Start condition begins with the SDA and SCL pins address is the same, arbitration must be
deasserted. When the SDA pin is sampled high, the allowed to continue into the data portion,
Baud Rate Generator is loaded and counts down. If the Repeated Start or Stop conditions.
SCL pin is sampled low while SDA is high, a bus
collision occurs because it is assumed that another
master is attempting to drive a data ‘1’ during the Start
condition.

FIGURE 32-33: BUS COLLISION DURING START CONDITION (SDA ONLY)

SDA goes low before the SEN bit is set.
Set BCL1IF,
S bit and SSP1IF set because
SDA = 0, SCL = 1.

SDA

SCL
Set SEN, enable Start SEN cleared automatically because of bus collision.
condition if SDA = 1, SCL = 1 SSP module reset into Idle state.
SEN
SDA sampled low before
Start condition. Set BCL1IF.
S bit and SSP1IF set because
BCL1IF SDA = 0, SCL = 1.
SSP1IF and BCL1IF are
cleared by software

SSP1IF

SSP1IF and BCL1IF are

cleared by software

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 PIC16(L)F15313/23
FIGURE 32-34: BUS COLLISION DURING START CONDITION (SCL = 0)
SDA = 0, SCL = 1

TBRG TBRG

SDA

SCL Set SEN, enable Start

sequence if SDA = 1, SCL = 1
SCL = 0 before SDA = 0,
bus collision occurs. Set BCL1IF.
SEN
SCL = 0 before BRG time-out,
bus collision occurs. Set BCL1IF.
BCL1IF
Interrupt cleared
by software
S ’0’ ’0’

SSP1IF ’0’ ’0’

FIGURE 32-35: BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION
SDA = 0, SCL = 1
Set S Set SSP1IF
Less than TBRG
TBRG

SDA SDA pulled low by other master.

Reset BRG and assert SDA.

SCL S
SCL pulled low after BRG
time-out
SEN
Set SEN, enable Start
sequence if SDA = 1, SCL = 1
BCL1IF ’0’

SSP1IF
SDA = 0, SCL = 1, Interrupts cleared
set SSP1IF by software

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 PIC16(L)F15313/23
32.6.13.2 Bus Collision During a Repeated counting. If SDA goes from high-to-low before the BRG
Start Condition times out, no bus collision occurs because no two
masters can assert SDA at exactly the same time.
During a Repeated Start condition, a bus collision
occurs if: If SCL goes from high-to-low before the BRG times out
and SDA has not already been asserted, a bus collision
a) A low level is sampled on SDA when SCL goes
occurs. In this case, another master is attempting to
from low level to high level (Case 1).
transmit a data ‘1’ during the Repeated Start condition,
b) SCL goes low before SDA is asserted low, see Figure 32-37.
indicating that another master is attempting to
transmit a data ‘1’ (Case 2). If, at the end of the BRG time-out, both SCL and SDA
are still high, the SDA pin is driven low and the BRG is
When the user releases SDA and the pin is allowed to reloaded and begins counting. At the end of the count,
float high, the BRG is loaded with SSP1ADD and regardless of the status of the SCL pin, the SCL pin is
counts down to zero. The SCL pin is then deasserted driven low and the Repeated Start condition is
and when sampled high, the SDA pin is sampled. complete.
If SDA is low, a bus collision has occurred (i.e., another
master is attempting to transmit a data ‘0’, Figure 32-36).
If SDA is sampled high, the BRG is reloaded and begins

FIGURE 32-36: BUS COLLISION DURING A REPEATED START CONDITION (CASE 1)

SDA

SCL

Sample SDA when SCL goes high.

If SDA = 0, set BCL1IF and release SDA and SCL.

RSEN

BCL1IF

Cleared by software
S ’0’

SSP1IF ’0’

FIGURE 32-37: BUS COLLISION DURING REPEATED START CONDITION (CASE 2)

TBRG TBRG

SDA

SCL

SCL goes low before SDA,

BCL1IF set BCL1IF. Release SDA and SCL.
Interrupt cleared
by software
RSEN

S ’0’

SSP1IF

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32.6.13.3 Bus Collision During a Stop The Stop condition begins with SDA asserted low.
Condition When SDA is sampled low, the SCL pin is allowed to
float. When the pin is sampled high (clock arbitration),
Bus collision occurs during a Stop condition if:
the Baud Rate Generator is loaded with SSP1ADD and
a) After the SDA pin has been deasserted and counts down to zero. After the BRG times out, SDA is
allowed to float high, SDA is sampled low after sampled. If SDA is sampled low, a bus collision has
the BRG has timed out (Case 1). occurred. This is due to another master attempting to
b) After the SCL pin is deasserted, SCL is sampled drive a data ‘0’ (Figure 32-38). If the SCL pin is sampled
low before SDA goes high (Case 2). low before SDA is allowed to float high, a bus collision
occurs. This is another case of another master
attempting to drive a data ‘0’ (Figure 32-39).

FIGURE 32-38: BUS COLLISION DURING A STOP CONDITION (CASE 1)

TBRG TBRG TBRG SDA sampled

low after TBRG,
set BCL1IF
SDA

SDA asserted low

SCL

PEN

BCL1IF

P ’0’

SSP1IF ’0’

FIGURE 32-39: BUS COLLISION DURING A STOP CONDITION (CASE 2)

TBRG TBRG TBRG

SDA

Assert SDA SCL goes low before SDA goes high,

set BCL1IF
SCL

PEN

BCL1IF

P ’0’

SSP1IF ’0’

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32.7 BAUD RATE GENERATOR module clock line. The logic dictating when the reload
signal is asserted depends on the mode the MSSP is
The MSSP module has a Baud Rate Generator avail- being operated in.
able for clock generation in both I2C and SPI Master
Table 32-4 demonstrates clock rates based on
modes. The Baud Rate Generator (BRG) reload value
instruction cycles and the BRG value loaded into
is placed in the SSP1ADD register (Register 32-6).
SSP1ADD.
When a write occurs to SSP1BUF, the Baud Rate
Generator will automatically begin counting down.
EQUATION 32-1:
Once the given operation is complete, the internal clock
will automatically stop counting and the clock pin will FOSC
FCLOCK = ---------------------------------------------------
remain in its last state.  SSP 1ADD + 1   4 

An internal signal “Reload” in Figure 32-40 triggers the

value from SSP1ADD to be loaded into the BRG
counter. This occurs twice for each oscillation of the

FIGURE 32-40: BAUD RATE GENERATOR BLOCK DIAGRAM

SSPM<3:0> SSP1ADD<7:0>

SSPM<3:0> Reload Reload

SCL Control

SSPCLK BRG Down Counter FOSC/2

Note: Values of 0x00, 0x01 and 0x02 are not

valid for SSP1ADD when used as a Baud
Rate Generator for I2C. This is an
implementation limitation.

TABLE 32-2: MSSP CLOCK RATE W/BRG

FCLOCK
FOSC FCY BRG Value
(2 Rollovers of BRG)
32 MHz 8 MHz 13h 400 kHz
32 MHz 8 MHz 19h 308 kHz
32 MHz 8 MHz 4Fh 100 kHz
16 MHz 4 MHz 09h 400 kHz
16 MHz 4 MHz 0Ch 308 kHz
16 MHz 4 MHz 27h 100 kHz
4 MHz 1 MHz 09h 100 kHz
Note: Refer to the I/O port electrical specifications in Table 37-4 to ensure the system is designed to support IOL
requirements.

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32.8 Register Definitions: MSSP1 Control
REGISTER 32-1: SSP1STAT: SSP1 STATUS REGISTER
R/W-0/0 R/W-0/0 R/HS/HC-0 R/HS/HC-0 R/HS/HC-0 R/HS/HC-0 R/HS/HC-0 R/HS/HC-0
SMP CKE(1) D/A P(2) S(2) R/W UA BF
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared HS/HC = Hardware set/clear

bit 7 SMP: SPI Data Input Sample bit

SPI Master mode:
1 = Input data sampled at end of data output time
0 = Input data sampled at middle of data output time
SPI Slave mode:
SMP must be cleared when SPI is used in Slave mode
In I2 C Master or Slave mode:
1 = Slew rate control disabled for Standard Speed mode (100 kHz and 1 MHz)
0 = Slew rate control enabled for High-Speed mode (400 kHz)
bit 6 CKE: SPI Clock Edge Select bit (SPI mode only)(1)
In SPI Master or Slave mode:
1 = Transmit occurs on transition from active to Idle clock state
0 = Transmit occurs on transition from Idle to active clock state
In I2 C mode only:
1 = Enable input logic so that thresholds are compliant with SMBus specification
0 = Disable SMBus specific inputs
bit 5 D/A: Data/Address bit (I2C mode only)
1 = Indicates that the last byte received or transmitted was data
0 = Indicates that the last byte received or transmitted was address
bit 4 P: Stop bit(2)
(I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.)
1 = Indicates that a Stop bit has been detected last (this bit is ‘0’ on Reset)
0 = Stop bit was not detected last
bit 3 S: Start bit (2)
(I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.)
1 = Indicates that a Start bit has been detected last (this bit is ‘0’ on Reset)
0 = Start bit was not detected last
bit 2 R/W: Read/Write bit information (I2C mode only)
This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the
next Start bit, Stop bit, or not ACK bit.
In I2 C Slave mode:
1 = Read
0 = Write
In I2 C Master mode:
1 = Transmit is in progress
0 = Transmit is not in progress
OR-ing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is in IDLE mode.
bit 1 UA: Update Address bit (10-bit I2C mode only)
1 = Indicates that the user needs to update the address in the SSP1ADD register
0 = Address does not need to be updated
bit 0 BF: Buffer Full Status bit
Receive (SPI and I2 C modes):
1 = Receive complete, SSPBUF is full
0 = Receive not complete, SSPBUF is empty
Transmit (I2 C mode only):
1 = Data transmit in progress (does not include the ACK and Stop bits), SSP1BUF is full
0 = Data transmit complete (does not include the ACK and Stop bits), SSP1BUF is empty
Note 1: Polarity of clock state is set by the CKP bit of the SSP1CON register.
2: This bit is cleared on Reset and when SSPEN is cleared.

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REGISTER 32-2: SSP1CON1: SSP1 CONTROL REGISTER 1

R/C/HS-0/0 R/C/HS-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
WCOL SSPOV(1) SSPEN CKP SSPM<3:0>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared HS = Bit is set by hardware C = User cleared

bit 7 WCOL: Write Collision Detect bit (Transmit mode only)

1 = The SSP1BUF register is written while it is still transmitting the previous word (must be cleared in software)
0 = No collision
bit 6 SSPOV: Receive Overflow Indicator bit(1)
In SPI mode:
1 = A new byte is received while the SSP1BUF register is still holding the previous data. In case of overflow, the data in SSP1SR is
lost. Overflow can only occur in Slave mode. In Slave mode, the user must read the SSP1BUF, even if only transmitting data, to
avoid setting overflow. In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing
to the SSP1BUF register (must be cleared in software).
0 = No overflow
In I2C mode:
1 = A byte is received while the SSP1BUF register is still holding the previous byte. SSPOV is a “don’t care” in Transmit mode
(must be cleared in software).
0 = No overflow
bit 5 SSPEN: Synchronous Serial Port Enable bit
In both modes, when enabled, the following pins must be properly configured as input or output
In SPI mode:
1 = Enables serial port and configures SCK, SDO, SDI and SS as the source of the serial port pins(2)
0 = Disables serial port and configures these pins as I/O port pins
In I2C mode:
1 = Enables the serial port and configures the SDA and SCL pins as the source of the serial port pins(3)
0 = Disables serial port and configures these pins as I/O port pins
bit 4 CKP: Clock Polarity Select bit
In SPI mode:
1 = Idle state for clock is a high level
0 = Idle state for clock is a low level
In I2C Slave mode:
SCL release control
1 = Enable clock
0 = Holds clock low (clock stretch). (Used to ensure data setup time.)
In I2C Master mode:
Unused in this mode
bit 3-0 SSPM<3:0>: Synchronous Serial Port Mode Select bits
1111 = I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled
1110 = I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled
1101 = Reserved
1100 = Reserved
1011 = I2C firmware controlled Master mode (slave idle)
1010 = SPI Master mode, clock = FOSC/(4 * (SSP1ADD+1))(5)
1001 = Reserved
1000 = I2C Master mode, clock = FOSC / (4 * (SSP1ADD+1))(4)
0111 = I2C Slave mode, 10-bit address
0110 = I2C Slave mode, 7-bit address
0101 = SPI Slave mode, clock = SCK pin, SS pin control disabled, SS can be used as I/O pin
0100 = SPI Slave mode, clock = SCK pin, SS pin control enabled
0011 = SPI Master mode, clock = T2_match/2
0010 = SPI Master mode, clock = FOSC/64
0001 = SPI Master mode, clock = FOSC/16
0000 = SPI Master mode, clock = FOSC/4
Note 1: In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSP1BUF register.
2: When enabled, these pins must be properly configured as input or output. Use SSP1SSPPS, SSP1CLKPPS, SSP1DATPPS, and
RxyPPS to select the pins.
3: When enabled, the SDA and SCL pins must be configured as inputs. Use SSP1CLKPPS, SSP1DATPPS, and RxyPPS to select the pins.
4: SSP1ADD values of 0, 1 or 2 are not supported for I2C mode.
5: SSP1ADD value of ‘0’ is not supported. Use SSPM = 0000 instead.

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REGISTER 32-3: SSP1CON2: SSP1 CONTROL REGISTER 2 (I2C MODE ONLY)(1)

R/W-0/0 R/HS/HC-0 R/W-0/0 R/S/HC-0/0 R/S/HC-0/0 R/S/HC-0/0 R/S/HC-0/0 R/S/HC-0/0
GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared HC = Cleared by hardware S = User set

bit 7 GCEN: General Call Enable bit (in I2C Slave mode only)
1 = Enable interrupt when a general call address (0x00 or 00h) is received in the SSP1SR
0 = General call address disabled
bit 6 ACKSTAT: Acknowledge Status bit (in I2C mode only)
1 = Acknowledge was not received
0 = Acknowledge was received
bit 5 ACKDT: Acknowledge Data bit (in I2C mode only)
In Receive mode:
Value transmitted when the user initiates an Acknowledge sequence at the end of a receive
1 = Not Acknowledge
0 = Acknowledge
bit 4 ACKEN: Acknowledge Sequence Enable bit (in I2C Master mode only)
In Master Receive mode:
1 = Initiate Acknowledge sequence on SDA and SCL pins, and transmit ACKDT data bit.
Automatically cleared by hardware.
0 = Acknowledge sequence idle
bit 3 RCEN: Receive Enable bit (in I2C Master mode only)
1 = Enables Receive mode for I2C
0 = Receive idle
bit 2 PEN: Stop Condition Enable bit (in I2C Master mode only)
SCKMSSP Release Control:
1 = Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Stop condition Idle
bit 1 RSEN: Repeated Start Condition Enable bit (in I2C Master mode only)
1 = Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Repeated Start condition Idle
bit 0 SEN: Start Condition Enable/Stretch Enable bit
In Master mode:
1 = Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Start condition Idle
In Slave mode:
1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled)
0 = Clock stretching is disabled

Note 1: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the IDLE mode, this bit may not be
set (no spooling) and the SSP1BUF may not be written (or writes to the SSP1BUF are disabled).

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REGISTER 32-4: SSP1CON3: SSP1 CONTROL REGISTER 3

R-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
ACKTIM(3) PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 ACKTIM: Acknowledge Time Status bit (I2C mode only)(3)

1 = Indicates the I2C bus is in an Acknowledge sequence, set on 8th falling edge of SCL clock
0 = Not an Acknowledge sequence, cleared on 9TH rising edge of SCL clock
bit 6 PCIE: Stop Condition Interrupt Enable bit (I2C mode only)
1 = Enable interrupt on detection of Stop condition
0 = Stop detection interrupts are disabled(2)
bit 5 SCIE: Start Condition Interrupt Enable bit (I2C mode only)
1 = Enable interrupt on detection of Start or Restart conditions
0 = Start detection interrupts are disabled(2)
bit 4 BOEN: Buffer Overwrite Enable bit
In SPI Slave mode:(1)
1 = SSPBUF updates every time that a new data byte is shifted in ignoring the BF bit
0 = If new byte is received with BF bit of the SSPSTAT register already set, SSPOV bit of the SSPCON1
register is set, and the buffer is not updated
In I2 C Master mode and SPI Master mode:
This bit is ignored.
In I2 C Slave mode:
1 = SSPBUF is updated and ACK is generated for a received address/data byte, ignoring the state of the
SSPOV bit only if the BF bit = 0.
0 = SSPBUF is only updated when SSPOV is clear
bit 3 SDAHT: SDA Hold Time Selection bit (I2C mode only)
1 = Minimum of 300 ns hold time on SDA after the falling edge of SCL
0 = Minimum of 100 ns hold time on SDA after the falling edge of SCL
bit 2 SBCDE: Slave Mode Bus Collision Detect Enable bit (I2C Slave mode only)
If, on the rising edge of SCL, SDA is sampled low when the module is outputting a high state, the BCL1IF bit of the
PIR3 register is set, and bus goes idle
1 = Enable slave bus collision interrupts
0 = Slave bus collision interrupts are disabled
bit 1 AHEN: Address Hold Enable bit (I2C Slave mode only)
1 = Following the eighth falling edge of SCL for a matching received address byte; CKP bit of the SSPCON1
register will be cleared and the SCL will be held low.
0 = Address holding is disabled
bit 0 DHEN: Data Hold Enable bit (I2C Slave mode only)
1 = Following the eighth falling edge of SCL for a received data byte; slave hardware clears the CKP bit of the SSP-
CON1 register and SCL is held low.
0 = Data holding is disabled

Note 1: For daisy-chained SPI operation; allows the user to ignore all but the last received byte. SSPOV is still set when a new
byte is received and BF = 1, but hardware continues to write the most recent byte to SSPBUF.
2: This bit has no effect in Slave modes that Start and Stop condition detection is explicitly listed as enabled.
3: The ACKTIM Status bit is only active when the AHEN bit or DHEN bit is set.

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REGISTER 32-5: SSP1MSK: SSP1 MASK REGISTER

R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1
SSP1MSK<7:0>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-1 SSP1MSK<7:1>: Mask bits

1 = The received address bit n is compared to SSP1ADD<n> to detect I2C address match
0 = The received address bit n is not used to detect I2C address match
bit 0 SSP1MSK<0>: Mask bit for I2C Slave mode, 10-bit Address
I2C Slave mode, 10-bit address (SSPM<3:0> = 0111 or 1111):
1 = The received address bit 0 is compared to SSP1ADD<0> to detect I2C address match
0 = The received address bit 0 is not used to detect I2C address match
I2C Slave mode, 7-bit address:
MSK0 bit is ignored.

REGISTER 32-6: SSP1ADD: MSSP1 ADDRESS AND BAUD RATE REGISTER (I2C MODE)
R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
SSP1ADD<7:0>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

Master mode:

bit 7-0 SSP1ADD<7:0>: Baud Rate Clock Divider bits

SCL pin clock period = ((ADD<7:0> + 1) *4)/FOSC
10-Bit Slave mode – Most Significant Address Byte:

bit 7-3 Not used: Unused for Most Significant Address Byte. Bit state of this register is a “don’t care”. Bit
pattern sent by master is fixed by I2C specification and must be equal to ‘11110’. However, those bits
are compared by hardware and are not affected by the value in this register.
bit 2-1 SSP1ADD<2:1>: Two Most Significant bits of 10-bit address
bit 0 Not used: Unused in this mode. Bit state is a “don’t care”.
10-Bit Slave mode – Least Significant Address Byte:

bit 7-0 SSP1ADD<7:0>: Eight Least Significant bits of 10-bit address

7-Bit Slave mode:

bit 7-1 SSP1ADD<7:1>: 7-bit address

bit 0 Not used: Unused in this mode. Bit state is a “don’t care”.

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REGISTER 32-7: SSP1BUF: MSSP1 BUFFER REGISTER
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
SSP1BUF<7:0>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-0 SSP1BUF<7:0>: MSSP Buffer bits

TABLE 32-3: SUMMARY OF REGISTERS ASSOCIATED WITH MSSP1

Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
on Page

INTCON GIE PEIE — — — — — INTEDG 121

PIR1 OSFIF CSWIF — — — — — ADIF 131
PIE1 OSFIE CSWIE — — — — ― ADIE 123
SSP1STAT SMP CKE D/A P S R/W UA BF 405
SSP1CON1 WCOL SSPOV SSPEN CKP SSPM<3:0> 406
SSP1CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 407
SSP1CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 405
SSP1MSK SSPMSK<7:0> 409
SSP1ADD SSPADD<7:0> 409
SSP1BUF SSPBUF<7:0> 410
SSP1CLKPPS — — SSP1CLKPPS<5:0> 191
SSP1DATPPS — — SSP1DATPPS<5:0> 191
SSP1SSPPS — — SSP1SSPPS<5:0> 191
RxyPPS — — — RxyPPS<4:0> 192
Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by the MSSP module
Note 1: When using designated I2C pins, the associated pin values in INLVLx will be ignored.

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33.0 ENHANCED UNIVERSAL The EUSART module includes the following capabilities:
SYNCHRONOUS • Full-duplex asynchronous transmit and receive
ASYNCHRONOUS RECEIVER • Two-character input buffer
TRANSMITTER (EUSART) • One-character output buffer
• Programmable 8-bit or 9-bit character length
The Enhanced Universal Synchronous Asynchronous
• Address detection in 9-bit mode
Receiver Transmitter (EUSART) module is a serial I/O
communications peripheral. It contains all the clock • Input buffer overrun error detection
generators, shift registers and data buffers necessary • Received character framing error detection
to perform an input or output serial data transfer • Half-duplex synchronous master
independent of device program execution. The • Half-duplex synchronous slave
EUSART, also known as a Serial Communications • Programmable clock polarity in synchronous
Interface (SCI), can be configured as a full-duplex modes
asynchronous system or half-duplex synchronous
• Sleep operation
system. Full-Duplex mode is useful for
communications with peripheral systems, such as CRT The EUSART module implements the following
terminals and personal computers. Half-Duplex additional features, making it ideally suited for use in
Synchronous mode is intended for communications Local Interconnect Network (LIN) bus systems:
with peripheral devices, such as A/D or D/A integrated • Automatic detection and calibration of the baud rate
circuits, serial EEPROMs or other microcontrollers.
• Wake-up on Break reception
These devices typically do not have internal clocks for
baud rate generation and require the external clock • 13-bit Break character transmit
signal provided by a master synchronous device. Block diagrams of the EUSART transmitter and
receiver are shown in Figure 33-1 and Figure 33-2.
The EUSART transmit output (TX_out) is available to
the TX/CK pin and internally to the following peripherals:
• Configurable Logic Cell (CLC)

FIGURE 33-1: EUSART TRANSMIT BLOCK DIAGRAM

Data Bus
TXxIE
SYNC
Interrupt
CSRC
TXxREG Register TXxIF
8 RxyPPS(1)
CK pin TXEN
MSb LSb RX/DT pin
PPS 1 (8) 0 Pin Buffer
• • • and Control PPS
0 Transmit Shift Register (TSR)
CKPPS SYNC

TRMT TX_out
Baud Rate Generator FOSC
÷n
TX9
BRG16 n
+1 Multiplier x4 x16 x64
TX9D TX/CK pin
SYNC 1 X 0 0 0 0
PPS
SPxBRGH SPxBRGL BRGH X 1 1 0 0
1
BRG16 X 1 0 1 0
RxyPPS
SYNC
Note 1: In Synchronous mode the DT output and RX input PPS CSRC
selections should enable the same pin.

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FIGURE 33-2: EUSART RECEIVE BLOCK DIAGRAM

SPEN CREN OERR RCIDL

RXPPS(1)
RX/DT pin MSb RSR Register LSb
Pin Buffer Data
PPS and Control Recovery
Stop (8) 7 ••• 1 0 Start

Baud Rate Generator FOSC RX9

÷n

BRG16
+1 n
Multiplier x4 x16 x64
SYNC 1 X 0 0 0
SPxBRGH SPxBRGL BRGH FIFO
X 1 1 0 0 FERR RX9D RCxREG Register
BRG16 X 1 0 1 0
8
Data Bus

Note 1: In Synchronous mode the DT output and RX input PPS RXxIF Interrupt
selections should enable the same pin. RXxIE

The operation of the EUSART module is controlled

through three registers:
• Transmit Status and Control (TX1STA)
• Receive Status and Control (RC1STA)
• Baud Rate Control (BAUD1CON)
These registers are detailed in Register 33-1,
Register 33-2 and Register 33-3, respectively.
The RX input pin is selected with the RXPPS. The CK
input is selected with the TXPPS register. TX, CK, and
DT output pins are selected with each pin’s RxyPPS
register. Since the RX input is coupled with the DT output
in Synchronous mode, it is the user’s responsibility to
select the same pin for both of these functions when
operating in Synchronous mode. The EUSART control
logic will control the data direction drivers automatically.

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33.1 EUSART Asynchronous Mode 33.1.1.2 Transmitting Data
The EUSART transmits and receives data using the A transmission is initiated by writing a character to the
standard non-return-to-zero (NRZ) format. NRZ is TX1REG register. If this is the first character, or the
implemented with two levels: a VOH Mark state which previous character has been completely flushed from
represents a ‘1’ data bit, and a VOL Space state which the TSR, the data in the TX1REG is immediately
represents a ‘0’ data bit. NRZ refers to the fact that transferred to the TSR register. If the TSR still contains
consecutively transmitted data bits of the same value all or part of a previous character, the new character
stay at the output level of that bit without returning to a data is held in the TX1REG until the Stop bit of the
neutral level between each bit transmission. An NRZ previous character has been transmitted. The pending
transmission port idles in the Mark state. Each character character in the TX1REG is then transferred to the TSR
transmission consists of one Start bit followed by eight in one TCY immediately following the Stop bit
or nine data bits and is always terminated by one or transmission. The transmission of the Start bit, data bits
more Stop bits. The Start bit is always a space and the and Stop bit sequence commences immediately
Stop bits are always marks. The most common data following the transfer of the data to the TSR from the
format is eight bits. Each transmitted bit persists for a TX1REG.
period of 1/(Baud Rate). An on-chip dedicated
8-bit/16-bit Baud Rate Generator is used to derive 33.1.1.3 Transmit Data Polarity
standard baud rate frequencies from the system The polarity of the transmit data can be controlled with
oscillator. See Table 33-3 for examples of baud rate the SCKP bit of the BAUD1CON register. The default
configurations. state of this bit is ‘0’ which selects high true transmit idle
The EUSART transmits and receives the LSb first. The and data bits. Setting the SCKP bit to ‘1’ will invert the
EUSART’s transmitter and receiver are functionally transmit data resulting in low true idle and data bits. The
independent, but share the same data format and baud SCKP bit controls transmit data polarity in
rate. Parity is not supported by the hardware, but can Asynchronous mode only. In Synchronous mode, the
be implemented in software and stored as the ninth SCKP bit has a different function. See Section 33.4.1.2
data bit. “Clock Polarity”.

33.1.1 EUSART ASYNCHRONOUS 33.1.1.4 Transmit Interrupt Flag

TRANSMITTER The TX1IF interrupt flag bit of the PIR3 register is set
whenever the EUSART transmitter is enabled and no
The EUSART transmitter block diagram is shown in
character is being held for transmission in the TX1REG.
Figure 33-1. The heart of the transmitter is the serial
In other words, the TX1IF bit is only clear when the TSR
Transmit Shift Register (TSR), which is not directly
is busy with a character and a new character has been
accessible by software. The TSR obtains its data from
queued for transmission in the TX1REG. The TX1IF flag
the transmit buffer, which is the TX1REG register.
bit is not cleared immediately upon writing TX1REG.
33.1.1.1 Enabling the Transmitter TX1IF becomes valid in the second instruction cycle
following the write execution. Polling TX1IF immediately
The EUSART transmitter is enabled for asynchronous following the TX1REG write will return invalid results.
operations by configuring the following three control The TX1IF bit is read-only, it cannot be set or cleared by
bits: software.
• TXEN = 1 The TX1IF interrupt can be enabled by setting the
• SYNC = 0 TX1IE interrupt enable bit of the PIE3 register. How-
• SPEN = 1 ever, the TX1IF flag bit will be set whenever the
TX1REG is empty, regardless of the state of TX1IE
All other EUSART control bits are assumed to be in
enable bit.
their default state.
To use interrupts when transmitting data, set the TX1IE
Setting the TXEN bit of the TX1STA register enables the
bit only when there is more data to send. Clear the
transmitter circuitry of the EUSART. Clearing the SYNC
TX1IE interrupt enable bit upon writing the last charac-
bit of the TX1STA register configures the EUSART for
ter of the transmission to the TX1REG.
asynchronous operation. Setting the SPEN bit of the
RC1STA register enables the EUSART and
automatically configures the TX/CK I/O pin as an output.
If the TX/CK pin is shared with an analog peripheral, the
analog I/O function must be disabled by clearing the
corresponding ANSEL bit.
Note: The TX1IF Transmitter Interrupt flag is set
when the TXEN enable bit is set.

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33.1.1.5 TSR Status 33.1.1.7 Asynchronous Transmission Set-up:
The TRMT bit of the TX1STA register indicates the 1. Initialize the SP1BRGH, SP1BRGL register pair
status of the TSR register. This is a read-only bit. The and the BRGH and BRG16 bits to achieve the
TRMT bit is set when the TSR register is empty and is desired baud rate (see Section 33.3 “EUSART
cleared when a character is transferred to the TSR Baud Rate Generator (BRG)”).
register from the TX1REG. The TRMT bit remains clear 2. Enable the asynchronous serial port by clearing
until all bits have been shifted out of the TSR register. the SYNC bit and setting the SPEN bit.
No interrupt logic is tied to this bit, so the user has to 3. If 9-bit transmission is desired, set the TX9
poll this bit to determine the TSR status. control bit. A set ninth data bit will indicate that
Note: The TSR register is not mapped in data the eight Least Significant data bits are an
memory, so it is not available to the user. address when the receiver is set for address
detection.
33.1.1.6 Transmitting 9-Bit Characters 4. Set SCKP bit if inverted transmit is desired.
The EUSART supports 9-bit character transmissions. 5. Enable the transmission by setting the TXEN
When the TX9 bit of the TX1STA register is set, the control bit. This will cause the TX1IF interrupt bit
EUSART will shift nine bits out for each character trans- to be set.
mitted. The TX9D bit of the TX1STA register is the 6. If interrupts are desired, set the TX1IE interrupt
ninth, and Most Significant data bit. When transmitting enable bit of the PIE3 register. An interrupt will
9-bit data, the TX9D data bit must be written before occur immediately provided that the GIE and
writing the eight Least Significant bits into the TX1REG. PEIE bits of the INTCON register are also set.
All nine bits of data will be transferred to the TSR shift 7. If 9-bit transmission is selected, the ninth bit
register immediately after the TX1REG is written. should be loaded into the TX9D data bit.
A special 9-bit Address mode is available for use with 8. Load 8-bit data into the TX1REG register. This
multiple receivers. See Section 33.1.2.7 “Address will start the transmission.
Detection” for more information on the Address mode.

FIGURE 33-3: ASYNCHRONOUS TRANSMISSION

Write to TXxREG
Word 1
BRG Output
(Shift Clock)
TX/CK
pin Start bit bit 0 bit 1 bit 7/8 Stop bit
Word 1
TXxIF bit
(Transmit Buffer 1 TCY
Reg. Empty Flag)

Word 1
TRMT bit Transmit Shift Reg.
(Transmit Shift
Reg. Empty Flag)

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FIGURE 33-4: ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK)

Write to TXxREG
Word 1 Word 2
BRG Output
(Shift Clock)
TX/CK
pin Start bit bit 0 bit 1 bit 7/8 Stop bit Start bit bit 0
TXxIF bit 1 TCY Word 1 Word 2
(Transmit Buffer
Reg. Empty Flag) 1 TCY

TRMT bit Word 1 Word 2

(Transmit Shift Transmit Shift Reg. Transmit Shift Reg.
Reg. Empty Flag)

Note: This timing diagram shows two consecutive transmissions.

33.1.2 EUSART ASYNCHRONOUS 33.1.2.2 Receiving Data

RECEIVER The receiver data recovery circuit initiates character
The Asynchronous mode is typically used in RS-232 reception on the falling edge of the first bit. The first bit,
systems. The receiver block diagram is shown in also known as the Start bit, is always a zero. The data
Figure 33-2. The data is received on the RX/DT pin and recovery circuit counts one-half bit time to the center of
drives the data recovery block. The data recovery block the Start bit and verifies that the bit is still a zero. If it is
is actually a high-speed shifter operating at 16 times not a zero then the data recovery circuit aborts
the baud rate, whereas the serial Receive Shift character reception, without generating an error, and
Register (RSR) operates at the bit rate. When all eight resumes looking for the falling edge of the Start bit. If
or nine bits of the character have been shifted in, they the Start bit zero verification succeeds then the data
are immediately transferred to a two character recovery circuit counts a full bit time to the center of the
First-In-First-Out (FIFO) memory. The FIFO buffering next bit. The bit is then sampled by a majority detect
allows reception of two complete characters and the circuit and the resulting ‘0’ or ‘1’ is shifted into the RSR.
start of a third character before software must start This repeats until all data bits have been sampled and
servicing the EUSART receiver. The FIFO and RSR shifted into the RSR. One final bit time is measured and
registers are not directly accessible by software. the level sampled. This is the Stop bit, which is always
Access to the received data is via the RC1REG a ‘1’. If the data recovery circuit samples a ‘0’ in the
register. Stop bit position then a framing error is set for this
character, otherwise the framing error is cleared for this
33.1.2.1 Enabling the Receiver character. See Section 33.1.2.4 “Receive Framing
The EUSART receiver is enabled for asynchronous Error” for more information on framing errors.
operation by configuring the following three control bits: Immediately after all data bits and the Stop bit have
• CREN = 1 been received, the character in the RSR is transferred
to the EUSART receive FIFO and the RX1IF interrupt
• SYNC = 0
flag bit of the PIR3 register is set. The top character in
• SPEN = 1 the FIFO is transferred out of the FIFO by reading the
All other EUSART control bits are assumed to be in RC1REG register.
their default state.
Note: If the receive FIFO is overrun, no additional
Setting the CREN bit of the RC1STA register enables characters will be received until the overrun
the receiver circuitry of the EUSART. Clearing the SYNC condition is cleared. See Section 33.1.2.5
bit of the TX1STA register configures the EUSART for “Receive Overrun Error” for more
asynchronous operation. Setting the SPEN bit of the information on overrun errors.
RC1STA register enables the EUSART. The
programmer must set the corresponding TRIS bit to
configure the RX/DT I/O pin as an input.
Note: If the RX/DT function is on an analog pin,
the corresponding ANSEL bit must be
cleared for the receiver to function.

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33.1.2.3 Receive Interrupts 33.1.2.6 Receiving 9-Bit Characters
The RX1IF interrupt flag bit of the PIR3 register is set The EUSART supports 9-bit character reception. When
whenever the EUSART receiver is enabled and there is the RX9 bit of the RC1STA register is set the EUSART
an unread character in the receive FIFO. The RX1IF will shift nine bits into the RSR for each character
interrupt flag bit is read-only, it cannot be set or cleared received. The RX9D bit of the RC1STA register is the
by software. ninth and Most Significant data bit of the top unread
RX1IF interrupts are enabled by setting all of the character in the receive FIFO. When reading 9-bit data
following bits: from the receive FIFO buffer, the RX9D data bit must
be read before reading the eight Least Significant bits
• RX1IE, Interrupt Enable bit of the PIE3 register from the RC1REG.
• PEIE, Peripheral Interrupt Enable bit of the
INTCON register 33.1.2.7 Address Detection
• GIE, Global Interrupt Enable bit of the INTCON A special Address Detection mode is available for use
register when multiple receivers share the same transmission
The RX1IF interrupt flag bit will be set when there is an line, such as in RS-485 systems. Address detection is
unread character in the FIFO, regardless of the state of enabled by setting the ADDEN bit of the RC1STA
interrupt enable bits. register.
Address detection requires 9-bit character reception.
33.1.2.4 Receive Framing Error When address detection is enabled, only characters
Each character in the receive FIFO buffer has a with the ninth data bit set will be transferred to the
corresponding framing error Status bit. A framing error receive FIFO buffer, thereby setting the RX1IF interrupt
indicates that a Stop bit was not seen at the expected bit. All other characters will be ignored.
time. The framing error status is accessed via the Upon receiving an address character, user software
FERR bit of the RC1STA register. The FERR bit determines if the address matches its own. Upon
represents the status of the top unread character in the address match, user software must disable address
receive FIFO. Therefore, the FERR bit must be read detection by clearing the ADDEN bit before the next
before reading the RC1REG. Stop bit occurs. When user software detects the end of
The FERR bit is read-only and only applies to the top the message, determined by the message protocol
unread character in the receive FIFO. A framing error used, software places the receiver back into the
(FERR = 1) does not preclude reception of additional Address Detection mode by setting the ADDEN bit.
characters. It is not necessary to clear the FERR bit.
Reading the next character from the FIFO buffer will
advance the FIFO to the next character and the next
corresponding framing error.
The FERR bit can be forced clear by clearing the SPEN
bit of the RC1STA register which resets the EUSART.
Clearing the CREN bit of the RC1STA register does not
affect the FERR bit. A framing error by itself does not
generate an interrupt.
Note: If all receive characters in the receive
FIFO have framing errors, repeated reads
of the RC1REG will not clear the FERR bit.

33.1.2.5 Receive Overrun Error

The receive FIFO buffer can hold two characters. An
overrun error will be generated if a third character, in its
entirety, is received before the FIFO is accessed. When
this happens the OERR bit of the RC1STA register is
set. The characters already in the FIFO buffer can be
read but no additional characters will be received until
the error is cleared. The error must be cleared by either
clearing the CREN bit of the RC1STA register or by
resetting the EUSART by clearing the SPEN bit of the
RC1STA register.

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33.1.2.8 Asynchronous Reception Setup: 33.1.2.9 9-bit Address Detection Mode Setup
1. Initialize the SP1BRGH, SP1BRGL register pair This mode would typically be used in RS-485 systems.
and the BRGH and BRG16 bits to achieve the To set up an Asynchronous Reception with Address
desired baud rate (see Section 33.3 “EUSART Detect Enable:
Baud Rate Generator (BRG)”). 1. Initialize the SP1BRGH, SP1BRGL register pair
2. Clear the ANSEL bit for the RX pin (if applicable). and the BRGH and BRG16 bits to achieve the
3. Enable the serial port by setting the SPEN bit. desired baud rate (see Section 33.3 “EUSART
The SYNC bit must be clear for asynchronous Baud Rate Generator (BRG)”).
operation. 2. Clear the ANSEL bit for the RX pin (if applicable).
4. If interrupts are desired, set the RX1IE bit of the 3. Enable the serial port by setting the SPEN bit.
PIE3 register and the GIE and PEIE bits of the The SYNC bit must be clear for asynchronous
INTCON register. operation.
5. If 9-bit reception is desired, set the RX9 bit. 4. If interrupts are desired, set the RX1IE bit of the
6. Enable reception by setting the CREN bit. PIE3 register and the GIE and PEIE bits of the
7. The RX1IF interrupt flag bit will be set when a INTCON register.
character is transferred from the RSR to the 5. Enable 9-bit reception by setting the RX9 bit.
receive buffer. An interrupt will be generated if 6. Enable address detection by setting the ADDEN
the RX1IE interrupt enable bit was also set. bit.
8. Read the RC1STA register to get the error flags 7. Enable reception by setting the CREN bit.
and, if 9-bit data reception is enabled, the ninth 8. The RX1IF interrupt flag bit will be set when a
data bit. character with the ninth bit set is transferred
9. Get the received eight Least Significant data bits from the RSR to the receive buffer. An interrupt
from the receive buffer by reading the RC1REG will be generated if the RX1IE interrupt enable
register. bit was also set.
10. If an overrun occurred, clear the OERR flag by 9. Read the RC1STA register to get the error flags.
clearing the CREN receiver enable bit. The ninth data bit will always be set.
10. Get the received eight Least Significant data bits
from the receive buffer by reading the RC1REG
register. Software determines if this is the
device’s address.
11. If an overrun occurred, clear the OERR flag by
clearing the CREN receiver enable bit.
12. If the device has been addressed, clear the
ADDEN bit to allow all received data into the
receive buffer and generate interrupts.

FIGURE 33-5: ASYNCHRONOUS RECEPTION

Start Start Start
RX/DT pin bit bit 0 bit 1 bit 7/8 Stop bit bit 0 bit 7/8 Stop bit bit 7/8 Stop
bit bit bit
Rcv Shift
Reg
Rcv Buffer Reg.
Word 1 Word 2
RCxREG RCxREG
RCIDL

Read Rcv
Buffer Reg.
RCxREG

RXxIF
(Interrupt Flag)

OERR bit
CREN

Note: This timing diagram shows three words appearing on the RX input. The RCxREG (receive buffer) is read after the third word,
causing the OERR (overrun) bit to be set.

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33.2 Clock Accuracy with
Asynchronous Operation
The factory calibrates the internal oscillator block
output (INTOSC). However, the INTOSC frequency
may drift as VDD or temperature changes, and this
directly affects the asynchronous baud rate. Two
methods may be used to adjust the baud rate clock, but
both require a reference clock source of some kind.
The first (preferred) method uses the OSCTUNE
register to adjust the INTOSC output. Adjusting the
value in the OSCTUNE register allows for fine resolution
changes to the system clock source. See
Section 9.2.2.2 “Internal Oscillator Frequency
Adjustment” for more information.
The other method adjusts the value in the Baud Rate
Generator. This can be done automatically with the
Auto-Baud Detect feature (see Section 33.3.1
“Auto-Baud Detect”). There may not be fine enough
resolution when adjusting the Baud Rate Generator to
compensate for a gradual change in the peripheral
clock frequency.

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33.3 EUSART Baud Rate Generator EXAMPLE 33-1: CALCULATING BAUD
(BRG) RATE ERROR
The Baud Rate Generator (BRG) is an 8-bit or 16-bit For a device with FOSC of 16 MHz, desired baud rate
timer that is dedicated to the support of both the of 9600, Asynchronous mode, 8-bit BRG:
asynchronous and synchronous EUSART operation. FOSC
Desired Baud Rate = ------------------------------------------------------------------------
By default, the BRG operates in 8-bit mode. Setting the 64  [SPBRGH:SPBRGL] + 1 
BRG16 bit of the BAUD1CON register selects 16-bit
mode. Solving for SPxBRGH:SPxBRGL:
The SP1BRGH, SP1BRGL register pair determines the F OS C
---------------------------------------------
period of the free running baud rate timer. In Desired Baud Rate
X = --------------------------------------------- – 1
64
Asynchronous mode the multiplier of the baud rate
period is determined by both the BRGH bit of the 16000000
------------------------
TX1STA register and the BRG16 bit of the BAUD1CON 9600
= ------------------------ – 1
register. In Synchronous mode, the BRGH bit is ignored. 64

Table 33-1 contains the formulas for determining the =  25.042  = 25

baud rate. Example 33-1 provides a sample calculation 16000000
for determining the baud rate and baud rate error. Calculated Baud Rate = ---------------------------
64  25 + 1 
Typical baud rates and error values for various
Asynchronous modes have been computed for your = 9615
convenience and are shown in Table 33-3. It may be Calc. Baud Rate – Desired Baud Rate
advantageous to use the high baud rate (BRGH = 1), Error = --------------------------------------------------------------------------------------------
Desired Baud Rate
or the 16-bit BRG (BRG16 = 1) to reduce the baud rate
error. The 16-bit BRG mode is used to achieve slow  9615 – 9600 
= ---------------------------------- = 0.16%
baud rates for fast oscillator frequencies. 9600

Writing a new value to the SP1BRGH, SP1BRGL

register pair causes the BRG timer to be reset (or
cleared). This ensures that the BRG does not wait for a
timer overflow before outputting the new baud rate.
If the system clock is changed during an active receive
operation, a receive error or data loss may result. To
avoid this problem, check the status of the RCIDL bit to
make sure that the receive operation is idle before
changing the system clock.

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33.3.1 AUTO-BAUD DETECT 1/8th the BRG base clock rate. The resulting byte
measurement is the average bit time when clocked at
The EUSART module supports automatic detection
full speed.
and calibration of the baud rate.
Note 1: If the WUE bit is set with the ABDEN bit,
In the Auto-Baud Detect (ABD) mode, the clock to the
auto-baud detection will occur on the byte
BRG is reversed. Rather than the BRG clocking the
following the Break character (see
incoming RX signal, the RX signal is timing the BRG.
Section 33.3.3 “Auto-Wake-up on
The Baud Rate Generator is used to time the period of
Break”).
a received 55h (ASCII “U”) which is the Sync character
for the LIN bus. The unique feature of this character is 2: It is up to the user to determine that the
that it has five rising edges including the Stop bit edge. incoming character baud rate is within the
range of the selected BRG clock source.
Setting the ABDEN bit of the BAUD1CON register
Some combinations of oscillator frequency
starts the auto-baud calibration sequence. While the
and EUSART baud rates are not possible.
ABD sequence takes place, the EUSART state
machine is held in Idle. On the first rising edge of the 3: During the auto-baud process, the
receive line, after the Start bit, the SP1BRG begins auto-baud counter starts counting at one.
counting up using the BRG counter clock as shown in Upon completion of the auto-baud
Figure 33-6. The fifth rising edge will occur on the RX sequence, to achieve maximum accuracy,
pin at the end of the eighth bit period. At that time, an subtract 1 from the SP1BRGH:SP1BRGL
accumulated value totaling the proper BRG period is register pair.
left in the SP1BRGH, SP1BRGL register pair, the
ABDEN bit is automatically cleared and the RX1IF TABLE 33-1: BRG COUNTER CLOCK RATES
interrupt flag is set. The value in the RC1REG needs to
BRG Base BRG ABD
be read to clear the RX1IF interrupt. RC1REG content BRG16 BRGH
Clock Clock
should be discarded. When calibrating for modes that
do not use the SP1BRGH register the user can verify 0 0 FOSC/64 FOSC/512
that the SP1BRGL register did not overflow by
checking for 00h in the SP1BRGH register. 0 1 FOSC/16 FOSC/128

The BRG auto-baud clock is determined by the BRG16 1 0 FOSC/16 FOSC/128

and BRGH bits as shown in Table 33-1. During ABD, 1 1 FOSC/4 FOSC/32
both the SP1BRGH and SP1BRGL registers are used Note: During the ABD sequence, SP1BRGL and
as a 16-bit counter, independent of the BRG16 bit SP1BRGH registers are both used as a
setting. While calibrating the baud rate period, the 16-bit counter, independent of the BRG16
SP1BRGH and SP1BRGL registers are clocked at setting.

FIGURE 33-6: AUTOMATIC BAUD RATE CALIBRATION

BRG Value XXXXh 0000h 001Ch

Edge #1 Edge #2 Edge #3 Edge #4 Edge #5

RX pin Start bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 Stop bit

BRG Clock

Set by User Auto Cleared

ABDEN bit

RCIDL

RXxIF bit
(Interrupt)

Read
RCxREG

SPxBRGL XXh 1Ch

SPxBRGH XXh 00h

Note 1: The ABD sequence requires the EUSART module to be configured in Asynchronous mode.

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33.3.2 AUTO-BAUD OVERFLOW 33.3.3.1 Special Considerations
During the course of automatic baud detection, the Break Character
ABDOVF bit of the BAUD1CON register will be set if To avoid character errors or character fragments during
the baud rate counter overflows before the fifth rising a wake-up event, the wake-up character must be all
edge is detected on the RX pin. The ABDOVF bit zeros.
indicates that the counter has exceeded the maximum
count that can fit in the 16 bits of the When the wake-up is enabled the function works
SP1BRGH:SP1BRGL register pair. The overflow independent of the low time on the data stream. If the
condition will set the RX1IF flag. The counter continues WUE bit is set and a valid non-zero character is
to count until the fifth rising edge is detected on the RX received, the low time from the Start bit to the first rising
pin. The RCIDL bit will remain false (‘0’) until the fifth edge will be interpreted as the wake-up event. The
rising edge at which time the RCIDL bit will be set. If the remaining bits in the character will be received as a
RC1REG is read after the overflow occurs but before fragmented character and subsequent characters can
the fifth rising edge then the fifth rising edge will set the result in framing or overrun errors.
RX1IF again. Therefore, the initial character in the transmission must
Terminating the auto-baud process early to clear an be all ‘0’s. This must be ten or more bit times, 13-bit
overflow condition will prevent proper detection of the times recommended for LIN bus, or any number of bit
sync character fifth rising edge. If any falling edges of times for standard RS-232 devices.
the sync character have not yet occurred when the Oscillator Start-up Time
ABDEN bit is cleared then those will be falsely detected
Oscillator start-up time must be considered, especially
as Start bits. The following steps are recommended to
in applications using oscillators with longer start-up
clear the overflow condition:
intervals (i.e., LP, XT or HS/PLL mode). The Sync
1. Read RC1REG to clear RX1IF. Break (or wake-up signal) character must be of
2. If RCIDL is ‘0’ then wait for RDCIF and repeat sufficient length, and be followed by a sufficient
step 1. interval, to allow enough time for the selected oscillator
3. Clear the ABDOVF bit. to start and provide proper initialization of the EUSART.
WUE Bit
33.3.3 AUTO-WAKE-UP ON BREAK
The wake-up event causes a receive interrupt by
During Sleep mode, all clocks to the EUSART are setting the RX1IF bit. The WUE bit is cleared in
suspended. Because of this, the Baud Rate Generator hardware by a rising edge on RX/DT. The interrupt
is inactive and a proper character reception cannot be condition is then cleared in software by reading the
performed. The Auto-Wake-up feature allows the RC1REG register and discarding its contents.
controller to wake-up due to activity on the RX/DT line.
To ensure that no actual data is lost, check the RCIDL
This feature is available only in Asynchronous mode.
bit to verify that a receive operation is not in process
The Auto-Wake-up feature is enabled by setting the before setting the WUE bit. If a receive operation is not
WUE bit of the BAUD1CON register. Once set, the occurring, the WUE bit may then be set just prior to
normal receive sequence on RX/DT is disabled, and the entering the Sleep mode.
EUSART remains in an Idle state, monitoring for a
wake-up event independent of the CPU mode. A
wake-up event consists of a high-to-low transition on the
RX/DT line. (This coincides with the start of a Sync Break
or a wake-up signal character for the LIN protocol.)
The EUSART module generates an RX1IF interrupt
coincident with the wake-up event. The interrupt is
generated synchronously to the Q clocks in normal CPU
operating modes (Figure 33-7), and asynchronously if
the device is in Sleep mode (Figure 33-8). The interrupt
condition is cleared by reading the RC1REG register.
The WUE bit is automatically cleared by the low-to-high
transition on the RX line at the end of the Break. This
signals to the user that the Break event is over. At this
point, the EUSART module is in IDLE mode waiting to
receive the next character.

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FIGURE 33-7: AUTO-WAKE-UP BIT (WUE) TIMING DURING NORMAL OPERATION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
Bit set by user Auto Cleared
WUE bit
RX/DT Line

RXxIF
Cleared due to User Read of RCxREG

Note 1: The EUSART remains in Idle while the WUE bit is set.

FIGURE 33-8: AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP

Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4

OSC1
Bit Set by User Auto Cleared
WUE bit
RX/DT Line
Note 1
RXxIF
Cleared due to User Read of RCxREG
Sleep Command Executed Sleep Ends

Note 1: If the wake-up event requires long oscillator warm-up time, the automatic clearing of the WUE bit can occur while the stposc signal is
still active. This sequence should not depend on the presence of Q clocks.
2: The EUSART remains in Idle while the WUE bit is set.

33.3.4 BREAK CHARACTER SEQUENCE 33.3.4.1 Break and Sync Transmit Sequence
The EUSART module has the capability of sending the The following sequence will start a message frame
special Break character sequences that are required by header made up of a Break, followed by an auto-baud
the LIN bus standard. A Break character consists of a Sync byte. This sequence is typical of a LIN bus
Start bit, followed by 12 ‘0’ bits and a Stop bit. master.
To send a Break character, set the SENDB and TXEN 1. Configure the EUSART for the desired mode.
bits of the TX1STA register. The Break character 2. Set the TXEN and SENDB bits to enable the
transmission is then initiated by a write to the TX1REG. Break sequence.
The value of data written to TX1REG will be ignored 3. Load the TX1REG with a dummy character to
and all ‘0’s will be transmitted. initiate transmission (the value is ignored).
The SENDB bit is automatically reset by hardware after 4. Write ‘55h’ to TX1REG to load the Sync
the corresponding Stop bit is sent. This allows the user character into the transmit FIFO buffer.
to preload the transmit FIFO with the next transmit byte 5. After the Break has been sent, the SENDB bit is
following the Break character (typically, the Sync reset by hardware and the Sync character is
character in the LIN specification). then transmitted.
The TRMT bit of the TX1STA register indicates when the When the TX1REG becomes empty, as indicated by
transmit operation is active or idle, just as it does during the TX1IF, the next data byte can be written to
normal transmission. See Figure 33-9 for the timing of TX1REG.
the Break character sequence.

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33.3.5 RECEIVING A BREAK CHARACTER
The Enhanced EUSART module can receive a Break
character in two ways.
The first method to detect a Break character uses the
FERR bit of the RC1STA register and the received data
as indicated by RC1REG. The Baud Rate Generator is
assumed to have been initialized to the expected baud
rate.
A Break character has been received when:
• RX1IF bit is set
• FERR bit is set
• RC1REG = 00h
The second method uses the Auto-Wake-up feature
described in Section 33.3.3 “Auto-Wake-up on
Break”. By enabling this feature, the EUSART will
sample the next two transitions on RX/DT, cause an
RX1IF interrupt, and receive the next data byte fol-
lowed by another interrupt.
Note that following a Break character, the user will
typically want to enable the Auto-Baud Detect feature.
For both methods, the user can set the ABDEN bit of
the BAUD1CON register before placing the EUSART in
Sleep mode.

FIGURE 33-9: SEND BREAK CHARACTER SEQUENCE

Write to TXxREG
Dummy Write

BRG Output
(Shift Clock)

TX (pin) Start bit bit 0 bit 1 bit 11 Stop bit

Break
TXxIF bit
(Transmit
Interrupt Flag)
TRMT bit
(Transmit Shift
Empty Flag)
SENDB Sampled Here Auto Cleared
SENDB
(send Break
control bit)

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33.4 EUSART Synchronous Mode 33.4.1.2 Clock Polarity
Synchronous serial communications are typically used A clock polarity option is provided for Microwire
in systems with a single master and one or more compatibility. Clock polarity is selected with the SCKP
slaves. The master device contains the necessary bit of the BAUD1CON register. Setting the SCKP bit
circuitry for baud rate generation and supplies the clock sets the clock Idle state as high. When the SCKP bit is
for all devices in the system. Slave devices can take set, the data changes on the falling edge of each clock.
advantage of the master clock by eliminating the Clearing the SCKP bit sets the Idle state as low. When
internal clock generation circuitry. the SCKP bit is cleared, the data changes on the rising
edge of each clock.
There are two signal lines in Synchronous mode: a
bidirectional data line and a clock line. Slaves use the 33.4.1.3 Synchronous Master Transmission
external clock supplied by the master to shift the serial
data into and out of their respective receive and trans- Data is transferred out of the device on the RX/DT pin.
mit shift registers. Since the data line is bidirectional, The RX/DT and TX/CK pin output drivers are automat-
synchronous operation is half-duplex only. Half-duplex ically enabled when the EUSART is configured for
refers to the fact that master and slave devices can synchronous master transmit operation.
receive and transmit data but not both simultaneously. A transmission is initiated by writing a character to the
The EUSART can operate as either a master or slave TX1REG register. If the TSR still contains all or part of
device. a previous character the new character data is held in
Start and Stop bits are not used in synchronous the TX1REG until the last bit of the previous character
transmissions. has been transmitted. If this is the first character, or the
previous character has been completely flushed from
33.4.1 SYNCHRONOUS MASTER MODE the TSR, the data in the TX1REG is immediately trans-
ferred to the TSR. The transmission of the character
The following bits are used to configure the EUSART commences immediately following the transfer of the
for synchronous master operation: data to the TSR from the TX1REG.
• SYNC = 1 Each data bit changes on the leading edge of the
• CSRC = 1 master clock and remains valid until the subsequent
• SREN = 0 (for transmit); SREN = 1 (for receive) leading clock edge.
• CREN = 0 (for transmit); CREN = 1 (for receive) Note: The TSR register is not mapped in data
• SPEN = 1 memory, so it is not available to the user.
Setting the SYNC bit of the TX1STA register configures
the device for synchronous operation. Setting the CSRC 33.4.1.4 Synchronous Master Transmission
bit of the TX1STA register configures the device as a Set-up:
master. Clearing the SREN and CREN bits of the 1. Initialize the SP1BRGH, SP1BRGL register pair
RC1STA register ensures that the device is in the and the BRGH and BRG16 bits to achieve the
Transmit mode, otherwise the device will be configured desired baud rate (see Section 33.3 “EUSART
to receive. Setting the SPEN bit of the RC1STA register Baud Rate Generator (BRG)”).
enables the EUSART.
2. Enable the synchronous master serial port by
33.4.1.1 Master Clock setting bits SYNC, SPEN and CSRC.
3. Disable Receive mode by clearing bits SREN
Synchronous data transfers use a separate clock line,
and CREN.
which is synchronous with the data. A device config-
ured as a master transmits the clock on the TX/CK line. 4. Enable Transmit mode by setting the TXEN bit.
The TX/CK pin output driver is automatically enabled 5. If 9-bit transmission is desired, set the TX9 bit.
when the EUSART is configured for synchronous 6. If interrupts are desired, set the TX1IE bit of the
transmit or receive operation. Serial data bits change PIE3 register and the GIE and PEIE bits of the
on the leading edge to ensure they are valid at the INTCON register.
trailing edge of each clock. One clock cycle is gener- 7. If 9-bit transmission is selected, the ninth bit
ated for each data bit. Only as many clock cycles are should be loaded in the TX9D bit.
generated as there are data bits. 8. Start transmission by loading data to the
TX1REG register.

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FIGURE 33-10: SYNCHRONOUS TRANSMISSION
RX/DT
pin bit 0 bit 1 bit 2 bit 7 bit 0 bit 1 bit 7
Word 1 Word 2
TX/CK pin
(SCKP = 0)

TX/CK pin
(SCKP = 1)
Write to
TXxREG Reg Write Word 1 Write Word 2
TXxIF bit
(Interrupt Flag)

TRMT bit

‘1’ ‘1’
TXEN bit

Note: Sync Master mode, SPxBRGL = 0, continuous transmission of two 8-bit words.

FIGURE 33-11: SYNCHRONOUS TRANSMISSION (THROUGH TXEN)

RX/DT pin bit 0 bit 1 bit 2 bit 6 bit 7

TX/CK pin

Write to
TXxREG reg

TXxIF bit

TRMT bit

TXEN bit

33.4.1.5 Synchronous Master Reception To initiate reception, set either SREN or CREN. Data is
sampled at the RX/DT pin on the trailing edge of the
Data is received at the RX/DT pin. The RX/DT pin
TX/CK clock pin and is shifted into the Receive Shift
output driver is automatically disabled when the
Register (RSR). When a complete character is
EUSART is configured for synchronous master receive
received into the RSR, the RX1IF bit is set and the
operation.
character is automatically transferred to the two char-
In Synchronous mode, reception is enabled by setting acter receive FIFO. The Least Significant eight bits of
either the Single Receive Enable bit (SREN of the the top character in the receive FIFO are available in
RC1STA register) or the Continuous Receive Enable RC1REG. The RX1IF bit remains set as long as there
bit (CREN of the RC1STA register). are unread characters in the receive FIFO.
When SREN is set and CREN is clear, only as many Note: If the RX/DT function is on an analog pin,
clock cycles are generated as there are data bits in a the corresponding ANSEL bit must be
single character. The SREN bit is automatically cleared cleared for the receiver to function.
at the completion of one character. When CREN is set,
clocks are continuously generated until CREN is
cleared. If CREN is cleared in the middle of a character
the CK clock stops immediately and the partial charac-
ter is discarded. If SREN and CREN are both set, then
SREN is cleared at the completion of the first character
and CREN takes precedence.

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33.4.1.6 Slave Clock received. The RX9D bit of the RC1STA register is the
ninth, and Most Significant, data bit of the top unread
Synchronous data transfers use a separate clock line,
character in the receive FIFO. When reading 9-bit data
which is synchronous with the data. A device configured
from the receive FIFO buffer, the RX9D data bit must
as a slave receives the clock on the TX/CK line. The
be read before reading the eight Least Significant bits
TX/CK pin output driver is automatically disabled when
from the RC1REG.
the device is configured for synchronous slave transmit
or receive operation. Serial data bits change on the
33.4.1.9 Synchronous Master Reception
leading edge to ensure they are valid at the trailing edge
Set-up:
of each clock. One data bit is transferred for each clock
cycle. Only as many clock cycles should be received as 1. Initialize the SP1BRGH, SP1BRGL register pair
there are data bits. for the appropriate baud rate. Set or clear the
BRGH and BRG16 bits, as required, to achieve
Note: If the device is configured as a slave and the desired baud rate.
the TX/CK function is on an analog pin, the
2. Clear the ANSEL bit for the RX pin (if applicable).
corresponding ANSEL bit must be cleared.
3. Enable the synchronous master serial port by
33.4.1.7 Receive Overrun Error setting bits SYNC, SPEN and CSRC.
4. Ensure bits CREN and SREN are clear.
The receive FIFO buffer can hold two characters. An
overrun error will be generated if a third character, in its 5. If interrupts are desired, set the RX1IE bit of the
entirety, is received before RC1REG is read to access PIE3 register and the GIE and PEIE bits of the
the FIFO. When this happens the OERR bit of the INTCON register.
RC1STA register is set. Previous data in the FIFO will 6. If 9-bit reception is desired, set bit RX9.
not be overwritten. The two characters in the FIFO 7. Start reception by setting the SREN bit or for
buffer can be read, however, no additional characters continuous reception, set the CREN bit.
will be received until the error is cleared. The OERR bit 8. Interrupt flag bit RX1IF will be set when recep-
can only be cleared by clearing the overrun condition. tion of a character is complete. An interrupt will
If the overrun error occurred when the SREN bit is set be generated if the enable bit RX1IE was set.
and CREN is clear then the error is cleared by reading 9. Read the RC1STA register to get the ninth bit (if
RC1REG. If the overrun occurred when the CREN bit is enabled) and determine if any error occurred
set then the error condition is cleared by either clearing during reception.
the CREN bit of the RC1STA register or by clearing the
10. Read the 8-bit received data by reading the
SPEN bit which resets the EUSART.
RC1REG register.
33.4.1.8 Receiving 9-bit Characters 11. If an overrun error occurs, clear the error by
either clearing the CREN bit of the RC1STA
The EUSART supports 9-bit character reception. When
register or by clearing the SPEN bit which resets
the RX9 bit of the RC1STA register is set the EUSART
the EUSART.
will shift nine bits into the RSR for each character

FIGURE 33-12: SYNCHRONOUS RECEPTION (MASTER MODE, SREN)

RX/DT
pin bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7

TX/CK pin
(SCKP = 0)

TX/CK pin
(SCKP = 1)

Write to
bit SREN

SREN bit

CREN bit ‘0’ ‘0’

RXxIF bit
(Interrupt)
Read
RCxREG

Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.

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33.4.2 SYNCHRONOUS SLAVE MODE 33.4.2.1 EUSART Synchronous Slave
The following bits are used to configure the EUSART Transmit
for synchronous slave operation: The operation of the Synchronous Master and Slave
• SYNC = 1 modes are identical (see Section 33.4.1.3
“Synchronous Master Transmission”), except in the
• CSRC = 0
case of the Sleep mode.
• SREN = 0 (for transmit); SREN = 1 (for receive)
If two words are written to the TX1REG and then the
• CREN = 0 (for transmit); CREN = 1 (for receive)
SLEEP instruction is executed, the following will occur:
• SPEN = 1
1. The first character will immediately transfer to
Setting the SYNC bit of the TX1STA register configures the TSR register and transmit.
the device for synchronous operation. Clearing the
2. The second word will remain in the TX1REG
CSRC bit of the TX1STA register configures the device
register.
as a slave. Clearing the SREN and CREN bits of the
RC1STA register ensures that the device is in the 3. The TX1IF bit will not be set.
Transmit mode, otherwise the device will be configured to 4. After the first character has been shifted out of
receive. Setting the SPEN bit of the RC1STA register TSR, the TX1REG register will transfer the
enables the EUSART. second character to the TSR and the TX1IF bit
will now be set.
5. If the PEIE and TX1IE bits are set, the interrupt
will wake the device from Sleep and execute the
next instruction. If the GIE bit is also set, the
program will call the Interrupt Service Routine.

33.4.2.2 Synchronous Slave Transmission

Set-up:
1. Set the SYNC and SPEN bits and clear the
CSRC bit.
2. Clear the ANSEL bit for the CK pin (if applicable).
3. Clear the CREN and SREN bits.
4. If interrupts are desired, set the TX1IE bit of the
PIE3 register and the GIE and PEIE bits of the
INTCON register.
5. If 9-bit transmission is desired, set the TX9 bit.
6. Enable transmission by setting the TXEN bit.
7. If 9-bit transmission is selected, insert the Most
Significant bit into the TX9D bit.
8. Start transmission by writing the Least
Significant eight bits to the TX1REG register.

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33.4.2.3 EUSART Synchronous Slave 33.4.2.4 Synchronous Slave Reception
Reception Set-up:
The operation of the Synchronous Master and Slave 1. Set the SYNC and SPEN bits and clear the
modes is identical (Section 33.4.1.5 “Synchronous CSRC bit.
Master Reception”), with the following exceptions: 2. Clear the ANSEL bit for both the CK and DT pins
• Sleep (if applicable).
• CREN bit is always set, therefore the receiver is 3. If interrupts are desired, set the RX1IE bit of the
never idle PIE3 register and the GIE and PEIE bits of the
• SREN bit, which is a “don’t care” in Slave mode INTCON register.
4. If 9-bit reception is desired, set the RX9 bit.
A character may be received while in Sleep mode by
setting the CREN bit prior to entering Sleep. Once the 5. Set the CREN bit to enable reception.
word is received, the RSR register will transfer the data 6. The RX1IF bit will be set when reception is
to the RC1REG register. If the RX1IE enable bit is set, complete. An interrupt will be generated if the
the interrupt generated will wake the device from Sleep RX1IE bit was set.
and execute the next instruction. If the GIE bit is also 7. If 9-bit mode is enabled, retrieve the Most
set, the program will branch to the interrupt vector. Significant bit from the RX9D bit of the RC1STA
register.
8. Retrieve the eight Least Significant bits from the
receive FIFO by reading the RC1REG register.
9. If an overrun error occurs, clear the error by
either clearing the CREN bit of the RC1STA
register or by clearing the SPEN bit which resets
the EUSART.

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33.5 EUSART Operation During Sleep 33.5.2 SYNCHRONOUS TRANSMIT
DURING SLEEP
The EUSART will remain active during Sleep only in the
Synchronous Slave mode. All other modes require the To transmit during Sleep, all the following conditions
system clock and therefore cannot generate the neces- must be met before entering Sleep mode:
sary signals to run the Transmit or Receive Shift • The RC1STA and TX1STA Control registers must
registers during Sleep. be configured for synchronous slave transmission
Synchronous Slave mode uses an externally generated (see Section 33.4.2.2 “Synchronous Slave
clock to run the Transmit and Receive Shift registers. Transmission Set-up:”).
• The TX1IF interrupt flag must be cleared by writ-
33.5.1 SYNCHRONOUS RECEIVE DURING ing the output data to the TX1REG, thereby filling
SLEEP the TSR and transmit buffer.
To receive during Sleep, all the following conditions • If interrupts are desired, set the TX1IE bit of the
must be met before entering Sleep mode: PIE3 register and the PEIE bit of the INTCON
register.
• RC1STA and TX1STA Control registers must be
configured for Synchronous Slave Reception (see • Interrupt enable bits TX1IE of the PIE3 register
Section 33.4.2.4 “Synchronous Slave and PEIE of the INTCON register must set.
Reception Set-up:”). Upon entering Sleep mode, the device will be ready to
• If interrupts are desired, set the RX1IE bit of the accept clocks on TX/CK pin and transmit data on the
PIE3 register and the GIE and PEIE bits of the RX/DT pin. When the data word in the TSR has been
INTCON register. completely clocked out by the external device, the
• The RX1IF interrupt flag must be cleared by read- pending byte in the TX1REG will transfer to the TSR
ing RC1REG to unload any pending characters in and the TX1IF flag will be set. Thereby, waking the
the receive buffer. processor from Sleep. At this point, the TX1REG is
available to accept another character for transmission,
Upon entering Sleep mode, the device will be ready to which will clear the TX1IF flag.
accept data and clocks on the RX/DT and TX/CK pins,
respectively. When the data word has been completely Upon waking from Sleep, the instruction following the
clocked in by the external device, the RX1IF interrupt SLEEP instruction will be executed. If the Global
flag bit of the PIR3 register will be set. Thereby, waking Interrupt Enable (GIE) bit is also set then the Interrupt
the processor from Sleep. Service Routine at address 0004h will be called.

Upon waking from Sleep, the instruction following the

SLEEP instruction will be executed. If the Global
Interrupt Enable (GIE) bit of the INTCON register is
also set, then the Interrupt Service Routine at address
004h will be called.

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33.6 Register Definitions: EUSART Control
REGISTER 33-1: TX1STA: TRANSMIT STATUS AND CONTROL REGISTER
R/W-/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R-1/1 R/W-0/0
(1)
CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 CSRC: Clock Source Select bit

Asynchronous mode:
Unused in this mode – value ignored
Synchronous mode:
1 = Master mode (clock generated internally from BRG)
0 = Slave mode (clock from external source)
bit 6 TX9: 9-bit Transmit Enable bit
1 = Selects 9-bit transmission
0 = Selects 8-bit transmission
bit 5 TXEN: Transmit Enable bit(1)
1 = Transmit enabled
0 = Transmit disabled
bit 4 SYNC: EUSART Mode Select bit
1 = Synchronous mode
0 = Asynchronous mode
bit 3 SENDB: Send Break Character bit
Asynchronous mode:
1 = Send SYNCH BREAK on next transmission – Start bit, followed by 12 ‘0’ bits, followed by Stop
bit; cleared by hardware upon completion
0 = SYNCH BREAK transmission disabled or completed
Synchronous mode:
Unused in this mode – value ignored
bit 2 BRGH: High Baud Rate Select bit
Asynchronous mode:
1 = High speed
0 = Low speed
Synchronous mode:
Unused in this mode – value ignored
bit 1 TRMT: Transmit Shift Register Status bit
1 = TSR empty
0 = TSR full
bit 0 TX9D: Ninth bit of Transmit Data
Can be address/data bit or a parity bit.

Note 1: SREN/CREN overrides TXEN in Sync mode.

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REGISTER 33-2: RC1STA: RECEIVE STATUS AND CONTROL REGISTER

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R-0/0 R-0/0 R-0/0
(1)
SPEN RX9 SREN CREN ADDEN FERR OERR RX9D
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 SPEN: Serial Port Enable bit(1)

1 = Serial port enabled
0 = Serial port disabled (held in Reset)
bit 6 RX9: 9-Bit Receive Enable bit
1 = Selects 9-bit reception
0 = Selects 8-bit reception
bit 5 SREN: Single Receive Enable bit
Asynchronous mode:
Unused in this mode – value ignored
Synchronous mode – Master:
1 = Enables single receive
0 = Disables single receive
This bit is cleared after reception is complete.
Synchronous mode – Slave
Unused in this mode – value ignored
bit 4 CREN: Continuous Receive Enable bit
Asynchronous mode:
1 = Enables continuous receive until enable bit CREN is cleared
0 = Disables continuous receive
Synchronous mode:
1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)
0 = Disables continuous receive
bit 3 ADDEN: Address Detect Enable bit
Asynchronous mode 9-bit (RX9 = 1):
1 = Enables address detection – enable interrupt and load of the receive buffer when the ninth bit in
the receive buffer is set
0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit
Asynchronous mode 8-bit (RX9 = 0):
Unused in this mode – value ignored
bit 2 FERR: Framing Error bit
1 = Framing error (can be updated by reading RCxREG register and receive next valid byte)
0 = No framing error
bit 1 OERR: Overrun Error bit
1 = Overrun error (can be cleared by clearing bit CREN)
0 = No overrun error
bit 0 RX9D: Ninth bit of Received Data
This can be address/data bit or a parity bit and must be calculated by user firmware.

Note 1: The EUSART module automatically changes the pin from tri-state to drive as needed. Configure the
associated TRIS bits for TX/CK and RX/DT to 1.

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REGISTER 33-3: BAUD1CON: BAUD RATE CONTROL REGISTER

R/W-0/0 R-1/1 U-0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0
ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 ABDOVF: Auto-Baud Detect Overflow bit

Asynchronous mode:
1 = Auto-baud timer overflowed
0 = Auto-baud timer did not overflow
Synchronous mode:
Don’t care
bit 6 RCIDL: Receive Idle Flag bit
Asynchronous mode:
1 = Receiver is Idle
0 = Start bit has been received and the receiver is receiving
Synchronous mode:
Don’t care
bit 5 Unimplemented: Read as ‘0’
bit 4 SCKP: Clock/Transmit Polarity Select bit
Asynchronous mode:
1 = Idle state for transmit (TX) is a low level
0 = Idle state for transmit (TX) is a high level
Synchronous mode:
1 = Idle state for clock (CK) is a high level
0 = Idle state for clock (CK) is a low level
bit 3 BRG16: 16-bit Baud Rate Generator bit
1 = 16-bit Baud Rate Generator is used
0 = 8-bit Baud Rate Generator is used
bit 2 Unimplemented: Read as ‘0’
bit 1 WUE: Wake-up Enable bit
Asynchronous mode:
1 = USART will continue to sample the Rx pin – interrupt generated on falling edge; bit cleared in
hardware on following rising edge.
0 = RX pin not monitored nor rising edge detected
Synchronous mode:
Unused in this mode – value ignored
bit 0 ABDEN: Auto-Baud Detect Enable bit
Asynchronous mode:
1 = Enable baud rate measurement on the next character – requires reception of a SYNCH field
(55h);
cleared in hardware upon completion
0 = Baud rate measurement disabled or completed
Synchronous mode:
Unused in this mode – value ignored

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REGISTER 33-4: RC1REG(1): RECEIVE DATA REGISTER
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
RC1REG<7:0>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-0 RC1REG<7:0>: Lower eight bits of the received data; read-only; see also RX9D (Register 33-2)

Note 1: RC1REG (including the 9th bit) is double buffered, and data is available while new data is being received.

REGISTER 33-5: TX1REG(1): TRANSMIT DATA REGISTER

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
TX1REG<7:0>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-0 TX1REG<7:0>: Lower eight bits of the received data; read-only; see also RX9D (Register 33-1)

Note 1: TX1REG (including the 9th bit) is double buffered, and can be written when previous data has started
shifting.

REGISTER 33-6: SP1BRGL(1): BAUD RATE GENERATOR REGISTER

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
SP1BRG<7:0>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-0 SP1BRG<7:0>: Lower eight bits of the Baud Rate Generator

Note 1: Writing to SP1BRG resets the BRG counter.

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REGISTER 33-7: SP1BRGH(1, 2): BAUD RATE GENERATOR HIGH REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
SP1BRG<15:8>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 SP1BRG<15:8>: Upper eight bits of the Baud Rate Generator

Note 1: SP1BRGH value is ignored for all modes unless BAUDxCON<BRG16> is active.
2: Writing to SP1BRGH resets the BRG counter.

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TABLE 33-2: SUMMARY OF REGISTERS ASSOCIATED WITH EUSART

Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
on Page

INTCON GIE PEIE ― ― ― ― ― INTEDG 121

PIE3 — — RC1IE TX1IE — — BCL1IE SSP1IE 125
PIR3 — — RC1IF TX1IF — — BCL1IF SSP1IF 133
RCxSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 431
TXxSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 430
BAUDxCON ABDOVF RCIDL ― SCKP BRG16 ― WUE ABDEN 432
RCxREG EUSART Receive Data Register 433*
TXxREG EUSART Transmit Data Register 433*
SPxBRGL SPxBRG<7:0> 433*
SPxBRGH SPxBRG<15:8> 434*
RXPPS ― ― RXPPS<5:0> 191
CKPPS ― ― CXPPS<5:0> 191
RxyPPS ― ― ― RxyPPS<4:0> 192
CLCxSELy ― ― LCxDyS<5:0> 352
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for the EUSART module.
* Page with register information.

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TABLE 33-3: BAUD RATE FORMULAS
Configuration Bits
BRG/EUSART Mode Baud Rate Formula
SYNC BRG16 BRGH

0 0 0 8-bit/Asynchronous FOSC/[64 (n+1)]

0 0 1 8-bit/Asynchronous
FOSC/[16 (n+1)]
0 1 0 16-bit/Asynchronous
0 1 1 16-bit/Asynchronous
1 0 x 8-bit/Synchronous FOSC/[4 (n+1)]
1 1 x 16-bit/Synchronous
Legend: x = Don’t care, n = value of SPxBRGH, SPxBRGL register pair.

TABLE 33-4: BAUD RATE FOR ASYNCHRONOUS MODES

SYNC = 0, BRGH = 0, BRG16 = 0
FOSC = 32.000 MHz FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 11.0592 MHz
BAUD
RATE SPBRG SPBRG SPBRG SPBRG
Actual % Actual % Actual % Actual %
value value value value
Rate Error Rate Error Rate Error Rate Error
(decimal) (decimal) (decimal) (decimal)
300 — — — — — — — — — — — —
1200 — — — 1221 1.73 255 1200 0.00 239 1200 0.00 143
2400 2404 0.16 207 2404 0.16 129 2400 0.00 119 2400 0.00 71
9600 9615 0.16 51 9470 -1.36 32 9600 0.00 29 9600 0.00 17
10417 10417 0.00 47 10417 0.00 29 10286 -1.26 27 10165 -2.42 16
19.2k 19.23k 0.16 25 19.53k 1.73 15 19.20k 0.00 14 19.20k 0.00 8
57.6k 55.55k -3.55 3 — — — 57.60k 0.00 7 57.60k 0.00 2
115.2k — — — — — — — — — — — —

SYNC = 0, BRGH = 0, BRG16 = 0

FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 1.000 MHz
BAUD
RATE SPBRG SPBRG SPBRG SPBRG
Actual % Actual % Actual % Actual %
value value value value
Rate Error Rate Error Rate Error Rate Error
(decimal) (decimal) (decimal) (decimal)
300 — — — 300 0.16 207 300 0.00 191 300 0.16 51
1200 1202 0.16 103 1202 0.16 51 1200 0.00 47 1202 0.16 12
2400 2404 0.16 51 2404 0.16 25 2400 0.00 23 — — —
9600 9615 0.16 12 — — — 9600 0.00 5 — — —
10417 10417 0.00 11 10417 0.00 5 — — — — — —
19.2k — — — — — — 19.20k 0.00 2 — — —
57.6k — — — — — — 57.60k 0.00 0 — — —
115.2k — — — — — — — — — — — —

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TABLE 33-4: BAUD RATE FOR ASYNCHRONOUS MODES (CONTINUED)
SYNC = 0, BRGH = 1, BRG16 = 0

BAUD FOSC = 32.000 MHz FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 11.0592 MHz
RATE SPBRG SPBRG SPBRG SPBRG
Actual % Actual % Actual % Actual %
value value value value
Rate Error Rate Error Rate Error Rate Error
(decimal) (decimal) (decimal) (decimal)
300 — — — — — — — — — — — —
1200 — — — — — — — — — — — —
2400 — — — — — — — — — — — —
9600 9615 0.16 207 9615 0.16 129 9600 0.00 119 9600 0.00 71
10417 10417 0.00 191 10417 0.00 119 10378 -0.37 110 10473 0.53 65
19.2k 19.23k 0.16 103 19.23k 0.16 64 19.20k 0.00 59 19.20k 0.00 35
57.6k 57.14k -0.79 34 56.82k -1.36 21 57.60k 0.00 19 57.60k 0.00 11
115.2k 117.64k 2.12 16 113.64k -1.36 10 115.2k 0.00 9 115.2k 0.00 5

SYNC = 0, BRGH = 1, BRG16 = 0

BAUD FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 1.000 MHz
RATE SPBRG SPBRG SPBRG SPBRG
Actual % Actual % Actual % Actual %
value value value value
Rate Error Rate Error Rate Error Rate Error
(decimal) (decimal) (decimal) (decimal)
300 — — — — — — — — — 300 0.16 207
1200 — — — 1202 0.16 207 1200 0.00 191 1202 0.16 51
2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.16 25
9600 9615 0.16 51 9615 0.16 25 9600 0.00 23 — — —
10417 10417 0.00 47 10417 0.00 23 10473 0.53 21 10417 0.00 5
19.2k 19231 0.16 25 19.23k 0.16 12 19.2k 0.00 11 — — —
57.6k 55556 -3.55 8 — — — 57.60k 0.00 3 — — —
115.2k — — — — — — 115.2k 0.00 1 — — —

SYNC = 0, BRGH = 0, BRG16 = 1

BAUD FOSC = 32.000 MHz FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 11.0592 MHz
RATE SPBRG SPBRG SPBRG SPBRG
Actual % Actual % Actual % Actual %
value value value value
Rate Error Rate Error Rate Error Rate Error
(decimal) (decimal) (decimal) (decimal)
300 300.0 0.00 6666 300.0 -0.01 4166 300.0 0.00 3839 300.0 0.00 2303
1200 1200 -0.02 3332 1200 -0.03 1041 1200 0.00 959 1200 0.00 575
2400 2401 -0.04 832 2399 -0.03 520 2400 0.00 479 2400 0.00 287
9600 9615 0.16 207 9615 0.16 129 9600 0.00 119 9600 0.00 71
10417 10417 0.00 191 10417 0.00 119 10378 -0.37 110 10473 0.53 65
19.2k 19.23k 0.16 103 19.23k 0.16 64 19.20k 0.00 59 19.20k 0.00 35
57.6k 57.14k -0.79 34 56.818 -1.36 21 57.60k 0.00 19 57.60k 0.00 11
115.2k 117.6k 2.12 16 113.636 -1.36 10 115.2k 0.00 9 115.2k 0.00 5

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TABLE 33-4: BAUD RATE FOR ASYNCHRONOUS MODES (CONTINUED)
SYNC = 0, BRGH = 0, BRG16 = 1

BAUD FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 1.000 MHz
RATE SPBRG SPBRG SPBRG SPBRG
Actual % Actual % Actual % Actual %
value value value value
Rate Error Rate Error Rate Error Rate Error
(decimal) (decimal) (decimal) (decimal)
300 299.9 -0.02 1666 300.1 0.04 832 300.0 0.00 767 300.5 0.16 207
1200 1199 -0.08 416 1202 0.16 207 1200 0.00 191 1202 0.16 51
2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.16 25
9600 9615 0.16 51 9615 0.16 25 9600 0.00 23 — — —
10417 10417 0.00 47 10417 0.00 23 10473 0.53 21 10417 0.00 5
19.2k 19.23k 0.16 25 19.23k 0.16 12 19.20k 0.00 11 — — —
57.6k 55556 -3.55 8 — — — 57.60k 0.00 3 — — —
115.2k — — — — — — 115.2k 0.00 1 — — —

SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1

BAUD FOSC = 32.000 MHz FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 11.0592 MHz
RATE SPBRG SPBRG SPBRG SPBRG
Actual % Actual % Actual % Actual %
value value value value
Rate Error Rate Error Rate Error Rate Error
(decimal) (decimal) (decimal) (decimal)
300 300.0 0.00 26666 300.0 0.00 16665 300.0 0.00 15359 300.0 0.00 9215
1200 1200 0.00 6666 1200 -0.01 4166 1200 0.00 3839 1200 0.00 2303
2400 2400 0.01 3332 2400 0.02 2082 2400 0.00 1919 2400 0.00 1151
9600 9604 0.04 832 9597 -0.03 520 9600 0.00 479 9600 0.00 287
10417 10417 0.00 767 10417 0.00 479 10425 0.08 441 10433 0.16 264
19.2k 19.18k -0.08 416 19.23k 0.16 259 19.20k 0.00 239 19.20k 0.00 143
57.6k 57.55k -0.08 138 57.47k -0.22 86 57.60k 0.00 79 57.60k 0.00 47
115.2k 115.9k 0.64 68 116.3k 0.94 42 115.2k 0.00 39 115.2k 0.00 23

SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1

BAUD FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 1.000 MHz
RATE SPBRG SPBRG SPBRG SPBRG
Actual % Actual % Actual % Actual %
value value value value
Rate Error Rate Error Rate Error Rate Error
(decimal) (decimal) (decimal) (decimal)
300 300.0 0.00 6666 300.0 0.01 3332 300.0 0.00 3071 300.1 0.04 832
1200 1200 -0.02 1666 1200 0.04 832 1200 0.00 767 1202 0.16 207
2400 2401 0.04 832 2398 0.08 416 2400 0.00 383 2404 0.16 103
9600 9615 0.16 207 9615 0.16 103 9600 0.00 95 9615 0.16 25
10417 10417 0 191 10417 0.00 95 10473 0.53 87 10417 0.00 23
19.2k 19.23k 0.16 103 19.23k 0.16 51 19.20k 0.00 47 19.23k 0.16 12
57.6k 57.14k -0.79 34 58.82k 2.12 16 57.60k 0.00 15 — — —
115.2k 117.6k 2.12 16 111.1k -3.55 8 115.2k 0.00 7 — — —

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34.0 REFERENCE CLOCK OUTPUT 34.3 SELECTABLE DUTY CYCLE
MODULE The CLKRDC<1:0> bits of the CLKRCON register can
The reference clock output module provides the ability be used to modify the duty cycle of the output clock. A
to send a clock signal to the clock reference output pin duty cycle of 25%, 50%, or 75% can be selected for all
(CLKR). clock rates, with the exception of the undivided base
FOSC value.
The reference clock output module has the following
features: The duty cycle can be changed while the module is
enabled; however, in order to prevent glitches on the
• Selectable input clock output, the CLKRDC<1:0> bits should only be changed
• Programmable clock divider when the module is disabled (CLKREN = 0).
• Selectable duty cycle

34.1 CLOCK SOURCE Note: The CLKRDC1 bit is reset to ‘1’. This
makes the default duty cycle 50% and not
The reference clock output module has a selectable 0%.
clock source. The CLKRCLK register (Register 34-2)
controls which input is used.
34.4 OPERATION IN SLEEP MODE
34.1.1 CLOCK SYNCHRONIZATION
The reference clock output module clock is based on
Once the reference clock enable (CLKREN) is set, the the system clock. When the device goes to Sleep, the
module is ensured to be glitch-free at start-up. module outputs will remain in their current state. This
When the reference clock output is disabled, the output will have a direct effect on peripherals using the
signal will be disabled immediately. reference clock output as an input signal.

Clock dividers and clock duty cycles can be changed

while the module is enabled, but glitches may occur on
the output. To avoid possible glitches, clock dividers
and clock duty cycles should be changed only when the
CLKREN is clear.

34.2 PROGRAMMABLE CLOCK

DIVIDER
The module takes the system clock input and divides it
based on the value of the CLKRDIV<2:0> bits of the
CLKRCON register (Register 34-1).
The following configurations can be made based on the
CLKRDIV<2:0> bits:
• Base clock value
• Base clock value divided by 2
• Base clock value divided by 4
• Base clock value divided by 8
• Base clock value divided by 16
• Base clock value divided by 32
• Base clock value divided by 64
• Base clock value divided by 128
The clock divider values can be changed while the
module is enabled; however, in order to prevent
glitches on the output, the CLKRDIV<2:0> bits should
only be changed when the module is disabled
(CLKREN = 0).

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 PIC16(L)F15313/23
FIGURE 34-1: CLOCK REFERENCE BLOCK DIAGRAM

Rev. 10-000261A
9/10/2015

CLKRDIV<2:0>
CLKREN Counter Reset
128
111

Reference Clock Divider

See 64 CLKRDC<1:0>
110
CLKRCLK 32
Register 101
16 CLKR
100
8 Duty Cycle PPS
011
4
010
2
001 To Peripherals

CLKREN
D Q 000
CLKRCLK<3:0>
FREEZE ENABLED(1) EN
ICD FREEZE MODE(1)

FIGURE 34-2: CLOCK REFERENCE TIMING

P1 P2

FOSC

CLKREN

CLKR Output
CLKRDIV[2:0] = 001
Duty Cycle
CLKRDC[1:0] = 10
(50%)

CLKR Output FOSC / 2

CLKRDIV[2:0] = 001
CLKRDC[1:0] = 01

Duty Cycle (25%)

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REGISTER 34-1: CLKRCON: REFERENCE CLOCK CONTROL REGISTER

R/W-0/0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
CLKREN — — CLKRDC<1:0> CLKRDIV<2:0>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 CLKREN: Reference Clock Module Enable bit

1 = Reference clock module enabled
0 = Reference clock module is disabled
bit 6-5 Unimplemented: Read as ‘0’
bit 4-3 CLKRDC<1:0>: Reference Clock Duty Cycle bits (1)
11 = Clock outputs duty cycle of 75%
10 = Clock outputs duty cycle of 50%
01 = Clock outputs duty cycle of 25%
00 = Clock outputs duty cycle of 0%
bit 2-0 CLKRDIV<2:0>: Reference Clock Divider bits
111 = Base clock value divided by 128
110 = Base clock value divided by 64
101 = Base clock value divided by 32
100 = Base clock value divided by 16
011 = Base clock value divided by 8
010 = Base clock value divided by 4
001 = Base clock value divided by 2
000 = Base clock value

Note 1: Bits are valid for reference clock divider values of two or larger, the base clock cannot be further divided.

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 PIC16(L)F15313/23
REGISTER 34-2: CLKRCLK: CLOCK REFERENCE CLOCK SELECTION REGISTER
U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— — — — CLKRCLK<3:0>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-4 Unimplemented: Read as ‘0’

bit 3-0 CLKRCLK<3:0>: CLKR Input bits
Clock Selection
1111 = Reserved
•
•
•
1011 = Reserved
1010 = LC4_out
1001 = LC3_out
1000 = LC2_out
0111 = LC1_out
0110 = NCO1_out
0101 = Reserved
0100 = MFINTOSC (31.25 kHz)
0011 = MFINTOSC (500 kHz)
0010 = LFINTOSC
0001 = HFINTOSC
0000 = FOSC

TABLE 34-1: SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK REFERENCE OUTPUT

Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
on Page
CLKRCON CLKREN — — CLKRDC<1:0> CLKRDIV<2:0> 441
CLKRCLK — — — — CLKRCLK<3:0> 442
CLCxSELy — — LCxDyS<5:0> 352
RxyPPS — — — RxyPPS<4:0> 192
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the CLKR module.

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 PIC16(L)F15313/23
35.0 IN-CIRCUIT SERIAL 35.3 Common Programming Interfaces
PROGRAMMING™ (ICSP™) Connection to a target device is typically done through
ICSP™ programming allows customers to manufacture an ICSP™ header. A commonly found connector on
circuit boards with unprogrammed devices. Programming development tools is the RJ-11 in the 6P6C (6-pin,
can be done after the assembly process, allowing the 6-connector) configuration. See Figure 35-1.
device to be programmed with the most recent firmware
or a custom firmware. Five pins are needed for ICSP™ FIGURE 35-1: ICD RJ-11 STYLE
programming: CONNECTOR INTERFACE
• ICSPCLK
• ICSPDAT
• MCLR/VPP
• VDD
ICSPDAT
• VSS
2 4 6 NC
VDD
In Program/Verify mode the program memory, User IDs ICSPCLK
and the Configuration Words are programmed through 1 3 5
Target
serial communications. The ICSPDAT pin is a VPP/MCLR PC Board
VSS
bidirectional I/O used for transferring the serial data Bottom Side
and the ICSPCLK pin is the clock input. For more
information on ICSP™ refer to the “PIC16(L)F153XX
Memory Programming Specification” (DS40001838). Pin Description*

1 = VPP/MCLR
35.1 High-Voltage Programming Entry 2 = VDD Target
Mode 3 = VSS (ground)

The device is placed into High-Voltage Programming 4 = ICSPDAT

Entry mode by holding the ICSPCLK and ICSPDAT 5 = ICSPCLK

pins low then raising the voltage on MCLR/VPP to VIHH. 6 = No Connect

35.2 Low-Voltage Programming Entry Another connector often found in use with the PICkit™
Mode programmers is a standard 6-pin header with 0.1 inch
spacing. Refer to Figure 35-2.
The Low-Voltage Programming Entry mode allows the
PIC® Flash MCUs to be programmed using VDD only, For additional interface recommendations, refer to your
without high voltage. When the LVP bit of Configuration specific device programmer manual prior to PCB
Words is set to ‘1’, the low-voltage ICSP programming design.
entry is enabled. To disable the Low-Voltage ICSP It is recommended that isolation devices be used to
mode, the LVP bit must be programmed to ‘0’. The LVP separate the programming pins from other circuitry.
bit can only be reprogrammed to ‘0’ by using the The type of isolation is highly dependent on the specific
High-Voltage Programming mode. application and may include devices such as resistors,
Entry into the Low-Voltage Programming Entry mode diodes, or even jumpers. See Figure 35-3 for more
requires the following steps: information.
1. MCLR is brought to VIL.
2. A 32-bit key sequence is presented on
ICSPDAT, while clocking ICSPCLK.
Once the key sequence is complete, MCLR must be
held at VIL for as long as Program/Verify mode is to be
maintained.
If low-voltage programming is enabled (LVP = 1), the
MCLR Reset function is automatically enabled and
cannot be disabled. See Section 8.5“MCLR” for more
information.

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 PIC16(L)F15313/23
FIGURE 35-2: PICkit™ PROGRAMMER STYLE CONNECTOR INTERFACE
Rev. 10-000128A
7/30/2013

Pin 1 Indicator

Pin Description*
1 = VPP/MCLR
1
2
2 = VDD Target
3
4 3 = VSS (ground)
5
6 4 = ICSPDAT
5 = ICSPCLK
6 = No connect

FIGURE 35-3: TYPICAL CONNECTION FOR ICSP™ PROGRAMMING

Rev. 10-000129A
7/30/2013

External Device to be
Programming VDD Programmed
Signals

VDD VDD

VPP MCLR/VPP
VSS VSS

Data ICSPDAT
Clock ICSPCLK

* * *

To Normal Connections

* Isolation devices (as required).

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36.0 INSTRUCTION SET SUMMARY 36.1 Read-Modify-Write Operations
Each instruction is a 14-bit word containing the Any instruction that specifies a file register as part of
operation code (opcode) and all required operands. the instruction performs a Read-Modify-Write (R-M-W)
The opcodes are broken into three broad categories. operation. The register is read, the data is modified,
and the result is stored according to either the instruc-
• Byte Oriented
tion, or the destination designator ‘d’. A read operation
• Bit Oriented is performed on a register even if the instruction writes
• Literal and Control to that register.
The literal and control category contains the most
varied instruction word format. TABLE 36-1: OPCODE FIELD
Table 36-3 lists the instructions recognized by the DESCRIPTIONS
MPASMTM assembler. Field Description
All instructions are executed within a single instruction f Register file address (0x00 to 0x7F)
cycle, with the following exceptions, which may take
W Working register (accumulator)
two or three cycles:
b Bit address within an 8-bit file register
• Subroutine entry takes two cycles (CALL, CALLW)
• Returns from interrupts or subroutines take two k Literal field, constant data or label
cycles (RETURN, RETLW, RETFIE) x Don’t care location (= 0 or 1).
• Program branching takes two cycles (GOTO, BRA, The assembler will generate code with x = 0.
BRW, BTFSS, BTFSC, DECFSZ, INCSFZ) It is the recommended form of use for
• One additional instruction cycle will be used when compatibility with all Microchip software tools.
any instruction references an indirect file register d Destination select; d = 0: store result in W,
and the file select register is pointing to program d = 1: store result in file register f.
memory. Default is d = 1.
One instruction cycle consists of 4 oscillator cycles; for n FSR or INDF number. (0-1)
an oscillator frequency of 4 MHz, this gives a nominal mm Prepost increment-decrement mode selection
instruction execution rate of 1 MHz.
All instruction examples use the format ‘0xhh’ to TABLE 36-2: ABBREVIATION
represent a hexadecimal number, where ‘h’ signifies a
DESCRIPTIONS
hexadecimal digit.
Field Description
PC Program Counter
TO Time-Out bit
C Carry bit
DC Digit Carry bit
Z Zero bit
PD Power-Down bit

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36.2 General Format for Instructions

TABLE 36-3: INSTRUCTION SET

Mnemonic, 14-Bit Opcode Status
Description Cycles Notes
Operands MSb LSb Affected

BYTE-ORIENTED FILE REGISTER OPERATIONS

ADDWF f, d Add W and f 1 00 0111 dfff ffff C, DC, Z 2
ADDWFC f, d Add with Carry W and f 1 11 1101 dfff ffff C, DC, Z 2
ANDWF f, d AND W with f 1 00 0101 dfff ffff Z 2
ASRF f, d Arithmetic Right Shift 1 11 0111 dfff ffff C, Z 2
LSLF f, d Logical Left Shift 1 11 0101 dfff ffff C, Z 2
LSRF f, d Logical Right Shift 1 11 0110 dfff ffff C, Z 2
CLRF f Clear f 1 00 0001 lfff ffff Z 2
CLRW – Clear W 1 00 0001 0000 00xx Z
COMF f, d Complement f 1 00 1001 dfff ffff Z 2
DECF f, d Decrement f 1 00 0011 dfff ffff Z 2
INCF f, d Increment f 1 00 1010 dfff ffff Z 2
IORWF f, d Inclusive OR W with f 1 00 0100 dfff ffff Z 2
MOVF f, d Move f 1 00 1000 dfff ffff Z 2
MOVWF f Move W to f 1 00 0000 1fff ffff 2
RLF f, d Rotate Left f through Carry 1 00 1101 dfff ffff C 2
RRF f, d Rotate Right f through Carry 1 00 1100 dfff ffff C 2
SUBWF f, d Subtract W from f 1 00 0010 dfff ffff C, DC, Z 2
SUBWFB f, d Subtract with Borrow W from f 1 11 1011 dfff ffff C, DC, Z 2
SWAPF f, d Swap nibbles in f 1 00 1110 dfff ffff 2
XORWF f, d Exclusive OR W with f 1 00 0110 dfff ffff Z 2
BYTE ORIENTED SKIP OPERATIONS

DECFSZ f, d Decrement f, Skip if 0 1(2) 00 1011 dfff ffff 1, 2

INCFSZ f, d Increment f, Skip if 0 1(2) 00 1111 dfff ffff 1, 2

BIT-ORIENTED FILE REGISTER OPERATIONS

BCF f, b Bit Clear f 1 01 00bb bfff ffff 2

BSF f, b Bit Set f 1 01 01bb bfff ffff 2

BIT-ORIENTED SKIP OPERATIONS

BTFSC f, b Bit Test f, Skip if Clear 1 (2) 01 10bb bfff ffff 1, 2
BTFSS f, b Bit Test f, Skip if Set 1 (2) 01 11bb bfff ffff 1, 2
LITERAL OPERATIONS
ADDLW k Add literal and W 1 11 1110 kkkk kkkk C, DC, Z
ANDLW k AND literal with W 1 11 1001 kkkk kkkk Z
IORLW k Inclusive OR literal with W 1 11 1000 kkkk kkkk Z
MOVLB k Move literal to BSR 1 00 000 0k kkkk
MOVLP k Move literal to PCLATH 1 11 0001 1kkk kkkk
MOVLW k Move literal to W 1 11 0000 kkkk kkkk
SUBLW k Subtract W from literal 1 11 1100 kkkk kkkk C, DC, Z
XORLW k Exclusive OR literal with W 1 11 1010 kkkk kkkk Z
Note 1: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second
cycle is executed as a NOP.
2: If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require
one additional instruction cycle.

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 PIC16(L)F15313/23
TABLE 36-3: INSTRUCTION SET (CONTINUED)
Mnemonic, 14-Bit Opcode Status
Description Cycles Notes
Operands MSb LSb Affected

CONTROL OPERATIONS
BRA k Relative Branch 2 11 001k kkkk kkkk
BRW – Relative Branch with W 2 00 0000 0000 1011
CALL k Call Subroutine 2 10 0kkk kkkk kkkk
CALLW – Call Subroutine with W 2 00 0000 0000 1010
GOTO k Go to address 2 10 1kkk kkkk kkkk
RETFIE k Return from interrupt 2 00 0000 0000 1001
RETLW k Return with literal in W 2 11 0100 kkkk kkkk
RETURN – Return from Subroutine 2 00 0000 0000 1000
INHERENT OPERATIONS
CLRWDT – Clear Watchdog Timer 1 00 0000 0110 0100 TO, PD
NOP – No Operation 1 00 0000 0000 0000
RESET – Software device Reset 1 00 0000 0000 0001
SLEEP – Go into Standby or IDLE mode 1 00 0000 0110 0011 TO, PD
TRIS f Load TRIS register with W 1 00 0000 0110 0fff
C-COMPILER OPTIMIZED
ADDFSR n, k Add Literal k to FSRn 1 11 0001 0nkk kkkk
MOVIW n mm Move Indirect FSRn to W with pre/post inc/dec 1 00 0000 0001 0nmm Z 2, 3
modifier, mm
k[n] Move INDFn to W, Indexed Indirect. 1 11 1111 0nkk kkkk Z 2
MOVWI n mm Move W to Indirect FSRn with pre/post inc/dec 1 00 0000 0001 1nmm 2, 3
modifier, mm
k[n] Move W to INDFn, Indexed Indirect. 1 11 1111 1nkk kkkk 2
Note 1: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second
cycle is executed as a NOP.
2: If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require
one additional instruction cycle.
3: See Table in the MOVIW and MOVWI instruction descriptions.

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 PIC16(L)F15313/23
36.3 Instruction Descriptions

ADDFSR Add Literal to FSRn ANDLW AND literal with W

Syntax: [ label ] ADDFSR FSRn, k Syntax: [ label ] ANDLW k
Operands: -32  k  31 Operands: 0  k  255
n  [ 0, 1]
Operation: (W) .AND. (k)  (W)
Operation: FSR(n) + k  FSR(n)
Status Affected: Z
Status Affected: None Description: The contents of W register are
Description: The signed 6-bit literal ‘k’ is added to AND’ed with the 8-bit literal ‘k’. The
the contents of the FSRnH:FSRnL result is placed in the W register.
register pair.

FSRn is limited to the range

0000h-FFFFh. Moving beyond these
bounds will cause the FSR to
wrap-around.

ANDWF AND W with f

ADDLW Add literal and W
Syntax: [ label ] ANDWF f,d
Syntax: [ label ] ADDLW k Operands: 0  f  127
Operands: 0  k  255 d 0,1
Operation: (W) + k  (W) Operation: (W) .AND. (f)  (destination)
Status Affected: C, DC, Z Status Affected: Z
Description: The contents of the W register are Description: AND the W register with register ‘f’. If
added to the 8-bit literal ‘k’ and the ‘d’ is ‘0’, the result is stored in the W
result is placed in the W register. register. If ‘d’ is ‘1’, the result is stored
back in register ‘f’.

ASRF Arithmetic Right Shift

ADDWF Add W and f
Syntax: [ label ] ASRF f {,d}
Syntax: [ label ] ADDWF f,d Operands: 0  f  127
Operands: 0  f  127 d [0,1]
d 0,1 Operation: (f<7>) dest<7>
Operation: (W) + (f)  (destination) (f<7:1>)  dest<6:0>,
(f<0>)  C,
Status Affected: C, DC, Z
Status Affected: C, Z
Description: Add the contents of the W register
with register ‘f’. If ‘d’ is ‘0’, the result is Description: The contents of register ‘f’ are shifted
stored in the W register. If ‘d’ is ‘1’, the one bit to the right through the Carry
result is stored back in register ‘f’. flag. The MSb remains unchanged. If
‘d’ is ‘0’, the result is placed in W. If ‘d’
is ‘1’, the result is stored back in
register ‘f’.

register f C
ADDWFC ADD W and CARRY bit to f
Syntax: [ label ] ADDWFC f {,d}
Operands: 0  f  127
d [0,1]
Operation: (W) + (f) + (C)  dest
Status Affected: C, DC, Z
Description: Add W, the Carry flag and data mem-
ory location ‘f’. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed in data memory location ‘f’.

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 PIC16(L)F15313/23

BCF Bit Clear f BTFSC Bit Test f, Skip if Clear

Syntax: [ label ] BCF f,b Syntax: [ label ] BTFSC f,b

Operands: 0  f  127 Operands: 0  f  127

0b7 0b7

Operation: 0  (f<b>) Operation: skip if (f<b>) = 0

Status Affected: None Status Affected: None

Description: Bit ‘b’ in register ‘f’ is cleared. Description: If bit ‘b’ in register ‘f’ is ‘1’, the next
instruction is executed.
If bit ‘b’, in register ‘f’, is ‘0’, the next
instruction is discarded, and a NOP is
executed instead, making this a
2-cycle instruction.

BRA Relative Branch BTFSS Bit Test f, Skip if Set

Syntax: [ label ] BRA label Syntax: [ label ] BTFSS f,b
[ label ] BRA $+k Operands: 0  f  127
Operands: -256  label - PC + 1  255 0b<7
-256  k  255 Operation: skip if (f<b>) = 1
Operation: (PC) + 1 + k  PC Status Affected: None
Status Affected: None Description: If bit ‘b’ in register ‘f’ is ‘0’, the next
Description: Add the signed 9-bit literal ‘k’ to the instruction is executed.
PC. Since the PC will have If bit ‘b’ is ‘1’, then the next instruction
incremented to fetch the next is discarded and a NOP is executed
instruction, the new address will be instead, making this a 2-cycle
PC + 1 + k. This instruction is a instruction.
2-cycle instruction. This branch has a
limited range.

BRW Relative Branch with W

Syntax: [ label ] BRW
Operands: None
Operation: (PC) + (W)  PC
Status Affected: None
Description: Add the contents of W (unsigned) to
the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 1 + (W). This instruction is a
2-cycle instruction.

BSF Bit Set f

Syntax: [ label ] BSF f,b
Operands: 0  f  127
0b7
Operation: 1  (f<b>)
Status Affected: None
Description: Bit ‘b’ in register ‘f’ is set.

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 PIC16(L)F15313/23

CALL Call Subroutine CLRWDT Clear Watchdog Timer

Syntax: [ label ] CALL k Syntax: [ label ] CLRWDT
Operands: 0  k  2047 Operands: None
Operation: (PC)+ 1 TOS, Operation: 00h  WDT
k  PC<10:0>, 0  WDT prescaler,
(PCLATH<6:3>)  PC<14:11> 1  TO
Status Affected: None 1  PD
Description: Call Subroutine. First, return address Status Affected: TO, PD
(PC + 1) is pushed onto the stack. Description: CLRWDT instruction resets the Watch-
The 11-bit immediate address is dog Timer. It also resets the prescaler
loaded into PC bits <10:0>. The upper of the WDT. Status bits TO and PD
bits of the PC are loaded from are set.
PCLATH. CALL is a 2-cycle
instruction.

CALLW Subroutine Call With W COMF Complement f

Syntax: [ label ] CALLW Syntax: [ label ] COMF f,d

Operands: None Operands: 0  f  127

d  [0,1]
Operation: (PC) +1  TOS,
(W)  PC<7:0>, Operation: (f)  (destination)
(PCLATH<6:0>) PC<14:8> Status Affected: Z
Description: The contents of register ‘f’ are
Status Affected: None complemented. If ‘d’ is ‘0’, the result is
Description: Subroutine call with W. First, the stored in W. If ‘d’ is ‘1’, the result is
return address (PC + 1) is pushed stored back in register ‘f’.
onto the return stack. Then, the
contents of W is loaded into PC<7:0>,
and the contents of PCLATH into
PC<14:8>. CALLW is a 2-cycle
instruction.

CLRF Clear f DECF Decrement f

Syntax: [ label ] CLRF f Syntax: [ label ] DECF f,d
Operands: 0  f  127 Operands: 0  f  127
d  [0,1]
Operation: 00h  (f)
1Z Operation: (f) - 1  (destination)
Status Affected: Z Status Affected: Z
Description: The contents of register ‘f’ are cleared Description: Decrement register ‘f’. If ‘d’ is ‘0’, the
and the Z bit is set. result is stored in the W register. If ‘d’
is ‘1’, the result is stored back in
register ‘f’.
CLRW Clear W
Syntax: [ label ] CLRW
Operands: None
Operation: 00h  (W)
1Z
Status Affected: Z
Description: W register is cleared. Zero bit (Z) is
set.

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DECFSZ Decrement f, Skip if 0 INCFSZ Increment f, Skip if 0

Syntax: [ label ] DECFSZ f,d Syntax: [ label ] INCFSZ f,d
Operands: 0  f  127 Operands: 0  f  127
d  [0,1] d  [0,1]
Operation: (f) - 1  (destination); Operation: (f) + 1  (destination),
skip if result = 0 skip if result = 0
Status Affected: None Status Affected: None
Description: The contents of register ‘f’ are decre- Description: The contents of register ‘f’ are incre-
mented. If ‘d’ is ‘0’, the result is placed mented. If ‘d’ is ‘0’, the result is placed
in the W register. If ‘d’ is ‘1’, the result in the W register. If ‘d’ is ‘1’, the result
is placed back in register ‘f’. is placed back in register ‘f’.
If the result is ‘1’, the next instruction is If the result is ‘1’, the next instruction is
executed. If the result is ‘0’, then a executed. If the result is ‘0’, a NOP is
NOP is executed instead, making it a executed instead, making it a 2-cycle
2-cycle instruction. instruction.

GOTO Unconditional Branch IORLW Inclusive OR literal with W

Syntax: [ label ] GOTO k Syntax: [ label ] IORLW k
Operands: 0  k  2047 Operands: 0  k  255
Operation: k  PC<10:0> Operation: (W) .OR. k  (W)
PCLATH<6:3>  PC<14:11>
Status Affected: Z
Status Affected: None Description: The contents of the W register are
Description: GOTO is an unconditional branch. The OR’ed with the 8-bit literal ‘k’. The
11-bit immediate value is loaded into result is placed in the W register.
PC bits <10:0>. The upper bits of PC
are loaded from PCLATH<4:3>. GOTO
is a 2-cycle instruction.

INCF Increment f IORWF Inclusive OR W with f

Syntax: [ label ] INCF f,d Syntax: [ label ] IORWF f,d
Operands: 0  f  127 Operands: 0  f  127
d  [0,1] d  [0,1]
Operation: (f) + 1  (destination) Operation: (W) .OR. (f)  (destination)
Status Affected: Z Status Affected: Z
Description: The contents of register ‘f’ are incre- Description: Inclusive OR the W register with regis-
mented. If ‘d’ is ‘0’, the result is placed ter ‘f’. If ‘d’ is ‘0’, the result is placed in
in the W register. If ‘d’ is ‘1’, the result the W register. If ‘d’ is ‘1’, the result is
is placed back in register ‘f’. placed back in register ‘f’.

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 PIC16(L)F15313/23

LSLF Logical Left Shift MOVF Move f

Syntax: [ label ] LSLF f {,d} Syntax: [ label ] MOVF f,d
Operands: 0  f  127 Operands: 0  f  127
d [0,1] d  [0,1]
Operation: (f<7>)  C Operation: (f)  (dest)
(f<6:0>)  dest<7:1>
Status Affected: Z
0  dest<0>
Description: The contents of register f is moved to
Status Affected: C, Z
a destination dependent upon the
Description: The contents of register ‘f’ are shifted status of d. If d = 0, destination is W
one bit to the left through the Carry flag. register. If d = 1, the destination is file
A ‘0’ is shifted into the LSb. If ‘d’ is ‘0’, register f itself. d = 1 is useful to test a
the result is placed in W. If ‘d’ is ‘1’, the file register since status flag Z is
result is stored back in register ‘f’. affected.

C register f 0 Words: 1
Cycles: 1
Example: MOVF FSR, 0
After Instruction
LSRF Logical Right Shift
W = value in FSR register
Syntax: [ label ] LSRF f {,d} Z = 1
Operands: 0  f  127
d [0,1]
Operation: 0  dest<7>
(f<7:1>)  dest<6:0>,
(f<0>)  C,
Status Affected: C, Z
Description: The contents of register ‘f’ are shifted
one bit to the right through the Carry
flag. A ‘0’ is shifted into the MSb. If ‘d’ is
‘0’, the result is placed in W. If ‘d’ is ‘1’,
the result is stored back in register ‘f’.

0 register f C

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 PIC16(L)F15313/23

MOVIW Move INDFn to W MOVLP Move literal to PCLATH

Syntax: [ label ] MOVIW ++FSRn Syntax: [ label ] MOVLP k
[ label ] MOVIW --FSRn
Operands: 0  k  127
[ label ] MOVIW FSRn++
[ label ] MOVIW FSRn-- Operation: k  PCLATH
[ label ] MOVIW k[FSRn] Status Affected: None
Operands: n  [0,1] Description: The 7-bit literal ‘k’ is loaded into the
mm  [00,01, 10, 11] PCLATH register.
-32  k  31
Operation: INDFn  W
Effective address is determined by MOVLW Move literal to W
• FSR + 1 (preincrement)
Syntax: [ label ] MOVLW k
• FSR - 1 (predecrement)
• FSR + k (relative offset) Operands: 0  k  255
After the Move, the FSR value will be
Operation: k  (W)
either:
• FSR + 1 (all increments) Status Affected: None
• FSR - 1 (all decrements) Description: The 8-bit literal ‘k’ is loaded into W reg-
• Unchanged ister. The “don’t cares” will assemble as
Status Affected: Z ‘0’s.
Words: 1

Mode Syntax mm Cycles: 1

Preincrement ++FSRn 00 Example: MOVLW 0x5A

Predecrement --FSRn 01 After Instruction

W = 0x5A
Postincrement FSRn++ 10
Postdecrement FSRn-- 11
MOVWF Move W to f
Syntax: [ label ] MOVWF f
Description: This instruction is used to move data
between W and one of the indirect Operands: 0  f  127
registers (INDFn). Before/after this Operation: (W)  (f)
move, the pointer (FSRn) is updated by
Status Affected: None
pre/post incrementing/decrementing it.
Description: Move data from W register to register
Note: The INDFn registers are not ‘f’.
physical registers. Any instruction that Words: 1
accesses an INDFn register actually
accesses the register at the address Cycles: 1
specified by the FSRn. Example: MOVWF LATA
Before Instruction
FSRn is limited to the range 0000h -
LATA = 0xFF
FFFFh. Incrementing/decrementing it
W = 0x4F
beyond these bounds will cause it to
After Instruction
wrap-around.
LATA = 0x4F
W = 0x4F
MOVLB Move literal to BSR
Syntax: [ label ] MOVLB k
Operands: 0k
Operation: k  BSR
Status Affected: None
Description: The 6-bit literal ‘k’ is loaded into the
Bank Select Register (BSR).

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 PIC16(L)F15313/23

MOVWI Move W to INDFn NOP No Operation

Syntax: [ label ] MOVWI ++FSRn Syntax: [ label ] NOP

[ label ] MOVWI --FSRn Operands: None
[ label ] MOVWI FSRn++
Operation: No operation
[ label ] MOVWI FSRn--
[ label ] MOVWI k[FSRn] Status Affected: None

Operands: n  [0,1] Description: No operation.

mm  [00,01, 10, 11] Words: 1
-32  k  31
Cycles: 1
Operation: W  INDFn
Example: NOP
Effective address is determined by
• FSR + 1 (preincrement)
• FSR - 1 (predecrement)
• FSR + k (relative offset)
After the Move, the FSR value will be
either:
RESET Software Reset
• FSR + 1 (all increments) Syntax: [ label ] RESET
• FSR - 1 (all decrements)
Operands: None
Unchanged
Operation: Execute a device Reset. Resets the
Status Affected: None
RI flag of the PCON register.
Status Affected: None
Mode Syntax mm
Description: This instruction provides a way to
Preincrement ++FSRn 00 execute a hardware Reset by
Predecrement --FSRn 01 software.

Postincrement FSRn++ 10
Postdecrement FSRn-- 11
RETFIE Return from Interrupt
Syntax: [ label ] RETFIE k
Description: This instruction is used to move data
Operands: None
between W and one of the indirect
registers (INDFn). Before/after this Operation: TOS  PC,
move, the pointer (FSRn) is updated by 1  GIE
pre/post incrementing/decrementing it. Status Affected: None

Note: The INDFn registers are not Description: Return from Interrupt. Stack is POPed
physical registers. Any instruction that and Top-of-Stack (TOS) is loaded in
accesses an INDFn register actually the PC. Interrupts are enabled by
accesses the register at the address setting Global Interrupt Enable bit,
specified by the FSRn. GIE (INTCON<7>). This is a 2-cycle
instruction.
FSRn is limited to the range Words: 1
0000h-FFFFh.
Cycles: 2
Incrementing/decrementing it beyond
these bounds will cause it to Example: RETFIE
wrap-around. After Interrupt
PC = TOS
The increment/decrement operation on GIE = 1
FSRn WILL NOT affect any Status bits.

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 PIC16(L)F15313/23

RETLW Return with literal in W RLF Rotate Left f through Carry

Syntax: [ label ] RETLW k Syntax: [ label ] RLF f,d

Operands: 0  k  255 Operands: 0  f  127

d  [0,1]
Operation: k  (W);
TOS  PC Operation: See description below
Status Affected: C
Status Affected: None
Description: The W register is loaded with the 8-bit Description: The contents of register ‘f’ are rotated
one bit to the left through the Carry
literal ‘k’. The program counter is
loaded from the top of the stack (the flag. If ‘d’ is ‘0’, the result is placed in
return address). This is a 2-cycle the W register. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.
instruction.
C Register f
Words: 1
Cycles: 2
Words: 1
Example: CALL TABLE;W contains table
Cycles: 1
;offset value
• ;W now has table value Example: RLF REG1,0
TABLE • Before Instruction
• REG1 = 1110 0110
ADDWF PC ;W = offset C = 0
RETLW k1 ;Begin table After Instruction
RETLW k2 ; REG1 = 1110 0110
• W = 1100 1100
• C = 1
•
RETLW kn ; End of table
RRF Rotate Right f through Carry
Before Instruction
W = 0x07 Syntax: [ label ] RRF f,d
After Instruction Operands: 0  f  127
W = value of k8 d  [0,1]
Operation: See description below

RETURN Return from Subroutine Status Affected: C

Description: The contents of register ‘f’ are rotated
Syntax: [ label ] RETURN one bit to the right through the Carry
Operands: None flag. If ‘d’ is ‘0’, the result is placed in
the W register. If ‘d’ is ‘1’, the result is
Operation: TOS  PC
placed back in register ‘f’.
Status Affected: None
C Register f
Description: Return from subroutine. The stack is
POPed and the top of the stack (TOS)
is loaded into the program counter.
This is a 2-cycle instruction.

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 PIC16(L)F15313/23

SUBWF Subtract W from f

SLEEP Enter Sleep mode Syntax: [ label ] SUBWF f,d

Syntax: [ label ] SLEEP Operands: 0 f 127

d  [0,1]
Operands: None
Operation: (f) - (W) destination)
Operation: 00h  WDT,
0  WDT prescaler, Status Affected: C, DC, Z
1  TO, Description: Subtract (2’s complement method) W
0  PD register from register ‘f’. If ‘d’ is ‘0’, the
Status Affected: TO, PD result is stored in the W
register. If ‘d’ is ‘1’, the result is stored
Description: The power-down Status bit, PD is
back in register ‘f.
cleared. Time-out Status bit, TO is
set. Watchdog Timer and its C=0 Wf
prescaler are cleared.
See Section 11.2 “Sleep Mode” for C=1 Wf
more information. DC = 0 W<3:0>  f<3:0>
DC = 1 W<3:0>  f<3:0>

SUBWFB Subtract W from f with Borrow

Syntax: SUBWFB f {,d}
Operands: 0  f  127
d  [0,1]
Operation: (f) – (W) – (B) dest
Status Affected: C, DC, Z
Description: Subtract W and the BORROW flag
(CARRY) from register ‘f’ (2’s
complement method). If ‘d’ is ‘0’, the
result is stored in W. If ‘d’ is ‘1’, the
SUBLW Subtract W from literal result is stored back in register ‘f’.
Syntax: [ label ] SUBLW k
Operands: 0 k 255
SWAPF Swap Nibbles in f
Operation: k - (W) W)
Status Affected: C, DC, Z Syntax: [ label ] SWAPF f,d

Description: The W register is subtracted (2’s Operands: 0  f  127

complement method) from the 8-bit d  [0,1]
literal ‘k’. The result is placed in the W Operation: (f<3:0>)  (destination<7:4>),
register. (f<7:4>)  (destination<3:0>)
Status Affected: None
C=0 Wk
Description: The upper and lower nibbles of
C=1 Wk
register ‘f’ are exchanged. If ‘d’ is ‘0’,
DC = 0 W<3:0>  k<3:0> the result is placed in the W register. If
DC = 1 W<3:0>  k<3:0> ‘d’ is ‘1’, the result is placed in register
‘f’.

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 PIC16(L)F15313/23

TRIS Load TRIS Register with W XORLW Exclusive OR literal with W

Syntax: [ label ] TRIS f Syntax: [ label ] XORLW k
Operands: 5f7 Operands: 0 k 255
Operation: (W)  TRIS register ‘f’ Operation: (W) .XOR. k W)
Status Affected: None Status Affected: Z
Description: Move data from W register to TRIS Description: The contents of the W register are
register. XOR’ed with the 8-bit literal ‘k’. The
When ‘f’ = 5, TRISA is loaded. result is placed in the W register.
When ‘f’ = 6, TRISB is loaded.
When ‘f’ = 7, TRISC is loaded.

XORWF Exclusive OR W with f

Syntax: [ label ] XORWF f,d
Operands: 0  f  127
d  [0,1]
Operation: (W) .XOR. (f) destination)
Status Affected: Z
Description: Exclusive OR the contents of the W
register with register ‘f’. If ‘d’ is ‘0’, the
result is stored in the W register. If ‘d’
is ‘1’, the result is stored back in
register ‘f’.

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 PIC16(L)F15313/23
37.0 ELECTRICAL SPECIFICATIONS
37.1 Absolute Maximum Ratings(†)
Ambient temperature under bias...................................................................................................... -40°C to +125°C
Storage temperature ........................................................................................................................ -65°C to +150°C
Voltage on pins with respect to VSS
on VDD pin
PIC16F15313/23 ....................................................................................................... -0.3V to +6.5V
PIC16LF15313/23 ..................................................................................................... -0.3V to +4.0V
on MCLR pin ........................................................................................................................... -0.3V to +9.0V
on all other pins ............................................................................................................ -0.3V to (VDD + 0.3V)
Maximum current
on VSS pin(1)
-40°C  TA  +85°C .............................................................................................................. 250 mA
85°C  TA  +125°C ............................................................................................................... 85 mA
on VDD pin for 28-Pin devices(1)
-40°C  TA  +85°C .............................................................................................................. 250 mA
85°C  TA  +125°C ............................................................................................................... 85 mA
on VDD pin for 40-Pin devices(1)
-40°C  TA  +85°C .............................................................................................................. 350 mA
85°C  TA  +125°C ............................................................................................................. 120 mA
on any standard I/O pin ...................................................................................................................... 50 mA
Clamp current, IK (VPIN < 0 or VPIN > VDD) ................................................................................................... 20 mA
Total power dissipation(2)................................................................................................................................ 800 mW

Note 1: Maximum current rating requires even load distribution across I/O pins. Maximum current rating may be
limited by the device package power dissipation characterizations, see Table 37-6 to calculate device
specifications.
2: Power dissipation is calculated as follows:
PDIS = VDD x {IDD - IOH} + VDD - VOH) x IOH} + VOI x IOL

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for
extended periods may affect device reliability.

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 PIC16(L)F15313/23
37.2 Standard Operating Conditions
The standard operating conditions for any device are defined as:
Operating Voltage: VDDMIN VDD VDDMAX
Operating Temperature: TA_MIN TA TA_MAX
VDD — Operating Supply Voltage(1)
PIC16LF15313/23
VDDMIN (Fosc  16 MHz) ......................................................................................................... +1.8V
VDDMIN (Fosc  32 MHz) ......................................................................................................... +2.5V
VDDMAX .................................................................................................................................... +3.6V
PIC16F15313/23
VDDMIN (Fosc  16 MHz) ......................................................................................................... +2.3V
VDDMIN (Fosc  32 MHz) ......................................................................................................... +2.5V
VDDMAX .................................................................................................................................... +5.5V
TA — Operating Ambient Temperature Range
Industrial Temperature
TA_MIN ...................................................................................................................................... -40°C
TA_MAX .................................................................................................................................... +85°C
Extended Temperature
TA_MIN ...................................................................................................................................... -40°C
TA_MAX .................................................................................................................................. +125°C
Note 1: See Parameter Supply Voltage, DS Characteristics: Supply Voltage.

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 PIC16(L)F15313/23
FIGURE 37-1: VOLTAGE FREQUENCY GRAPH, -40°C  TA +125°C, PIC16(L)F15313/23 ONLY

5.5

VDD (V)

2.5

2.3

0 4 10 16 32
Frequency (MHz)

Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: Refer to Table 37-7 for each Oscillator mode’s supported frequencies.

FIGURE 37-2: VOLTAGE FREQUENCY GRAPH, -40°C  TA +125°C, PIC16(L)F15313/23 ONLY

VDD (V)

3.6

2.5

1.8

0 4 10 16 32
Frequency (MHz)

Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: Refer to Table 37-7 for each Oscillator mode’s supported frequencies.

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 PIC16(L)F15313/23
37.3 DC Characteristics
TABLE 37-1: SUPPLY VOLTAGE
PIC16LF15313/23 Standard Operating Conditions (unless otherwise stated)

PIC16F15313/23

Param.
Sym. Characteristic Min. Typ.† Max. Units Conditions
No.
Supply Voltage
D002 VDD 1.8 — 3.6 V FOSC  16 MHz
2.5 — 3.6 V FOSC  16 MHz
D002 VDD 2.3 — 5.5 V FOSC  16 MHz
2.5 — 5.5 V FOSC 16 MHz
RAM Data Retention(1)
D003 VDR 1.5 — — V Device in Sleep mode
D003 VDR 1.7 — — V Device in Sleep mode
Power-on Reset Release Voltage(2)
D004 VPOR — 1.6 — V BOR or LPBOR disabled(3)
D004 VPOR — 1.6 — V BOR or LPBOR disabled(3)
Power-on Reset Rearm Voltage(2)
D005 VPORR — 0.8 — V BOR or LPBOR disabled(3)
D005 VPORR — 1.5 — V BOR or LPBOR disabled(3)
VDD Rise Rate to ensure internal Power-on Reset signal(2)
D006 SVDD 0.05 — — V/ms BOR or LPBOR disabled(3)
D006 SVDD 0.05 — — V/ms BOR or LPBOR disabled(3)
† Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.
2: See Figure 37-3, POR and POR REARM with Slow Rising VDD.
3: See Table 37-11 for BOR and LPBOR trip point information.
4: = F device

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 PIC16(L)F15313/23
FIGURE 37-3: POR AND POR REARM WITH SLOW RISING VDD

VDD

VPOR
VPORR
SVDD

VSS
NPOR(1)

POR REARM

VSS

TVLOW(3) TPOR(2)

Note 1: When NPOR is low, the device is held in Reset.

2: TPOR 1 s typical.
3: TVLOW 2.7 s typical.

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 PIC16(L)F15313/23

TABLE 37-2: SUPPLY CURRENT (IDD)(1,2,4)

Standard Operating Conditions (unless otherwise
PIC16LF15313/23
stated)

PIC16F15313/23

Param. Conditions
Symbol Device Characteristics Min. Typ.† Max. Units
No. VDD Note
D100 IDDXT4 XT = 4 MHz — 360 400 A 3.0V
D100 IDDXT4 XT = 4 MHz — 380 450 A 3.0V
D101 IDDHFO16 HFINTOSC = 16 MHz — 1.4 1.8 mA 3.0V
D101 IDDHFO16 HFINTOSC = 16 MHz — 1.5 1.9 mA 3.0V
D102 IDDHFOPLL HFINTOSC = 32 MHz — 2.3 3.2 mA 3.0V
D102 IDDHFOPLL HFINTOSC = 32 MHz — 2.4 3.2 mA 3.0V
D103 IDDHSPLL32 HS+PLL = 32 MHz — 2.3 3.2 mA 3.0V
D103 IDDHSPLL32 HS+PLL = 32 MHz — 2.4 3.2 mA 3.0V
D104 IDDIDLE IDLE mode, HFINTOSC = 16 MHz — 1.05 1.5 mA 3.0V
D104 IDDIDLE IDLE mode, HFINTOSC = 16 MHz — 1.15 1.5 mA 3.0V
D105 IDDDOZE(3) DOZE mode, HFINTOSC = 16 MHz, Doze — 1.1 — mA 3.0V
Ratio = 16
D105 IDDDOZE(3) DOZE mode, HFINTOSC = 16 MHz, Doze — 1.2 — mA 3.0V
Ratio = 16
† Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from
rail-to-rail; all I/O pins are outputs driven low; MCLR = VDD; WDT disabled.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading
and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current
consumption.
3: IDDDOZE = [IDDIDLE*(N-1)/N] + IDDHFO16/N where N = DOZE Ratio (Register 11-2).
4: PMD bits are all in the default state, no modules are disabled.
5: = F device

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 PIC16(L)F15313/23

TABLE 37-3: POWER-DOWN CURRENT (IPD)(1,2)

PIC16LF15313/23 Standard Operating Conditions (unless otherwise stated)

Standard Operating Conditions (unless otherwise stated)

PIC16F15313/23
VREGPM = 1

Param. Max. Max. Conditions

Symbol Device Characteristics Min. Typ.† Units
No. +85°C +125°C VDD Note
D200 IPD IPD Base — 0.06 2 9 A 3.0V

D200 IPD IPD Base — 0.4 4 12 A 3.0V

D200A — 18 22 27 A 3.0V VREGPM = 0
D201 IPD_WDT Low-Frequency Internal — 0.8 4.0 11.5 A 3.0V
Oscillator/WDT
D201 IPD_WDT Low-Frequency Internal — 0.9 5.0 13 A 3.0V
Oscillator/WDT
D203 IPD_FVR FVR — 33 47 47 A 3.0V
D203 IPD_FVR FVR — 28 44 44 A 3.0V
D204 IPD_BOR Brown-out Reset (BOR) — 10 17 19 A 3.0V
D204 IPD_BOR Brown-out Reset (BOR) — 14 18 20 A 3.0V
D205 IPD_LPBOR Low-Power Brown-out Reset (LPBOR) — 0.5 4 10 A 3.0V
D207 IPD_ADCA ADC - Active — 250 — — A 3.0V ADC is converting (4)
D207 IPD_ADCA ADC - Active — 280 — — A 3.0V ADC is converting (4)
D208 IPD_CMP Comparator — 30 42 44 A 3.0V
D208 IPD_CMP Comparator — 33 44 45 A 3.0V
† Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: The peripheral current is the sum of the base IDD and the additional current consumed when this peripheral is enabled. The
peripheral ∆ current can be determined by subtracting the base IDD or IPD current from this limit. Max. values should be used
when calculating total current consumption.
2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part
in Sleep mode with all I/O pins in high-impedance state and tied to VSS.
3: All peripheral currents listed are on a per-peripheral basis if more than one instance of a peripheral is available.
4: ADC clock source is FRC.
5: = F device

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 PIC16(L)F15313/23

TABLE 37-4: I/O PORTS

Standard Operating Conditions (unless otherwise stated)

Param.
Sym. Characteristic Min. Typ† Max. Units Conditions
No.
VIL Input Low Voltage
I/O PORT:
D300 with TTL buffer — — 0.8 V 4.5V  VDD  5.5V
D301 — — 0.15 VDD V 1.8V  VDD  4.5V
D302 with Schmitt Trigger buffer — — 0.2 VDD V 2.0V  VDD  5.5V
D303 with I2C levels — — 0.3 VDD V
D304 with SMBus levels — — 0.8 V 2.7V  VDD  5.5V
D305 MCLR — — 0.2 VDD V
VIH Input High Voltage
I/O PORT:
D320 with TTL buffer 2.0 — — V 4.5V  VDD 5.5V
D321 0.25 VDD + — — V 1.8V  VDD  4.5V
0.8
D322 with Schmitt Trigger buffer 0.8 VDD — — V 2.0V  VDD  5.5V
D323 with I2C levels 0.7 VDD — — V
D324 with SMBus levels 2.1 — — V 2.7V  VDD  5.5V
D325 MCLR 0.7 VDD — — V
IIL Input Leakage Current(1)
D340 I/O Ports — ±5 ± 125 nA VSS  VPIN  VDD,
Pin at high-impedance, 85°C
D341 — ±5 ± 1000 nA VSS  VPIN  VDD,
Pin at high-impedance, 125°C
D342 MCLR(2) — ± 50 ± 200 nA VSS  VPIN  VDD,
Pin at high-impedance, 85°C
IPUR Weak Pull-up Current
D350 25 120 200 A VDD = 3.0V, VPIN = VSS
VOL Output Low Voltage
D360 I/O ports — — 0.6 V IOL = 10.0mA, VDD = 3.0V
VOH Output High Voltage
D370 I/O ports VDD - 0.7 — — V IOH = 6.0 mA, VDD = 3.0V
D380 CIO All I/O pins — 5 50 pF
†Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: Negative current is defined as current sourced by the pin.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent
normal operating conditions. Higher leakage current may be measured at different input voltages.

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TABLE 37-5: MEMORY PROGRAMMING SPECIFICATIONS

Standard Operating Conditions (unless otherwise stated)
Param.
Sym. Characteristic Min. Typ† Max. Units Conditions
No.
High Voltage Entry Programming Mode Specifications
MEM01 VIHH Voltage on MCLR/VPP pin to enter 8 — 9 V (Note 2, Note 3)
programming mode
MEM02 IPPGM Current on MCLR/VPP pin during — 1 — mA (Note 2)
programming mode
Programming Mode Specifications
MEM10 VBE VDD for Bulk Erase — 2.7 — V
MEM11 IDDPGM Supply Current during Programming — — 10 mA
operation
Program Flash Memory Specifications
MEM30 EP Flash Memory Cell Endurance 10k — — E/W -40C  TA  +85C
(Note 1)
MEM32 TP_RET Characteristic Retention — 40 — Year Provided no other
specifications are violated

MEM33 VP_RD VDD for Read operation VDDMIN — VDDMAX V

MEM34 VP_REW VDD for Row Erase or Write VDDMIN — VDDMAX V
operation
MEM35 TP_REW Self-Timed Row Erase or Self-Timed — 2.0 2.5 ms
Write
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: Flash Memory Cell Endurance for the Flash memory is defined as: One Row Erase operation and one Self-Timed
Write.
2: Required only if CONFIG4, bit LVP is disabled.
3: The MPLAB® ICD2 does not support variable VPP output. Circuitry to limit the ICD2 VPP voltage must be placed
between the ICD2 and target system when programming or debugging with the ICD2.

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TABLE 37-6: THERMAL CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)

Param.
Sym. Characteristic Typ. Units Conditions
No.

TH01 JA Thermal Resistance Junction to Ambient 70 C/W 8-pin PDIP package
95.3C C/W 8-pin SOIC package
100.0 C/W 8-pin DFN package
100.0 C/W 14-pin PDIP package
100.0 C/W 14-pin TSSOP package
77.7 C/W 14-pin SOIC package
51.5 C/W 16-pin UQFN 4x4mm package
TH02 JC Thermal Resistance Junction to Case 32.75 C/W 8-pin PDIP package
31.0 C/W 8-pin SOIC package
24.4 C/W 8-pin DFN package
5.4 C/W 14-pin PDIP package
27.5 C/W 14-pin TSSOP package
31.1 C/W 14-pin SOIC package
23.1 C/W 16-pin UQFN 4x4mm package
TH03 TJMAX Maximum Junction Temperature 150 C
TH04 PD Power Dissipation — W PD = PINTERNAL + PI/O
TH05 PINTERNAL Internal Power Dissipation — W PINTERNAL = IDD x VDD(1)
TH06 PI/O I/O Power Dissipation — W PI/O =  (IOL * VOL) +  (IOH * (VDD - VOH))
TH07 PDER Derated Power — W PDER = PDMAX (TJ - TA)/JA(2)
Note 1: IDD is current to run the chip alone without driving any load on the output pins.
2: TA = Ambient Temperature, TJ = Junction Temperature

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37.4 AC Characteristics

FIGURE 37-4: LOAD CONDITIONS

Rev. 10-000133A
8/1/2013

Load Condition

Pin

CL

VSS

Legend: CL=50 pF for all pins

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FIGURE 37-5: CLOCK TIMING

Q4 Q1 Q2 Q3 Q4 Q1

CLKIN
OS1 OS2 OS2

OS20
CLKOUT
(CLKOUT Mode)

Note 1: See Table 37-7.

TABLE 37-7: EXTERNAL CLOCK/OSCILLATOR TIMING REQUIREMENTS

Standard Operating Conditions (unless otherwise stated)

Param.
Sym. Characteristic Min. Typ† Max. Units Conditions
No.
ECL Oscillator
OS1 FECL Clock Frequency — — 500 kHz
OS2 TECL_DC Clock Duty Cycle 40 — 60 %
ECM Oscillator
OS3 FECM Clock Frequency — — 4 MHz
OS4 TECM_DC Clock Duty Cycle 40 — 60 %
ECH Oscillator
OS5 FECH Clock Frequency — — 32 MHz
OS6 TECH_DC Clock Duty Cycle 40 — 60 %
LP Oscillator
OS7 FLP Clock Frequency — — 100 kHz Note 4
XT Oscillator
OS8 FXT Clock Frequency — — 4 MHz Note 4
HS Oscillator
OS9 FHS Clock Frequency — — 20 MHz Note 4
System Oscillator
OS20 FOSC System Clock Frequency — — 32 MHz (Note 2, Note 3)
OS21 FCY Instruction Frequency — FOSC/4 — MHz
OS22 TCY Instruction Period 125 1/FCY — ns
* These parameters are characterized but not tested.
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on
characterization data for that particular oscillator type under standard operating conditions with the device executing
code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected
current consumption. All devices are tested to operate at “min” values with an external clock applied to OSC1 pin.
When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.
2: The system clock frequency (FOSC) is selected by the “main clock switch controls” as described in Section 9.0
“Oscillator Module (with Fail-Safe Clock Monitor)”.
3: The system clock frequency (FOSC) must meet the voltage requirements defined in the Section 37.2 “Standard
Operating Conditions”.
4: LP, XT and HS oscillator modes require an appropriate crystal or resonator to be connected to the device. For clocking
the device with the external square wave, one of the EC mode selections must be used.

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TABLE 37-8: INTERNAL OSCILLATOR PARAMETERS(1)
Standard Operating Conditions (unless otherwise stated)

Param.
Sym. Characteristic Min. Typ† Max. Units Conditions
No.
OS50 FHFOSC Precision Calibrated HFINTOSC — 4 — MHz (Note 2)
Frequency 8
12
16
32
OS51 FHFOSCLP Low-Power Optimized HFINTOSC — 1 — MHz
Frequency — 2 — MHz
OS52 FMFOSC Internal Calibrated MFINTOSC — 500 — kHz
Frequency
OS53 FLFOSC Internal LFINTOSC Frequency — 31 — kHz
OS54 THFOSCST HFINTOSC — 11 20 s VREGPM = 0
Wake-up from Sleep Start-up — 50 — s VREGPM = 1
Time
OS56 TLFOSCST LFINTOSC — 0.2 — ms
Wake-up from Sleep Start-up Time
†Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to
the device as possible. 0.1 F and 0.01 F values in parallel are recommended.
2: See Figure 37-6: Precision Calibrated HFINTOSC Frequency Accuracy Over Device VDD and Tempera-
ture.

FIGURE 37-6: PRECISION CALIBRATED HFINTOSC FREQUENCY ACCURACY OVER DEVICE

VDD AND TEMPERATURE

125

± 5%

85

± 3%
Temperature (°C)

60

± 2%

0
± 5%

-40
1.8 2.0 2.3 3.0 3.5 4.0 4.5 5.0 5.5

VDD (V)

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TABLE 37-9: PLL SPECIFICATIONS
Standard Operating Conditions (unless otherwise stated) VDD 2.5V
Param.
Sym. Characteristic Min. Typ† Max. Units Conditions
No.
PLL01 FPLLIN PLL Input Frequency Range 4 — 8 MHz
PLL02 FPLLOUT PLL Output Frequency Range 16 — 32 MHz Note 1
PLL03 TPLLST PLL Lock Time from Start-up — 200 — s
PLL04 FPLLJIT PLL Output Frequency Stability (Jitter) -0.25 — 0.25 %
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: The output frequency of the PLL must meet the FOSC requirements listed in Parameter D002.

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FIGURE 37-7: CLKOUT AND I/O TIMING

Cycle Write Fetch Read Execute

Q4 Q1 Q2 Q3
FOSC
IO1 IO2
IO10
CLKOUT
IO8, IO9 IO5 IO6, IO7
IO4
I/O pin
(Input)
IO3
I/O pin Old Value New Value
(Output)
IO6, IO7, IO8, IO9

TABLE 37-10: I/O AND CLKOUT TIMING SPECIFICATIONS

Standard Operating Conditions (unless otherwise stated)
Param.
Sym. Characteristic Min. Typ† Max. Units Conditions
No.
IO1* TCLKOUTH CLKOUT rising edge delay (rising — — 70 ns
edge Fosc (Q1 cycle) to falling edge
CLKOUT
IO2* TCLKOUTL CLKOUT falling edge delay (rising — — 72 ns
edge Fosc (Q3 cycle) to rising edge
CLKOUT
IO3* TIO_VALID Port output valid time (rising edge — 50 70 ns
Fosc (Q1 cycle) to port valid)
IO4* TIO_SETUP Port input setup time (Setup time 20 — — ns
before rising edge Fosc – Q2 cycle)
IO5* TIO_HOLD Port input hold time (Hold time after 50 — — ns
rising edge Fosc – Q2 cycle)
IO6* TIOR_SLREN Port I/O rise time, slew rate enabled — 25 — ns VDD = 3.0V
IO7* TIOR_SLRDIS Port I/O rise time, slew rate disabled — 5 — ns VDD = 3.0V
IO8* TIOF_SLREN Port I/O fall time, slew rate enabled — 25 — ns VDD = 3.0V
IO9* TIOF_SLRDIS Port I/O fall time, slew rate disabled — 5 — ns VDD = 3.0V
IO10* TINT INT pin high or low time to trigger an 25 — — ns
interrupt
IO11* TIOC Interrupt-on-Change minimum high or 25 — — ns
low time to trigger interrupt
*These parameters are characterized but not tested.

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FIGURE 37-8: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING

VDD

MCLR
RST01
Internal
POR
RST04
PWRT
Time-out RST05

OSC
Start-up Time

Internal Reset(1)

Watchdog Timer
Reset(1)
RST03
RST02 RST02

I/O pins

Note 1: Asserted low.

FIGURE 37-9: BROWN-OUT RESET TIMING AND CHARACTERISTICS

VDD
VBOR + VHYST
VBOR

(Device in Brown-out Reset) (Device not in Brown-out Reset)

(RST08)(1)

Reset
(RST04)(1)
(due to BOR)

Note 1: 64 ms delay only if PWRTE bit in the Configuration Word register is programmed to ‘1’; 2 ms
delay if PWRTE = 0.

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TABLE 37-11: RESET, WDT, OSCILLATOR START-UP TIMER, POWER-UP TIMER, BROWN-OUT
RESET AND LOW-POWER BROWN-OUT RESET SPECIFICATIONS
Standard Operating Conditions (unless otherwise stated)

Param.
Sym. Characteristic Min. Typ† Max. Units Conditions
No.

RST01* TMCLR MCLR Pulse Width Low to ensure Reset 2 — — s

RST02* TIOZ I/O high-impedance from Reset detection — — 2 s
RST03 TWDT Watchdog Timer Time-out Period — 16 — ms 16 ms Nominal Reset Time
RST04* TPWRT Power-up Timer Period — 65 — ms
RST05 TOST Oscillator Start-up Timer Period(1,2) — 1024 — TOSC
RST06 VBOR Brown-out Reset Voltage(4) 2.55 2.70 2.85 V BORV = 0
2.30 2.45 2.60 V BORV = 1 (F devices)
1.80 1.90 2.10 V BORV = 1 (LF devices)
RST07 VBORHYS Brown-out Reset Hysteresis — 40 — mV
RST08 TBORDC Brown-out Reset Response Time — 3 — s
RST09 VLPBOR Low-Power Brown-out Reset Voltage 1.8 1.9 2.2 V LF Devices Only
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: By design, the Oscillator Start-up Timer (OST) counts the first 1024 cycles, independent of frequency.
2: To ensure these voltage tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible.
0.1 F and 0.01 F values in parallel are recommended.

TABLE 37-12: ANALOG-TO-DIGITAL CONVERTER (ADC) ACCURACY SPECIFICATIONS(1,2):

Standard Operating Conditions (unless otherwise stated)
VDD = 3.0V, TA = 25°C
Param.
Sym. Characteristic Min. Typ† Max. Units Conditions
No.
AD01 NR Resolution — — 10 bit
AD02 EIL Integral Error — ±0.1 ±1.0 LSb ADCREF+ = 3.0V, ADCREF-= 0V
AD03 EDL Differential Error — ±0.1 ±1.0 LSb ADCREF+ = 3.0V, ADCREF-= 0V
AD04 EOFF Offset Error — 0.5 2.0 LSb ADCREF+ = 3.0V, ADCREF-= 0V
AD05 EGN Gain Error — ±0.2 ±1.0 LSb ADCREF+ = 3.0V, ADCREF-= 0V
AD06 VADREF ADC Reference Voltage 1.8 — VDD V
(ADREF+ - ADREF-)
AD07 VAIN Full-Scale Range ADREF- — ADREF+ V
AD08 ZAIN Recommended Impedance of — 10 — k
Analog Voltage Source
AD09 RVREF ADC Voltage Reference Ladder — 50 — k Note 3
Impedance
*These parameters are characterized but not tested.
†Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: Total Absolute Error is the sum of the offset, gain and integral non-linearity (INL) errors.
2: The ADC conversion result never decreases with an increase in the input and has no missing codes.
3: This is the impedance seen by the VREF pads when the external reference pads are selected.

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TABLE 37-13: ANALOG-TO-DIGITAL CONVERTER (ADC) CONVERSION TIMING SPECIFICATIONS
Standard Operating Conditions (unless otherwise stated)

Param.
Sym. Characteristic Min. Typ† Max. Units Conditions
No.
AD20 TAD ADC Clock Period 1 — 9 s The requirement is to set ADCCS
correctly to produce this
period/frequency.
AD21 1 2 6 s Using FRC as the ADC clock
source ADOSC = 1
AD22 TCNV Conversion Time — 11 — TAD Set of GO/DONE bit to Clear of
GO/DONE bit
AD23 TACQ Acquisition Time — 2 — s
AD24 THCD Sample and Hold Capacitor — — — s FOSC-based clock source
Disconnect Time FRC-based clock source
* These parameters are characterized but not tested.
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.

FIGURE 37-10: ADC CONVERSION TIMING (ADC CLOCK FOSC-BASED)

BSF ADCON0, GO
1 TCY
AD24
AD22
Q4

ADC Data 9 8 7 6 3 2 1 0

ADRES OLD_DATA NEW_DATA

ADIF 1 TCY

GO DONE
Sampling Stopped
Sample AD23

FIGURE 37-11: ADC CONVERSION TIMING (ADC CLOCK FROM ADCRC)

BSF ADCON0, GO
AD24 1 TCY
AD22
Q4
AD20
ADC_clk

ADC Data 9 8 7 6 3 2 1 0

ADRES OLD_DATA NEW_DATA

ADIF 1 TCY

GO DONE

AD23 Sampling Stopped

Sample

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TABLE 37-14: COMPARATOR SPECIFICATIONS
Standard Operating Conditions (unless otherwise stated)
VDD = 3.0V, TA = 25°C

Param.
Sym. Characteristics Min. Typ. Max. Units Comments
No.
CM01 VIOFF Input Offset Voltage — — ±50 mV VICM = VDD/2
CM02 VICM Input Common Mode Range GND — VDD V
CM03 CMRR Common Mode Input Rejection Ratio — 50 — dB
CM04 VHYST Comparator Hysteresis 15 25 35 mV
CM05 TRESP(1) Response Time, Rising Edge — 300 600 ns
Response Time, Falling Edge — 220 500 ns
CMOS6 TMCV2VO(2) Mode Change to Valid Output — — 10 µs
* These parameters are characterized but not tested.
Note 1: Response time measured with one comparator input at VDD/2, while the other input transitions from VSS to VDD.
2: A mode change includes changing any of the control register values, including module enable.

TABLE 37-15: 5-BIT DAC SPECIFICATIONS

Standard Operating Conditions (unless otherwise stated)
VDD = 3.0V, TA = 25°C

Param.
Sym. Characteristics Min. Typ. Max. Units Comments
No.

DSB01 VLSB Step Size — (VDACREF+ -VDACREF-) /32 — V

DSB01 VACC Absolute Accuracy — —  0.5 LSb
DSB03* RUNIT Unit Resistor Value — 5000 — 
DSB04* TST Settling Time(1) — — 10 s
* These parameters are characterized but not tested.
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: Settling time measured while DACR<4:0> transitions from ‘00000’ to ‘01111’.

TABLE 37-16: FIXED VOLTAGE REFERENCE (FVR) SPECIFICATIONS

Standard Operating Conditions (unless otherwise stated)

Param.
Symbol Characteristic Min. Typ. Max. Units Conditions
No.
FVR01 VFVR1 1x Gain (1.024V) -4 — +4 % VDD  2.5V, -40°C to
85°C
FVR02 VFVR2 2x Gain (2.048V) -4 — +4 % VDD  2.5V, -40°C to
85°C
FVR03 VFVR4 4x Gain (4.096V) -5 — +5 % VDD  4.75V, -40°C
to 85°C
FVR04 TFVRST FVR Start-up Time — 25 — us
FVR05 FVRA1X/FVRC1X FVR output voltage for 1x setting stored in — 1024 — mV
the DIA
FVR06 FVRA2X/FVRC2X FVR output voltage for 2x setting stored in — 2048 — mV
the DIA
FVR07 FVRA4X/FVRC4X FVR output voltage for 4x setting stored in — 4096 — mV
the DIA

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TABLE 37-17: ZERO CROSS DETECT (ZCD) SPECIFICATIONS
Standard Operating Conditions (unless otherwise stated)
VDD = 3.0V, TA = 25°C

Param.
Sym. Characteristics Min. Typ† Max. Units Comments
No.
ZC01 VPINZC Voltage on Zero Cross Pin — 0.75 — V
ZC02 IZCD_MAX Maximum source or sink current — — 600 A
ZC03 TRESPH Response Time, Rising Edge — 1 — s
TRESPL Response Time, Falling Edge — 1 — s
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.

FIGURE 37-12: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS

T0CKI

40 41

42

T1CKI
45 46

47 49

TMR0 or
TMR1

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TABLE 37-18: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Operating Temperature -40°C TA +125°C
Param.
Sym. Characteristic Min. Typ† Max. Units Conditions
No.
40* TT0H T0CKI High Pulse Width No Prescaler 0.5 TCY + 20 — — ns
With Prescaler 10 — — ns
41* TT0L T0CKI Low Pulse Width No Prescaler 0.5 TCY + 20 — — ns
With Prescaler 10 — — ns
42* TT0P T0CKI Period Greater of: — — ns N = prescale value
20 or TCY + 40
N
45* TT1H T1CKI High Synchronous, No Prescaler 0.5 TCY + 20 — — ns
Time Synchronous, with Prescaler 15 — — ns
Asynchronous 30 — — ns
46* TT1L T1CKI Low Synchronous, No Prescaler 0.5 TCY + 20 — — ns
Time Synchronous, with Prescaler 15 — — ns
Asynchronous 30 — — ns
47* TT1P T1CKI Input Synchronous Greater of: — — ns N = prescale value
Period 30 or TCY + 40
N
Asynchronous 60 — — ns
49* TCKEZTMR1 Delay from External Clock Edge to Timer 2 TOSC — 7 TOSC — Timers in Sync
Increment mode
* These parameters are characterized but not tested.
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.

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FIGURE 37-13: CAPTURE/COMPARE/PWM TIMINGS (CCP)
CCPx
(Capture mode)

CC01 CC02

CC03

Note: Refer to Figure 37-4 for load conditions.

TABLE 37-19: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP)

Standard Operating Conditions (unless otherwise stated)
Operating Temperature -40°C  TA  +125°C
Param.
Sym. Characteristic Min. Typ† Max. Units Conditions
No.
CC01* TccL CCPx Input Low Time No Prescaler 0.5TCY + 20 — — ns
With Prescaler 20 — — ns
CC02* TccH CCPx Input High Time No Prescaler 0.5TCY + 20 — — ns
With Prescaler 20 — — ns
CC03* TccP CCPx Input Period 3TCY + 40 — — ns N = prescale value
N
* These parameters are characterized but not tested.
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.

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FIGURE 37-14: CLC PROPAGATION TIMING
Rev. 10-000031A
6/16/2016

CLC LCx_in[n](1) CLC CLC

CLCxINn CLCx
Input time Module LCx_out(1) Output time

CLC CLC CLC

CLCxINn
Input time Module Output time
CLCx
LCx_in[n](1) LCx_out(1)

CLC01 CLC02 CLC03

Note 1: See Figure 31-1 to identify specific CLC signals.

TABLE 37-20: CONFIGURABLE LOGIC CELL (CLC) CHARACTERISTICS

Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +125°C
Param.
Sym. Characteristic Min. Typ† Max. Units Conditions
No.
CLC01* TCLCIN CLC input time — 7 IO5 ns (Note 1)
CLC02* TCLC CLC module input to output propagation time — 24 — ns VDD = 1.8V
— 12 — ns VDD > 3.6V
CLC03* TCLCOUT CLC output time Rise Time — IO7 — — (Note 1)
Fall Time — IO8 — — (Note 1)
CLC04* FCLCMAX CLC maximum switching frequency — 32 FOSC MHz
* These parameters are characterized but not tested.
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: See Table 37-10 for IO5, IO7 and IO8 rise and fall times.

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FIGURE 37-15: EUSART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING

CK
US121 US121

DT

US120 US122

Note: Refer to Figure 37-4 for load conditions.

TABLE 37-21: EUSART SYNCHRONOUS TRANSMISSION CHARACTERISTICS

Standard Operating Conditions (unless otherwise stated)

Param.
Symbol Characteristic Min. Max. Units Conditions
No.
US120 TCKH2DTV SYNC XMIT (Master and Slave) — 80 ns 3.0V  VDD  5.5V
Clock high to data-out valid — 100 ns 1.8V  VDD  5.5V
US121 TCKRF Clock out rise time and fall time — 45 ns 3.0V  VDD  5.5V
(Master mode) — 50 ns 1.8V  VDD  5.5V
US122 TDTRF Data-out rise time and fall time — 45 ns 3.0V  VDD  5.5V
— 50 ns 1.8V  VDD  5.5V

FIGURE 37-16: EUSART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING

CK
US125

DT
US126

Note: Refer to Figure 37-4 for load conditions.

TABLE 37-22: EUSART SYNCHRONOUS RECEIVE REQUIREMENTS

Standard Operating Conditions (unless otherwise stated)

Param.
Symbol Characteristic Min. Max. Units Conditions
No.
US125 TDTV2CKL SYNC RCV (Master and Slave)
Data-setup before CK  (DT hold time) 10 — ns
US126 TCKL2DTL Data-hold after CK  (DT hold time) 15 — ns

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FIGURE 37-17: SPI MASTER MODE TIMING (CKE = 0, SMP = 0)

SS

SP81
SCK
(CKP = 0)
SP71 SP72
SP78 SP79

SCK
(CKP = 1)

SP79 SP78
SP80

SDO MSb bit 6 - - - - - -1 LSb

SP75, SP76

SDI MSb In bit 6 - - - -1 LSb In

SP74
SP73

Note: Refer to Figure 37-4 for load conditions.

FIGURE 37-18: SPI MASTER MODE TIMING (CKE = 1, SMP = 1)

SS

SP81
SCK
(CKP = 0)
SP71 SP72
SP79
SP73
SCK
(CKP = 1)

SP80
SP78

SDO MSb bit 6 - - - - - -1 LSb

SP75, SP76

SDI MSb In bit 6 - - - -1 LSb In

SP74
SP73

Note: Refer to Figure 37-4 for load conditions.

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FIGURE 37-19: SPI SLAVE MODE TIMING (CKE = 0)

SS

SP70

SCK SP83
(CKP = 0)
SP71 SP72
SP78 SP79

SCK
(CKP = 1)

SP79 SP78
SP80

SDO MSb bit 6 - - - - - -1 LSb

SP75, SP76 SP77

SDI MSb In bit 6 - - - -1 LSb In

SP74

SP73

Note: Refer to Figure 37-4 for load conditions.

FIGURE 37-20: SPI SLAVE MODE TIMING (CKE = 1)

SP82
SS

SP70
SCK SP83
(CKP = 0)

SP71 SP72

SCK
(CKP = 1)

SP80

SDO MSb bit 6 - - - - - -1 LSb

SP77
SP75, SP76

SDI
MSb In bit 6 - - - -1 LSb In

SP74

SP73

Note: Refer to Figure 37-4 for load conditions.

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 PIC16(L)F15313/23
TABLE 37-23: SPI MODE REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)

Param.
Symbol Characteristic Min. Typ† Max. Units Conditions
No.

SP70* TSSL2SCH, SS to SCK or SCK input 2.25*TCY — — ns

TSSL2SCL
SP71* TSCH SCK input high time (Slave mode) TCY + 20 — — ns
SP72* TSCL SCK input low time (Slave mode) TCY + 20 — — ns
SP73* TDIV2SCH, Setup time of SDI data input to SCK 100 — — ns
TDIV2SCL edge
SP74* TSCH2DIL, Hold time of SDI data input to SCK edge 100 — — ns
TSCL2DIL
SP75* TDOR SDO data output rise time — 10 25 ns 3.0V  VDD  5.5V
— 25 50 ns 1.8V  VDD  5.5V
SP76* TDOF SDO data output fall time — 10 25 ns
SP77* TSSH2DOZ SS to SDO output high-impedance 10 — 50 ns
SP78* TSCR SCK output rise time — 10 25 ns 3.0V  VDD  5.5V
(Master mode) — 25 50 ns 1.8V  VDD  5.5V
SP79* TSCF SCK output fall time (Master mode) — 10 25 ns
SP80* TSCH2DOV, SDO data output valid after SCK edge — — 50 ns 3.0V  VDD  5.5V
TSCL2DOV — — 145 ns 1.8V  VDD  5.5V
SP81* TDOV2SCH, SDO data output setup to SCK edge 1 Tcy — — ns
TDOV2SCL
SP82* TSSL2DOV SDO data output valid after SS edge — — 50 ns
SP83* TSCH2SSH, SS after SCK edge 1.5 TCY + 40 — — ns
TSCL2SSH
* These parameters are characterized but not tested.
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.

 2017 Microchip Technology Inc. Preliminary DS40001897A-page 484

 PIC16(L)F15313/23
FIGURE 37-21: I2C BUS START/STOP BITS TIMING

SCL
SP91 SP93
SP90 SP92

SDA

Start Stop
Condition Condition

Note: Refer to Figure 37-4 for load conditions.

TABLE 37-24: I2C BUS START/STOP BITS REQUIREMENTS

Standard Operating Conditions (unless otherwise stated)

Param.
Symbol Characteristic Min. Typ Max. Units Conditions
No.

SP90* TSU:STA Start condition 100 kHz mode 4700 — — ns Only relevant for Repeated Start
Setup time 400 kHz mode 600 — — condition

SP91* THD:STA Start condition 100 kHz mode 4000 — — ns After this period, the first clock
Hold time 400 kHz mode 600 — — pulse is generated

SP92* TSU:STO Stop condition 100 kHz mode 4700 — — ns

Setup time 400 kHz mode 600 — —
SP93 THD:STO Stop condition 100 kHz mode 4000 — — ns
Hold time 400 kHz mode 600 — —
* These parameters are characterized but not tested.

FIGURE 37-22: I2C BUS DATA TIMING

SP103 SP100 SP102

SP101

SCL
SP90
SP106
SP107
SP91 SP92
SDA
In
SP110
SP109
SP109
SDA
Out

Note: Refer to Figure 37-4 for load conditions.

 2017 Microchip Technology Inc. Preliminary DS40001897A-page 485

 PIC16(L)F15313/23
TABLE 37-25: I2C BUS DATA REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)

Param.
Symbol Characteristic Min. Max. Units Conditions
No.

SP100* THIGH Clock high time 100 kHz mode 4.0 — s Device must operate at a
minimum of 1.5 MHz
400 kHz mode 0.6 — s Device must operate at a
minimum of 10 MHz
SSP module 1.5TCY —
SP101* TLOW Clock low time 100 kHz mode 4.7 — s Device must operate at a
minimum of 1.5 MHz
400 kHz mode 1.3 — s Device must operate at a
minimum of 10 MHz
SSP module 1.5TCY —
SP102* TR SDA and SCL rise 100 kHz mode — 1000 ns
time 400 kHz mode 20 + 0.1CB 300 ns CB is specified to be from
10-400 pF
SP103* TF SDA and SCL fall time 100 kHz mode — 250 ns
400 kHz mode 20 + 0.1CB 250 ns CB is specified to be from
10-400 pF
SP106* THD:DAT Data input hold time 100 kHz mode 0 — ns
400 kHz mode 0 0.9 s
SP107* TSU:DAT Data input setup time 100 kHz mode 250 — ns (Note 2)
400 kHz mode 100 — ns
SP109* TAA Output valid from 100 kHz mode — 3500 ns (Note 1)
clock 400 kHz mode — — ns
SP110* TBUF Bus free time 100 kHz mode 4.7 — s Time the bus must be free
400 kHz mode 1.3 — s before a new transmission
can start
SP111 CB Bus capacitive loading — 400 pF
* These parameters are characterized but not tested.
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns)
of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
2: A Fast mode (400 kHz) I2C bus device can be used in a Standard mode (100 kHz) I2C bus system, but the requirement
TSU:DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the low period of
the SCL signal. If such a device does stretch the low period of the SCL signal, it must output the next data bit to the SDA
line TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification), before the SCL
line is released.

 2017 Microchip Technology Inc. Preliminary DS40001897A-page 486

 PIC16(L)F15313/23
38.0 DC AND AC
CHARACTERISTICS GRAPHS
AND CHARTS
The graphs and tables provided in this section are for design guidance and are not tested.
In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD
range). This is for information only and devices are ensured to operate properly only within the specified range.
Unless otherwise noted, all graphs apply to both the L and LF devices.
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.
“Typical” represents the mean of the distribution at 25C. “Maximum”, “Max.”, “Minimum” or “Min.”
represents (mean + 3) or (mean - 3) respectively, where  is a standard deviation, over each
temperature range.
Charts and graphs are not available at this time.

 2017 Microchip Technology Inc. Preliminary DS40001897A-page 487

 PIC16(L)F15313/23
39.0 DEVELOPMENT SUPPORT 39.1 MPLAB X Integrated Development
Environment Software
The PIC® microcontrollers (MCU) and dsPIC® digital
signal controllers (DSC) are supported with a full range The MPLAB X IDE is a single, unified graphical user
of software and hardware development tools: interface for Microchip and third-party software, and
• Integrated Development Environment hardware development tool that runs on Windows®,
Linux and Mac OS® X. Based on the NetBeans IDE,
- MPLAB® X IDE Software
MPLAB X IDE is an entirely new IDE with a host of free
- MPLAB® XPRESS IDE Software software components and plug-ins for high-
• Compilers/Assemblers/Linkers performance application development and debugging.
- MPLAB XC Compiler Moving between tools and upgrading from software
- MPASMTM Assembler simulators to hardware debugging and programming
- MPLINKTM Object Linker/ tools is simple with the seamless user interface.
MPLIBTM Object Librarian With complete project management, visual call graphs,
- MPLAB Assembler/Linker/Librarian for a configurable watch window and a feature-rich editor
Various Device Families that includes code completion and context menus,
• Simulators MPLAB X IDE is flexible and friendly enough for new
users. With the ability to support multiple tools on
- MPLAB X SIM Software Simulator
multiple projects with simultaneous debugging, MPLAB
• Emulators X IDE is also suitable for the needs of experienced
- MPLAB REAL ICE™ In-Circuit Emulator users.
• In-Circuit Debuggers/Programmers Feature-Rich Editor:
- MPLAB ICD 3
• Color syntax highlighting
- PICkit™ 3
• Smart code completion makes suggestions and
• Device Programmers provides hints as you type
- MPLAB PM3 Device Programmer • Automatic code formatting based on user-defined
• Low-Cost Demonstration/Development Boards, rules
Evaluation Kits and Starter Kits • Live parsing
• Third-party development tools
User-Friendly, Customizable Interface:
• Fully customizable interface: toolbars, toolbar
buttons, windows, window placement, etc.
• Call graph window
Project-Based Workspaces:
• Multiple projects
• Multiple tools
• Multiple configurations
• Simultaneous debugging sessions
File History and Bug Tracking:
• Local file history feature
• Built-in support for Bugzilla issue tracker

 2017 Microchip Technology Inc. Preliminary DS40001897A-page 488

 PIC16(L)F15313/23
39.2 MPLAB XC Compilers 39.4 MPLINK Object Linker/
The MPLAB XC Compilers are complete ANSI C
MPLIB Object Librarian
compilers for all of Microchip’s 8, 16, and 32-bit MCU The MPLINK Object Linker combines relocatable
and DSC devices. These compilers provide powerful objects created by the MPASM Assembler. It can link
integration capabilities, superior code optimization and relocatable objects from precompiled libraries, using
ease of use. MPLAB XC Compilers run on Windows, directives from a linker script.
Linux or MAC OS X.
The MPLIB Object Librarian manages the creation and
For easy source level debugging, the compilers provide modification of library files of precompiled code. When
debug information that is optimized to the MPLAB X a routine from a library is called from a source file, only
IDE. the modules that contain that routine will be linked in
The free MPLAB XC Compiler editions support all with the application. This allows large libraries to be
devices and commands, with no time or memory used efficiently in many different applications.
restrictions, and offer sufficient code optimization for The object linker/library features include:
most applications.
• Efficient linking of single libraries instead of many
MPLAB XC Compilers include an assembler, linker and smaller files
utilities. The assembler generates relocatable object • Enhanced code maintainability by grouping
files that can then be archived or linked with other relo- related modules together
catable object files and archives to create an execut-
• Flexible creation of libraries with easy module
able file. MPLAB XC Compiler uses the assembler to
listing, replacement, deletion and extraction
produce its object file. Notable features of the assem-
bler include:
39.5 MPLAB Assembler, Linker and
• Support for the entire device instruction set
Librarian for Various Device
• Support for fixed-point and floating-point data
Families
• Command-line interface
• Rich directive set MPLAB Assembler produces relocatable machine
• Flexible macro language code from symbolic assembly language for PIC24,
PIC32 and dsPIC DSC devices. MPLAB XC Compiler
• MPLAB X IDE compatibility
uses the assembler to produce its object file. The
assembler generates relocatable object files that can
39.3 MPASM Assembler then be archived or linked with other relocatable object
The MPASM Assembler is a full-featured, universal files and archives to create an executable file. Notable
macro assembler for PIC10/12/16/18 MCUs. features of the assembler include:

The MPASM Assembler generates relocatable object • Support for the entire device instruction set
files for the MPLINK Object Linker, Intel® standard HEX • Support for fixed-point and floating-point data
files, MAP files to detail memory usage and symbol • Command-line interface
reference, absolute LST files that contain source lines • Rich directive set
and generated machine code, and COFF files for • Flexible macro language
debugging.
• MPLAB X IDE compatibility
The MPASM Assembler features include:
• Integration into MPLAB X IDE projects
• User-defined macros to streamline
assembly code
• Conditional assembly for multipurpose
source files
• Directives that allow complete control over the
assembly process

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39.6 MPLAB X SIM Software Simulator 39.8 MPLAB ICD 3 In-Circuit Debugger
The MPLAB X SIM Software Simulator allows code
System
development in a PC-hosted environment by simulat- The MPLAB ICD 3 In-Circuit Debugger System is
ing the PIC MCUs and dsPIC DSCs on an instruction Microchip’s most cost-effective, high-speed hardware
level. On any given instruction, the data areas can be debugger/programmer for Microchip Flash DSC and
examined or modified and stimuli can be applied from MCU devices. It debugs and programs PIC Flash
a comprehensive stimulus controller. Registers can be microcontrollers and dsPIC DSCs with the powerful,
logged to files for further run-time analysis. The trace yet easy-to-use graphical user interface of the MPLAB
buffer and logic analyzer display extend the power of IDE.
the simulator to record and track program execution,
The MPLAB ICD 3 In-Circuit Debugger probe is
actions on I/O, most peripherals and internal registers.
connected to the design engineer’s PC using a high-
The MPLAB X SIM Software Simulator fully supports speed USB 2.0 interface and is connected to the target
symbolic debugging using the MPLAB XC Compilers, with a connector compatible with the MPLAB ICD 2 or
and the MPASM and MPLAB Assemblers. The soft- MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3
ware simulator offers the flexibility to develop and supports all MPLAB ICD 2 headers.
debug code outside of the hardware laboratory envi-
ronment, making it an excellent, economical software 39.9 PICkit 3 In-Circuit Debugger/
development tool.
Programmer
39.7 MPLAB REAL ICE In-Circuit The MPLAB PICkit 3 allows debugging and program-
Emulator System ming of PIC and dsPIC Flash microcontrollers at a most
affordable price point using the powerful graphical user
The MPLAB REAL ICE In-Circuit Emulator System is interface of the MPLAB IDE. The MPLAB PICkit 3 is
Microchip’s next generation high-speed emulator for connected to the design engineer’s PC using a full-
Microchip Flash DSC and MCU devices. It debugs and speed USB interface and can be connected to the tar-
programs all 8, 16 and 32-bit MCU, and DSC devices get via a Microchip debug (RJ-11) connector (compati-
with the easy-to-use, powerful graphical user interface of ble with MPLAB ICD 3 and MPLAB REAL ICE). The
the MPLAB X IDE. connector uses two device I/O pins and the Reset line
The emulator is connected to the design engineer’s to implement in-circuit debugging and In-Circuit Serial
PC using a high-speed USB 2.0 interface and is Programming™ (ICSP™).
connected to the target with either a connector
compatible with in-circuit debugger systems (RJ-11) 39.10 MPLAB PM3 Device Programmer
or with the new high-speed, noise tolerant, Low-
Voltage Differential Signal (LVDS) interconnection The MPLAB PM3 Device Programmer is a universal,
(CAT5). CE compliant device programmer with programmable
voltage verification at VDDMIN and VDDMAX for
The emulator is field upgradeable through future firm- maximum reliability. It features a large LCD display
ware downloads in MPLAB X IDE. MPLAB REAL ICE (128 x 64) for menus and error messages, and a mod-
offers significant advantages over competitive emulators ular, detachable socket assembly to support various
including full-speed emulation, run-time variable package types. The ICSP cable assembly is included
watches, trace analysis, complex breakpoints, logic as a standard item. In Stand-Alone mode, the MPLAB
probes, a ruggedized probe interface and long (up to PM3 Device Programmer can read, verify and program
three meters) interconnection cables. PIC devices without a PC connection. It can also set
code protection in this mode. The MPLAB PM3
connects to the host PC via an RS-232 or USB cable.
The MPLAB PM3 has high-speed communications and
optimized algorithms for quick programming of large
memory devices, and incorporates an MMC card for file
storage and data applications.

 2017 Microchip Technology Inc. Preliminary DS40001897A-page 490

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39.11 Demonstration/Development 39.12 Third-Party Development Tools
Boards, Evaluation Kits, and Microchip also offers a great collection of tools from
Starter Kits third-party vendors. These tools are carefully selected
A wide variety of demonstration, development and to offer good value and unique functionality.
evaluation boards for various PIC MCUs and dsPIC • Device Programmers and Gang Programmers
DSCs allows quick application development on fully from companies, such as SoftLog and CCS
functional systems. Most boards include prototyping • Software Tools from companies, such as Gimpel
areas for adding custom circuitry and provide applica- and Trace Systems
tion firmware and source code for examination and • Protocol Analyzers from companies, such as
modification. Saleae and Total Phase
The boards support a variety of features, including LEDs, • Demonstration Boards from companies, such as
temperature sensors, switches, speakers, RS-232 MikroElektronika, Digilent® and Olimex
interfaces, LCD displays, potentiometers and additional • Embedded Ethernet Solutions from companies,
EEPROM memory. such as EZ Web Lynx, WIZnet and IPLogika®
The demonstration and development boards can be
used in teaching environments, for prototyping custom
circuits and for learning about various microcontroller
applications.
In addition to the PICDEM™ and dsPICDEM™
demonstration/development board series of circuits,
Microchip has a line of evaluation kits and demonstra-
tion software for analog filter design, KEELOQ® security
ICs, CAN, IrDA®, PowerSmart battery management,
SEEVAL® evaluation system, Sigma-Delta ADC, flow
rate sensing, plus many more.
Also available are starter kits that contain everything
needed to experience the specified device. This usually
includes a single application and debug capability, all
on one board.
Check the Microchip web page (www.microchip.com)
for the complete list of demonstration, development
and evaluation kits.

 2017 Microchip Technology Inc. Preliminary DS40001897A-page 491

 PIC16(L)F15313/23
40.0 PACKAGING INFORMATION
40.1 Package Marking Information

8-Lead PDIP (300 mil) Example

XXXXXXXX 16F15313
P e3 017
XXXXXNNN
YYWW 1525

8-Lead SOIC (3.90 mm) Example

16F15313
PIC16F18313
-I/SO e3 SN e3 1525
NNN 1304017 017

8-Lead UDFN (3x3x0.9 mm) Example

MGJ0
XXXX 1525
YYWW 017
NNN
PIN 1 PIN 1

Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC® designator for Matte Tin (Sn)
* This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.

Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.

 2017 Microchip Technology Inc. Preliminary DS40001897A-page 492

 PIC16(L)F15313/23
40.1 Package Marking Information

14-Lead PDIP (300 mil) Example

PIC16F15323
/SO e3
1525017

14-Lead TSSOP (4.4 mm) Example

XXXXXXXX 16F15323
YYWW 1525 e3
NNN 017

14-Lead SOIC (3.90 mm) Example

PIC16F15323
/SO e3
1525017

Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC® designator for Matte Tin (Sn)
* This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.

Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.

 2017 Microchip Technology Inc. Preliminary DS40001897A-page 493

 PIC16(L)F15313/23

40.1 Package Marking Information (Continued)

16-Lead UQFN (4x4x0.5 mm) Example

PIN 1 PIN 1
PIC16
F15323
/MV e3

525017

Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC® designator for Matte Tin (Sn)
* This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.

Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.

TABLE 40-1: 8-LEAD 3x3 UDFN TOP MARKING

Part Number Marking
PIC16F15313 MGJ0
PIC16LF15313 MGK0

 2017 Microchip Technology Inc. Preliminary DS40001897A-page 494

 PIC16(L)F15313/23
The following sections give the technical details of the packages.

8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

D A
N B

E1

NOTE 1
1 2
TOP VIEW

C A A2

PLANE
L c
A1

e eB
8X b1
8X b
.010 C

SIDE VIEW END VIEW

Microchip Technology Drawing No. C04-018D Sheet 1 of 2

 2017 Microchip Technology Inc. Preliminary DS40001897A-page 495

 PIC16(L)F15313/23

8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

ALTERNATE LEAD DESIGN

(VENDOR DEPENDENT)

DATUM A DATUM A

b b
e e
2 2

e e

Units INCHES
Dimension Limits MIN NOM MAX
Number of Pins N 8
Pitch e .100 BSC
Top to Seating Plane A - - .210
Molded Package Thickness A2 .115 .130 .195
Base to Seating Plane A1 .015 - -
Shoulder to Shoulder Width E .290 .310 .325
Molded Package Width E1 .240 .250 .280
Overall Length D .348 .365 .400
Tip to Seating Plane L .115 .130 .150
Lead Thickness c .008 .010 .015
Upper Lead Width b1 .040 .060 .070
Lower Lead Width b .014 .018 .022
Overall Row Spacing § eB - - .430
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed .010" per side.
4. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Microchip Technology Drawing No. C04-018D Sheet 2 of 2

 2017 Microchip Technology Inc. Preliminary DS40001897A-page 496

 PIC16(L)F15313/23

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

 2017 Microchip Technology Inc. Preliminary DS40001897A-page 497

 PIC16(L)F15313/23

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

 2017 Microchip Technology Inc. Preliminary DS40001897A-page 498

 PIC16(L)F15313/23

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

 2017 Microchip Technology Inc. Preliminary DS40001897A-page 499

 PIC16(L)F15313/23

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

 2017 Microchip Technology Inc. Preliminary DS40001897A-page 500

 PIC16(L)F15313/23

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

 2017 Microchip Technology Inc. Preliminary DS40001897A-page 501

 PIC16(L)F15313/23


 


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 2017 Microchip Technology Inc. Preliminary DS40001897A-page 502

 PIC16(L)F15313/23

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 2017 Microchip Technology Inc. Preliminary DS40001897A-page 503

 PIC16(L)F15313/23

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

 2017 Microchip Technology Inc. Preliminary DS40001897A-page 504

 PIC16(L)F15313/23

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

 2017 Microchip Technology Inc. Preliminary DS40001897A-page 505

 PIC16(L)F15313/23

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 2017 Microchip Technology Inc. Preliminary DS40001897A-page 506

 PIC16(L)F15313/23

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

 2017 Microchip Technology Inc. Preliminary DS40001897A-page 507

 PIC16(L)F15313/23

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

 2017 Microchip Technology Inc. Preliminary DS40001897A-page 508

 PIC16(L)F15313/23

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

 2017 Microchip Technology Inc. Preliminary DS40001897A-page 509

 PIC16(L)F15313/23

16-Lead Ultra Thin Plastic Quad Flat, No Lead Package (JQ) - 4x4x0.5 mm Body [UQFN]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

D A B
N
NOTE 1

2
E
(DATUM B)
(DATUM A)
2X
0.20 C

2X
0.20 C TOP VIEW

C 0.10 C A1
SEATING A
PLANE 16X
(A3) 0.08 C
SIDE VIEW
0.10 C A B
D2

0.10 C A B

E2
2
e
2
1

NOTE 1
K
N
L 16X b
e 0.10 C A B

BOTTOM VIEW
Microchip Technology Drawing C04-257A Sheet 1 of 2

 2017 Microchip Technology Inc. Preliminary DS40001897A-page 510

 PIC16(L)F15313/23

16-Lead Ultra Thin Plastic Quad Flat, No Lead Package (JQ) - 4x4x0.5 mm Body [UQFN]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

Units MILLIMETERS
Dimension Limits MIN NOM MAX
Number of Pins N 16
Pitch e 0.65 BSC
Overall Height A 0.45 0.50 0.55
Standoff A1 0.00 0.02 0.05
Terminal Thickness A3 0.127 REF
Overall Width E 4.00 BSC
Exposed Pad Width E2 2.50 2.60 2.70
Overall Length D 4.00 BSC
Exposed Pad Length D2 2.50 2.60 2.70
Terminal Width b 0.25 0.30 0.35
Terminal Length L 0.30 0.40 0.50
Terminal-to-Exposed-Pad K 0.20 - -
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package is saw singulated
3. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.

Microchip Technology Drawing C04-257A Sheet 2 of 2

 2017 Microchip Technology Inc. Preliminary DS40001897A-page 511

 PIC16(L)F15313/23

16-Lead Ultra Thin Plastic Quad Flat, No Lead Package (JQ) - 4x4x0.5 mm Body
[UQFN]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

C1
X2
16

1
2
C2 Y2

Y1

X1
E SILK SCREEN

RECOMMENDED LAND PATTERN

Units MILLIMETERS
Dimension Limits MIN NOM MAX
Contact Pitch E 0.65 BSC
Optional Center Pad Width X2 2.70
Optional Center Pad Length Y2 2.70
Contact Pad Spacing C1 4.00
Contact Pad Spacing C2 4.00
Contact Pad Width (X16) X1 0.35
Contact Pad Length (X16) Y1 0.80
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-2257A

 2017 Microchip Technology Inc. Preliminary DS40001897A-page 512

 PIC16(L)F15313/23
APPENDIX A: DATA SHEET
REVISION HISTORY

Revision A (4/2017)
Initial release of the document.

 2017 Microchip Technology Inc. Preliminary DS40001897A-page 513

 PIC16(L)F15313/23
THE MICROCHIP WEBSITE CUSTOMER SUPPORT
Microchip provides online support via our website at Users of Microchip products can receive assistance
www.microchip.com. This website is used as a means through several channels:
to make files and information easily available to • Distributor or Representative
customers. Accessible by using your favorite Internet
• Local Sales Office
browser, the website contains the following information:
• Field Application Engineer (FAE)
• Product Support – Data sheets and errata,
• Technical Support
application notes and sample programs, design
resources, user’s guides and hardware support Customers should contact their distributor,
documents, latest software releases and archived representative or Field Application Engineer (FAE) for
software support. Local sales offices are also available to help
• General Technical Support – Frequently Asked customers. A listing of sales offices and locations is
Questions (FAQ), technical support requests, included in the back of this document.
online discussion groups, Microchip consultant Technical support is available through the website
program member listing at: http://www.microchip.com/support
• Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of
Microchip sales offices, distributors and factory
representatives

CUSTOMER CHANGE NOTIFICATION

SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specified product family or development tool of interest.
To register, access the Microchip website at
www.microchip.com. Under “Support”, click on
“Customer Change Notification” and follow the
registration instructions.

 2017 Microchip Technology Inc. Preliminary DS40001897A-page 514

 PIC16(L)F15313/23
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO. [X](1) - X /XX XXX
Examples:
Device Tape and Reel Temperature Package Pattern a) PIC16F15323- E/P
Option Range Extended temperature
PDIP package

Device: PIC16F15313, PIC16LF15313

PIC16F15323, PIC16LF15323

Tape and Reel Blank = Standard packaging (tube or tray)

Option: T = Tape and Reel(1)

Temperature I = -40C to +85C (Industrial)

Range: E = -40C to +125C (Extended)

Package:(2) JQ = 16-lead UQFN 4x4x0.5mm

MF = 8-lead DFN 3x3mm Note 1: Tape and Reel identifier only appears in
P = 8-lead 14-lead PDIP the catalog part number description. This
SL = 14-lead SOIC identifier is used for ordering purposes and
SN = 8-lead SOIC
ST = 14-lead TSSOP is not printed on the device package.
Check with your Microchip Sales Office
for package availability with the Tape and
Reel option.
Pattern: QTP, SQTP, Code or Special Requirements 2: Small form-factor packaging options may
(blank otherwise) be available. Check
www.microchip.com/packaging for
small-form factor package availability, or
contact your local Sales Office.

 2017 Microchip Technology Inc. Preliminary DS40001897A-page 515

 PIC16(L)F15313/23

Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device Trademarks

applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, AnyRate, AVR,
and may be superseded by updates. It is your responsibility to AVR logo, AVR Freaks, BeaconThings, BitCloud, chipKIT, chipKIT
ensure that your application meets with your specifications. logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR,
MICROCHIP MAKES NO REPRESENTATIONS OR Heldo, JukeBlox, KEELOQ, KEELOQ logo, Kleer, LANCheck, LINK
WARRANTIES OF ANY KIND WHETHER EXPRESS OR MD, maXStylus, maXTouch, MediaLB, megaAVR, MOST, MOST
IMPLIED, WRITTEN OR ORAL, STATUTORY OR logo, MPLAB, OptoLyzer, PIC, picoPower, PICSTART, PIC32
OTHERWISE, RELATED TO THE INFORMATION, logo, Prochip Designer, QTouch, RightTouch, SAM-BA, SpyNIC,
INCLUDING BUT NOT LIMITED TO ITS CONDITION, SST, SST Logo, SuperFlash, tinyAVR, UNI/O, and XMEGA are
QUALITY, PERFORMANCE, MERCHANTABILITY OR registered trademarks of Microchip Technology Incorporated in
FITNESS FOR PURPOSE. Microchip disclaims all liability the U.S.A. and other countries.
arising from this information and its use. Use of Microchip ClockWorks, The Embedded Control Solutions Company,
devices in life support and/or safety applications is entirely at EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS,
the buyer’s risk, and the buyer agrees to defend, indemnify and mTouch, Precision Edge, and Quiet-Wire are registered
hold harmless Microchip from any and all damages, claims, trademarks of Microchip Technology Incorporated in the U.S.A.
suits, or expenses resulting from such use. No licenses are Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any
conveyed, implicitly or otherwise, under any Microchip Capacitor, AnyIn, AnyOut, BodyCom, CodeGuard,
intellectual property rights unless otherwise stated. CryptoAuthentication, CryptoCompanion, CryptoController,
dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM,
ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-
Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, Mindi,
MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB,
MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation,
PICDEM, PICDEM.net, PICkit, PICtail, PureSilicon, QMatrix,
RightTouch logo, REAL ICE, Ripple Blocker, SAM-ICE, Serial
Quad I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II,
Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan,
WiperLock, Wireless DNA, and ZENA are trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in
the U.S.A.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and Silicon Storage Technology is a registered trademark of Microchip
Tempe, Arizona; Gresham, Oregon and design centers in California Technology Inc. in other countries.
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping GestIC is a registered trademark of Microchip Technology
devices, Serial EEPROMs, microperipherals, nonvolatile memory and Germany II GmbH & Co. KG, a subsidiary of Microchip Technology
analog products. In addition, Microchip’s quality system for the design Inc., in other countries.
and manufacture of development systems is ISO 9001:2000 certified.
All other trademarks mentioned herein are property of their
respective companies.

QUALITY MANAGEMENT SYSTEM © 2017, Microchip Technology Incorporated, All Rights Reserved.
ISBN: 978-1-5224-1620-3
CERTIFIED BY DNV
== ISO/TS 16949 ==

 2017 Microchip Technology Inc. Preliminary DS40001897A-page 516

 Worldwide Sales and Service
AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE
Corporate Office Asia Pacific Office China - Xiamen Austria - Wels
2355 West Chandler Blvd. Suites 3707-14, 37th Floor Tel: 86-592-2388138 Tel: 43-7242-2244-39
Chandler, AZ 85224-6199 Tower 6, The Gateway Fax: 86-592-2388130 Fax: 43-7242-2244-393
Tel: 480-792-7200 Harbour City, Kowloon China - Zhuhai Denmark - Copenhagen
Fax: 480-792-7277 Hong Kong Tel: 86-756-3210040 Tel: 45-4450-2828
Technical Support: Tel: 852-2943-5100 Fax: 86-756-3210049 Fax: 45-4485-2829
http://www.microchip.com/ Fax: 852-2401-3431 India - Bangalore Finland - Espoo
support
Australia - Sydney Tel: 91-80-3090-4444 Tel: 358-9-4520-820
Web Address:
Tel: 61-2-9868-6733 Fax: 91-80-3090-4123 France - Paris
www.microchip.com
Fax: 61-2-9868-6755 India - New Delhi Tel: 33-1-69-53-63-20
Atlanta Tel: 91-11-4160-8631 Fax: 33-1-69-30-90-79
China - Beijing
Duluth, GA
Tel: 86-10-8569-7000 Fax: 91-11-4160-8632 France - Saint Cloud
Tel: 678-957-9614
Fax: 86-10-8528-2104 India - Pune Tel: 33-1-30-60-70-00
Fax: 678-957-1455
China - Chengdu Tel: 91-20-3019-1500 Germany - Garching
Austin, TX Tel: 86-28-8665-5511
Tel: 512-257-3370 Japan - Osaka Tel: 49-8931-9700
Fax: 86-28-8665-7889 Tel: 81-6-6152-7160 Germany - Haan
Boston Fax: 81-6-6152-9310 Tel: 49-2129-3766400
China - Chongqing
Westborough, MA
Tel: 86-23-8980-9588 Japan - Tokyo Germany - Heilbronn
Tel: 774-760-0087
Fax: 86-23-8980-9500 Tel: 81-3-6880- 3770 Tel: 49-7131-67-3636
Fax: 774-760-0088
China - Dongguan Fax: 81-3-6880-3771 Germany - Karlsruhe
Chicago Tel: 86-769-8702-9880 Korea - Daegu Tel: 49-721-625370
Itasca, IL
Tel: 630-285-0071 China - Guangzhou Tel: 82-53-744-4301 Germany - Munich
Fax: 630-285-0075 Tel: 86-20-8755-8029 Fax: 82-53-744-4302 Tel: 49-89-627-144-0
China - Hangzhou Korea - Seoul Fax: 49-89-627-144-44
Dallas
Tel: 86-571-8792-8115 Tel: 82-2-554-7200
Addison, TX Germany - Rosenheim
Tel: 972-818-7423 Fax: 86-571-8792-8116 Fax: 82-2-558-5932 or Tel: 49-8031-354-560
Fax: 972-818-2924 China - Hong Kong SAR 82-2-558-5934
Israel - Ra’anana
Tel: 852-2943-5100 Malaysia - Kuala Lumpur Tel: 972-9-744-7705
Detroit
Fax: 852-2401-3431 Tel: 60-3-6201-9857
Novi, MI Italy - Milan
Tel: 248-848-4000 Fax: 60-3-6201-9859
China - Nanjing Tel: 39-0331-742611
Tel: 86-25-8473-2460 Malaysia - Penang Fax: 39-0331-466781
Houston, TX
Tel: 281-894-5983 Fax: 86-25-8473-2470 Tel: 60-4-227-8870
Italy - Padova
Fax: 60-4-227-4068
Indianapolis
China - Qingdao Tel: 39-049-7625286
Tel: 86-532-8502-7355 Philippines - Manila
Noblesville, IN Netherlands - Drunen
Tel: 317-773-8323 Fax: 86-532-8502-7205 Tel: 63-2-634-9065
Tel: 31-416-690399
Fax: 317-773-5453 Fax: 63-2-634-9069
China - Shanghai Fax: 31-416-690340
Tel: 317-536-2380 Tel: 86-21-3326-8000 Singapore
Norway - Trondheim
Fax: 86-21-3326-8021 Tel: 65-6334-8870
Los Angeles Tel: 47-7289-7561
Mission Viejo, CA China - Shenyang Fax: 65-6334-8850
Poland - Warsaw
Tel: 949-462-9523 Tel: 86-24-2334-2829 Taiwan - Hsin Chu
Tel: 48-22-3325737
Fax: 949-462-9608 Fax: 86-24-2334-2393 Tel: 886-3-5778-366
Tel: 951-273-7800 Fax: 886-3-5770-955 Romania - Bucharest
China - Shenzhen
Tel: 40-21-407-87-50
Raleigh, NC Tel: 86-755-8864-2200 Taiwan - Kaohsiung
Tel: 919-844-7510 Fax: 86-755-8203-1760 Tel: 886-7-213-7830 Spain - Madrid
Tel: 34-91-708-08-90
New York, NY China - Wuhan Taiwan - Taipei
Fax: 34-91-708-08-91
Tel: 631-435-6000 Tel: 86-27-5980-5300 Tel: 886-2-2508-8600
Fax: 86-27-5980-5118 Fax: 886-2-2508-0102 Sweden - Gothenberg
San Jose, CA Tel: 46-31-704-60-40
Tel: 408-735-9110 China - Xian Thailand - Bangkok
Tel: 408-436-4270 Tel: 86-29-8833-7252 Tel: 66-2-694-1351 Sweden - Stockholm
Fax: 86-29-8833-7256 Fax: 66-2-694-1350 Tel: 46-8-5090-4654
Canada - Toronto
Tel: 905-695-1980 UK - Wokingham
Fax: 905-695-2078 Tel: 44-118-921-5800
Fax: 44-118-921-5820

 2017 Microchip Technology Inc. Preliminary DS40001897A-page 517

11/07/16
Mouser Electronics

Authorized Distributor

Click to View Pricing, Inventory, Delivery & Lifecycle Information:

Microchip:
PIC16F15313-I/SN PIC16F15323-I/P PIC16F15313-I/P PIC16LF15323-I/JQ PIC16F15313T-I/SN PIC16F15323-
I/SL PIC16LF15313-E/RF PIC16LF15323-I/ST PIC16F15323T-I/SL PIC16LF15313-E/P PIC16F15323-E/P
PIC16LF15323-I/P PIC16LF15323T-I/SL PIC16F15323-I/ST PIC16LF15323-I/SL PIC16LF15313-E/SN
PIC16F15323T-I/JQ PIC16F15313-E/SN PIC16LF15313T-I/SN PIC16F15323-I/JQ PIC16LF15323-E/SL
PIC16F15313T-I/RF PIC16LF15323-E/P PIC16F15313-E/P PIC16LF15323T-I/ST PIC16F15323-E/SL PIC16F15323-
E/ST PIC16LF15323-E/JQ PIC16LF15323T-I/JQ PIC16LF15313T-I/RF PIC16LF15313-I/RF PIC16LF15313-I/SN
PIC16LF15313-I/P PIC16LF15323-E/ST PIC16F15323T-I/ST PIC16F15323-E/JQ PIC16F15313-E/RF PIC16F15313-
I/RF